JP6277797B2 - Storage medium control apparatus, storage medium control method, and program - Google Patents

Description

  The present invention relates to a storage medium control device, a storage medium control method, and a program.

  A combination of multiple HDDs called RAID (Redundant Arrays of Independent Drives) 0 for high-speed access to HDDs (Hard Disk Drives) is configured as if it were a single HDD, and data is distributed to multiple HDDs. There is a way to remember at the same time. Hereinafter, “RAID0” may be referred to as “striping”. In other words, it is one of the RAID technology methods that collectively manage a plurality of external storage devices (such as HDDs) as a single device, and distributes data evenly to the plurality of storage devices and reads them simultaneously into each storage device. Or writing to increase the speed of data reading and writing. Also, the slowest transfer speed of the striped disks multiplied by the number of units becomes the overall transfer speed, and the data transfer speed is dramatically increased.

  Also, when only one HDD is connected to an HDD host controller that supports RAID 0 and used in a configuration without RAID 0 (striping), the transfer bandwidth of the HDD host controller may be wasted. Therefore, as a method for optimizing the transfer band of the HDD host controller, in the case of a configuration without RAID 0 (striping), a part of the clock frequency of the control circuit is made half of the configuration with RAID 0 (striping). The method is known.

  Patent Document 1 discloses a data recording / reproducing apparatus capable of eliminating the mismatch of the capability between the bandwidth of the interface section and the disk array apparatus section and enhancing the flexibility of system construction. The data recording / reproducing apparatus described in Patent Document 1 is a plurality of RAID disk array apparatuses configured in parallel and redundantly by a plurality of HDDs, an input / output interface unit capable of switching between 1 port and 2 ports, and data striping And a striping / ECC unit that sequentially supplies data to a plurality of HDD units and combines data supplied from the plurality of HDD units, and the bit width of data between the striping / ECC unit and the plurality of HDD units. In the 1-port mode, the operation clock frequency is switched to half of the 2-port mode.

  Data stored in the HDD may be subjected to encryption / decryption and compression / decompression processing. When the data processing speed of encryption / decryption and compression / decompression is slower than the transfer speed of the HDD device and the HDD host controller, the data processing speed becomes a bottleneck (impeding factor). There is a problem that the data transfer bandwidth is wasted.

  Further, in the method of changing the operating frequency of the data recording / reproducing apparatus described in Patent Document 1, encryption / decryption and compression / decompression are performed in a configuration with RAID 0 (striping) or a configuration without RAID 0 (striping). When the data processing speed such as decompression becomes a bottleneck, the data transfer bandwidth cannot be used effectively, and there is a problem that wasteful power is consumed.

  The present invention has been made in view of the above, and optimizes the data transfer bandwidth of the HDD host controller even when the data processing speed of encryption / decryption and compression / decompression becomes a bottleneck on the system. It is an object of the present invention to provide a storage medium control apparatus, a storage medium control method, and a program that can reduce power consumption.

  In order to solve the above-described problems and achieve the object, a storage medium control device according to the present invention includes a controller unit that controls writing processing and reading processing of the data to a first storage medium that stores data; A first mode in which an encryption process is performed on the write target data and a decryption process is performed on the encrypted read target data; and a second mode in which the encryption process is not performed on the write target data and the decryption process is not performed on the read target data. An encryption / decryption unit having a mode, a third mode in which compression processing is performed on the write target data, and decompression processing is performed on the compressed read target data, and compression processing and decompression processing are performed on the write target data. A compression / decompression unit having a fourth mode not implemented, a combination of the first mode and the third mode, the first mode and the first mode; Compare the processing speed for each mode combination of the mode, the combination of the second mode and the third mode, the combination of the second mode and the fourth mode, An operating mode control unit that sets the operating frequency for operating the controller unit in accordance with the processing speed of the mode, and a frequency for switching the operating frequency by selecting the operating frequency corresponding to the current combination of the modes And a switching unit.

  According to the present invention, even when the data processing speed of encryption / decryption and compression / decompression becomes a bottleneck on the system, the data transfer bandwidth of the HDD host controller can be optimized to reduce power consumption. , Has the advantageous effect of.

FIG. 1 is a diagram illustrating an example of a functional configuration of the storage medium control apparatus according to the present embodiment. FIG. 2 is a diagram illustrating an example of the relationship between the supply clock signal and the data transfer rate in the RAID 0 control unit. FIG. 3 is a diagram illustrating an example of a relationship between a supply clock signal and a data transfer rate in the DMAC. FIG. 4 shows, for each combination of each mode with or without striping processing, each mode with or without encryption processing and decryption processing, and each mode with or without compression processing and decompression processing. It is a figure which shows an example of the relationship of the data processing speed of this process. FIG. 5 is a diagram illustrating an example of the striping processing area and the single processing area. FIG. 6 is a diagram illustrating an example of detection of an HDD connected to the storage medium control device. FIG. 7 is a flowchart showing an example of the processing operation of the storage medium control apparatus according to this embodiment.

  DESCRIPTION OF EMBODIMENTS Hereinafter, an embodiment of a storage medium control device, a storage medium control method, and a program according to the present invention will be described in detail with reference to the accompanying drawings.

  The storage medium control apparatus according to the present embodiment includes a first mode in which encryption processing is performed on write target data and decryption processing is performed on the encrypted read target data, and encryption processing and read target is performed on the write target data. A second mode in which no decryption processing is performed on the data, a third mode in which compression processing is performed on the write target data, and decompression processing is performed on the compressed read target data, and the compression processing and read target data are performed on the write target data. Compare the processing speed of each process for each combination of the fourth mode in which no decompression processing is performed, the striping processing operation mode, and the single processing operation mode, and match the processing speed of the slowest mode. Operating frequency for operating DMAC (Direct Memory Access Controller) clk1 is set lower than. As a result, the storage medium control device reduces the data transfer speed between the DMAC and the memory, and even when the data processing speed of encryption / decryption and compression / decompression becomes a bottleneck on the system, The data transfer band of the HDD host controller (DMAC) can be optimized to reduce power consumption. The DMAC corresponds to a “controller section” in the claims.

  Hereinafter, as an example of the storage medium control device of the present embodiment, an example will be described in which the present invention is applied to a memory system in which one data is divided into two or more hard disk drives and simultaneously written and read. The type of the memory system to which the present invention is applied is arbitrary.

  FIG. 1 is a diagram illustrating an example of a functional configuration of the storage medium control apparatus according to the present embodiment. As shown in FIG. 1, the storage medium control apparatus 100 of the present embodiment includes an HDD_A1, an HDD_B2, a SATA control unit A3, a SATA control unit B4, a RAID0 control unit 5, an encryption / decryption unit 6, and a compression. / Expander 7, DMAC (Direct Memory Access Controller) 8, operation mode control unit 9, bus switch 10, memory 11, CPU 12, and frequency selector 13. Hereinafter, when it is not necessary to distinguish between HDD_A1 and HDD_B2, they are simply referred to as HDDs. In the following, the DMAC 8 corresponds to an HDD host controller.

  In the present embodiment, HDD_A1, HDD_B2, bus switch 10, memory 11, and CPU 12 are configured by hardware modules, and memory 11, CPU 12, SATA control unit A3, SATA control unit B4, The RAID0 control unit 5, the encryption / decryption unit 6, the compression / decompression unit 7, the DMAC 8, the operation mode control unit 9, and the frequency selector 13 are partially or entirely software (program), hardware It may be a circuit. Further, a form in which a part of each of the above units is mounted on the storage medium control apparatus 100 may be employed.

  The HDD_A1 and HDD_B2 are hard disk drives compliant with, for example, the SATA (Serial Advanced Technology Attachment) standard for storing various programs, data, and the like in a distributed manner. Note that the interface is not limited to SATA, and PCI Express, eMMC (embedded MMC), UFS (Universal Flash Storage), USB (Universal Serial Bus), and the like can be applied. HDD_A1 and HDD_B2 correspond to “second storage medium” in the claims.

  When configuring RAID 0 (striping), HDD_A1 and HDD_B2 use devices of the same type. Further, when the HDD_A1 and the HDD_B2 are used independently without configuring the RAID0, any device can be connected instead of the same type. Also, only one of HDD_A1 or HDD_B2 can be connected. In the present embodiment, it is assumed that the maximum data transfer rate of HDD_A1 and HDD_B2 is, for example, 300 MByte / s.

  The SATA control unit A3 has a function of executing data reading (reading) / writing (writing) under the control of the RAID0 control unit 5. Specifically, for example, according to a command issued by the RAID0 control unit 5, a control command is issued to the HDD_A1, and data reading / writing is executed. The SATA control unit A3 transmits the data read from the HDD_A1 to the RAID0 control unit 5 when reading the data. The SATA control unit A3 writes the data received from the RAID0 control unit 5 to the HDD_A1 when writing data. In the present embodiment, it is assumed that the maximum data transfer rate between the SATA control unit A3 and the HDD_A1 is, for example, 300 MByte / s. The data transfer rate between the SATA control unit A3 and the RAID0 control unit 5 is controlled by a clock signal (clock frequency) 14 supplied from the frequency selector 13 to the RAID0 control unit 5, and the maximum data transfer rate is For example, assume 300 MByte / s.

  The SATA control unit B4 has a function of executing data reading (reading) / writing (writing) under the control of the RAID0 control unit 5. Specifically, for example, according to a command issued by the RAID0 control unit 5, a control command is issued to the HDD_B2, and data reading / writing is executed. The SATA control unit B4 transmits the data read from the HDD_B2 to the RAID0 control unit 5 when reading the data. The SATA control unit B4 writes the data received from the RAID0 control unit 5 to the HDD_B2 when writing data. In the present embodiment, it is assumed that the maximum data transfer rate between the SATA control unit B4 and the HDD_B2 is, for example, 300 MByte / s. The data transfer rate between the SATA control unit B4 and the RAID0 control unit 5 is controlled by a clock signal (clock frequency) 14 supplied from the frequency selector 13 to the RAID0 control unit 5, and the maximum data transfer rate is For example, assume 300 MByte / s.

  The SATA control units A3 and B4 receive the command (write command or read command) transmitted from the RAID0 control unit 5. The SATA control units A3 and B4 perform encoding processing of information added to the received write command (information subject to write control by the SATA control units A3 and B4). In this example, the SATA control units A3 and B4 use redundant information (data bit even / oddity) for performing bit error correction processing (ECC processing) on information to be written to HDD_A1 and HDD_B2. (Referred to as parity). The SATA control units A3 and B4 perform error correction processing (ECC processing) on information read from the HDD_A1 and HDD_B2.

  SATA controllers A3 and B4 write information to HDD_A1 and HDD_B2 in accordance with the received write command. More specifically, the SATA controllers A3 and B4 write the information encoded by the SATA controllers A3 and B4 in the area indicated by the physical address added to the write command in the HDD_A1 and HDD_B2. The SATA control units A3 and B4 read information from the HDD_A1 and the HDD_B2 in accordance with the received read command. More specifically, the SATA control units A3 and B4 read out information stored in the area indicated by the physical address added to the read command in HDD_A1 and HDD_B2. The information read by the SATA control units A3 and B4 is decoded by error correction processing, and the decoded information is sent to the RAID0 control unit 5 as a response to the read command.

  The RAID0 control unit 5 generates a SATA control command for executing read (read) / write (write) to the HDD storage area designated by the operation mode control unit 9, and sends it to the SATA control unit A3 and the SATA control unit B4. Send a command. The RAID 0 control unit 5 divides data into one or more storage media (HDDs) and simultaneously writes and reads data in a RAID 0 (striping) processing operation mode, and data is not divided into one storage medium (HDD). A single processing operation mode for executing writing and reading. Hereinafter, the RAID 0 (striping) processing operation mode is referred to as “striping processing operation mode”. Note that switching between the operation mode of the striping processing operation mode and the single processing operation mode is performed, for example, under the control of the operation mode control unit 9 described later.

  When writing to the HDD in the striping processing operation mode, the RAID0 control unit 5 divides the data received from the encryption / decryption device 6 into data stored in the HDD_A1 and data stored in the HDD_B2, and each of the divided data is divided. , SATA control unit A3 and SATA control unit B4. Further, when reading from the HDD in the striping processing operation mode, the RAID0 control unit 5 integrates the data read from the HDD_A1 and the HDD_B2, and transmits the integrated data to the encryption / decryption device 6.

  When writing to the HDD in the single processing operation mode, the RAID0 control unit 5 transmits the data received from the encryption / decryption device 6 to the HDD_A1 or HDD_B2. When reading from the HDD in the single processing operation mode, the RAID0 control unit 5 transmits the data read from the HDD_A1 or HDD_B2 to the encryption / decryption device 6. Note that selection of which of HDD_A1 and HDD_B2 is to be accessed is made, for example, under the control of the operation mode control unit 9 described later.

  The RAID0 control unit 5 can accept a write request for requesting data write to the HDD_A1 and HDD_B2 and a read request for requesting data read from the HDD_A1 and HDD_B2 from the CPU 12 or the operation mode control unit 9. For example, the write request includes information that requests execution of writing, data that requests writing, and a logical address that indicates a location where data that requests writing is allocated among virtual space addresses on the program. Is done. On the other hand, the read request includes information requesting execution of reading and a logical address indicating a location to which data requesting reading is allocated among virtual space addresses on the program. The logical address is specified by the CPU 12 or the operation mode control unit 9.

  When receiving a write request, the RAID0 control unit 5 writes information including data requested to be written (data included in the write request, hereinafter sometimes referred to as “write target data”) to the HDD_A1 and the HDD_B2. Control (hereinafter sometimes referred to as “write control”) is performed. In the present embodiment, the RAID 0 control unit 5 generates a write command instructing execution of writing, and in response to the generated write command, information including data to be written (information to be subjected to write control), HDD_A1, and In the HDD_B2, a physical address indicating an area in which the write target data is written is added and transmitted to the SATA control unit A3 and the SATA control unit B4.

  When the RAID 0 control unit 5 receives the read request, the RAID 0 control unit 5 refers to the logical-physical conversion table, specifies the physical address associated with the logical address included in the read request (performs logical-physical conversion), and specifies the specified physical Control is performed to read information stored at the position indicated by the address. In the present embodiment, the RAID0 control unit 5 generates a read command that instructs the SATA control units A3 and B4 to execute reading, and the physical command obtained by the above-described logical-physical conversion is generated for the generated read command. The address is added and transmitted to the SATA control unit A3 and the SATA control unit B4. Then, the RAID0 control unit 5 can receive information read from the HDD_A1 and the HDD_B2 by the SATA control unit A3 and the SATA control unit B4 as a response to the read command.

  The maximum data transfer rate of the RAID 0 controller 5 is controlled by, for example, a clock signal 14 supplied from a frequency selector 13 described later. Here, with reference to FIG. 2, an example of the data transfer rate between the encryption / decryption device 6-RAID 0 control unit 5 and between the RAID 0 control unit 5 -SATA control units A 3 and B 4 will be described for each supply clock signal 14. . FIG. 2 is a diagram illustrating an example of the relationship between the supply clock signal and the data transfer rate in the RAID 0 control unit.

  As shown in FIG. 2, as an example of the clock signal 14 supplied from the frequency selector 13, for example, four types of clk1, clk1 / 2, clk1 / 3, and clk1 / 4 will be described. The supplied clock signal 14 indicates an operating frequency for operating the RAID 0 control unit 5. Hereinafter, the supplied clock signal 14 is referred to as a “supply clock signal”. The frequency of clk1 is arbitrarily set.

  First, when the supply clock signal 14 is clk1, the maximum data transfer rate between the encryption / decryption device 6 and the RAID0 control unit 5 is, for example, 600 MByte / s, and the RAID0 control unit 5 and the SATA control unit A3 Is assumed to be 300 MByte / s, for example, and the maximum data transfer rate between the RAID 0 control unit 5 and the SATA control unit B4 is assumed to be 300 MByte / s, for example. When the supply clock signal 14 is clk1 / 2, the maximum data transfer rate between the encryption / decryption device 6 and the RAID0 control unit 5 is, for example, 300 MByte / s, and the RAID0 control unit 5 and the SATA control unit A3 The maximum data transfer rate between them is, for example, 150 MByte / s, and the maximum data transfer rate between the RAID0 control unit 5 and the SATA control unit B4 is, for example, 150 MByte / s.

  When the supply clock signal 14 is clk1 / 3, the maximum data transfer rate between the encryption / decryption device 6 and the RAID0 control unit 5 is, for example, 200 MByte / s, and the RAID0 control unit 5 and the SATA control unit A3 The maximum data transfer rate between them is, for example, 100 MByte / s, and the maximum data transfer rate between the RAID0 control unit 5 and the SATA control unit B4 is, for example, 100 MByte / s. When the supply clock signal 14 is clk1 / 4, the maximum data transfer rate between the encryption / decryption device 6 and the RAID0 control unit 5 is, for example, 150 MByte / s, and the RAID0 control unit 5 and the SATA control unit A3 The maximum data transfer rate between them is, for example, 75 MByte / s, and the maximum data transfer rate between the RAID0 control unit 5 and the SATA control unit B4 is 75 MByte / s. Thus, the supply clock signal 14 having a plurality of frequencies is, for example, in-phase multiplied.

  Returning to FIG. 1, the description will be continued. The encryption / decryption device 6 includes an encryption mode for encrypting write target data, a decryption mode for decrypting encrypted read target data, and a through mode for relaying data transfer without any processing. It has. The encryption / decryption unit 6 performs a first mode in which encryption processing is performed on write target data and decryption processing is performed on encrypted read target data, and encryption processing is performed on the write target data and decryption is performed on the read target data. A second mode in which the conversion processing is not performed. In addition, switching of each operation mode shall be performed by control of the operation mode control part 9 mentioned later, for example.

  In the encryption mode, the encryption / decryption unit 6 encrypts the write target data received from the compression / decompression unit 7 and transmits it to the RAID 0 control unit 5. In the decryption mode, the encryption / decryption device 6 decrypts the encrypted read target data received from the RAID 0 control unit 5 and transmits it to the compression / decompression device 7. In the through mode, the encryption / decryption device 6 relays data transmission / reception between the compression / decompression device 7 and the RAID 0 control unit 5 without performing encryption / decryption processing.

  In the present embodiment, it is assumed that the encryption / decryption device 6 always operates with the above-described clk1 and the data processing speed of encryption / decryption is, for example, 200 MByte / s. Further, it is assumed that the maximum data transfer rate in the through mode is, for example, 600 MByte / s. The encryption / decryption device 6 corresponds to an “encryption / decryption unit” in the claims.

  The compression / decompression unit 7 includes a compression mode for compressing write target data, a decompression mode for decompressing compressed read target data, and a through mode for relaying data transfer without performing any processing. The compression / decompression unit 7 does not perform the compression process on the write target data and the decompression process on the compressed read target data, and does not perform the compression process on the write target data and the decompression process on the read target data. It has a fourth mode. In addition, switching of each operation mode shall be performed by control of the operation mode control part 9 mentioned later, for example.

  In the compression mode, the compressor / decompressor 7 compresses the write target data received from the DMAC 8 and transmits it to the encryption / decryption device 6. In the decompression mode, the compressor / decompressor 7 decompresses the compressed read target data received from the encryption / decryptor 6 and transmits it to the DMAC 8. In the through mode, the compression / decompression unit 7 relays data transmission / reception between the DMAC 8 and the encryption / decryption unit 6 without performing compression / decompression processing. In this embodiment, it is assumed that the compressor / decompressor 7 always operates with the above-described clk1, and the data processing speed of compression / decompression is, for example, 133 MByte / s. Further, it is assumed that the maximum data transfer rate in the through mode is, for example, 600 MByte / s. The compressor / expander 7 corresponds to the “compression / decompression unit” in the claims.

  The DMAC 8 is a direct memory access controller and controls data transfer processing. Specifically, the DMAC 8 controls data write processing and data read processing to the first storage medium (memory 11, such as RAM). The DMAC 8 accesses the memory 11 via the bus switch 10. Specifically, for example, when the DMAC 8 writes data to the HDD, the DMAC 8 reads the write target data from the memory 11 and transmits it to the compressor / decompressor 7. Further, when reading data from the HDD, the DMAC 8 writes the read target data received from the compressor / decompressor 7 into the memory 11. In the present embodiment, the access area of the memory 11 is specified by, for example, control of the operation mode control unit 9 described later.

  The DMAC 8 controls the data transfer speed with the memory 11. Specifically, the DMAC 8 controls communication in the DMA transfer in which the memory 11 performs data transfer without using the CPU 12. That is, the DMAC 8 performs data transfer directly between the HDD_A 1 and B 2 and the memory 11 without going through the CPU 12. The maximum data transfer rate between the DMAC 8 and the memory 11 is controlled by the supply clock signal 14 supplied from the frequency selector 13. The DMAC 8 corresponds to a “controller unit” in the claims.

  Here, an example of the data transfer rate between the DMAC 8 and the memory 11 will be described for each supply clock signal 14 with reference to FIG. FIG. 3 is a diagram illustrating an example of a relationship between a supply clock signal and a data transfer rate in the DMAC. As shown in FIG. 3, as an example of the supply clock signal 14 having a plurality of frequencies supplied from the frequency selector 13, for example, four types of clk1, clk1 / 2, clk1 / 3, and clk1 / 4 will be described. The supply clock signal 14 indicates an operating frequency for operating the DMAC 8. The frequency of clk1 is arbitrarily set.

  First, when the supply clock signal 14 is clk1, it is assumed that the maximum data transfer rate between the DMAC 8 and the memory 11 is, for example, 600 MByte / s. When the supply clock signal 14 is clk1 / 2, the data transfer rate between the DMAC 8 and the memory 11 is, for example, 300 MByte / s. When the supply clock signal 14 is clk1 / 3, the data transfer rate between the DMAC 8 and the memory 11 is, for example, 200 MByte / s. When the supply clock signal 14 is clk1 / 4, the data transfer rate between the DMAC 8 and the memory 11 is 150 MByte / s. Thus, the supply clock signals 14 having a plurality of frequencies are in-phase multiplied.

  The DMAC 8 can accept a write request for requesting data write to the memory 11 and a read request for requesting data read from the memory 11 from the CPU 12 or the operation mode control unit 9. For example, the write request includes information that requests execution of writing, data that requests writing, and a logical address that indicates a location where data that requests writing is allocated among virtual space addresses on the program. Is done. On the other hand, the read request includes information requesting execution of reading and a logical address indicating a location to which data requesting reading is allocated among virtual space addresses on the program. The logical address is specified by the CPU 12 or the operation mode control unit 9.

  When the DMAC 8 receives a write request, the DMAC 8 performs control to write information including data requested to be written (data included in the write request, hereinafter sometimes referred to as “data to be written”) into the memory 11. In the present embodiment, the DMAC 8 generates a write command instructing execution of writing, and in response to the generated write command, information including data to be written (information to be subjected to write control) and the memory 11 A physical address indicating an area in which data to be written is written is added and transmitted to the memory 11.

  When the DMAC 8 receives a read request, the DMAC 8 refers to the logical-physical conversion table to identify a physical address associated with the logical address included in the read request (performs logical-physical conversion), and the identified physical address indicates Control to read the information stored in the position. In this embodiment, the DMAC 8 generates a read command instructing execution of reading, adds the physical address obtained by the above-described logical-physical conversion to the generated read command, and transmits the read command to the memory 11. The DMAC 8 can receive information read from the memory 11 as a response to the read command.

  Returning to FIG. 1, the description will be continued. The operation mode control unit 9 includes a control unit 21, a processing operation mode switching unit 22, a striping region determination unit 23, and a detection unit 24. In the present embodiment, the control unit 21, the processing operation mode switching unit 22, the detection unit 24, and the striping region determination unit 23 provide the function of the operation mode control unit 9.

  The control unit 21 controls each operation mode of the RAID 0 control unit 5, the encryption / decryption unit 6, the compression / decompression unit 7, the DMAC 8, and the frequency selector 13. Further, the control unit 21 sets each operation mode of the compressor / decompressor 7, the encryption / decryptor 6, and the RAID 0 control unit 5 according to the operation mode set by the CPU 12, or controls switching of each operation mode. Further, the control unit 21 sets each operation mode of the compression / decompression unit 7, the encryption / decryption unit 6, and the RAID0 control unit 5 according to the operation mode set by the CPU 12, and for each combination of each operation mode, The data processing speed of the processing is compared, and the supply clock signal 14 output from the frequency selector 13 is set in accordance with the slowest processing speed. Specifically, the control unit 21 performs a first mode in which an encryption process is performed on the write target data and a decryption process is performed on the encrypted read target data, and an encryption process and a read target are performed on the write target data. A second mode in which no decryption processing is performed on the data, a third mode in which compression processing is performed on the write target data, and decompression processing is performed on the compressed read target data, and the compression processing and read target data are performed on the write target data. The data processing speed of each process is compared for each combination of the fourth mode in which no decompression processing is performed, the striping processing operation mode, and the single processing operation mode, and the data processing speed of the slowest mode is obtained. In addition, the operating frequency for operating the DMAC (controller unit) 8 is set lower than clk1, and the DMAC8 Reducing the data transfer rate between the memory 11. That is, the control unit 21 includes a combination of the striping process operation mode, the first mode, and the third mode, a combination of the striping process operation mode, the first mode, and the fourth mode, and the striping process operation mode, the second mode, and the third mode. Combination, combination of striping operation mode, second mode and fourth mode, combination of single processing operation mode, first mode and third mode, combination of single processing operation mode, first mode and fourth mode, single processing operation The processing speed of each process is compared for each mode combination of the mode, the second mode, and the third mode, and the combination of the single processing operation mode, the second mode, and the fourth mode. The operating frequency for operating the controller unit is set low in accordance with the processing speed.

  In addition, the control unit 21 performs a first mode in which an encryption process is performed on the write target data and a decryption process is performed on the encrypted read target data, and the write process data is encrypted and decrypted in the read target data. The second mode in which the data conversion process is not performed, the third mode in which the compression process is performed on the write target data, and the decompression process is performed on the compressed read target data, and the compression process and the decompression process are performed on the write target data. For each combination of modes in the fourth mode that does not perform the operation, the data processing speed of each processing is compared, and the operating frequency at which the DMAC (controller unit) 8 is operated in accordance with the data processing speed of the slower mode Is set lower than clk1 to reduce the data transfer rate between the DMAC 8 and the memory 11. That is, the control unit 21 is configured to select each mode of the first mode and the third mode, the first mode and the fourth mode, the second mode and the third mode, and the second mode and the fourth mode. For each combination, the processing speeds of the respective processes are compared, and the operating frequency for operating the controller unit is set low in accordance with the processing speed of the slower mode.

  Here, with reference to FIG. 3 and FIG. 4, a setting method of the supply clock signal 14 output from the frequency selector 13 in the control unit 21 of the operation mode control unit 9 will be described. FIG. 4 shows, for each combination of each mode with or without striping processing, each mode with or without encryption processing and decryption processing, and each mode with or without compression processing and decompression processing. It is a figure which shows an example of the information which linked | related the data processing speed of this process. The control unit 21 holds in advance information relating the data processing speed of each process for each combination of modes set by the CPU 12 shown in the example of FIG. The data processing speed of each process can be arbitrarily set in advance.

  As shown in the example of FIG. 4, the data processing speed of the striping process “present” is 600 MByte / s, the data processing speed of the encryption / decryption process “present” is 200 MByte / s, and the compression / decompression process is “present”. The data processing speed is a combination of 133 MByte / s. The data processing speed of the striping process “present” is 600 Mbyte / s, the data processing speed of the encryption / decryption process “present” is 200 Mbyte / s, and the data processing speed of the compression / decompression process “absent” is 600 MByte. / S combination. The data processing speed of the striping process “present” is 600 MByte / s, the data processing speed of the encryption / decryption process “absent” is 600 Mbyte / s, and the data processing speed of the compression / decompression process “present” is 133 MByte. / S combination. The data processing speed of the striping process “present” is 600 MByte / s, the data processing speed of the encryption / decryption process “None” is 600 MByte / s, and the data processing speed of the compression / decompression process “None” is 600 MByte. / S combination.

  In the example of FIG. 4, the data processing speed of the striping process “none” is 300 MByte / s, the data processing speed of the encryption / decryption process “present” is 200 Mbyte / s, and the compression / decompression process is “present”. The data processing speed is a combination of 133 MByte / s. In addition, the data processing speed of the striping process “none” is 300 MByte / s, the data processing speed of the encryption / decryption process “present” is 200 Mbyte / s, and the data processing speed of the compression / decompression process “none” is 600 MByte. / S combination. Further, the data processing speed of the striping process “none” is 300 Mbyte / s, the data processing speed of the encryption / decryption process “none” is 600 Mbyte / s, and the data processing speed of the compression / decompression process “present” is 133 Mbytes. / S combination. Further, the data processing speed of the striping process “none” is 300 MByte / s, the data processing speed of the encryption / decryption process “none” is 600 Mbyte / s, and the data processing speed of the compression / decompression process “none” is 600 MByte. / S combination.

  Therefore, for example, the controller 21 uses the information relating the data processing speed of each process for each combination of modes shown in the example of FIG. 4, and the RAID 0 controller 5 is in the striping process operation mode. When the encryption / decryption device 6 is in the through mode (no processing) and the compression / decompression device 7 is a combination of the through mode (no processing), it is determined that the slowest data processing speed is 600 MByte / s. 3, clk <b> 1 is set as the supply clock signal 14 output from the frequency selector 13.

  Further, the control unit 21 uses the information relating the data processing speed of each process for each combination of modes shown in the example of FIG. 4, so that the RAID 0 control unit 5 uses the single processing operation mode (no striping process). When the encryption / decryption device 6 is in the through mode (no processing) and the compression / decompression device 7 is a combination of the through mode (no processing), it is determined that the slowest data processing speed is 300 MByte / s. Then, referring to FIG. 3, clk1 / 2 is set as the supply clock signal 14 output from the frequency selector 13.

  Further, the control unit 21 uses the information relating the data processing speed of each process for each combination of the modes shown in the example of FIG. 4, so that the RAID 0 control unit 5 performs the striping processing operation mode or the single processing operation mode. When the encryption / decryption device 6 is in the encryption mode (with processing) or the decryption mode (with processing) and the compression / decompression device 7 is a combination of the through mode (no processing), the slowest data processing speed Is determined to be 200 MByte / s, and with reference to FIG. 3, clk1 / 3 is set as the supply clock signal 14 output from the frequency selector 13.

  The control unit 21 uses the information relating the data processing speed of each process for each mode combination shown in the example of FIG. In the mode (with processing), it is determined that the slowest data processing speed is 133 MByte / s regardless of the combination of the operation mode of the RAID 0 control unit 5 and the encryption / decryption unit 6, and see FIG. Then, clk1 / 4 is set as the supply clock signal 14 output from the frequency selector 13.

  Further, the controller 21 uses the information relating the data processing speed of each process for each combination of modes shown in the example of FIG. 4, and the encryption / decryption device 6 is in the through mode (no processing). When the compressor / decompressor 7 is a combination of the through mode (no processing), the slower data processing speed is determined to be 600 MByte / s, and the supply output by the frequency selector 13 with reference to FIG. As the clock signal 14, clk1 is set.

  The control unit 21 uses the information relating the data processing speed of each process for each combination of modes shown in the example of FIG. When the decoding mode (with processing) and the compressor / decompressor 7 is a combination of the through mode (without processing), the slower data processing speed is determined to be 200 MByte / s, and referring to FIG. As the supply clock signal 14 output from the frequency selector 13, clk1 / 3 is set.

  The control unit 21 uses the information relating the data processing speed of each process for each mode combination shown in the example of FIG. In the case of the mode (with processing), it is determined that the slower data processing speed is 133 Mbyte / s regardless of the combination of the operation modes of the encryption / decryption device 6, and referring to FIG. As the supply clock signal 14 output by 13, clk1 / 4 is set.

  That is, in the case of a combination of modes in which neither compression / decompression processing nor encryption / decryption processing is performed in the striping processing operation mode, the control unit 21 sets the data processing speed to 600 MByte / s and sets clk1. To do. Further, in the case where the compression / decompression process is not performed in the striping process operation mode and the combination of the modes in which the encryption / decryption process is performed, the control unit 21 has a data processing speed of 200 MByte / s, Set clk1 / 3. In addition, in the striping processing operation mode, the control unit 21 performs the compression / decompression processing regardless of the combination of the modes for whether or not the encryption / decryption processing is performed, and the data processing speed is 133 MByte / s and clk1 / 4 is set.

  In the case of a combination of modes in which the compression / decompression process and the encryption / decryption process are not performed in the single processing operation mode, the control unit 21 has a data processing speed of 300 MByte / s, and clk1 / 2 Set. In addition, in the case where the compression / decompression process is not performed in the single processing operation mode and the combination of the modes in which the encryption / decryption process is performed, the control unit 21 has a data processing speed of 200 MByte / s, Set clk1 / 3. Further, when the compression / decompression process is performed in the single processing mode, the control unit 21 has a data processing speed of 133 Mbyte / s regardless of the combination of the modes with or without the encryption / decryption process. , Clk1 / 4 is set.

  In this way, the control unit 21 includes each mode of presence / absence of striping processing, each mode of presence / absence of execution of encryption processing and decryption processing, and each mode of presence / absence of execution of compression processing and decompression processing. For each combination, the data processing speeds of the respective processes are compared, and the operating frequency for operating the DMAC (controller unit) 8 is set lower than an arbitrary clk1 in accordance with the data processing speed of the slowest mode. And the data transfer speed between the memory 11 are reduced.

  In addition, the control unit 21 determines the data processing speed of each process for each combination of each mode for performing the encryption process and the decryption process and each mode for performing the compression process and the decompression process. The operation frequency for operating the DMAC (controller unit) 8 is set lower than an arbitrary clk1 in accordance with the data processing speed of the slower mode, and the data transfer speed between the DMAC 8 and the memory 11 is set. Reduce.

  As a result, even when the data processing speed of encryption / decryption and compression / decompression becomes a bottleneck on the system, the data transfer bandwidth of the HDD host controller can be optimized to reduce power consumption. The frequency of clk1 is arbitrarily set.

  Further, the control unit 21 performs control by designating an access area (logical address) of the memory 11 when the DMAC 8 writes data to and reads data from the memory 11.

  In addition, the control unit 21 controls which of the HDD_A1 and the HDD_B2 is accessed when the RAID0 control unit 5 writes / reads data to / from the HDD in the single processing operation mode.

  Returning to FIG. 1, the description will be continued. The processing operation mode switching unit 22 divides data into a striping processing operation mode in which data is simultaneously written to and read from one or more second storage media (HDD), and one second storage medium (without dividing data). Control to switch between single processing operation modes for executing writing and reading to the HDD). The processing operation mode switching unit 22 generates a control command and transmits the command to the RAID0 control unit 5 when switching between the striping processing operation mode and the single processing operation mode.

  The processing operation mode switching unit 22 switches to the striping processing operation mode when the striping region determination unit 23 described later determines that it is a striping processing region from the address information when accessing the storage region of the storage medium (HDD). Switch. Further, the processing operation mode switching unit 22 enters the single processing operation mode when the striping region determination unit 23 described later determines that it is a single processing region from the address information when accessing the storage region of the storage medium (HDD). Switch.

  Further, the processing operation mode switching unit 22 switches to the single processing operation mode when there is only one storage medium (HDD) detected by the detection unit 24 described later. The processing operation mode switching unit 22 switches to the striping processing operation mode when there are a plurality of storage media (HDDs) detected by the detection unit 24 described later.

  When accessing the storage area of the storage medium (HDD), the striping area determination unit 23 determines whether the storage area of the storage medium (HDD) to be accessed for writing and reading data is a striping processing area. judge. First, the operation mode control unit 9 sets the storage area of the storage medium (HDD) separately into a striping process area and a single process area using address information for accessing the storage area of the storage medium (HDD) in advance. Keep it. When the striping area determination unit 23 accesses the storage area of the storage medium (HDD), whether the storage area of the storage medium (HDD) for writing and reading data from the address information is the striping process area. Determine whether or not. Therefore, when the storage area of the storage medium (HDD) is used by mixing the striping process area and the single process area, the processing operation mode of the RAID 0 control unit 5 is determined from the address information for accessing the storage medium (HDD). Can be set automatically. That is, the processing operation mode of the RAID 0 control unit 5 can be automatically set using address information for accessing the storage medium (HDD) without the intervention of the CPU 12.

  FIG. 5 is a diagram illustrating an example of the striping processing area and the single processing area. As shown in the example of FIG. 5, in HDD_A1, addresses 0x0000_0000 to 0x8000_0000 are set as the striping processing area (data storage area) 31 and addresses 0x8000_0000 to 0xC000_0000 are set as the single processing area (program storage area) 41. Is shown.

  In HDD_B2, addresses 0x0000_0000 to 0x8000_0000 are set as a striping processing area (data storage area) 32, addresses 0x8000_0000 to 0xC000_0000 are set as free areas, and addresses 0xC000_0000 to 0xZ000_0000 are set as a single processing area (program storage area) 42. Indicates that it has been set.

  The striping processing areas 31 and 32 are data storage areas for dividing and storing data in HDD_A1 and HDD_B2. The single processing areas 41 and 42 are program storage areas for storing data in only one HDD_A1 or HDD_B2. In this way, for example, the data storage areas 31 and 32 that are frequently accessed are used as the striping processing areas, and the program storage areas such as the OS are used as the single processing areas 41 and 42, thereby balancing the storage capacity and the access speed. be able to.

  Returning to FIG. 1, the description will be continued. The detection unit 24 detects one or more second storage media (HDD) connected to the storage medium control device 100. FIG. 6 is a diagram illustrating an example of detection of an HDD connected to the storage medium control device. As shown in the example of FIG. 6, the GND terminals of the HDD_Ach1 and HDD_Bch2 connection connectors and the input signals (detect_a, detect_b) to the detection unit 24 of the operation mode control unit 9 are connected, and this input signal path is pulled up. By detecting the connection, the HDD connection is detected. That is, when the HDD is connected, detect_a and detect_b are at the low level, and when the HDD is not connected, detect_a and detect_b are at the high level. Further, when either one of detect_a and detect_b is at a high level and the other is at a low level, RAID 0 (striping) that requires two or more HDDs is not configured. Therefore, when only one HDD (second storage medium) is detected by the detection unit 24, the processing operation mode switching unit 22 of the operation mode control unit 9 sets the operation mode of the RAID 0 control unit 5 to the single processing mode. By setting, software control by the CPU 12 can be simplified.

  Returning to FIG. 1, the description will be continued. The bus switch 10 is a switch that performs high-speed switching or disconnection of a bus line. The bus line electrically connects the above-described components as shown in FIG. Examples of the bus line include an address bus and a data bus. The bus switch 10 is connected to the DMAC 8 and the memory 11 via the MEM-IF. The bus switch 10 is connected to the operation mode control unit 9 and the CPU 12 via the CPU-IF. That is, the bus switch 10 switches the bus line among the DMAC 8, the operation mode control unit 9, the memory 11, and the CPU 12.

  The memory 11 is a storage medium and stores a program for the storage medium control device 100. The memory 11 stores various data. The memory 11 is also used as a work area for the CPU 12. That is, the memory 11 has a function of ROM (Read Only Memory) and RAM (Random Access Memory). The memory 11 corresponds to “first storage medium” in the claims.

  A CPU (Central Processing Unit) 12 controls the operation of the entire storage medium control device 100. For example, the CPU 12 causes the data to be read from the memory 11, distributes the data evenly between the HDD_A 1 and the HDD_B 2, and simultaneously writes or reads the target data to each HDD.

  The frequency selector 13 supplies a supply clock signal (clk1) 14 to the compressor / decompressor 7 and the encryption / decryptor 6. In addition, the frequency selector 13 is configured so that the operation mode control unit 9 determines whether the encryption process and the decryption process are performed, whether the compression process and the decompression process are performed, and the striping process operation mode. , And using the operating frequency (supply clock signal 14) set for each combination of the single processing operation mode, the operation frequency corresponding to the current combination of each mode is selected, and a supply clock having a plurality of frequencies is selected. The supply clock signal 14 to be supplied to the DMAC 8 and the RAID 0 controller 5 is switched from among the signals 14. As described above, the supply clock signal 14 can be selected from, for example, four types of clk1, clk1 / 2, clk1 / 3, and clk1 / 4. The frequency of clk1 / 2 is half of clk1, the frequency of clk1 / 3 is one third of clk1, and the frequency of clk1 / 4 is one quarter of clk1. That is, in the above example, the supply clock signals 14 having a plurality of frequencies have an in-phase multiplication relationship. The frequency of clk1 is arbitrarily set. The frequency selector 13 corresponds to a “frequency switching unit” in the claims.

  Note that the above-described program for the storage medium control device 100 may be recorded and distributed in a computer-readable recording medium such as a storage medium in an installable or executable format file.

  Next, processing operations in the storage medium control apparatus 100 according to the present embodiment will be described with reference to FIG. FIG. 7 is a flowchart showing an example of the processing operation of the storage medium control apparatus according to this embodiment.

  Upon receiving a data write / read request from the CPU 12, the operation mode control unit 9 of the storage medium control device 100 receives a write / read request including data to be written / read and a physical address / logical address indicating an area to be written. Is transmitted to the DMAC 8 and the RAID 0 controller 5 (step S1). Next, the operation mode control unit 9 determines whether or not the RAID0 control unit 5 is in the striping processing operation mode (step S2). When the operation mode is the striping processing operation mode (step S2: Yes), the operation mode control unit 9 determines whether or not the compression / decompression unit 7 is in the compression processing and expansion processing mode (step S3). If the compression / decompression processing mode is not set (step S3: No), the operation mode control unit 9 determines whether the encryption / decryption device 6 is in the encryption processing and decryption processing modes (step S4). . When it is not the encryption process and the decryption process mode (step S4: No), the operation mode control unit 9 determines that the slowest data processing speed is 600 MByte / s (step S5), and operates the operation frequency (supply clock signal). 14) is set to clk1 (step S6). Next, the process proceeds to step S19.

  Returning to step S2, if the operation mode is not the striping processing operation mode (step S2: No), the operation mode control unit 9 determines whether or not the compression / decompression unit 7 is in the compression processing and expansion processing mode (step S7). . If the compression / decompression processing mode is not set (step S7: No), the operation mode control unit 9 determines whether the encryption / decryption device 6 is in the encryption processing and decryption processing modes (step S8). . When the mode is not the encryption process or the decryption process mode (step S8: No), the operation mode control unit 9 determines that the slowest data processing speed is 300 MByte / s (step S9), and sets the operation frequency to clk1 / 2. (Step S10). Next, the process proceeds to step S19.

  Returning to step S3, when the compression processing and decompression processing modes are set (step S3: Yes), the operation mode control unit 9 determines that the slowest data processing speed is 133 MByte / s (step S11), and the operation frequency. Is set to clk1 / 4 (step S12). Next, the process proceeds to step S19.

  Returning to step S4, when it is in the encryption process and the decryption process mode (step S4: Yes), the operation mode control unit 9 determines that the slowest data processing speed is 200 MByte / s (step S13). The operating frequency is set to clk1 / 3 (step S14). Next, the process proceeds to step S19.

  Returning to step S7, if the compression processing and decompression processing modes are set (step S7: Yes), the operation mode control unit 9 determines that the slowest data processing speed is 133 MByte / s (step S15), and the operation frequency. Is set to clk1 / 4 (step S16). Next, the process proceeds to step S19.

  Returning to step S8, when it is the encryption processing and decryption processing mode (step S8: Yes), the operation mode control unit 9 determines that the slowest data processing speed is 200 MByte / s (step S17), The operating frequency is set to clk1 / 3 (step S18). Next, the process proceeds to step S19.

  Next, the processing operation mode switching unit 22 of the operation mode control unit 9 proceeds to step S19, and each of the step S6, step S10, step S12, step S14, step S16, and step S18 corresponding to each mode combination is performed. The operating frequency (supply clock signal 14) set in the step is selected, and the frequency selector 13 switches the operating frequency (step S19). Next, the compression / decompression unit 7, the encryption / decryption unit 6, and the RAID 0 control unit 5 of the storage medium control apparatus 100 execute each process based on the setting of the processing mode of each mode set by the CPU 12 (step S20). ). Next, for example, the DMAC 8 writes / reads data to / from the memory 11 at the switched operating frequency (supply clock signal 14). Further, for example, the SATA control units A3 and B4 write / read data to / from the HDD_A1 and B2 (step S21). Then, the process ends.

  In this manner, the storage medium control apparatus 100 according to the present embodiment is caused to perform the processing operation described above. As a result, the storage medium control apparatus 100 according to the present embodiment has each mode of whether or not to perform encryption processing and decryption processing, each mode of whether or not to perform compression processing and decompression processing, and a striping processing operation mode. For each combination of the single processing operation mode and each mode, the processing speed of each processing is compared, and the operating frequency for operating the DMAC (controller unit) 8 is lower than clk1 in accordance with the processing speed of the slowest mode. The data transfer speed between the DMAC 8 and the memory 11 is reduced by setting.

  In addition, the storage medium control device 100 according to the present embodiment has each mode for each combination of whether or not the encryption process and the decryption process are performed and each mode of whether or not the compression process and the decompression process are performed. Compared with the processing speed of the processing, the operating frequency for operating the DMAC (controller unit) 8 is set lower than clk1 in accordance with the processing speed of the slower mode, and data transfer between the DMAC 8 and the memory 11 is performed. Reduce speed.

  Therefore, according to the storage medium control apparatus 100 of this embodiment, even when the data processing speed of encryption / decryption and compression / decompression becomes a bottleneck on the system, the data transfer bandwidth of the HDD host controller (DMAC 8) Can be optimized to reduce power consumption.

  As mentioned above, although embodiment of this invention was described, each above-mentioned embodiment was shown as an example and is not intending limiting the range of invention. The present invention is not limited to the above-described embodiments as they are, and can be embodied by modifying the components without departing from the scope of the invention in the implementation stage. Further, various inventions can be formed by appropriately combining a plurality of constituent elements disclosed in the above-described embodiments. For example, some components may be deleted from all the components shown in the embodiment. Further, the above embodiments and modifications can be arbitrarily combined.

  The control program executed by the storage medium control device 100 of each of the embodiments described above is a file in an installable format or an executable format, and is a CD-ROM, a flexible disk (FD), a CD-R, a DVD (Digital The recording medium may be recorded on a computer-readable recording medium such as Versatile Disk).

  Further, the control program executed by the storage medium control device 100 of each of the above embodiments is stored on a computer connected to a network such as the Internet and provided by being downloaded via the network. Also good. Further, the control program executed by the storage medium control device 100 of each of the above-described embodiments may be configured to be provided or distributed via a network such as the Internet.

1 HDD_A
2 HDD_B
3 SATA control part A
4 SATA control part B
5 RAID0 control unit 6 Encryption / decryption unit 7 Compression / decompression unit 8 DMAC
9 Operation mode control unit 10 Bus switch 11 Memory 12 CPU
13 Frequency selector 14 Supply clock signal 21 Control unit 22 Processing operation mode switching unit 23 Striping region determination unit 24 Detection units 31 and 32 Striping processing region (data storage region)
41, 42 Single processing area (program storage area)

JP 2000-231455 A

Claims (9)

A controller for controlling the writing process and the reading process of the data to the first storage medium for storing data;
A first mode in which an encryption process is performed on the write target data and a decryption process is performed on the encrypted read target data; and a second mode in which the encryption process is not performed on the write target data and the decryption process is not performed on the read target data. An encryption / decryption unit having a mode;
A compression / compression mode having a third mode in which compression processing is performed on write target data and decompression processing is performed on compressed read target data, and a fourth mode in which compression processing is performed on the write target data and decompression processing is not performed on read target data. An extension,
Each of the combination of the first mode and the third mode, the combination of the first mode and the fourth mode, the combination of the second mode and the third mode, the combination of the second mode and the fourth mode For each combination of modes, an operation mode control unit that compares the processing speed of each process and sets the operating frequency for operating the controller unit in accordance with the processing speed of the slower mode;
A frequency switching unit that selects the operating frequency corresponding to the current combination of the modes and switches the operating frequency; and
A storage medium control device. One or more second storage media for storing data;
A striping processing operation mode in which the data is divided and simultaneously written and read on one or more second storage media, and the data is written and read on one second storage medium without being divided. A processing operation mode switching unit that switches between the single processing operation mode,
The operation mode control unit includes a combination of the striping process operation mode, the first mode, and the third mode, a combination of the striping process operation mode, the first mode, and the fourth mode, the striping process operation mode, and the A combination of the second mode and the third mode, a combination of the striping processing operation mode, the second mode and the fourth mode, a combination of the single processing operation mode, the first mode and the third mode, and the single processing. Combination of operation mode, first mode, and fourth mode, combination of single processing operation mode, second mode, and third mode, combination of single processing operation mode, second mode, and fourth mode For each combination of modes, compare the processing speed of each processing, the processing speed of the slowest mode Together storage medium control apparatus according to claim 1, characterized in that setting a low operating frequency for operating the controller. A detection unit that detects one or more second storage media connected to the storage medium control device;
The storage medium control device according to claim 2, wherein the processing operation mode switching unit switches to the single processing operation mode when only one second storage medium is detected by the detection unit. A striping area determination unit that determines whether a storage area of the second storage medium to be accessed for writing and reading the data is a striping process area;
The operation mode control unit sets the storage area of the second storage medium into a striping process area and a single process area by using address information for accessing the storage area of the second storage medium in advance.
The striping area determination unit determines whether or not the striping process area is based on the address information when accessing the storage area of the second storage medium,
In the case of the striping processing area, the processing operation mode switching unit switches to the striping processing operation mode.
The storage medium control device according to claim 2.   The storage medium control device according to claim 1, wherein the frequency switching unit selects the clock signal to be supplied to the controller unit from a plurality of clock signals having a plurality of frequencies, and switches the operating frequency.   6. The storage medium control apparatus according to claim 5, wherein the clock signals having a plurality of frequencies have an in-phase multiplication relationship.   3. The storage medium control device according to claim 2, wherein the one or more second storage media are the same type of hard disk drive. A controller step for controlling the writing process and the reading process of the data to the first storage medium for storing data;
A first mode in which an encryption process is performed on the write target data and a decryption process is performed on the encrypted read target data; and a second mode in which the encryption process is not performed on the write target data and the decryption process is not performed on the read target data. An encryption / decryption step having a mode;
A compression / compression mode having a third mode in which compression processing is performed on write target data and decompression processing is performed on compressed read target data, and a fourth mode in which compression processing is performed on the write target data and decompression processing is not performed on read target data. Stretching step;
Each of the combination of the first mode and the third mode, the combination of the first mode and the fourth mode, the combination of the second mode and the third mode, the combination of the second mode and the fourth mode An operation mode control step that compares the processing speed of each process for each mode combination, and sets the operating frequency for operating the controller step to match the processing speed of the slower mode;
A frequency switching step of selecting the operating frequency corresponding to the current combination of the modes and switching the operating frequency,
And a storage medium control method. In the storage medium control device,
A controller step for controlling the writing process and the reading process of the data to the first storage medium for storing data;
A first mode in which an encryption process is performed on the write target data and a decryption process is performed on the encrypted read target data; and a second mode in which the encryption process is not performed on the write target data and the decryption process is not performed on the read target data. An encryption / decryption step having a mode;
A compression / compression mode having a third mode in which compression processing is performed on write target data and decompression processing is performed on compressed read target data, and a fourth mode in which compression processing is performed on the write target data and decompression processing is not performed on read target data. Stretching step;
Each of the combination of the first mode and the third mode, the combination of the first mode and the fourth mode, the combination of the second mode and the third mode, the combination of the second mode and the fourth mode An operation mode control step that compares the processing speed of each process for each mode combination, and sets the operating frequency for operating the controller step to match the processing speed of the slower mode;
A frequency switching step of selecting the operating frequency corresponding to the current combination of the modes and switching the operating frequency;
A program for running

Images