JP6245904B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP6245904B2 JP6245904B2 JP2013186841A JP2013186841A JP6245904B2 JP 6245904 B2 JP6245904 B2 JP 6245904B2 JP 2013186841 A JP2013186841 A JP 2013186841A JP 2013186841 A JP2013186841 A JP 2013186841A JP 6245904 B2 JP6245904 B2 JP 6245904B2
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- Prior art keywords
- layer
- oxide
- film
- oxide semiconductor
- electrode layer
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- FHNFHKCVQCLJFQ-UHFFFAOYSA-N xenon atom Chemical compound [Xe] FHNFHKCVQCLJFQ-UHFFFAOYSA-N 0.000 description 1
- NAWDYIZEMPQZHO-UHFFFAOYSA-N ytterbium Chemical compound [Yb] NAWDYIZEMPQZHO-UHFFFAOYSA-N 0.000 description 1
- 229910001928 zirconium oxide Inorganic materials 0.000 description 1
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- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
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- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
Description
本実施の形態では、本発明の一態様の半導体装置について図面を用いて詳細に説明する。図1に本発明の一態様の半導体装置を示す。図1(B)は本発明の一態様の半導体装置の上面図を示し、図1(A)は図1(B)の一点鎖線A−Bにおける断面図を示す。
本実施の形態では、実施の形態1とは異なる半導体装置について説明する。なお、実施の形態1と同様の箇所については、同様の符号を付し、詳細な説明を省略する。図6に本実施の形態の半導体装置を示す。図6(B)は本実施の形態の半導体装置の上面図を示し、図6(A)は図6(B)に示す一点鎖線C−Dにおける断面図である。
半導体装置の一例として、論理回路であるNOR型回路の回路図の一例を図11(A)に示す。図11(B)はNAND型回路の回路図である。
本実施の形態では、実施の形態1及び実施の形態2に示すトランジスタを使用し、電力が供給されない状況でも記憶内容の保持が可能で、かつ、書き込み回数にも制限が無い半導体装置(記憶装置)の一例を、図面を用いて説明する。
本実施の形態では、先の実施の形態で示した半導体装置を携帯電話、スマートフォン、電子書籍などの電子機器に応用した場合の例を図13乃至図16を用いて説明する。
251 メモリセルアレイ
251a メモリセルアレイ
251b メモリセルアレイ
253 周辺回路
254 容量素子
260 トランジスタ
262 トランジスタ
264 容量素子
400 基板
402 下地絶縁層
404a 第1の酸化物層
404b 酸化物半導体層
404c 第2の酸化物層
405 酸化物膜
406a ソース電極層
406b ドレイン電極層
407 ゲート絶縁膜
408 ゲート絶縁層
410 ゲート電極層
411 絶縁膜
412 酸化物絶縁層
413 側壁絶縁層
414 絶縁層
416a ソース電極層
416b ドレイン電極層
418a ソース電極層
418b ドレイン電極層
420 トランジスタ
430 トランジスタ
440 トランジスタ
450 トランジスタ
460 トランジスタ
470 トランジスタ
520 トランジスタ
530 トランジスタ
540 トランジスタ
550 トランジスタ
560 トランジスタ
570 トランジスタ
801 トランジスタ
802 トランジスタ
803 トランジスタ
804 トランジスタ
812 トランジスタ
813 トランジスタ
901 RF回路
902 アナログベースバンド回路
903 デジタルベースバンド回路
904 バッテリー
905 電源回路
906 アプリケーションプロセッサ
907 CPU
908 DSP
910 フラッシュメモリ
911 ディスプレイコントローラ
912 メモリ回路
913 ディスプレイ
914 表示部
915 ソースドライバ
916 ゲートドライバ
917 音声回路
918 キーボード
919 タッチセンサ
950 メモリ回路
951 メモリコントローラ
952 メモリ
953 メモリ
954 スイッチ
955 スイッチ
956 ディスプレイコントローラ
957 ディスプレイ
1001 バッテリー
1002 電源回路
1003 マイクロプロセッサ
1004 フラッシュメモリ
1005 音声回路
1006 キーボード
1007 メモリ回路
1008 タッチパネル
1009 ディスプレイ
1010 ディスプレイコントローラ
9033 留め具
9034 スイッチ
9035 電源スイッチ
9036 スイッチ
9038 操作スイッチ
9630 筐体
9631a 表示部
9631b 表示部
9632a 領域
9632b 領域
9633 太陽電池
9634 充放電制御回路
9635 バッテリー
9636 DCDCコンバータ
9638 操作キー
9639 ボタン
Claims (3)
- 第1の酸化物層と、
前記第1の酸化物層上の酸化物半導体層と、
前記酸化物半導体層上に接するソース電極層及びドレイン電極層と、
前記酸化物半導体層上、前記ソース電極層上及び前記ドレイン電極層上の第2の酸化物層と、
前記第2の酸化物層上の絶縁層と、
前記絶縁層上のゲート電極層と、
前記ゲート電極層上の酸化物絶縁層と、を有し、
前記第1の酸化物層は、インジウム、亜鉛及びガリウムを有し、
前記酸化物半導体層は、インジウム、亜鉛及びガリウムを有し、
前記第2の酸化物層は、インジウム、亜鉛及びガリウムを有し、
前記第2の酸化物層の対向する一対の側面のうち、一方の側面は前記ソース電極層の上面と重なり、他方の側面は前記ドレイン電極層の上面と重なり、
前記絶縁層の対向する一対の側面のうち、一方の側面は前記ソース電極層の上面と重なり、他方の側面は前記ドレイン電極層の上面と重なる半導体装置。 - 請求項1において、
前記酸化物半導体層は、前記第1の酸化物層及び前記第2の酸化物層よりも電子親和力が0.2eV以上大きい半導体装置。 - 請求項1または請求項2において、
前記酸化物半導体層のインジウム、亜鉛、及びガリウムの原子数比は、前記第1の酸化物層及び前記第2の酸化物層の原子数比とは異なり、
前記酸化物半導体層は、前記第1の酸化物層及び前記第2の酸化物層よりも高い原子数比でインジウムを有する半導体装置。
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US20140027762A1 (en) * | 2012-07-27 | 2014-01-30 | Semiconductor Energy Laboratory Co. Ltd. | Semiconductor device |
JP6283191B2 (ja) | 2012-10-17 | 2018-02-21 | 株式会社半導体エネルギー研究所 | 半導体装置 |
JP6320009B2 (ja) | 2012-12-03 | 2018-05-09 | 株式会社半導体エネルギー研究所 | 半導体装置及びその作製方法 |
KR102207028B1 (ko) | 2012-12-03 | 2021-01-22 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | 반도체 장치 |
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JP6329762B2 (ja) | 2012-12-28 | 2018-05-23 | 株式会社半導体エネルギー研究所 | 半導体装置 |
US9190527B2 (en) | 2013-02-13 | 2015-11-17 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and manufacturing method of semiconductor device |
TWI620324B (zh) | 2013-04-12 | 2018-04-01 | 半導體能源研究所股份有限公司 | 半導體裝置 |
US9893192B2 (en) | 2013-04-24 | 2018-02-13 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
DE102014208859B4 (de) | 2013-05-20 | 2021-03-11 | Semiconductor Energy Laboratory Co., Ltd. | Halbleitervorrichtung |
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JP6435124B2 (ja) | 2013-07-08 | 2018-12-05 | 株式会社半導体エネルギー研究所 | 半導体装置の作製方法 |
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