JP6237045B2 - Imaging device and imaging apparatus - Google Patents

Description

  The present invention relates to an imaging element and an imaging apparatus.

In an imaging device having a plurality of pixels, a configuration is known in which an AD converter is arranged for each pixel (see, for example, Patent Document 1 and FIG. 2).
Patent Document 1 Japanese Patent No. 4928674

  The above-described imaging device acquires an image for each frame having a different exposure time. Then, by combining the images of each frame, the dynamic range of the AD converter is widened. For this reason, in order to increase the resolution of the AD converter, the number of frames must be increased. However, high resolution is difficult because image data must be stored for each frame.

  The first aspect of the present invention includes a plurality of photoelectric conversion units that generate charges according to incident light, and individual processing units provided for each photoelectric conversion unit, and each individual processing unit corresponds to A detection unit that detects that the accumulated amount of charge generated by the photoelectric conversion unit exceeds a predetermined threshold value, a reset unit that resets the accumulated amount when the accumulated amount exceeds a predetermined threshold value, Provided is an imaging device having a counting unit that counts the number of times that an accumulated amount exceeds a prescribed threshold within a prescribed period.

  According to a second aspect of the present invention, there is provided an imaging apparatus including the imaging element according to the first aspect.

  It should be noted that the above summary of the invention does not enumerate all the necessary features of the present invention. In addition, a sub-combination of these feature groups can also be an invention.

1 is a diagram illustrating an outline of an image sensor 100 according to an embodiment of the present invention. 3 is a block diagram illustrating a configuration example of an individual processing unit 212. FIG. FIG. 3 is a diagram illustrating an operation example of an individual processing unit 212 illustrated in FIG. 2. 12 is a block diagram illustrating another configuration example of the individual processing unit 212. FIG. 1 is a diagram illustrating an example of a cross section of an image sensor 100. FIG. 3 is a diagram illustrating a circuit configuration example of an individual processing unit 212. FIG. 7 is a diagram illustrating another circuit configuration example of an individual processing unit 212. FIG. 7 is a diagram illustrating another circuit configuration example of an individual processing unit 212. FIG. It is a figure which shows the operation example of the separate process part 212 shown in FIG. 7 is a diagram illustrating another circuit configuration example of an individual processing unit 212. FIG. 7 is a diagram illustrating another circuit configuration example of an individual processing unit 212. FIG. 7 is a diagram illustrating another circuit configuration example of an individual processing unit 212. FIG. It is a block diagram which shows the structural example of the imaging device 500 which concerns on embodiment of this invention.

  Hereinafter, the present invention will be described through embodiments of the invention, but the following embodiments do not limit the invention according to the claims. In addition, not all the combinations of features described in the embodiments are essential for the solving means of the invention.

  FIG. 1 is a diagram showing an overview of an image sensor 100 according to an embodiment of the present invention. The image sensor 100 generates image data corresponding to incident light from a subject. The image sensor 100 includes a light receiving unit 200 and a signal processing unit 210.

  The light receiving unit 200 includes a plurality of photoelectric conversion units 202. The plurality of photoelectric conversion units 202 in this example are arranged along the matrix direction. Each photoelectric conversion unit 202 generates an electric charge according to incident light from a subject. The photoelectric conversion unit 202 includes a photoelectric conversion element such as a photodiode.

  The signal processing unit 210 generates a pixel signal corresponding to the amount of charge generated by each photoelectric conversion unit 202. The signal processing unit 210 includes a plurality of individual processing units 212. The individual processing unit 212 is provided for each photoelectric conversion unit 202.

  Each individual processing unit 212 generates a digital pixel signal corresponding to the amount of charge generated by the corresponding photoelectric conversion unit 202. The plurality of individual processing units 212 may read analog charge amounts generated by the plurality of photoelectric conversion units 202 in parallel. Thereby, a global shutter can be realized. Note that it is preferable that at least a part of the components of the individual processing unit 212 is arranged in a layer different from the photoelectric conversion unit 202 in order to increase the area of the conversion region that converts incident light into electric charges.

  FIG. 2 is a block diagram illustrating a configuration example of the individual processing unit 212. The individual processing unit 212 of this example includes a detection unit 214, a reset unit 216, a counting unit 218, and a memory 220. When the photoelectric conversion unit 202 receives incident light, charges are generated according to the incident light. The charges generated by the photoelectric conversion unit 202 are accumulated in the photoelectric conversion unit 202 and the like.

  The detection unit 214 detects that the charge accumulation amount in the corresponding photoelectric conversion unit 202 exceeds a predetermined threshold value. The detection unit 214 in this example receives an accumulation voltage Vin indicating the amount of charge accumulated in the corresponding photoelectric conversion unit 202 and a threshold voltage Vth corresponding to the specified threshold. When the accumulated voltage Vin is smaller than the threshold voltage Vth, the detection unit 214 in this example determines that the amount of accumulated charge has exceeded a specified threshold and outputs a detection signal.

  The reset unit 216 resets the charge accumulation amount in the corresponding photoelectric conversion unit 202 when the charge accumulation amount in the corresponding photoelectric conversion unit 202 exceeds the specified threshold. When the detection signal is input from the detection unit 214, the reset unit 216 of this example resets the amount of accumulated charge in the corresponding photoelectric conversion unit 202. For example, the reset unit 216 resets the amount of accumulated charge by connecting a region in which the charge generated by the corresponding photoelectric conversion unit 202 is accumulated to a reference potential. Even after resetting, the amount of stored charge increases again due to the charge generated by the photoelectric conversion unit 202. That is, the charge accumulation amount is repeatedly increased and reset.

  The counting unit 218 counts the number of times that the accumulated amount of charge in the corresponding photoelectric conversion unit 202 exceeds the specified threshold within a predetermined specified period. The counting unit 218 of this example counts the number of times the detection signal is input from the detection unit 214. The counting unit 218 causes the memory 220 to store information on the count value at the time when the specified period ends as a pixel signal of the corresponding photoelectric conversion unit 202. One memory 220 may be provided for a plurality of individual processing units 212.

  FIG. 3 is a diagram illustrating an operation example of the individual processing unit 212 illustrated in FIG. 2. In FIG. 3, the horizontal axis indicates time, and the vertical axis indicates the intensity of the accumulated voltage Vin. In this example, the accumulated voltage Vin decreases as the accumulated charge amount increases.

  When light enters the corresponding photoelectric conversion unit 202, charge accumulation starts (t = 0). While the photoelectric conversion unit 202 receives incident light, the accumulated voltage Vin decreases with a slope corresponding to the intensity of the incident light. When the accumulated voltage Vin becomes equal to or lower than the threshold voltage Vth (t = T1), the detection unit 214 outputs a detection signal.

  The reset unit 216 resets the charge accumulation amount in the corresponding photoelectric conversion unit 202 according to the detection signal. Thereby, the accumulated voltage Vin returns to a predetermined initial voltage. The counting unit 218 increments the count value according to the detection signal.

  When a predetermined time elapses after the reset by the reset unit 216, the accumulated voltage Vin becomes the predetermined reset voltage Vrst. Then, the accumulated voltage Vin decreases again according to the intensity of incident light in the photoelectric conversion unit 202. When the accumulated voltage Vin becomes equal to or lower than the threshold voltage Vth, the detection unit 214 outputs a detection signal. Such an operation is repeated from the start of charge accumulation until a predetermined time period elapses (t = 0 to Tm). At the time when a predetermined specified period has elapsed (t = Tm), the counting unit 218 stores the count value in the memory 220. The counter 218 also resets the count value to prepare for the generation of the next pixel signal.

  With such an operation, the individual processing unit 212 can generate a pixel signal (a count value in this example) corresponding to the amount of charge generated by the corresponding photoelectric conversion unit 202 within a specified period. In addition, since the individual processing unit 212 can be realized with a simple configuration of the detection unit 214, the reset unit 216, and the counting unit 218, the individual processing unit 212 can be easily provided for each photoelectric conversion unit 202.

  Moreover, the sensitivity of the image sensor 100 can be controlled by changing the threshold voltage Vth. For example, when the difference between the threshold voltage Vth and the reset voltage Vrst is reduced, a pixel signal can be generated with high accuracy with respect to incident light having a low intensity. Further, if the difference between the threshold voltage Vth and the reset voltage Vrst is increased, overflow in the counting unit 218 can be prevented, and a pixel signal can be generated with high accuracy for incident light having a high intensity.

  The sensitivity of the image sensor 100 can also be controlled by changing the specified period. Increasing the specified period improves the accuracy for low-intensity incident light, and shortening the specified period improves the accuracy for strong-intensity incident light. Thus, the image sensor 100 of this example can easily control the sensitivity, and can easily generate a pixel signal that reproduces the intensity of incident light with high resolution.

  Further, even for a subject such as flicker having a sharp luminance change, image data in which the luminance change is averaged can be acquired. In addition, noise generated in the photoelectric conversion unit 202 and the like can be averaged.

  The counting unit 218 may store the count value in the memory 220 when the count value reaches a predetermined value within the specified period, reset the count value, and restart counting from the initial value. . The memory 220 may store the sum total of the count values received from the counting unit 218 within the specified period. Thereby, it is possible to avoid the count value of the counting unit 218 from overflowing. For this reason, the scale of the counting unit 218 can be reduced.

  The amount of incident light within the specified period corresponds to a value obtained by multiplying the difference between the threshold voltage Vth and the reset voltage Vrst by a count value. The memory 220 may store the multiplication value, and may store the count value and the voltage difference in association with each other. Moreover, it can convert into the incident light quantity per unit time by dividing the incident light quantity in a regulation period by the length of a regulation period. The memory 220 may further store the length of the specified period, and may store the amount of incident light per unit time. If the reset voltage Vrst is known, the threshold voltage Vth may be stored instead of the voltage difference.

  FIG. 4 is a block diagram illustrating another configuration example of the individual processing unit 212. The individual processing unit 212 of this example further includes a threshold control unit 222 and a period control unit 224 in addition to the configuration of the individual processing unit 212 shown in FIG.

  The threshold control unit 222 controls a specified threshold (a threshold voltage Vth in this example) in the corresponding detection unit 214 in accordance with the characteristics of incident light. The characteristic of incident light is, for example, the intensity of incident light. The intensity of incident light may be the intensity of incident light with respect to the corresponding photoelectric conversion unit 202, or may be the average of the intensity of incident light with respect to the plurality of photoelectric conversion units 202. The threshold control unit 222 may calculate the intensity of incident light with respect to the corresponding photoelectric conversion unit 202 based on the slope of the change in the corresponding accumulated voltage Vin.

  The threshold controller 222 may decrease the difference between the threshold voltage Vth and the reset voltage Vrst as the intensity of the incident light is smaller. That is, the threshold controller 222 may increase the difference between the threshold voltage Vth and the reset voltage Vrst as the incident light intensity increases. By such control, the sensitivity of the image sensor 100 can be controlled in accordance with the characteristics of incident light. Further, the sensitivity can be controlled for each pixel including the photoelectric conversion unit 202 and the individual processing unit 212. For this reason, even when the difference in the intensity of incident light is large on the light receiving surface, the sensitivity of each pixel can be appropriately controlled.

  The threshold control unit 222 may divide the plurality of photoelectric conversion units 202 into a plurality of blocks and control the threshold voltage Vth independently for each block. In this case, the threshold control unit 222 controls the threshold voltage Vth in the block using the average value of the intensity of incident light with respect to the photoelectric conversion unit 202 in the block.

  In this case, one threshold control unit 222 may be provided for each block. Further, the range of each block may be variable. For example, the threshold control unit 222 divides the plurality of photoelectric conversion units 202 into a plurality of blocks along the edge of the subject image. The edge of an image refers to an area where the difference (contrast) in pixel signal strength between adjacent pixels is equal to or greater than a predetermined value.

  The period control unit 224 controls the specified period in each counting unit 218 according to the characteristics of the incident light. However, the specified period is preferably the same in all the individual processing units 212. That is, it is preferable that the period control unit 224 controls the specified period in the entire signal processing unit 210 based on the average value of the intensity of incident light in all the photoelectric conversion units 202.

  The period control unit 224 may lengthen the specified period as the intensity of incident light is smaller. That is, the period control unit 224 may shorten the specified period as the incident light intensity increases. By such control, the sensitivity of the image sensor 100 can be controlled in accordance with the characteristics of incident light.

  FIG. 5 is a diagram illustrating an example of a cross section of the image sensor 100. In this example, the back-illuminated image sensor 100 is shown, but the image sensor 100 is not limited to the back-illuminated image sensor. The imaging device 100 of this example includes an imaging chip 113 that outputs a signal corresponding to incident light, a signal processing chip 111 that processes a signal from the imaging chip 113, and a memory that stores image data processed by the signal processing chip 111. Chip 112. The imaging chip 113, the signal processing chip 111, and the memory chip 112 are stacked, and are electrically connected to each other by a conductive bump 109 such as Cu.

  Note that the imaging chip 113 is provided with a plurality of photoelectric conversion units 202. The signal processing chip 111 is provided with at least part of the configuration of the signal processing unit 210. For example, the signal processing chip 111 is provided with a counting unit 218 in each individual processing unit 212. The memory 220 may be provided in the memory chip 112 or may be provided in the signal processing chip 111.

  As shown in the figure, incident light is incident mainly in the direction indicated by the white arrow. In the present embodiment, in the imaging chip 113, the surface on the side where incident light is incident is referred to as a back surface. An example of the imaging chip 113 is a back-illuminated MOS image sensor. The imaging chip 113 corresponds to the light receiving unit 200. The PD (photodiode) layer 106 is disposed on the back side of the wiring layer 108. The PD layer 106 includes a plurality of PD sections 104 that are two-dimensionally arranged and accumulate charges corresponding to incident light, and transistors 105 that are provided corresponding to the PD sections 104. The PD unit 104 is an example of the photoelectric conversion unit 202.

  A color filter 102 is provided on the incident side of incident light in the PD layer 106 via a passivation film 103. The color filter 102 has a plurality of types that transmit different wavelength regions, and has a specific arrangement corresponding to each of the PD units 104. The arrangement of the color filter 102 will be described later. A set of the color filter 102, the PD unit 104, and the plurality of transistors 105 is included in one pixel. By controlling on / off of the plurality of transistors 105, the light reception start timing (reset timing) of each pixel is controlled.

  On the incident light incident side of the color filter 102, a microlens 101 is provided corresponding to each pixel. The microlens 101 condenses incident light toward the corresponding PD unit 104.

  The wiring layer 108 includes a wiring 107 that transmits a signal from the PD layer 106 to the signal processing chip 111. The wiring 107 may be multilayer, and a passive element and an active element may be provided.

  A plurality of bumps 109 are disposed on the surface of the wiring layer 108. The plurality of bumps 109 are aligned with the plurality of bumps 109 provided on the opposing surfaces of the signal processing chip 111, and the imaging chip 113 and the signal processing chip 111 are pressed and aligned. The bumps 109 are joined and electrically connected.

  Similarly, a plurality of bumps 109 are disposed on the mutually facing surfaces of the signal processing chip 111 and the memory chip 112. The bumps 109 are aligned with each other, and the signal processing chip 111 and the memory chip 112 are pressurized, so that the aligned bumps 109 are joined and electrically connected.

  The bonding between the bumps 109 is not limited to Cu bump bonding by solid phase diffusion, and micro bump bonding by solder melting may be employed. Further, about one bump 109 may be provided for one unit block. Therefore, the size of the bump 109 may be larger than the pitch of the PD unit 104. Further, a bump larger than the bump 109 corresponding to the imaging region may be provided in a peripheral region other than the imaging region where the pixels are arranged.

  The signal processing chip 111 has a TSV (silicon through electrode) 110 that connects circuits provided on the front and back surfaces to each other. The TSV 110 is preferably provided in the peripheral area. The TSV 110 may also be provided in the peripheral area of the imaging chip 113 and the memory chip 112.

  FIG. 6 is a diagram illustrating a circuit configuration example of the individual processing unit 212. The photoelectric conversion unit 202 is also shown. The individual processing unit 212 of this example includes a detection unit 214, a reset unit 216, a counting unit 218, and a memory 220.

  The detection unit 214 of this example has a CMOS inverter. The CMOS inverter has a PMOS transistor 232 and an NMOS transistor 234. The input terminal of the CMOS inverter is connected to the output terminal of the photoelectric conversion unit 202. The charge generated by the photoelectric conversion unit 202 is accumulated in a parasitic capacitance or the like between the photoelectric conversion unit 202 and the detection unit 214. A stored voltage Vin corresponding to the stored charge is input to the CMOS inverter.

  The output of the CMOS inverter starts from the first logic value (L logic in this example) when the accumulated voltage Vin becomes smaller than the threshold voltage of the CMOS inverter (that is, when the amount of accumulated charge exceeds a specified threshold). Transition to two logic values (H logic in this example). An edge at which the output of the detection unit 214 transitions from L logic to H logic functions as the detection signal described above. Further, the threshold voltage of the CMOS inverter corresponds to the threshold voltage Vth described above.

  The reset unit 216 includes a reset transistor 230. The reset transistor 230 has a source and a drain provided between the output terminal of the photoelectric conversion unit 202 and a predetermined high-voltage side reference potential. The gate of the reset transistor 230 is connected to the output terminal of the CMOS inverter. The reset transistor 230 connects the wiring between the photoelectric conversion unit 202 and the detection unit 214 to the high-voltage side reference potential when the output of the CMOS inverter transitions from L logic to H logic. As a result, the accumulated charge is reset, and the output of the detection unit 214 transitions to the L logic.

  The counting unit 218 counts the number of times the output of the detection unit 214 has transitioned from L logic to H logic within a specified period. The counting unit 218 stores the count value at the time when the specified period ends in the memory 220. With such a configuration, the individual processing unit 212 can be realized with a small circuit scale.

  As in this example, when the output of the photoelectric conversion unit 202 is directly connected to the input terminal of the CMOS inverter of the detection unit 214, the detection unit 214 is preferably provided in the imaging chip 113. Direct connection refers to, for example, a state where there is no element such as a transistor or a buffer that blocks the movement of charges between the output of the photoelectric conversion unit 202 and the input terminal of the CMOS inverter. Thereby, it is possible to prevent the parasitic capacitance between the photoelectric conversion unit 202 and the detection unit 214 from becoming too large. For this reason, it can prevent that the sensitivity of the image sensor 100 falls.

  FIG. 7 is a diagram illustrating another circuit configuration example of the individual processing unit 212. The individual processing unit 212 of this example further includes a threshold control unit 222 in addition to the configuration of the individual processing unit 212 shown in FIG. The threshold control unit 222 includes a threshold control transistor 236 and a threshold control transistor 238 provided for each MOS transistor of the CMOS inverter.

  The threshold control transistors 236 and 238 are connected to the sources of the corresponding PMOS transistor 232 and NMOS transistor 234, respectively, and control the threshold value of the CMOS inverter. The threshold control transistor 236 is a PMOS transistor whose source and drain are connected between the high-voltage side reference potential and the source of the PMOS transistor 232. The threshold control transistor 238 is an NMOS transistor whose source and drain are connected between the low-voltage side reference potential and the source of the NMOS transistor 234.

  A threshold control signal Vth cont is input to the gates of the threshold control transistor 236 and the threshold control transistor 238. With such a configuration, the threshold voltage of the CMOS transistor in the detection unit 214 can be controlled by the threshold control signal Vth cont. As described above, the threshold control unit 222 may generate the threshold control signal Vth cont according to the characteristic value of the incident light.

  Note that the detection unit 214 of this example is preferably provided in the imaging chip 113. The threshold control transistor 236 and the threshold control transistor 238 may be provided in the imaging chip 113 or may be provided in the signal processing chip 111.

  FIG. 8 is a diagram illustrating another circuit configuration example of the individual processing unit 212. The individual processing unit 212 of this example further includes a synchronization circuit 240 in addition to the configuration of any of the individual processing units 212 shown in FIG. 6 or FIG. FIG. 8 illustrates a configuration in which a synchronization circuit 240 is added to the configuration of the individual processing unit 212 illustrated in FIG. 7.

  The synchronization circuit 240 is provided between the output terminal of the detection unit 214 and the gate of the reset transistor 230. The synchronization circuit 240 receives the detection signal output from the detection unit 214 and the synchronization signal. The synchronization signal is input to the synchronization circuit 240 at a predetermined cycle.

  The synchronization circuit 240 causes the reset unit 216 to reset the accumulated amount of electric charges on the condition that the CMOS inverter outputs H logic while receiving the synchronization signal. As a result, the upper limit of the number of times the accumulated amount is reset within the specified period is limited to the number of synchronization signals within the specified period. For this reason, the overflow of the count value in the counting part 218 can be prevented. The number of times that the synchronization signal is input to the synchronization circuit 240 within the specified period may be the same as the upper limit value of the count value in the counting unit 218. The synchronization circuit 240 may be provided in the signal processing chip 111.

  FIG. 9 is a diagram illustrating an operation example of the individual processing unit 212 illustrated in FIG. 8. In the operation of the individual processing unit 212 in this example, the reset unit 216 resets the charge accumulation amount only when the detection unit 214 outputs the H logic and the synchronization signal of the H logic is input to the synchronization circuit 240. Except for this point, the operation is the same as that shown in FIG.

  At t = T1, as in FIG. 3, the output of the detection unit 214 transitions from L logic to H logic. At this time, in the example of FIG. 9, since the H logic synchronization signal is input to the synchronization circuit 240, the accumulated voltage Vin is reset. Also, at t = T2, the output of the detection unit 214 transits from L logic to H logic. However, in the example of FIG. 9, since the H logic synchronization signal is not input to the synchronization circuit 240, t = T2. The accumulated voltage Vin is not reset at the timing. For this reason, the output of the detection unit 214 is maintained at the H logic.

  At the timing of t = T3, an H logic synchronization signal is input. At this time, since the output of the detection unit 214 is H logic, the reset unit 216 resets the accumulated voltage Vin. With such an operation, the counting timing in the counting unit 218 can be controlled by the period of the synchronization signal.

  The image sensor 100 may control the period of the synchronization signal according to a characteristic value such as the intensity of incident light. For example, when the intensity of incident light is smaller, the period of the synchronization signal is made smaller (that is, the number of synchronization signals within the specified period is increased). When the intensity of incident light is larger, the period of the synchronization signal is increased. The sensitivity of the image sensor 100 can also be controlled by such control. The period of the synchronization signal may be controlled independently for each individual processing unit 212. Further, the period of the synchronization signal may be controlled for each block of pixels.

  FIG. 10 is a diagram illustrating another circuit configuration example of the individual processing unit 212. The individual processing unit 212 of this example further includes a source follower circuit 242 and a transistor 244 in addition to the configuration of any of the individual processing units 212 described with reference to FIGS. 10 shows an example in which a source follower circuit 242 and a transistor 244 are added to the configuration of the individual processing unit 212 shown in FIG.

  The source follower circuit 242 is disposed between the output terminal of the photoelectric conversion unit 202 and the input terminal of the CMOS inverter of the detection unit 214. The source follower circuit 242 of this example includes an NMOS transistor in which the output terminal of the photoelectric conversion unit 202 is connected to the gate. The charge generated by the photoelectric conversion unit 202 is accumulated in a parasitic capacitance between the photoelectric conversion unit 202 and the source follower circuit 242. The source follower circuit 242 inputs an accumulated voltage corresponding to the accumulated charge amount to the CMOS inverter.

  The transistor 244 is disposed between the low-voltage side reference potential and the input terminal of the CMOS inverter of the detection unit 214. The transistor 244 switches whether to connect the input terminal of the CMOS inverter to the low-voltage side reference potential according to the control signal cont.

  In this example, the CMOS inverter of the detection unit 214 is provided in the signal processing chip 111. The source follower circuit 242 is provided in the imaging chip 113. The transistor 244 may be provided in the signal processing chip 111. Thereby, the number of transistors provided in the imaging chip 113 can be reduced, and the area of the photoelectric conversion unit 202 can be increased.

  FIG. 11 is a diagram illustrating another circuit configuration example of the individual processing unit 212. The individual processing unit 212 of this example further includes a delay unit 250 and a clamp unit 252 in addition to the configuration of any one of the individual processing units 212 described with reference to FIGS. 11 shows an example in which a delay unit 250 and a clamp unit 252 are added to the configuration of the individual processing unit 212 shown in FIG.

  The delay unit 250 branches and receives a detection signal input from the CMOS inverter of the detection unit 214 to the reset unit 216, and generates a clamp signal obtained by delaying the detection signal. The delay amount in the delay unit 250 corresponds to a period from when the reset unit 216 resets the accumulated voltage Vin until the accumulated voltage Vin becomes smaller than a predetermined reset voltage Vrst. The delay amount may correspond to a period from when the reset unit 216 resets the accumulated voltage Vin until the accumulated voltage Vin becomes the feedthrough voltage.

  The clamp unit 252 clamps the voltage (accumulated voltage Vin) of the signal output from the source follower circuit 242 at the timing of the clamp signal. That is, after the reset unit 216 resets the accumulated voltage Vin, the clamp unit 252 holds the clamp voltage obtained by clamping the accumulated voltage Vin that is lower than the predetermined reset voltage Vrst.

  The clamp unit 252 inputs the difference between the accumulated voltage Vin and the clamp voltage after the clamp signal timing to the CMOS inverter in the detection unit 214. With such an operation, since the stored voltage Vin with reference to the clamp voltage is input to the CMOS inverter, the influence of offset, noise, and the like in the source follower circuit 242 can be reduced.

  The clamp unit 252 of this example includes a clamp capacitor 246 and a clamp transistor 248. The clamp capacitor 246 is provided between the output terminal of the source follower circuit 242 and the input terminal of the CMOS inverter. The clamp transistor 248 connects the electrode of the clamp capacitor 246 on the input terminal side of the CMOS inverter to a predetermined potential PORTBOTH-R when a clamp signal is input to the gate. As a result, the clamp capacitor 246 clamps the voltage of the accumulated voltage Vin at the timing of the clamp signal.

  With such a configuration, it is possible to reduce the influence of noise or the like in each of the waveforms of the accumulated voltage Vin repeated within a specified period. Note that the delay unit 250 and the clamp unit 252 in this example may be provided in the signal processing chip 111. However, the clamp capacitor 246 may be provided in the imaging chip 113.

  FIG. 12 is a diagram illustrating another circuit configuration example of the individual processing unit 212. The individual processing unit 212 of this example further includes a capacity switching unit 254 in addition to the configuration of any of the individual processing units 212 described with reference to FIGS. 12 illustrates an example in which a capacity switching unit 254 is added to the configuration of the individual processing unit 212 illustrated in FIG.

  The capacitance switching unit 254 switches the magnitude of the charge detection capacitance connected to the output terminal of the photoelectric conversion unit 202-1 corresponding to the individual processing unit 212. In this example, the charge detection capacitor is a parasitic capacitor connected to the output terminal of the photoelectric conversion unit 202-1.

  The capacity switching unit 254 of this example switches whether to connect the output terminal of the photoelectric conversion unit 202-1 and the output terminal of another photoelectric conversion unit 202-2 according to the gain control signal Gain Cont. It is. Note that an individual processing unit 212 is provided for each of the photoelectric conversion unit 202-1 and the photoelectric conversion unit 202-2, but in FIG. 12, the individual processing unit 212 corresponding to the photoelectric conversion unit 202-2 is omitted. ing. However, the capacitance switching unit 254 is provided in common to the photoelectric conversion unit 202-1 and the photoelectric conversion unit 202-2.

  When the capacitance switching unit 254 is turned on, a parasitic capacitance for the photoelectric conversion unit 202-2 is also connected to the output terminal of the photoelectric conversion unit 202-1. For this reason, when the capacitance switching unit 254 is turned on, the parasitic capacitance connected to the output terminal of the photoelectric conversion unit 202-1 is twice as large as when the capacitance switching unit 254 is turned off.

  As described above, the capacitance switching unit 254 can switch the magnitude of the parasitic capacitance with respect to the photoelectric conversion unit 202-1, and can switch the gain (that is, sensitivity) of the pixel signal with respect to the incident light amount in the pixel. Note that the capacitance switching unit 254 may variably control the number of other photoelectric conversion units 202 connected to the photoelectric conversion unit 202-1. Thereby, more various gains can be realized.

  FIG. 13 is a block diagram illustrating a configuration example of the imaging apparatus 500 according to the embodiment of the present invention. The imaging apparatus 500 includes a photographic lens 520 as a photographic optical system, and the photographic lens 520 guides a subject luminous flux incident along the optical axis OA to the imaging element 100. The photographing lens 520 may be an interchangeable lens that can be attached to and detached from the imaging apparatus 500. The imaging apparatus 500 mainly includes an imaging device 100, a system control unit 501, a drive unit 502, a photometry unit 503, a work memory 504, a recording unit 505, a display unit 506, and a drive unit 514.

  The photographing lens 520 is composed of a plurality of optical lens groups, and forms an image of a subject light flux from the scene in the vicinity of its focal plane. In FIG. 13, the photographic lens 520 is representatively represented by a single virtual lens arranged in the vicinity of the pupil.

  The driving unit 514 drives the taking lens 520. More specifically, the drive unit 514 moves the optical lens group of the photographing lens 520 to change the focus position. Further, the iris diaphragm in the photographing lens 520 is driven to control the amount of the subject luminous flux incident on the image sensor 100.

  The drive unit 502 is a control circuit that executes charge accumulation control such as timing control and area control of the image sensor 100 in accordance with instructions from the system control unit 501. The driving unit 502 operates the light receiving unit 200 and the signal processing unit 210 of the image sensor 100 as described with reference to FIGS. Further, the operation unit 508 receives an instruction from the photographer through a release button or the like.

  The image sensor 100 is the same as the image sensor 100 described with reference to FIGS. The image sensor 100 delivers the pixel signal to the image processing unit 511 of the system control unit 501. The image processing unit 511 generates image data subjected to various image processes using the work memory 504 as a work space. For example, when generating image data in JPEG file format, a compression process is executed after generating a color video signal from a signal obtained by the Bayer array. The generated image data is recorded in the recording unit 505, converted into a display signal, and displayed on the display unit 506 for a preset time.

  The photometric unit 503 detects the luminance distribution of the scene prior to a series of shooting sequences for generating image data. The photometry unit 503 includes, for example, an AE sensor having about 1 million pixels. The calculation unit 512 of the system control unit 501 receives the output of the photometry unit 503 and calculates the luminance for each area of the scene.

  The calculation unit 512 determines the shutter speed, aperture value, and ISO sensitivity according to the calculated luminance distribution. The light metering unit 503 may be shared by the image sensor 100. Note that the arithmetic unit 512 also executes various arithmetic operations for operating the imaging device 500. A part or all of the drive unit 502 may be mounted on the image sensor 100. A part of the system control unit 501 may be mounted on the image sensor 100.

  As mentioned above, although this invention was demonstrated using embodiment, the technical scope of this invention is not limited to the range as described in the said embodiment. It will be apparent to those skilled in the art that various modifications or improvements can be added to the above-described embodiment. It is apparent from the scope of the claims that the embodiments added with such changes or improvements can be included in the technical scope of the present invention.

  The order of execution of each process such as operations, procedures, steps, and stages in the apparatus, system, program, and method shown in the claims, the description, and the drawings is particularly “before” or “prior to”. It should be noted that the output can be realized in any order unless the output of the previous process is used in the subsequent process. Regarding the operation flow in the claims, the description, and the drawings, even if it is described using “first”, “next”, etc. for convenience, it means that it is essential to carry out in this order. It is not a thing.

  100 Image sensor, 101 Micro lens, 102 Color filter, 103 Passivation film, 104 PD part, 105 Transistor, 106 PD layer, 107 Wiring, 108 Wiring layer, 109 Bump, 110 TSV, 111 Signal processing chip, 112 Memory chip, 113 Imaging chip, 200 light receiving unit, 202 photoelectric conversion unit, 210 signal processing unit, 212 individual processing unit, 214 detection unit, 216 reset unit, 218 counting unit, 220 memory, 222 threshold control unit, 224 period control unit, 230 reset transistor 232 PMOS transistor, 234 NMOS transistor, 236 threshold control transistor, 238 threshold control transistor, 240 synchronization circuit, 242 source follower circuit, 244 transistor, 246 transistor Amplifier, 248 clamp transistor, 250 delay section, 252 clamp section, 254 capacitance switching section, 500 imaging device, 501 system control section, 502 drive section, 503 photometry section, 504 work memory, 505 recording section, 506 display section, 508 Operation unit, 511 image processing unit, 512 calculation unit, 514 drive unit, 520 photographing lens

Claims (13)

A photoelectric conversion unit that photoelectrically converts incident light to generate charges;
A detection unit that outputs a detection signal when the voltage based on the electric charge generated by the photoelectric conversion unit is equal to or higher than a threshold value, having an inverter that receives a voltage based on the electric charge generated by the photoelectric conversion unit;
Based on the detection signal, a reset unit that resets the charge generated by the photoelectric conversion unit,
A counting unit that counts the number of times the charge is reset by the reset unit based on the detection signal;
An output unit that outputs a voltage based on the charge generated by the photoelectric conversion unit, and a source follower circuit disposed between the inverter,
A delay unit that outputs a clamp signal obtained by delaying the detection signal;
A clamp unit that inputs a difference between a clamp voltage obtained by clamping the voltage output from the source follower circuit at a timing when a clamp signal is output from the delay unit and a voltage output by the source follower circuit;
An imaging device comprising: An imaging chip before Symbol photoelectric conversion unit is plurality,
The laminated on the imaging chip, the imaging device according to claim 1, and a signal processing chip provided the counting section. On the basis of the characteristics of the incident light, the imaging device according to claim 1 or 2 comprising a that control section to control the threshold value. The imaging device according to any one of claims 1 to 3, wherein the counting unit counts the number of times that a voltage based on the electric charge generated by the photoelectric conversion unit is equal to or greater than a threshold value within a predetermined period. On the basis of the characteristics of the incident light, the imaging device according to claim 4 to obtain Bei the period control unit that controls between pre SL period before Symbol counter. Said inverter when the voltage based on the electric charges generated by the photoelectric conversion section is equal to or greater than the threshold value, the logic value of the output changes from the first logic value to a second logic value,
When the output of the inverter transitions from the first logic value to the second logic value, the reset unit resets the charge generated by the photoelectric conversion unit ,
The counting unit, the imaging device according to claim 1, any one of 5 to count the number of times the output of the inverter transitions to the second logic value from the first logic value. The reset section, source and drain, the provided between the output and the criteria potential of the photoelectric conversion unit, any one of claims 1 to 6, having a reset transistor having a gate connected to the output of the inverter The imaging device according to item . Charges generated by the photoelectric conversion unit in the reset unit are received on the condition that the inverter outputs the second logic value while receiving the synchronization signal at a predetermined cycle and receiving the synchronization signal. the imaging device according to claim 6 to obtain Bei a synchronization circuit for resetting the. The inverter is a CMOS inverter;
The imaging according to any one of claims 1 to 8, further comprising a threshold control transistor that is provided for each MOS transistor of the CMOS inverter, is connected to a source of the corresponding MOS transistor, and controls a threshold of the CMOS inverter. element. The output of the photoelectric conversion unit is connected to the input of the inverter,
The imaging device according to claim 2 , wherein the inverter is provided in the imaging chip. The source follower circuit is provided in the imaging chip;
The imaging device according to claim 2 , wherein the inverter is provided in the signal processing chip. The imaging device according to claim 2 , wherein the delay unit is provided in the signal processing chip. An imaging device comprising the imaging device according to any one of claims 1 to 12 .

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