JP6231041B2 - Game machine - Google Patents

Description

  The present invention relates to a gaming machine such as a pachinko machine, an arrangement ball machine, a sparrow game machine, and a spinning machine, and more particularly to a gaming machine that effectively uses a control memory having a limited storage capacity.

  A gaming machine such as a pachinko machine is generally composed of a plurality of circuit boards separated by function, and a main control board mainly responsible for game control and a sub-control that operates based on control commands received from the main control board Divided into substrates.

  In the case of a pachinko machine, the sub-control board includes a payout control board that controls the payout operation of the game ball, and one or a plurality of effect control boards that control various effect operations such as sound effects, lamp effects, and symbol effects. It is common to be classified.

JP 2004-41262 A

  By the way, in this type of gaming machine, there is a legal restriction on the memory capacity that can be used on the main control board and the payout control board. Under these restrictions, a smooth payout operation is realized and the player's preference It is necessary to upgrade the control operation to meet the requirements.

  From this point of view, the applicant transfers data such as operation status and control flags for smooth execution of the game ball payout operation, and initial values of the counter and timer from the ROM data storage area to the RAM work area. A unified transfer process is proposed (Patent Document 1).

  According to the invention described in Patent Document 1, a single transfer process can be used regardless of differences in transfer source ROM address, transfer destination RAM address, transfer data amount, and the like.

  However, it is necessary to further enhance the control operation under legal restrictions on memory capacity.

The present invention has been made in view of the above problems, and in a transfer process for transferring a group of data , a control memory having a limited storage capacity can be effectively removed by eliminating a count operation of the number of transfers. An object is to provide a game machine that can be used.

In order to achieve the above object, the present invention provides an indirect address scheme using a reference register for address reference, and a data acquisition instruction for incrementing the value of the reference register after reading data from the memory to the acquisition register. As a result of execution, when the acquisition data of the acquisition register is a specific value, or the subroutine end instruction for executing the determination as to whether or not to end the subroutine processing with reference to the data of the memory, the reference data of the memory is specified. When the value is a value, the CPU having a configuration in which the Z flag is set is used for the memory capacity of the ROM accessed by the CPU as in the case where the calculation result of the internal calculation operation is zero. a gaming machine with a regulated capacity for, the ROM, the lower 1 byte and R forwarding address Setting data to the AM of the working area, one or more sets stored in bytes, these one or more sets of the last configured to store the specific value set of data tables is provided, the setting data , said a working area, and the upper 1 byte wherein a fixed value of the transfer destination address, transfer processing is provided as a subroutine process of transferring to a transfer destination specified by the lower 1 byte of the destination address, the transfer process, the data acquisition command, or a result of executing the subroutine end instruction, if the Z flag is set, or the instruction following the data acquisition command, the execution of the subroutine end instruction, subroutine Configured to finish .

  In the present invention, the transfer process can be completed without performing arithmetic operations such as logical operations and arithmetic operations.

Further, the count operation of the number of executions of the transfer process and the management value comparison operation shown in the embodiment can be omitted.

  FIGS. 11A and 11B are a flowchart of the data transfer process TRANS1 of Reference Example 1 and its source program, and show that the count-down operation (SS55) of the number of transfer processes is essential.

  Specifically, in Reference Example 1, the number of executions of the transfer process is managed by the B register of the CPU (SS51). The transfer process execution count is stored at the head of the data set table D_TBL. After decrementing the B register (SS55), the Z (zero) flag is determined. If the Z flag is set, a series of processes is performed. (SS56).

  As shown in FIG. 11 (c), the data set table D_TBL includes N pieces of control information including a transfer destination lower address (1 byte) and storage data (1 byte) to be transferred to the transfer destination address. Pairs are stored, and the number N of pairs means the number of transfers. The start address value of the RAM work area has its lower address (1 byte value) of 00H, and the upper address @@ (1 byte value) is set by an instruction of LD D, @@ in the data transfer process TRANS1. (SS51). Further, the address (2-byte value) of the data set table D_TBL is set in the HL register at the time of a subroutine call by CALL TRANS1 (LD HL, D_TBL).

  FIGS. 11D to 11E illustrate the source program and the data structure of the data set table D_TBL for the data transfer process TRANS2 of the reference example 2. In the reference example 2, instead of not counting the number of transfers, it is determined whether the acquired data (transfer destination lower address) by LDA, (HL) is the end data 00H, and it is 00H. Determines that the transfer process has been completed. In Reference Example 2, it is assumed that the lower address of the transfer destination is never 00H.

  In each of Reference Example 1 and Reference Example 2, an arithmetic operation for setting the Z flag built in the CPU is essential, and the use area of the ROM increases accordingly. Here, the operation instruction corresponds to the DEC B operation included in DJNZ LOOP1 of Reference Example 1 and the AND A operation of Reference Example 2.

  The total number of bytes of the machine code necessary for functioning the subroutine TRANS1 in Reference Example 1 is 20 bytes, and the total number of bytes of the machine code for functioning the subroutine TRANS2 in Reference Example 2 is 22 bytes. is there. The right column of the source programs TRANS1 and TRANS2 describes the byte length of each instruction (machine code).

  FIGS. 9A and 9B show a flowchart of the data transfer processing TRANS and the source program for the embodiment of the present invention compared with the reference example 1 and the reference example 2 described above. The configuration of FIG. 9A is similar to that of Reference Example 2 (FIG. 11D), and the data set table D_TBL includes the lower 1 byte value of the transfer destination address and the setting data to be transferred in the order. Each set of control information is stored, and finally, end data 00H as a management value is stored.

  Further, the CPU used in the embodiment of FIG. 9A is not only when the calculation result of the internal calculation operation such as the DEC B calculation and the AND A calculation is zero, but the acquired data to the internal register is zero. Even in some cases, the built-in Z flag of the CPU is set. In the operation of whether or not the built-in Z flag is set, it does not matter whether the acquired data to the internal register is 1 byte or 2 bytes.

  Therefore, in the illustrated embodiment, the Z flag is determined immediately after execution of the LDE, (HL +) instruction in order to effectively utilize the function of the CPU. Hereinafter, the configuration of the embodiment including this point will be described. Prior to the subroutine call (CALL TRANS) of the data transfer process TRANS, the head address of the data set table D_TBL is set to the CPU's address by the LD HL, D_TBL instruction. Acquired in the HL register.

  In the data transfer process TRANS, first, the upper 1 byte of the address value in the RAM work area is acquired in the D register of the CPU (ST51). In FIG. 9, the upper 1 byte of the address value of the work area is expressed as @@. However, under the current legal regulations, the storage capacity of the RAM work area does not exceed 256 bytes, and the transfer destination The upper 1 byte of the address always has the same value @@.

  Therefore, in the present invention, an arbitrary transfer destination typically has a common upper 1 byte value of the address. Also, the lower 1 byte value of the head address of the work area is typically zero.

  Next, with the indirect load instruction of the HL register, the lower 1 byte of the RAM address of the data transfer destination is acquired in the E register of the CPU, and the HL register is incremented (ST52). As shown in the right column of the source program TRANS, the LDE, (HL +) instruction has a machine code byte length of 2 bytes.

  As described above, in this CPU, the Z flag is set even when the acquired data to the internal register is zero. Therefore, the RET Z instruction is subsequently executed to set the Z flag. In this case, the subroutine processing is finished (ST53). On the other hand, if the E register is not 0 and the Z flag is not set, the transfer data (setting data) to the transfer destination address is acquired in the A register by the indirect load instruction of the HL register, and the HL register is set. Increment (ST54).

  Next, the transfer data acquired in the A register is transferred to the transfer destination address by the indirect load instruction of the DE register (ST55), and then unconditionally jumps to the TRNS address.

  When the processing of steps ST51 to ST55 is repeated in this way, the final data (management value 00H) is acquired in response to the LDE, (HL +) instruction, so that the DEC operation, the AND operation, the comparison operation CP, etc. The subroutine processing is finished without going through the internal calculation (ST53).

  In FIG. 9, the numerical value shown in the right column of the source program is the byte length of the machine code. The total number of bytes of the machine code that implements the data transfer process TRANS is 18 bytes, and the consumption of 2 to 4 bytes of ROM is suppressed as compared with Reference Example 1 and Reference Example 2. Here, even though it is only 2 to 4 bytes, the restrained amount is effective in the legal regulation of the memory capacity, and can be distributed to other control data and control program.

  9D to 9E show a flowchart of the data transfer process TRANS when using another CPU and a source program. In this CPU, a conditional subroutine return instruction (RT Z) that can refer to the data value of the memory is provided, and this instruction is effectively used in this CPU.

  Prior to the subroutine call (RST TRNS) of the data transfer process TRANS, the head address of the data set table D_TBL is acquired in the HL register by the LD HL, D_TBL instruction. Also in this embodiment, the data structure of the data set table D_TBL is as shown in FIG.

  In the data transfer process TRANS, first, the Z flag is caused to function by an indirect determination instruction of the HL register (ST61). If the Z flag is in the set state, the data transfer process TRANS is terminated. If the Z flag is not in the set state, the indirect load instruction of the HL register is used to transfer the lower 1 byte of the RAM address of the data transfer destination to the CPU. Obtained in the E register (ST62).

  Next, the upper 1 byte (@@) of the work area address value is set in the D register and the HL register is incremented (ST63). Then, the transfer data is transferred to the A register of the CPU by an indirect load instruction of the HL register. Obtain (ST64). Then, the indirect load instruction of the DE register stores the data in the A register in the transfer destination (ST65), and then increments the HL register and jumps to the TRNS address (ST66).

  Also in this embodiment, when the processing of steps ST61 to ST66 is repeated, the Z flag is eventually set by the RTZ, (HL) instruction. In this case, the DEC operation, AND operation, comparison operation CP, etc. The subroutine processing is finished without undergoing internal computation (ST61). Even with such a configuration, the amount of ROM consumed can be suppressed as compared with Reference Example 1 and Reference Example 2.

  The control information is preferably a part of the address value of the transfer destination address (typically the lower 1 byte) and the setting data (typically 1 byte), as in the embodiment of FIG. Although configured, the setting data may be a plurality of bytes. Needless to say, the control information is not limited to a plurality of sets, and may be a single set. In any case, when such a configuration is adopted, it is preferable that the start address of the work area is not used for the transfer process.

  In addition, as in the embodiment of FIG. 9, the transfer destination address is 2 bytes long, and the lower 1 byte value of the transfer destination address is typically stored in the data set table. It is not limited. In the data pair of the transfer destination address and the setting data, the order may be preceded by the setting data, and the management value is not necessarily 1 byte long. The control information may be a series of setting data groups that do not include address information, but may be used as long as the CPU includes a block transfer instruction (LDIR).

  The present invention is a gaming machine that executes a symbol variation game in which a predetermined symbol is variably displayed, and a winning game is started when the symbol reaches a predetermined display mode, and at the start of the winning game and / or symbol variation It is preferable that the transfer process is executed at the start of the display game, or at the end of the winning game and / or at the end of the symbol variation display game. Further, the present invention is a gaming machine in which a game medium is paid out to a player under a predetermined condition, and the transfer process is executed at the time of transfer of control information for controlling a payout motor for executing a game medium payout operation. It is also preferable.

  According to the present invention described above, it is possible to effectively use a control memory with a limited storage capacity.

It is a perspective view of the pachinko machine shown in an example. It is the front view which illustrated the game board of the pachinko machine of FIG. It is a block diagram which shows the whole structure of the pachinko machine of FIG. It is a circuit diagram which shows the internal circuit of a one-chip microcomputer. It is a flowchart explaining the main process of a main control part. It is a flowchart explaining the timer interruption process of a main control part. It is drawing explaining a part of operation | movement of a payout control part. It is a figure explaining transition of an operation flag. It is a program which illustrates the data transfer process by this invention. It is drawing explaining another data transfer process. It is drawing explaining the data transfer process of a reference example.

  Examples of the present invention will be described in detail below. FIG. 1 is a perspective view showing a pachinko machine GM of the present embodiment. This pachinko machine GM includes a rectangular frame-shaped wooden outer frame 1 that is detachably mounted on an island structure, and a front frame 3 that is pivotably mounted via a hinge 2 fixed to the outer frame 1. It is configured. A game board 5 is detachably attached to the front frame 3 from the front side rather than from the back side, and a glass door 6 and a front plate 7 are pivotally attached to the front side so as to be openable and closable.

  On the outer periphery of the glass door 6, an electric lamp such as an LED lamp is arranged in a substantially C shape. An upper plate 8 for storing game balls for launch is mounted on the front plate 7, and a lower plate 9 for storing game balls overflowing from or extracted from the upper plate 8 and a launch handle 10 are mounted at the bottom of the front frame 3. And are provided. The launch handle 10 is interlocked with the launch motor, and a game ball is launched by a striking rod that operates according to the rotation angle of the launch handle 10.

  A chance button 11 is provided on the outer peripheral surface of the upper plate 8. The chance button 11 is provided at a position where it can be operated with the left hand of the player, and the player can operate the chance button 11 without releasing the right hand from the firing handle 10. The chance button 11 does not function normally, but when the game state becomes the button chance state, the built-in lamp is turned on and can be operated. The button chance state is a game state provided as necessary.

  On the right side of the upper plate 8, an operation panel 12 for ball lending operation with respect to the card-type ball lending machine is provided, a frequency display unit for displaying the remaining amount of the card with a three-digit number, and a ball of game balls for a predetermined amount A ball lending switch for instructing lending and a return switch for instructing to return the card at the end of the game are provided.

  As shown in FIG. 2, the game board 5 is provided with a guide rail 13 formed of a metal outer rail and an inner rail in an annular shape, and a liquid crystal color display DISP is provided at the approximate center of the game area 5a inside. Has been placed. In addition, at a suitable place in the game area 5a, a symbol start opening 15, a big winning opening 16, a plurality of normal winning openings 17 (four on the right and left of the large winning opening 16), and a gate 18 serving as a passing opening are arranged. Yes. Each of these winning openings 15 to 18 has a detection switch inside, and can detect the passage of a game ball.

  The liquid crystal display DISP is a device that variably displays a specific symbol related to a big hit state and displays a background image and various characters in an animated manner. This liquid crystal display DISP has special symbol display portions Da to Dc in the center portion and a normal symbol display portion 19 in the upper right portion. And, in the special symbol display parts Da to Dc, a reach effect is executed that expects a big hit state to be invited, or in the special symbol display parts Da to Dc and the surroundings, a notice effect that informs the result of the success / failure is executed. Is done.

  The normal symbol display unit 19 displays a normal symbol. When a game ball that has passed through the gate 18 is detected, the normal symbol fluctuates for a predetermined time, and the lottery extracted at the time when the game ball passes through the gate 18 is extracted. The stop symbol determined by the random number for use is displayed and stopped.

  For example, the symbol start opening 15 is configured to be opened and closed by an electric tulip having a pair of left and right opening and closing claws 15a. When the stop symbol after the fluctuation of the normal symbol display unit 19 displays a winning symbol, the symbol start port 15 is opened and closed. The claw 15a is opened only for a predetermined time or until a predetermined number of game balls are detected.

  When a game ball wins the symbol start opening 15, the special symbols displayed on the special symbol display portions Da to Dc change for a predetermined time, and based on the lottery result corresponding to the winning timing of the game ball to the symbol start opening 15. Stop at the determined stop symbol. In addition, in special symbol display parts Da-Dc and its circumference, a notice effect may be performed between a series of symbol effects.

  The big winning opening 16 is controlled to open and close by, for example, an opening / closing plate 16a that can be opened forward, but when the stop symbol after the symbol change of the special symbol display portions Da to Dc is a big hit symbol such as “777”, the “big hit game” Is started, and the opening / closing plate 16a is opened. Various game modes such as 8 rounds and 16 rounds are provided as the number of special game rounds. Here, the larger the prescribed number of rounds, the more advantageous to the player.

  After the opening / closing plate 16a of the big prize opening 16 is opened, the opening / closing plate 16a is closed when a predetermined time elapses or when a predetermined number (for example, 10) of game balls wins. In such an operation, the special game of the prescribed number of rounds as described above is continued and controlled in a state advantageous to the player. In addition, when the stop symbol after the change of the special symbol display parts Da to Dc is a specific symbol of the special symbols, the game after the end of the special game is in a high probability state (hereinafter referred to as a probability variation state). The privilege is granted.

  FIG. 3 is a block diagram showing an overall circuit configuration of the pachinko machine GM that realizes the above-described operations. A dashed line in the figure mainly indicates a DC voltage line.

  As shown in the figure, this pachinko machine GM is provided with a power supply board 20 that receives AC 24V and outputs various DC voltages, system reset signals (power reset signals) SYS, and the like, and a main control board 21 that plays a central role in game control operations. And an effect control board 22 that executes a lamp effect and a sound effect based on the control command CMD received from the main control board 21, and a liquid crystal that drives the liquid crystal display DISP based on the control command CMD ′ received from the effect control board 22. The control board 23, the payout control board 24 for controlling the payout motor M based on the control command CMD "received from the main control board 21 and paying out the game ball, and the game ball is fired in response to the player's operation. The launch control board 25 is mainly configured.

  In this embodiment, the control command CMD output from the main control board 21 is transmitted to the effect control board 22 via the effect interface board 27. The control command CMD ′ output from the effect control board 22 is transmitted to the liquid crystal control board 23 via the effect interface board 27, and the control command CMD ″ output from the main control board 21 is the main board relay board. It is transmitted to the payout control board 24 via 28.

  The main control board 21, the effect control board 22, the liquid crystal control board 23, and the payout control board 24 are each equipped with a computer circuit including a one-chip microcomputer. Accordingly, the circuits mounted on the control boards 21 to 24 and the operations realized by the circuits are collectively referred to as a function. In this specification, the main control unit 21, the effect control unit 22, and the liquid crystal control unit 23 are used. , And the payout control unit 24. All or part of the effect control unit 22, the liquid crystal control unit 23, and the payout control unit 24 is a sub-control unit.

  Here, the performance of the CPU of the one-chip microcomputer constituting the main control unit 21 and the payout control unit 24 is legally restricted from the viewpoint of crime prevention. Further, the memory space of ROM and RAM accessed by the CPU is also limited. Therefore, in the present embodiment, the internal configuration of the CPU and the configuration of the control program are devised in order to suppress the memory space consumed for the routine processing as much as possible and enhance other control performance.

  More specifically, based on legal regulations, the basic unit of CPU operation is 1 byte. However, the CPU of this embodiment can perform addition / subtraction (ADD / SUB / INC / DEC, etc.) or logical operation (OR / AND). The Z flag is set by a load instruction, or a conditional subroutine return instruction based on the Z flag functions.

  These points are the same as described above with reference to FIG. 9, and the load instruction in which the Z flag is set is, for example, an HL indirect load instruction of mnemonic [LD E, (HL +)], which is indicated by the HL register. One byte data of the address is acquired in the E register. If the value of the acquired data is zero, the Z flag is set. Note that HL + means that the HL register is incremented by +1 by execution of this instruction.

  Further, in this CPU, even when 2-byte data is acquired, the Z flag is set based on the acquired data. For example, in the case of an HL indirect load instruction of mnemonic [LD WA, (HL +)], 1-byte data at the address indicated by the HL register is acquired in the A register, and 1-byte data at the next address is acquired in the W register. The By executing this instruction, the HL register is incremented by +2.

  The predetermined determination return instruction is, for example, a mnemonic [RT Z, (HL)] subroutine return instruction. If the 1-byte data at the address indicated by the HL register is zero, the subroutine processing is terminated. Yes.

  As described with reference to FIG. 9, in this embodiment, [LDE, (HL +) instruction] or [LDWA, (HL +) instruction] or [RTZ, (HL) instruction] is used. Thus, the memory space consumed for routine processing is effectively suppressed.

  If the explanation is continued based on FIG. 3, the pachinko machine GM is roughly divided into a frame side member GM1 surrounded by a broken line in FIG. 3 and a board side member GM2 fixed to the back of the game board 5. The frame side member GM1 includes a front frame 3 on which a glass door 6 and a front plate 7 are pivotally attached, and a wooden outer frame 1 on the outside thereof. Is fixedly installed. On the other hand, the board side member GM2 is replaced in response to the model change, and the new board side member GM2 is attached to the frame side member GM1 instead of the original board side member. All except the frame side member 1 is the panel side member GM2.

  As shown in the broken line frame in FIG. 3, the frame-side member GM1 includes a power supply board 20, a payout control board 24, a launch control board 25, and a frame relay board 32, and these circuit boards are Each is fixed in place on the front frame 3. On the other hand, on the back of the game board 5, a main control board 21, an effect control board 22, and a liquid crystal control board 23 are fixed together with a liquid crystal display DISP and other circuit boards. And the frame side member GM1 and the board | substrate side member GM2 are electrically connected by the connection connectors C1-C4 concentratedly arranged in one place.

  The power supply board 20 is connected to the main board relay board 28 through the connection connector C2, and is connected to the power supply relay board 30 through the connection connector C3. The main board relay board 28 outputs the system reset signal SYS, the RAM clear signal DEL, the voltage drop signal, the backup power supplies BAK, DC12V, and DC32V received from the power board 20 to the main controller 21 as they are. Similarly, the power relay board 30 also outputs the system reset signal SYS received from the power board 20 and the AC and DC power supply voltages to the effect interface board 27 as they are. The production interface board 27 outputs the received system reset signal SYS to the production control unit 22 and the liquid crystal control unit 23 as they are.

  On the other hand, the payout control board 24 is directly connected to the power supply board 20 without going through the relay board, and the system reset signal SYS, the RAM clear signal DEL, the voltage drop signal, the backup power supply, which are received by the main control unit 21. BAK is received directly along with other power supply voltages.

  Here, the system reset signal SYS output from the power supply board 20 is a power supply reset signal indicating that the AC power supply 24V is turned on to the power supply board 20, and the one-chip microcomputers of the respective control units 21 to 24 by this power supply reset signal. The other IC elements are reset in power supply.

  The RAM clear signal DEL received from the power supply board 20 by the main control unit 21 and the payout control unit 24 is a signal that determines whether or not to initialize all areas of the built-in RAM of the one-chip microcomputer of each control unit 21 and 24. Therefore, it has a value corresponding to the ON / OFF state of the initialization switch SWT operated by the attendant.

  The voltage drop signal received from the power supply board 20 by the main control unit 21 and the payout control unit 24 is a signal indicating that the AC power supply 24V has started to drop. By receiving this voltage drop signal, each control unit 21, In 24, a necessary termination process is started prior to a power failure or business termination. The backup power supply BAK is a DC5V DC power source that retains data in the RAM of the one-chip microcomputer of the main control unit 21 and the payout control unit 24 even after the AC power supply 24V is shut off due to business termination or power failure. Therefore, the main control unit 21 and the payout control unit 25 can resume the game operation before power-off after power-on (power backup function). This pachinko machine is designed to retain the stored contents of the RAM of each one-chip microcomputer for at least several days.

  On the other hand, the effect control unit 22 and the liquid crystal control unit 23 are not provided with the power supply backup function described above. However, as described above, the system reset signal SYS is commonly supplied to the effect control unit 22 and the liquid crystal control unit 23 via the power relay board 30 and the effect interface board 27. A power supply reset operation is realized at a timing substantially synchronized with the control units 21 and 24.

  As illustrated, the main control unit 21 transmits a control command CMD "to the payout control unit 25 via the main board relay board 28, while the payout control unit 25 receives a prize ball indicating a payout operation of the game ball. A count signal and a status signal CON relating to an abnormality in the payout operation are received, and the status signal CON includes, for example, a replenishment out signal, a payout shortage error signal, and a lower plate full signal.

  Further, the main control unit 21 is connected to each game component of the game board 5 directly or via the game board relay board 29. And while receiving the switch signal of the detection switch built in each winning opening 16-18 on a game board, solenoids, such as an electric tulip, are driven. As shown in the figure, the winning switch signal SG is directly transmitted to the main control unit 21, and the other switch signals are transmitted to the main control unit 21 via the game board relay board 29.

  FIG. 4 illustrates a part of the internal configuration of the one-chip microcomputer 21 </ b> A of the main control unit 21. Here, the portion including the winning switch signal SG received from the detection switch SW of the symbol start port 15 is also shown. As shown in the figure, the one-chip microcomputer 21A includes a 1-byte CPU core (hereinafter referred to as CPU), a counter timer circuit CTC equivalent to Z80CTC (counter timer circuit), a ROM and RAM memory circuit, and a watchdog. A timer WDT, a random number generation circuit GNR, and an input port INP are built in.

  As shown in the figure, the winning switch signal SG from the detection switch SW is supplied to the random number generation circuit GNR of the one-chip microcomputer 21A via the buffer circuit BUF. The input port INP is supplied with a switch signal from a detection switch such as the big winning opening 16, the normal winning opening 17, or the gate 18.

  The random number generation circuit GNR includes a latch control circuit 30 that receives a switch signal such as a winning switch signal SG and outputs a latch pulse LT, a frequency divider 31 that divides the system clock CLK and the external clock XCLK by 2, and 2 A selection circuit 32 that selects one of the two divided clock signals as the update clock Φ, a sequence generation group 33G that includes N number generation units 33 that operate based on the update clock Φ, and latch control A latch group 34G composed of a plurality of latch circuits 34 that obtains a generated value of the sequence generator 33 based on a latch pulse LT received from the circuit 30, and a control parameter that defines the operation of each unit and an operation status indicating the operation state of each unit. A configuration including a control register group 35G to be held and an abnormality detection circuit 36 for detecting an operation abnormality of the sequence generator 33. Has been.

  Next, the gaming operation of the main control unit 21 executed by the above-described CPU will be described. FIGS. 5 and 6 are flowcharts showing the control program of the main control unit 21. The system reset process (FIG. 5) is started when the power supply voltage is restored or turned on, and is started every predetermined time (4 mS). And maskable timer interrupt processing (FIG. 6).

  Hereinafter, the system reset processing program (main processing) will be described with reference to FIG. The main process is started when the initialization switch SWT is OFF and the power is turned ON, such as when recovering from a power failure, and when the game hall is opened, the initialization switch SWT is ON. There is a case where the power source is turned on by being operated. In some cases, the watchdog timer WDT is activated and the CPU is forcibly reset.

  In either case, the CPU first initializes the value of the stack pointer SP in the CPU corresponding to the final address of the stack area (ST1). Next, the values of various registers including the control register group 35G of the random number generation circuit GNR of the one-chip microcomputer are initialized (ST2).

  A specific program is, for example, as shown in FIG. 5B, and reads necessary setting data (control parameter) from the data set table D_TBL0 secured in the built-in ROM of the one-chip microcomputer, and corresponds to this. Transfer to control register. Although not particularly limited, the present embodiment employs a port-mapped I / O method, and therefore, a series of control parameters are transferred by an OUT command.

  The port-mapped I / O method is a concept that is contrasted with the memory-mapped I / O method (Memory-mapped I / O). A dedicated OUT instruction or IN instruction is used for reading / writing. However, the present invention is not limited to the port mapped I / O method, and a memory mapped I / O method in which a memory and an IO device coexist in the address space can also be adopted. The LD command is used instead of the OUT command.

  In any case, the data set table D_TBL0 used in the initial setting process (ST2) has the structure shown on the right side of FIG. 5B, and includes one set of setting data 1 byte and port number 1 byte. The control information is stored continuously. Since the setting data and the port number are both configured to be zero, a 2-byte length of zero is stored as end data at the end of the data set table D_TBL0.

  The specific contents of the transfer process are as shown on the left side of FIG. First, the head address of the data set table D_TBL0 is set in the HL register of the CPU by LD HL, D_TBL0, the port number is acquired in the W register of the CPU by LD WA, (HL +), and the A register of the CPU is acquired. Get setting data (control parameters). The acquired setting data is initialized in various control registers built in the one-chip microcomputer by OUT (W), A.

  After such transfer processing is repeated, if the acquired data in the WA register becomes 0000H by LD WA, (HL +), a series of processing is completed by RET Z. Here, RET Z operates based on the Z flag built in the CPU. However, the CPU of this embodiment sets the Z flag based on the acquired data when executing LD WA, (HL +). It is not necessary to set the Z flag by an arithmetic operation such as an INC instruction or a logical operation such as an AND instruction or a comparison instruction.

  In this way, when the initial setting process in step ST2 is completed, the RAM clear signal DEL is acquired from the input port INP (ST3). The RAM clear signal DEL is a signal for determining whether or not to initialize all the areas of the built-in RAM of the one-chip microcomputer 21A, and has a value corresponding to the ON / OFF state of the initialization switch SWT operated by the staff. Have.

  Next, the level of the RAM clear signal DEL is determined (ST4). Assuming that the RAM clear signal DEL is in the ON state, the entire area of the built-in RAM is cleared to zero (ST8). Next, a control command for notifying that the RAM area has been cleared to zero is output (ST9).

  Next, the CTC that outputs the interrupt signal INT for starting the timer interrupt operation (FIG. 6) is initialized (ST10). Then, with the CPU set to the interrupt disabled state (ST11), if there is a necessary counter, update processing is executed for this (ST12), then the CPU is returned to the interrupt enabled state (ST13), and step ST11. Return to.

  However, in this embodiment, since a large number of random values can be acquired from the random number generation circuit GNR, all the processes in steps ST11 to ST13 can be eliminated. Therefore, the storage capacity of the ROM can be saved by the amount of ST11 to ST13, and other control processes can be enriched.

  Next, returning to the determination process in step ST4, the RAM clear signal DEL is in the OFF state when the CPU is forcibly reset by the watchdog timer WDT or the like, or when recovering from the power failure state. In such a case, the content of the backup flag BFL is determined following the determination in step ST4 (ST5). The backup flag BFL is data indicating that the backup process has been executed in the power supply monitoring process (ST20). In this embodiment, the backup flag BFL is set to 5AH when the power is shut off, and the process of step ST20 after the power is restored. Is cleared to zero.

  Therefore, when the power is turned on or when recovering from the power failure state, the content of the backup flag BFL is 5AH. However, if the program goes into a runaway state for some reason and a CPU reset operation is caused by the watchdog timer, the backup flag BFL = 00H. Therefore, when BFL ≠ 5AH (normally BFL = 00H), the process proceeds from step ST5 to step ST8 to return the operation of the gaming machine to the initial state.

  On the other hand, if the backup flag BFL = 5AH, a checksum calculation for calculating a checksum value is executed (ST6). Here, the checksum operation is an 8-bit addition operation for the work area of the built-in RAM. When the checksum value is calculated, the calculation result is compared with the stored value at the SUM address in the RAM (ST7).

  In the SUM address, a checksum value obtained by the same checksum calculation is stored in the power supply monitoring process (ST20) executed when the voltage drops. The stored calculation result is maintained by a backup power source together with other data of the built-in RAM. Therefore, the two should be matched by the determination in step ST7.

  However, if the checksum operation cannot be executed when the power is turned off, or if it can be executed, but the work area data is damaged before the checksum operation (ST6) of the main process is executed. In such a case, the determination result in step ST7 is inconsistent.

  Therefore, if data corruption is detected due to a discrepancy in the determination results, the process proceeds to step ST8, RAM clear processing is executed, and the operation of the gaming machine is returned to the initial state. On the other hand, if it is determined in step ST7 that the checksum value obtained by the checksum calculation (ST8) matches the stored value at the SUM address, the process proceeds to step ST10 described above.

  Next, a timer interrupt processing program (FIG. 6) that is started every 4 mS while interrupting the above-described main processing will be described. When the timer interrupt occurs, the power supply monitoring process is immediately executed without saving the CPU register (ST20). This is because the timing at which the timer interrupt process is started is fixed immediately after step ST13.

  In the power supply monitoring process (ST20), the level of the voltage drop signal supplied from the power supply board 20 is determined. If the level is abnormal, the backup flag BAKFLG is set to 5AH, the checksum value is calculated, and the SUM address is calculated. And wait for the power to be cut off.

  Next, a random number generating process for updating the winning counter RG used in the lottery process in the normal symbol process ST28 is executed (ST21). The winning counter RG is incremented (+1) within a predetermined numerical value range, and the updated counter value is utilized in the winning / not determining lottery process as a winning determination random value. Specifically, as the value of the winning counter RG, when the game ball passes through the gate 18, the winning counter RG is used in the winning lottery process in the normal symbol process (ST18).

  Note that the random number RND for lottery used in the jackpot lottery process in the special symbol process (ST32) is acquired from the random number generation circuit GNR and is not updated by software processing.

  Next, a timer subtraction process is performed for the timer that manages the game operation time (ST22). The timer to be subtracted manages the opening time of the special winning opening 16 and other game effect times. When such a timer subtraction process is completed, switch signals of various switches including the symbol start port 15 and the detection switch of the gate 18 are acquired and stored (ST23). The winning switch signal SG related to the symbol start port 15 is obtained by accessing the signal input register 35f of the random number generation circuit GNR. On the other hand, switch signals from other detection switches are obtained from the input port INP of the one-chip microcomputer.

  When the switch input process (ST23) is completed, an error management process is executed (ST24). The error management process means a determination as to whether an abnormality has occurred inside the device, such as whether or not the supply of game balls has stopped or the game balls are clogged. When the error management process (ST24) is completed, a control command for the payout control unit 33 is created (ST25), and the control command generated at this stage is transmitted to the corresponding sub-control unit ( ST26).

  Subsequently, the normal symbol process is executed on the condition that the current operation mode is not the hit mode (ST28). The normal symbol process means a determination as to whether or not to operate an ordinary electric accessory, and when it is determined that the game ball has passed through the gate according to the switch input result in step ST23, a random number generation process (ST21). The winning counter RG updated in step) is compared with the winning winning value. If the comparison result is a winning state, the operation mode is changed to the winning operation mode. Further, if it is hit, processing for the operation of the ordinary electric accessory is performed (ST30).

  Next, a necessary control command is transmitted to the corresponding sub-control unit (ST31), and special symbol processing is performed (ST32). The special symbol process is a determination of whether or not to operate a special electric accessory such as the big prize opening 16, and is a process including a big hit lottery process.

  As specific processing, when it is determined that the winning switch signal SG has been turned ON based on the switch input result of step ST23, the value of the random number register of the random number generation circuit GNR is acquired, and the random number value for the big hit lottery Store as RND. Also, the value of another random number register is acquired and stored as a random number value RND ′ for symbol lottery.

  At this timing, when the symbol effect processing (the symbol variation processing of the symbol display portions Da to Dc) is completed and there is no preceding winning switch signal SG in the lottery pending state, the random value RND is set. The big hit lottery process is executed based on the random number value RND ′, and the symbol lottery is executed (ST32). In the winning state of the big hit lottery process, whether or not the game is a probable change and the number of special games rounds are determined by the symbol lottery process, and in the out of the big hit lottery process, the off symbol is determined by the symbol lottery process.

  Further, in the process of step ST32, the variation pattern command is determined by lottery including the specification of the stop symbol after the variation operation. The variation pattern command is a control command for effect operation transmitted to the effect control unit 22, and defines a symbol variation operation in the image control unit 23. This variation pattern command is stored in the command buffer by specifying the total time of effect operations such as reach effects as well as the success / failure result of the big win lottery. The variation pattern command stored in the command buffer is transmitted to the effect control unit 22 at the timing of subsequent step ST35.

  On the other hand, if this timing is during the symbol production process, the big hit lottery process will be in a standby state (lottery pending state), the running symbol production will end, and if the subsequent symbol presentation accompanying the big jackpot lottery ends, As the process of step ST32 at that timing, a lottery process using a random number value RND for jackpot lottery in a stored state or a random value RND ′ is executed.

  In any case, if the winning state is achieved by the big win lottery process of the special symbol process (ST32), the operation mode is changed to the big hit operation mode, and the process for the operation of the special electric accessory such as the big prize opening is performed (ST34).

  Next, the variation pattern command generated in step ST32 is transmitted to the effect control unit 22 (ST35), and the timer interrupt ends. As a result, the process returns to the process of the main routine (not shown), but when the predetermined time (4 mS) has elapsed, the process of step ST11 is started again, so that the processes of steps ST20 to ST35 are repeated every 4 mS. It will be.

  In the above-described operation, in this embodiment, the changing operation of the special symbol, the changing operation of the normal symbol, the opening / closing operation of the special electric accessory (large winning prize opening 16), the opening / closing operation of the ordinary electric accessory (electric tulip), the jackpot Game progress and the like during the game are all managed by various operation statuses, control flags, and control timers.

  For example, in the special symbol or normal symbol variation operation, the operation status and control flag are switched at the start of the operation, during the variation operation, and at the end of the variation operation, and an appropriate initial value is set for the control timer to smooth the operation transition. Is set.

  The operation status, the control flag, and the control timer are set in common in the sense that the setting value data in the ROM is transferred to the corresponding address in the work area of the RAM, although the setting values are different. Therefore, in this embodiment, the setting process of the operation status, the control flag, and the control timer is executed by a subroutine call (CALL TRNS) of the data transfer process TRNS shown in FIG.

  As described above, prior to the subroutine call (CALL TRNS), the head address of the corresponding data set table D_TBLi is loaded into the HL register (LD HL, D_TBLi), and the end of the transfer processing is performed by the corresponding data set table. This is determined by the end data (00H) stored at the final address of D_TBLi. Therefore, according to the configuration of the present embodiment, the consumption of the control program and control data in the ROM and RAM can be suppressed, and the suppression can be utilized elsewhere.

  Although the main control unit has been described above, the data transfer process TRNS shown in FIG. 9 is also used in the payout control unit. FIG. 7 exemplifies a motor process for rotating the payout motor. The motor status is set to any one of 0 to 3, and the motor driving start (ST67a) and the motor driving process (ST67b) are selected. ), Motor stop processing (ST67c), motor retry processing (ST67d).

  Further, it is shown that the operation of the payout motor is managed by a payout stop flag, a post-return payout stop flag, a payout motor flag, a motor stop timer, and the like. Further, as shown in FIG. 8, the payout operation is smoothly executed by appropriately changing the value of the prize ball flag or the payout motor flag.

  Therefore, in this embodiment, the payout control unit also uses the data transfer process TRNS shown in FIG. 9 in the setting process of these various operation statuses, control flags, and control timers, thereby consuming control programs and control data. The amount is suppressed.

  Although the embodiments have been described in detail above, the specific description does not particularly limit the present invention and can be appropriately changed.

  For example, in the program of FIG. 9B, the processing of LD D, @@ is executed every time data is transferred, but as shown in FIG. 10A, the number of times of processing of LD D, @@ is once. You may limit to. This configuration is substantially the same as the configuration of FIG. 9B, but the number of machine cycles is suppressed by executing LD D, @@ prior to the subroutine call. Incidentally, the total number of machine cycles is 21 * N + 24 with respect to the data transfer count N, and the execution speed is microscopically increased.

  However, if such a configuration is adopted, the ROM capacity is consumed by an extra 3 bytes for the subroutine call processing instead of the subroutine body being compressed by 3 bytes, which is disadvantageous when the number of subroutine calls is large. Overall, the configuration of FIG. 9B is superior. That is, in view of the current CPU operating speed (system clock frequency), the suppression of the number of machine cycles is not so much value.

  In the data transfer process TRNS in FIG. 9B, the lower 1 byte of the transfer destination address is not 00H. However, if the transfer data does not include zero, the data in the data set table D_TBL The structure may be reversed so that setting data (1 byte transfer data) → transfer destination address lower 1 byte is in order. It should be noted that the setting data is not necessarily 1 byte including the case of this modified embodiment.

  The end data is not necessarily 1 byte, and may be 2 bytes as shown in FIG. However, such a configuration is not suitable in that the memory consumption in the data set table D_TBL increases.

  Note that the application of the present invention is not limited to a ball game machine, and can be applied to various game machines including a spinning machine.

GM gaming machine 21 main control means 21A one-chip microcomputer

Claims (1)

After the data is read from the memory to the acquisition register by the indirect address method using the reference register for address reference, the acquired data of the acquisition register is specified as a result of executing the data acquisition instruction that increments the value of the reference register If the value is a value, or the subroutine end instruction is executed by referring to the data in the memory to determine whether or not to finish the subroutine processing, the result of the internal arithmetic operation when the memory reference data is a specific value As in the case where is zero, a CPU having a configuration in which the Z flag is set executes a control operation, and is a gaming machine with a restriction on a usable capacity with respect to a memory capacity of a ROM accessed by the CPU,
The ROM stores one or more sets of lower byte 1 of the transfer destination address and setting data in the RAM work area in byte units , and the specific value is stored at the end of the one or more sets. A configured data set table is provided ,
The setting data, wherein a working area, and the upper 1 byte wherein a fixed value of the transfer destination address, a transfer process is a subroutine process of transferring to a transfer destination specified by the lower 1 byte of the destination address Provided,
The transfer process, the data acquisition command, or a result of executing the subroutine end instruction, if the Z flag is set, or the instruction following the data acquisition command, the execution of the subroutine end instruction, subroutine A gaming machine that is configured to finish the game.

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