JP6227480B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device that has integrated partial circuit parts such as a plurality of inverter parts and is capable of suppressing a surge voltage by mounting a snubber circuit.

  2. Description of the Related Art Conventionally, in a semiconductor device such as a power semiconductor module in which an inverter circuit is modularized, a switching device such as an IGBT (Insulated Gate Bipolar Transistor) or a MOSFET that constitutes the inverter circuit generates a surge voltage. For the purpose of suppressing this surge voltage, for example, Patent Document 1 proposes a semiconductor device having a power wiring board in which a snubber circuit is connected from the outside in the immediate vicinity of a collector-emitter terminal of an IGBT constituting a power semiconductor module. Has been.

Japanese Patent Laid-Open No. 5-110215

  Regarding the connection of the snubber circuit related to the prior art disclosed in Patent Document 1, etc., the snubber circuit is connected in the immediate vicinity of the main terminal for external connection of the power semiconductor module. Each power semiconductor chip (IGBT, MOSFET, etc.) has a problem that it cannot exert a sufficient surge voltage suppression effect even if a snubber circuit is connected due to the influence of the inductance component contained in the internal wiring leading to each electrode. there were. The problem is that when an inverter circuit consisting of a plurality of inverter parts is provided in the module, the distance to the main terminal is different between the plurality of inverter parts. Inverter parts that require longer internal wiring than other inverter parts inevitably exist, and this is particularly noticeable.

  The present invention has been made to solve the above problems, and reduces the inductance component contained in the internal wiring while adopting a structure in which a plurality of partial circuit parts such as a plurality of inverter parts are integrated in the module. An object of the present invention is to obtain a semiconductor device capable of realizing a sufficient surge voltage suppression effect.

According to a first aspect of the present invention, there is provided a semiconductor device in which a plurality of partial circuit portions each provided by being electrically connected between a first terminal and a second terminal which are external terminals are integrated. A semiconductor device having an entire circuit portion, comprising: a first wiring pattern electrically connected to the first terminal; and a second wiring pattern electrically connected to the second terminal. The plurality of partial circuit portions are respectively corresponding first and second partial circuit formation regions among the plurality of first and second partial circuit formation regions allocated on the first and second wiring patterns. A plurality of first mounting portions provided at least in part on the plurality of first partial circuit formation regions, and a plurality of second mounting portions provided on the plurality of second partial circuit formation regions. A second mounting portion, wherein the plurality of first and first portions Each of the mounting portions is configured such that one terminal of a snubber circuit having one terminal and the other terminal is mounted on the first mounting portion and the other terminal is mounted on the second mounting portion. first and second in one-to-one correspondence with the inter mounting portion have a snubber circuit mounting structure for mounting a plurality of snubber circuits, at least one of the terminals of the one terminal and the other terminal of the snubber circuit of A plurality of first and second mounting portions are mounted on the first reactor portion, in which the reactor portion is mounted on the first mounting portion instead of one terminal of the snubber circuit, and on the other side. It has the reactor part mounting structure which implement | achieves at least 1 reactor part mounting | wearing among the 2nd reactor part mounting | wearing which mounts the said reactor part on a 2nd mounting part instead of a terminal, It is characterized by the above-mentioned .

In the semiconductor device according to the first aspect of the present invention according to the present invention, each of the plurality of first and second mounting portions provided on the plurality of first and second partial circuit regions is one of the snubber circuits. mounting the terminal to the first mounting portion, the Rukoto configured for mounting the other terminal to the second mounting portion, in a one-to-one correspondence between a plurality of first and second mounting portions plurality It is characterized by having a snubber circuit mounting structure for mounting the snubber circuit.

  The present invention according to claim 1 has the above-mentioned characteristics, and corresponding to each of a plurality of integrated partial circuit portions, corresponding first and second snubber circuits in a wiring mode through only a relatively short internal wiring. It can be attached by the second mounting part.

  As a result, the surge voltage suppression function by the snubber circuit can be effectively applied to the corresponding partial circuit portions, so that a high surge voltage suppression effect for each of the plurality of partial circuit portions can be exhibited with good uniformity.

It is explanatory drawing which shows the circuit structure of the inverter circuit in the power semiconductor module which is Embodiment 1 of this invention. FIG. 3 is an explanatory diagram schematically showing an actual wiring structure of an inverter circuit in the power semiconductor module according to the first embodiment. FIG. 6 is an explanatory diagram schematically showing a state of mounting a snubber circuit by an upper mounting section and a lower mounting section in the first embodiment. It is explanatory drawing which shows the cross-section of the mounting condition of the snubber circuit by the upper stage mounting part and lower stage mounting part in the power semiconductor module of Embodiment 2. FIG. 10 is a perspective view schematically showing a mounting state of a snubber circuit by an upper mounting section and a lower mounting section in the second embodiment. FIG. 10 is an explanatory diagram schematically showing a cross-sectional structure of a mounting state of a snubber circuit by an upper mounting portion and a lower mounting portion in the power semiconductor module according to the third embodiment. FIG. 10 is a perspective view schematically showing a mounting state of a snubber circuit by an upper mounting section and a lower mounting section in the third embodiment. FIG. 10 is an explanatory diagram schematically showing a cross-sectional structure of a mounting state of a snubber circuit by an upper mounting portion and a lower mounting portion in a power semiconductor module according to a fourth embodiment. FIG. 10 is a perspective view schematically showing a mounting state of a snubber circuit by an upper mounting portion and a lower mounting portion in the fourth embodiment. FIG. 10 is a perspective view schematically showing a non-mounted state of a snubber circuit by an upper mounting portion in the power semiconductor module of the fifth embodiment. FIG. 10 is a perspective view schematically showing a mounting state of a snubber circuit by an upper mounting portion in the power semiconductor module of the fifth embodiment. FIG. 24 is a perspective view schematically showing a structure of an upper mounting portion in the power semiconductor module according to the sixth embodiment. FIG. 25 is a perspective view schematically showing the structure of the upper mounting portion when a conductive member is inserted in the power semiconductor module of the sixth embodiment. It is explanatory drawing which shows typically the circuit structure of the power semiconductor module which is Embodiment 7 of this invention. FIG. 29 is an explanatory diagram schematically showing a mounting state of a reactor of a snubber circuit by an upper mounting portion in a power semiconductor module according to an eighth embodiment. It is explanatory drawing which shows typically the example of a snubber circuit installation in the conventional power semiconductor module.

<Embodiment 1>
1 and 2 are explanatory views showing the configuration of the inverter circuit 10 in the power semiconductor module (semiconductor device) according to the first embodiment of the present invention. FIG. 1 schematically shows the circuit configuration of the inverter circuit 10. FIG. 2 schematically shows an actual wiring structure and the like of the inverter circuit 10.

  As shown in these drawings, the inverter circuit 10 (overall circuit portion) is composed of three arm portions (partial circuit portions) each constituting a unit of an inverter portion, a U-phase circuit portion 5U and a V-phase circuit portion. It is composed of 5V and W phase circuit section 5W.

  The U-phase circuit unit 5U includes IGBTs 11 and 21 and diodes D11 and D21. The V-phase circuit unit 5V includes IGBTs 12 and 22 and diodes D12 and D22. The W-phase circuit unit 5W includes IGBTs 13 and 23 and diodes D13 and D23. Consists of

  In the U-phase circuit unit 5U, IGBTs 11 and 21 are connected in series, and diodes D11 and D21 having the emitter side as an anode (electrode) are interposed between the collectors (electrodes) and emitters (electrodes) of the IGBTs 11 and 21. In the V-phase circuit unit 5V, the IGBTs 12 and 22 are connected in series, and diodes D12 and D22 having the emitter side as an anode are interposed between the collectors and emitters of the IGBTs 12 and 22. In the W-phase circuit unit 5W, IGBTs 13 and 23 are connected in series, and diodes D13 and D23 having an emitter on the anode side are interposed between the collectors and emitters of the IGBTs 13 and 23, respectively.

  Node N11 that is a connection point between the collector of IGBT 11 and the cathode (electrode) of diode D11 in U-phase circuit unit 5U, node N12 that is a connection point between the collector of IGBT 12 and the cathode of diode D12 in V-phase circuit unit 5V, and the W phase A node N13 that is a connection point between the collector of the IGBT 13 and the cathode of the diode D13 in the circuit unit 5W is commonly connected to the P terminal 1 (first terminal) that is an external terminal. Then, mounting portions P11 to P13 are provided in electrical connection with the nodes N11 to N13.

  Node N21 which is a connection point between the emitter of IGBT 21 and the anode of diode D21 in U-phase circuit unit 5U, node N22 which is a connection point between the emitter of IGBT 22 and the anode of diode D22 in V-phase circuit unit 5V, and the W-phase circuit unit A node N23 which is a connection point between the emitter of the IGBT 23 and the anode of the diode D23 at 5 W is commonly connected to an N terminal 2 (second terminal) which is an external terminal. Then, mounting portions P21 to P23 are provided in electrical connection with the nodes N21 to N23.

  A node N31 which is a connection point between the emitter of the IGBT 11 (the anode of the diode D11) and the collector of the IGBT 21 (the cathode of the diode D21) in the U-phase circuit unit 5U, and a connection point between the emitter of the IGBT 12 and the collector of the IGBT 22 in the V-phase circuit unit 5V. A node N33, which is a connection point between the emitter of the IGBT 13 and the collector of the IGBT 23 in the W-phase circuit unit 5W, is connected to the intermediate terminals 31, 32, and 33. These intermediate terminals 31 to 33 are terminals for U phase, V phase and R phase.

  In order to realize the circuit configuration shown in FIG. 1, the power semiconductor module has a P terminal wiring pattern 51 (first wiring pattern) and an N terminal wiring pattern 52 (second wiring) on a substrate 50 as shown in FIG. Pattern), intermediate wiring patterns 61 to 63, and intermediate terminal patterns 71 to 73, and the inverter circuit 10 is formed on these patterns.

  Specifically, as shown in FIG. 2, the P terminal wiring pattern 51 for the P terminal 1 is allocated substantially equally for the areas for the U phase circuit unit 5U, the V phase circuit unit 5V, and the W phase circuit unit 5W. The IGBT 11 (exactly the emitter region of the IGBT 11) and the diode D11 (exactly the anode region of the diode D11) are formed in the allocation region for the U-phase circuit unit 5U (region of about one third of the left in the figure). Is done.

  Further, an IGBT 12 (exactly the emitter region of the IGBT 12) and a diode D12 (exactly the anode of the diode D12) are arranged in an allocation region (region of about 1/3 of the center in the figure) of the P terminal wiring pattern 51 of the V-phase circuit unit 5V. Region) is formed. Similarly, the IGBT 13 (exactly the emitter region of the IGBT 13) and the diode D13 (exactly the diode D13) are allocated to the allocation region (region of about 1/3 right in the figure) of the P terminal wiring pattern 51 of the W-phase circuit unit 5W. Anode region).

  As described above, the U-phase circuit unit 5U, the V-phase circuit unit 5V, and the W-phase circuit unit 5W are arranged on three allocation areas (a plurality of first partial circuit formation areas) allocated on the P terminal wiring pattern 51. The IGBTs 11 to 13 and the diodes D11 to D13, which are part of the constituent elements, are formed.

  Further, in order to realize the circuit configuration of FIG. 1 on the above-described allocation areas for the U-phase circuit unit 5U, the V-phase circuit unit 5V, and the W-phase circuit unit 5W of the P terminal wiring pattern 51, (upper stage) mounting unit P11 , P12 and P13 (a plurality of first mounting portions) are provided. That is, the mounting parts P11 to P13 are formed on three assigned areas for the U-phase circuit part 5U, the V-phase circuit part 5V, and the W-phase circuit part 5W assigned on the P terminal wiring pattern 51.

  On the other hand, the N terminal wiring pattern 52 of the N terminal 2 is assigned substantially equally to the areas for the U-phase circuit unit 5U, the V-phase circuit unit 5V, and the W-phase circuit unit 5W, like the P-terminal wiring pattern 51. Then, on the allocation area for the U-phase circuit section 5U (the area about 1/3 on the left in the figure), the allocation area for the mounting portion P21 and the V-phase circuit section 5V (the area about 1/3 in the center in the figure) The mounting portion P23 is provided on the allocation region (region of about 1/3 right in the drawing) of the mounting portion P22 and the W-phase circuit portion 5W.

  The U-phase circuit unit 5U, the V-phase circuit unit 5V, and the W-phase circuit unit 5W are one of the constituent elements on the three allocation areas (a plurality of second partial circuit formation areas) allocated on the N terminal wiring pattern 52. Bonding wires W21 to W23, which will be described later, are formed. The mounting portions P21 to P23 (a plurality of second mounting portions) are arranged on the N-terminal wiring pattern 52, as described above, to realize the circuit configuration of FIG. It is formed on three allocation areas for V-phase circuit unit 5V and W-phase circuit unit 5W.

  In FIG. 2, intermediate wiring patterns 61 to 63 are provided independently of each other on the lower side of the N terminal wiring pattern 52 in the drawing, and an IGBT 21 (more precisely, an emitter region of the IGBT 21) and a diode D 21 are provided in the intermediate wiring pattern 61. (To be precise, the anode region of the diode D21) is formed.

  Similarly, the IGBT 22 (exactly the emitter region of the IGBT 22) and the diode D22 (exactly the anode region of the diode D22) are formed in the intermediate wiring pattern 62, and the IGBT 23 (exactly, the IGBT 23 of the IGBT 23) is formed in the intermediate wiring pattern 63. An emitter region) and a diode D23 (more precisely, the anode region of the diode D23).

  Further, in FIG. 2, intermediate terminal patterns 71 to 73 for the intermediate terminals 31 to 33 are provided below the intermediate wiring patterns 61 to 63 in the drawing.

  In order to realize the circuit connection shown in FIG. 1, the following wiring is made using bonding wires W11 to W13, W21 to W23, and W31 to W33 as shown in FIG.

  First, the emitter region of the upper IGBT 1i (i = 1 to 3), the collector region of the lower IGBT 2i (the region of the intermediate wiring pattern 6i serving as the outer periphery of the lower IGBT 2i and the lower diode D2i), and the anode and lower diode of the upper diode D1i The cathode of D2i (the region of the intermediate wiring pattern 6i that is the outer peripheral portion of the lower stage IGBT 2i and the lower stage diode D2i) is electrically connected via the bonding wire W1i.

  Further, the emitter of the lower stage IGBT 2i and the anode of the lower stage diode D2i are electrically connected to the N terminal wiring pattern 52 via the bonding wire W2i provided above. In addition, the intermediate wiring pattern 6i and the intermediate terminal pattern 7i are electrically connected via a bonding wire W3i provided above.

  FIG. 3 is an explanatory diagram schematically showing a mounting state of the snubber circuit 8 by the upper mounting portion P1i and the lower mounting portion P2i in the power semiconductor module of the first embodiment.

  As shown in the figure, the upper mounting portion P1i provided in the allocation region 51i of the P terminal wiring pattern 51 and the lower mounting portion P2i provided in the allocation region 52i of the N terminal wiring pattern 52 are one side of the snubber circuit 8. The terminals 81 and 82 provided as the terminal and the other terminal are provided at positions and shapes that can be attached. Note that the upper mounting portion P1i and the lower mounting portion P2i are formed so that at least part of the upper mounting portion P1i protrudes outside the module even after the inverter circuit 10 is modularized by resin sealing or the like.

  Therefore, after completion of the power semiconductor module of the first embodiment in which the inverter circuit 10 is modularized, the mounted terminal 81 of the snubber circuit 8 is inserted into the upper mounting portion P1i, and the snubber circuit 8 is inserted into the lower mounting portion P2i. By inserting the mounted terminals 82, the mounted terminals 81 and 82 of the snubber circuit 8 can be mounted on the modularized inverter circuit 10.

  After the snubber circuit 8 is mounted on the mounting portion pair P1i and P2i, the snubber circuit 8 is lifted upward to change the mounting state between the mounting portion pair P1i and P2i and the mounted terminals 81 and 82. The snubber circuit 8 can be detached from the inverter circuit 10 by releasing the signal. That is, the snubber circuit 8 can be attached to and detached from the power semiconductor module of the first embodiment even after the device is completed.

  The power semiconductor module according to the first embodiment has mounting portions P11 to P13 and mounting portions P21 to P23 provided in assigned areas on the P terminal wiring pattern 51 and the N terminal wiring pattern 52. And a snubber circuit mounting structure in which the mounted terminal 81 of the snubber circuit 8 having 82 (one terminal and the other terminal) is mounted on the upper mounting portion P1i and the mounted terminal 82 is mounted on the lower mounting portion P2i. Have.

  As described above, the power semiconductor module of the first embodiment has a snubber circuit mounting structure, so that a plurality of arm portions (the U-phase circuit portion 5U, the V-phase circuit portion 5V, and the W-phase circuit) in the integrated inverter circuit 10 are provided. The corresponding snubber circuit 8 can be attached via only the extremely short internal wiring corresponding to each of the parts 5W;

  FIG. 16 is an explanatory view schematically showing a snubber circuit mounting example in a conventional power semiconductor module. As shown in the figure, a snubber circuit 108 is provided between a P terminal 101 and an N terminal 102 outside a power semiconductor module 100 in which a plurality of arm portions (partial circuit portions) are integrated. In such a connection of the snubber circuit 108, it is inevitable that the inductance component in the internal wiring of the U-phase circuit unit 5U, the V-phase circuit unit 5V, and the W-phase circuit unit 5W increases as the distance from the snubber circuit 108 increases. .

  On the other hand, in the power semiconductor module of the first embodiment, the inductance components of the U-phase circuit unit 5U, V-phase circuit unit 5V, and W-phase circuit unit 5W that are modularized are effectively reduced by the above-described snubber circuit mounting structure. It is possible to arrange the snubber circuit 8 corresponding to the closest distance that can be realized. For this reason, the power semiconductor module of Embodiment 1 can effectively reduce the inductance components of the U-phase circuit unit 5U, the V-phase circuit unit 5V, and the W-phase circuit unit 5W.

  As a result, the power semiconductor module of the first embodiment can effectively operate the surge voltage suppression function by the snubber circuit 8 while realizing the reduction of the inductance component, so that a high surge voltage for each of the plurality of arm portions. The suppression effect can be exhibited with good uniformity.

<Embodiment 2>
FIGS. 4 and 5 are explanatory diagrams schematically showing the mounting state of the snubber circuit 8 by the upper mounting portion P1i and the lower mounting portion P2i in the power semiconductor module of the second embodiment. FIG. 4 shows a sectional structure, and FIG. 5 shows a perspective view seen obliquely from above.

  In the second embodiment, a lid 9A provided above the inverter circuit 10 shown in FIGS. 1 and 2 is provided. After the lid portion 9A is mounted on the inverter circuit 10, the internal inverter circuit 10 is shielded from the outside.

  The lid portion 9A has three sets of mounting holes 91 and 92 (a plurality of first and second mounting portions) provided corresponding to the three sets of upper mounting portions P1i and lower mounting portions P2i (i = 1 to 3). Hole). 4 and 5, for convenience of explanation, a pair of mounting holes 91 and 92 corresponding to one set of the upper mounting part P1i and the lower mounting part P2i are shown as representatives. Corresponds to three sets of upper mounting portions P1i and lower mounting portions P2i, and three sets of mounting holes 91 and 92 are provided in the lid portion 9A.

  In the power semiconductor module according to the second embodiment, each of the three sets of mounting holes 91 and 92 provided in the lid portion 9A passes through the corresponding mounted terminal 81 (one terminal) of the corresponding snubber circuit 8 so as to pass through the upper mounting portion. It is characterized in that it can be attached to P1i and can be attached to the lower attachment portion P2i through the attached terminal 82 (the other terminal) of the corresponding snubber circuit 8.

  As described above, the power semiconductor module according to the second embodiment includes the mounting portion pair P1i to which the snubber circuit 8 can be attached to and detached from each arm (one unit of inverter circuit portion) by the same insertion / removal operation as in the first embodiment. A structure in which the snubber circuit 8 is combined with the power semiconductor module by providing mounting holes 91 and 92 through which the mounting terminals 81 and 82 of the snubber circuit 8 can be inserted and passed in the lid portion 9A. Can be realized.

  That is, the power semiconductor module according to the second embodiment further includes a cover portion 9A having three sets of mounting holes 91 and 92 in addition to the three sets of mounting portion pairs P1i and P2i. Since the configuration in which the snubber circuit 8 is directly provided can be realized relatively easily, even after the apparatus is completed, there is an effect that a plurality of types of snubber circuits 8 can be selectively used according to the needs of the user.

  As a result, the power semiconductor module of the second embodiment can appropriately select the appropriate number of snubber circuits 8 according to the needs of the user, and can be selected depending on the main circuit (capacitor (smoothing electrolytic capacitor, film capacitor, etc.)). The constant can be easily optimized.

<Embodiment 3>
6 and 7 are explanatory views schematically showing the mounting state of the snubber circuit 8 by the upper mounting portion P1i and the lower mounting portion P2i in the power semiconductor module of the third embodiment. FIG. 6 shows a cross-sectional structure, and FIG. 7 shows a perspective view viewed obliquely from above.

  In the third embodiment, a lid portion 9B provided above the inverter circuit 10 shown in FIGS. 1 and 2 is provided. After the lid portion 9B is mounted on the inverter circuit 10, the internal inverter circuit 10 is shielded from the outside.

  The lid portion 9B has three snubber attachment holes 93 (a plurality of snubber attachments) provided corresponding to the three snubber circuits 8 attached to the three sets of the upper attachment portion P1i and the lower attachment portion P2i (i = 1 to 3). Hole). 6 and 7, for the convenience of explanation, one snubber mounting hole 93 corresponding to one snubber circuit 8 is shown as a representative, but actually, three sets of upper mounting portions P1i and lower steps are shown. Corresponding to the mounting portion P2i and the three snubber circuits 8, three snubber mounting holes 93 are provided in the lid portion 9B.

  The three snubber mounting holes 93 are inserted into the corresponding snubber circuit 8 while penetrating through the main body portion (portions other than the mounted terminals 81 and 82), while the mounted terminal 81 provided below the main body portion is inserted into the upper mounting portion. The cover 9B is provided on the lid 9B so as to be mounted on P1i and the mounted terminal 82 can be mounted on the lower mounting portion P2i.

  As described above, the power semiconductor module according to the third embodiment is provided with the detachable mounting portion pair P1i and P2i for each arm (one unit of inverter circuit portion) as in the first and second embodiments. Furthermore, by providing a snubber mounting hole 93 that can be fitted and fixed while penetrating the main body portion of the snubber circuit 8 in the lid portion 9B, a structure in which the snubber circuit 8 is combined with the power semiconductor module can be realized. .

  That is, the power semiconductor module of the third embodiment further includes a lid portion 9B having three snubber mounting holes 93 in addition to the three sets of mounting portion pairs P1i and P2i, so that the main body of the snubber circuit 8 is provided in the lid portion 9B. Since the configuration for directly fixing the unit can be realized relatively easily, there is an effect that a plurality of types of snubber circuits 8 can be selectively used according to the needs of the user even after the apparatus is completed.

  Furthermore, since the power semiconductor module according to the third embodiment can be stably fixed by inserting the main body portion of the snubber circuit 8 through the snubber mounting hole 93, the snubber circuit 8 There is also an effect of preventing the drop-out after the attachment.

<Embodiment 4>
FIG. 8 and FIG. 9 are explanatory diagrams schematically showing the mounting state of the snubber circuit 8 by the upper mounting portion P1i and the lower mounting portion P2i in the power semiconductor module of the fourth embodiment. FIG. 8 shows a sectional structure, and FIG. 9 shows a perspective view seen obliquely from above.

  In the fourth embodiment, a lid portion 9C provided above the inverter circuit 10 shown in FIGS. 1 and 2 is provided. After the lid portion 9C is mounted on the inverter circuit 10, the internal inverter circuit 10 is shielded from the outside.

  The lid portion 9C is provided with three snubber circuits 8 on its bottom surface, and these three snubber circuits 8 can be mounted on three sets of upper mounting portions P1i and lower mounting portions P2i (i = 1 to 3). 8 and 9, for convenience of explanation, a mode in which one snubber circuit 8 is provided on the bottom surface of the lid portion 9C is shown as a representative, but in reality, three snubber circuits 8 are provided on the lid portion 9C. It is provided on the bottom.

  Then, the lid portion 9C, with respect to the three sets of mounting portion pairs P1i and P2i, mounts the mounted terminal 81 of the snubber circuit 8 having the mounted terminals 81 and 82 on the upper mounting portion P1i and mounts the mounted terminal 82 on the lower stage. The three snubber circuits 8 are arranged and fixed on the bottom surface so that the snubber circuit mounting structure configured to be mounted on the part P2i is realized.

  As described above, the power semiconductor module of the fourth embodiment is provided with the detachable mounting portion pairs P1i and P2i for each arm (one unit of inverter circuit portion) as in the first to third embodiments. Furthermore, by providing the three snubber circuits 8 so that the snubber circuit mounting structure is realized on the bottom surface of the lid 9C, a structure in which the snubber circuit 8 is combined with the power semiconductor module can be realized.

  That is, the power semiconductor module according to the fourth embodiment further includes a lid portion 9C having three snubber circuits 8 provided on the bottom surface in addition to the three sets of mounting portion pairs P1i and P2i. 9C can be attached to the entire circuit portion relatively easily.

  For this reason, the power semiconductor module according to the fourth embodiment can selectively use a plurality of types of snubber circuits 8 together with the lid 9C according to the needs of the user even after the device is completed, and the lid 9C. Since the snubber circuit 8 can be stored below the lid portion 9C after mounting, the power semiconductor module with snubber circuit can be reduced in size and space.

<Embodiment 5>
10 and 11 are perspective views schematically showing the mounting state of the snubber circuit 8 by the upper mounting portion P1i (lower mounting portion P2i) in the power semiconductor module of the fifth embodiment. FIG. 10 shows a non-wearing state, and FIG. 11 shows a wearing state.

  As shown in these drawings, the upper mounting portion P1i (lower mounting portion P2i) is configured by a combination of conductive pattern members 53 and 54 selectively formed on a P terminal wiring pattern 51 (N terminal wiring pattern 52). The tip portions 53a and 54a formed so as to face each other and protrude upward are substantial portions of the upper mounting portion P1i. The conductive pattern members 53 and 54 are made of a conductor material that exerts an elastic force at least between the tip portions 53a and 54a. Therefore, the conductive pattern members 53 and 54 have at least the tip portions 53a and 54a as a spring structure.

  Thus, the front-end | tip parts 53a and 54a of the electroconductive pattern members 53 and 54 in the power semiconductor module of Embodiment 4 are comprised as each substantial part of the mounting parts P11-P13 and the mounting parts P21-P23.

  As shown in FIG. 10, when the mounted terminal 81 (82) of the snubber circuit 8 is not mounted, that is, when no external force is applied to the conductive pattern members 53 and 54, the conductive pattern member. By the extending action of 53 and 54, the tip portions 53a and 54a are brought into contact with each other, and the conductive pattern members 53 and 54 are electrically connected to each other. When mounted, the upper portions of the tip portions 53a and 54a are formed to warp away from each other, thereby having a tip spread portion 59.

  On the other hand, as shown in FIG. 11, the mounted terminal 81 (82) of the snubber circuit 8 is inserted from above the tip portions 53a and 54a with the tip wide portions 59 (see FIG. 10) of the tip portions 53a and 54a as inlets. The tip portions 53a and 54a are separated by the contraction action of the tip portions 53a and 54a accompanying the insertion of the attached terminal 81, and the attached terminal 81 is sandwiched to realize the snubber circuit attachment structure.

  Further, when the mounted terminal 81 in the mounted state is pulled upward from the upper mounting portion P1i, and brought into the non-mounted state, the state returns to the state shown in FIG. 10 again due to the extending action of the tip portions 53a and 54a, and the conductive pattern member 53 and 54 are electrically connected.

  As described above, in the fifth embodiment, the upper mounting portion P1i (lower mounting portion P2i) is configured by the conductive pattern members 53 and 54 whose tip portions 53a and 54a have an elastic function. And the tip part 53a and 54a used as a pair of partial mounting part has implement | achieved the snubber circuit mounting structure by inserting the to-be-attached terminal 81 (82) of the snubber circuit 8 between tip part 53a and 54a.

  In addition, when the conductive pattern members 53 and 54 are not attached to the attached terminal 81 of the snubber circuit 8, the tip portions 53a and 54a come into contact with each other by the extension action provided in the spring structure having an elastic function. The conductive pattern members 53 and 54 have an electrical connection function for electrical connection.

  Thus, since the upper mounting portion P1i (lower mounting portion P2i) in the power semiconductor module of the fifth embodiment has an electrical connection function when the mounted terminal 81 (82) is not mounted, even after the device is completed, The presence or absence of the snubber circuit 8 can be selected in addition to the selective use of a plurality of types of snubber circuits according to the needs of the user.

  Furthermore, the tip portions 53a and 54a, which are a pair of elastic portions constituting the upper mounting portion P1i (lower mounting portion P2i) in the fifth embodiment, are springs when the mounted terminal 81 (82) of the snubber circuit 8 is not mounted. Since the electrical connection function is realized by bringing the tip portions 53a and 54a into contact with each other by the extending action provided in the structure, selection of the presence or absence of the snubber circuit can be realized with a relatively simple configuration. For example, regarding each of the U phase, the V phase, and the W phase, it is possible to select whether to use a snubber circuit for each phase.

<Embodiment 6>
12 and 13 are perspective views schematically showing the structure of the upper mounting portion P1i (lower mounting portion P2i) in the power semiconductor module of the sixth embodiment. FIG. 12 shows a state where the conductive member 58 is not attached, and FIG. 13 shows a state where the conductive member 58 is attached.

  As shown in these drawings, the upper mounting portion P1i (lower mounting portion P2i) is configured by a combination of conductive pattern members 55 and 56 selectively formed on a P terminal wiring pattern 51 (N terminal wiring pattern 52). In the conductive pattern members 55 and 56, the arc-shaped front end portions 55a and 56a (a pair of outer frame portions) that are separated from each other along the outer periphery of the hollow portion 57 that is circular in plan view. Is a substantial part of the upper mounting portion P1i.

  As described above, in the power semiconductor module according to the sixth embodiment, the pair of tip portions 55a and 56a configured by the substantially columnar structure having the cavity portion 57 are substantial portions of the mounting portions P11 to P13 and the mounting portions P21 to P23, respectively. It is configured as.

  The cavity 57 provided between the inner surfaces of the tip portions 55a and 56a is formed in a shape that matches the mounted terminal 81 (82) of the snubber circuit 8. For this reason, a snubber circuit mounting structure is realized by inserting the mounted terminal 81 (82) of the snubber circuit 8 into the cavity 57.

  On the other hand, as shown in FIG. 12, since the tip portions 55a and 56a are arranged separately from each other when the mounted terminal 81 (82) is not mounted, the conductive pattern members 55 and 56 are electrically insulated from each other. It becomes a state.

  However, as shown in FIG. 13, like the mounted terminal 81, by inserting a conductive member 58 having a shape matching the cavity 57 into the cavity 57, the outer peripheral surface of the conductive member 58 and the tip portions 55a and 56a By contacting the inner surface, the conductive pattern members 55 and 56 are electrically connected via the conductive member 58. Therefore, in the power semiconductor module of the sixth embodiment, by inserting the conductive member 58, the conductive pattern members 55 and 56 are electrically connected even when the mounted terminal 81 of the snubber circuit 8 is not mounted. It has an electrical connection function.

  Thus, the upper mounting portion P1i (lower mounting portion P2i) in the power semiconductor module of the sixth embodiment has an electrical connection function via the conductive member 58 when the mounted terminal 81 (82) is not mounted. Even after the device is completed, in addition to the selective use of a plurality of types of snubber circuits according to the needs of the user, the selection of the presence or absence of a snubber circuit can be realized with a relatively simple configuration as in the fifth embodiment. it can.

  Furthermore, the power semiconductor module of the sixth embodiment is a pair of outer frame portions formed separately from each other along the outer periphery of the insertion cavity portion 57 of the mounted terminal 81 (82) of the snubber circuit 8. The conductive pattern members 55 and 56 are electrically connected by contact between the outer peripheral surface of the mounted terminal 81 and the inner surfaces of the distal end portions 55a and 56a when the mounted terminal 81 is mounted. Yes. For this reason, by suppressing the contact resistance between the mounted terminal 81 and the tip portions 55a and 56a, the surge voltage suppression function by the snubber circuit 8 can be exhibited with good stability.

  In FIGS. 12 and 13, a substantially cylindrical structure is shown as the structure of the pair of tip portions 55a and 56a (including the cavity portion 57), but it matches the shape of the mounted terminal 81 (82) and the conductive member 58. If the structure is such that the conductive pattern members 55 and 56 can be electrically connected via the mounted terminal 81 and the conductive member 58, the shape of the pair of tip portions 55a and 56a is another structure. Also good.

<Embodiment 7>
FIG. 14 is an explanatory diagram schematically showing a circuit configuration of a power semiconductor module (semiconductor device) according to the seventh embodiment of the present invention.

  As shown in the figure, the power semiconductor module includes a U-phase circuit unit 5U, a V-phase circuit unit 5V, and a W-phase circuit, each of which includes three arm units (partial circuit units) that constitute a unit of inverter circuit unit. It has the inverter circuit 10B comprised from the part 5W.

  The power semiconductor module according to the seventh embodiment is similar to the power semiconductor module according to the first embodiment shown in FIGS. 1 to 3 in that the P terminal wiring pattern 51 (see FIG. 2) for the P terminal 1 is replaced with the U phase circuit portion 5U. , V-phase circuit section 5V and W-phase circuit section 5W are allocated almost equally, and N terminal wiring pattern 52 for N terminal 2 (see FIG. 2) is assigned to U-phase circuit section 5U, V-phase circuit section 5V, and Almost evenly assigned as an area for the W-phase circuit section 5W.

  Further, similarly to the mounting portions P11 to P13 and the mounting portions P21 to P23 of the first embodiment shown in FIG. 2, the U-phase circuit portion 5U, the V-phase circuit portion 5V, and the W-phase circuit portion 5W of the P terminal wiring pattern 51 are used. The mounting portions P31, P32, and P33 are provided on the above-described allocation region for use, and on the above-described allocation region for the U-phase circuit unit 5U, the V-phase circuit unit 5V, and the W-phase circuit unit 5W of the N terminal wiring pattern 52. Mounting portions P41, P42 and P43 are provided.

  Note that each of the mounting portions P31 to P33 and the mounting portions P41 to P43 is, for example, the pair of tip portions 53a and 54a of the fifth embodiment shown in FIGS. 10 and 11 or the implementation shown in FIGS. It is comprised by a pair of partial mounting part (a pair of outer frame part) equivalent to the structure of a pair of front-end | tip parts 55a and 56a of the form 6. That is, in FIGS. 10 to 13, a structure in which the upper mounting portion P1i and the lower mounting portion P2i are replaced with the upper mounting portion P3i and the lower mounting portion P4i is adopted as the mounting portions P31 to P33 and the mounting portions P41 to P43. .

  As described above, the mounting portions P31 to P33 and the mounting portions P41 to P43 in the seventh embodiment are each configured by the pair of partial mounting portions described above, and the pair of partial mountings of the mounted terminals 81 (82) of the snubber circuit 8 are performed. The above-described snubber circuit mounting structure is realized by insertion between the parts.

  Furthermore, the pair of partial mounting portions have an electrical connection function (see FIGS. 10 and 13) that electrically connects the pair of partial mounting portions even when the mounted terminal 81 of the snubber circuit 8 is not mounted. doing.

  As described above, the mounting portions P31 to P33 and the mounting portions P41 to P43 of the power semiconductor module according to the seventh embodiment can each mount the mounted terminal 81 and can be electrically connected when the mounted terminal 81 is not mounted. Connection function. Therefore, the seventh embodiment has an effect that even after the device is completed, the presence or absence of the snubber circuit 8 can be selected in addition to the selective use of a plurality of types of snubber circuits according to the needs of the user.

  In the seventh embodiment, the structure shown in the fifth or sixth embodiment is exemplified as the structure of each of the mounting portions P31 to P33 and the mounting portions P41 to P43. However, the structure is not limited to the above-described structure. Other structures may be employed as long as the structure has the mounting function of the mounted terminal 81 and the electrical connection function when not mounted.

<Eighth embodiment>
FIG. 15 is an explanatory view schematically showing a mounting state of the reactor 40 of the snubber circuit 8 by the upper mounting portion P3i (lower mounting portion P4i) in the power semiconductor module of the eighth embodiment.

  As shown in the figure, the upper mounting portion P3i (lower mounting portion P4i) is composed of, for example, the combination of the conductive pattern members 53 and 54 shown in the fifth embodiment, and is formed so as to protrude upward facing each other. The pair of tip portions 53a and 54a to be used are substantial portions of the upper mounting portion P3i. That is, the upper mounting portion P3i (P4i) has a structure substantially equivalent to the upper mounting portion P1i (P2i) of the fifth embodiment.

  However, in Embodiment 8, the reactor 40 of the snubber circuit 8L in which the reactor 40 is provided in at least one of the mounted terminals 81 and 82 (one terminal and the other terminal) is added as a mounting target. Different from other embodiments. The reactor 40 is configured by providing an insulator 43 between the electrodes 41 and 42.

  In the power semiconductor module according to the eighth embodiment, the mounting portions P31 to P33 and the mounting portions P41 to P43 (a plurality of first and second mounting portions) replace the mounted terminal 81 of the snubber circuit 8 with the reactor 40 in the upper stage. At least one reactor part mounting is realized among the first reactor part mounting to be mounted on the mounting part P3i and the second reactor part mounting to mount the reactor 40 on the lower mounting part P4i instead of the mounted terminal 82. It has a reactor part mounting structure.

  As shown in FIG. 15, the wide end portion of the pair of tip portions 53a and 54a of the eighth embodiment can be used as an inlet, and the reactor 40 of the snubber circuit 8 can be inserted vertically from above the tip portions 53a and 54a. Then, the contracting action of the pair of tip portions 53a and 54a accompanying the insertion of the reactor 40 separates the tip portions 53a and 54a, thereby sandwiching the tip portion of the reactor 40, thereby realizing the reactor portion mounting structure.

  As described above, the power semiconductor module according to the eighth embodiment realizes the reactor mounting structure by inserting the reactor 40 of the snubber circuit 8L between the tip portions 53a and 54a of the conductive pattern members 53 and 54.

  As a result, the power semiconductor module according to the eighth embodiment can exhibit the function of preventing the oscillation of the voltage waveform by the reactor 40 of the snubber circuit 8L by the reactor part mounting structure.

  The reactor mounting structure described above may be realized by at least one of the upper mounting part P3i and the lower mounting part P4i, and the other is the reactor mounting structure or the mounted terminal as in the first to seventh embodiments. It is conceivable to adopt a snubber circuit mounting structure 81 (82).

  Further, the reactor mounting structure is not limited to the structure of the pair of tip portions 53a and 54a shown in FIG. 15, and it is needless to say that any structure can be used as long as the reactor 40 is detachable.

  It should be noted that the present invention can be freely combined with each other within the scope of the invention, and each embodiment can be appropriately modified or omitted.

  1 P terminal, 2 N terminal, 5U U phase circuit part, 5V V phase circuit part, 5W W phase circuit part, 8, 8L snubber circuit, 9A-9C lid part, 10, 10B inverter circuit, 11-13, 21-21 23 IGBT, 40 reactor, 51 P terminal wiring pattern, 52 N terminal wiring pattern, 53-56 conductive pattern member, 81, 82 Mounted terminal, 91, 92 mounting hole, 93 snubber mounting hole, D11-D13, D21 to D23 Diode, P11 to P13, P21 to P23, P31 to P33, P41 to P43 (upper and lower stages) mounting part.

Claims (7)

A semiconductor device having an entire circuit unit configured by integrating a plurality of partial circuit units each provided by being electrically connected between a first terminal and a second terminal which are external terminals,
A first wiring pattern electrically connected to the first terminal;
A second wiring pattern electrically connected to the second terminal,
The plurality of partial circuit portions are respectively on the corresponding first and second partial circuit formation regions among the plurality of first and second partial circuit formation regions allocated on the first and second wiring patterns. At least partly formed,
A plurality of first mounting portions provided on the plurality of first partial circuit formation regions;
A plurality of second mounting portions provided on the plurality of second partial circuit formation regions;
Each of the plurality of first and second mounting portions is configured such that one terminal of a snubber circuit having one terminal and the other terminal is mounted on the first mounting portion and the other terminal is mounted on the second mounting portion. It is by the, have a snubber circuit mounting structure for mounting a plurality of snubber circuits in one-to-one correspondence with between a plurality of first and second mounting portions configured to,
A reactor part is provided in at least one terminal among the one terminal and the other terminal of the snubber circuit,
The plurality of first and second mounting portions include a first reactor portion mounting for mounting the reactor portion on the first mounting portion instead of one terminal of the snubber circuit, and the reactor portion instead of the other terminal. Of the second reactor part mounting that is mounted on the second mounting part, it has a reactor part mounting structure that realizes at least one reactor part mounting,
Semiconductor device. The semiconductor device according to claim 1,
A lid provided above the entire circuit unit;
The lid portion has a plurality of first and second mounting holes provided corresponding to the plurality of first and second mounting portions,
Each of the plurality of first and second mounting hole portions mounts one terminal of the snubber circuit to the corresponding first mounting portion through the first mounting hole portion and the other terminal to the second mounting portion. It is provided in the lid part so as to be attached to the corresponding second attachment part through the hole for use,
Semiconductor device. The semiconductor device according to claim 1,
A lid provided above the entire circuit unit;
The lid portion is provided corresponding to the plurality of first and second mounting portions, each having a plurality of snubber mounting holes penetrating the lid portion,
Each of the plurality of snubber attachment holes is provided so as to fit and attach a corresponding snubber circuit so as to realize the snubber circuit mounting structure.
Semiconductor device. The semiconductor device according to claim 1,
A lid portion provided above the entire circuit portion;
A plurality of snubber circuits provided on the bottom surface of the lid portion;
The lid portion is characterized in that the plurality of snubber circuits are arranged on a bottom surface so that the snubber circuit mounting structure is realized for each of the plurality of snubber circuits.
Semiconductor device. The semiconductor device according to any one of claims 1 to 4, wherein:
Each of the plurality of first and second mounting portions is constituted by a pair of partial mounting portions, and the pair of partial mounting portions are the pair of partial mounting portions of the mounted terminal that is one terminal or the other terminal of the snubber circuit. Realize the snubber circuit mounting structure by inserting between,
The pair of partial mounting portions have an electrical connection function of electrically connecting the pair of partial mounting portions even when the mounted terminal of the snubber circuit is not mounted.
Semiconductor device. The semiconductor device according to claim 5,
The pair of partial mounting portions includes a pair of elastic portions,
The pair of elastic parts realizes the electrical connection function by contacting the pair of elastic parts by an extension action when the attached terminal of the snubber circuit is not attached, and the attached terminal is inserted when the attached terminal is attached. The snubber circuit mounting structure is realized by separating the pair of elastic portions by the contracting action accompanying the pinching and sandwiching the mounted terminal.
Semiconductor device. A semiconductor device having an entire circuit unit configured by integrating a plurality of partial circuit units each provided by being electrically connected between a first terminal and a second terminal which are external terminals,
A first wiring pattern electrically connected to the first terminal;
A second wiring pattern electrically connected to the second terminal,
The plurality of partial circuit portions are respectively on the corresponding first and second partial circuit formation regions among the plurality of first and second partial circuit formation regions allocated on the first and second wiring patterns. At least partly formed,
A plurality of first mounting portions provided on the plurality of first partial circuit formation regions;
A plurality of second mounting portions provided on the plurality of second partial circuit formation regions;
Each of the plurality of first and second mounting portions is configured such that one terminal of a snubber circuit having one terminal and the other terminal is mounted on the first mounting portion and the other terminal is mounted on the second mounting portion. Having a snubber circuit mounting structure for mounting a plurality of snubber circuits in a one-to-one correspondence between the plurality of first and second mounting portions.
Each of the plurality of first and second mounting portions is constituted by a pair of partial mounting portions, and the pair of partial mounting portions are the pair of partial mounting portions of the mounted terminal that is one terminal or the other terminal of the snubber circuit. Realize the snubber circuit mounting structure by inserting between,
The pair of partial mounting portions have an electrical connection function of electrically connecting the pair of partial mounting portions even when the mounted terminal of the snubber circuit is not mounted.
The pair of partial mounting portions includes a pair of outer frame portions that are formed separately from each other along the outer periphery of the cavity portion for insertion of the mounted terminal of the snubber circuit,
The pair of outer frame parts are separated and electrically insulated from each other when the attached terminal is not attached, and are electrically connected to each other via the attached terminal when the attached terminal is attached. Realizing the electrical connection function by inserting a matching shape of the conductive member into the cavity,
Semiconductor device.

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