JP6216349B2 - 層構造の製造方法 - Google Patents
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- JP6216349B2 JP6216349B2 JP2015097663A JP2015097663A JP6216349B2 JP 6216349 B2 JP6216349 B2 JP 6216349B2 JP 2015097663 A JP2015097663 A JP 2015097663A JP 2015097663 A JP2015097663 A JP 2015097663A JP 6216349 B2 JP6216349 B2 JP 6216349B2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
- H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
- H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02373—Group 14 semiconducting materials
- H01L21/02381—Silicon, silicon germanium, germanium
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02439—Materials
- H01L21/02455—Group 13/15 materials
- H01L21/02458—Nitrides
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02494—Structure
- H01L21/02496—Layer structure
- H01L21/02505—Layer structure consisting of more than two layers
- H01L21/02507—Alternating layers, e.g. superlattice
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- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02538—Group 13/15 materials
- H01L21/0254—Nitrides
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
- H01L21/02639—Preparation of substrate for selective deposition
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- H—ELECTRICITY
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- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0093—Wafer bonding; Removal of the growth substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/26—Materials of the light emitting region
- H01L33/30—Materials of the light emitting region containing only elements of group III and group V of the periodic system
- H01L33/32—Materials of the light emitting region containing only elements of group III and group V of the periodic system containing nitrogen
Description
− 窒化アルミニウムからなる核形成層(nucleation layer)2。
− 窒化アルミニウムからなるバッファ層3。この層は、核形成層2よりも高い成長温度(例えば少なくとも1000℃)で堆積させる。
− AlGaN層4。この層内では、アルミニウム濃度が成長方向Rに最大95%から少なくとも15%に段階的に減少する。
− 最初のGaN層5。
− AlN層またはAlGaN層7。この層は、約850℃の低い成長温度で成長させることができる。
− 第2のGaN層8。
− さらなるAlN層またはAlGaN層10。この層は約850℃で成長させることができる。
− 第3のGaN層11。この層の中にマスキング層12が配置される。
− AlN層またはAlGaN層15。
− シリコン表面1aを有するキャリア基板1。
− 核形成層2およびバッファ層3。これらの層それぞれは、例えば窒化アルミニウムからなり、合わせて約200nmの厚さとする。
− GaN層。この層は擬似格子整合的に成長させ、約100nmの厚さを有する。
− 第1のマスキング層12。この層は例えば窒化珪素を使用して形成し、1nm〜2nmの範囲内の厚さを有する。
− さらなるGaN層8。この層は約700nmの厚さを有する。
− 第1のAlN層10。この層は例えば約850℃の温度で成長させることができる。
− 第3のGaN層11。この層は例えば約700nmの厚さを有する。
− さらなるAlN層。この層は約850℃の低い成長温度で成長させることができる。
Claims (10)
- 層構造の製造方法であって、
− シリコン表面(1a)を有するキャリア基板(1)を形成するステップと、
− 前記シリコン表面(1a)上に、成長方向(R)に積層体(100)を堆積させるステップと、
を含んでおり、
− 前記積層体(100)が、窒化ガリウムを使用して形成されるGaN層(5)を含んでおり、
− 前記積層体(100)が、窒化珪素を使用して形成される第1のマスキング層(12)を含んでおり、
− 前記成長方向(R)において前記GaN層(5)の少なくとも一部分の後ろに、前記第1のマスキング層(12)が続いており、
− 前記積層体(100)が少なくとも2層のGaN層(5,8,11)を含んでおり、
− GaN層(5,8,11)それぞれの中にマスキング層が配置されており、
前記第1のマスキング層(12)は、前記積層体(100)において少なくとも1つのGaN層を成長させた後に堆積され、
前記積層体(100)は、前記GaN層(5)と前記シリコン表面(1a)との間にマスキング層が存在せず、
AlGaN遷移層(4)は、前記積層体(100)内において、AlNバッファ層(3)と第1のGaN層(5)との間に配置されている、
方法。 - − 前記第1のマスキング層(12)がGaN層の中に配置される、
請求項1に記載の方法。 - − 前記第1のマスキング層(12)が2層のGaN層に直接隣接している、
請求項1または請求項2に記載の方法。 - − 少なくとも2層のGaN層(5,8,11)が、前記成長方向(R)において前記第1のマスキング層(12)より上流に配置される、
請求項1から請求項3のいずれか一項に記載の方法。 - − 前記積層体(100)が少なくとも2層のGaN層(5,8,11)を含んでおり、
− 前記成長方向(R)においてGaN層(5,8,11)それぞれの後ろにAlN層(7,10,15)が続いている、
請求項1から請求項4のいずれか一項に記載の方法。 - − 前記積層体(100)が少なくとも2層のGaN層(5,8,11)を含んでおり、
− 前記成長方向(R)においてGaN層(5,8,11)それぞれの後ろにAlGaN層(7,10,15)が続いている、
請求項1から請求項4のいずれか一項に記載の方法。 - − 前記積層体(100)が少なくとも2層のGaN層(5,8,11)を含んでおり、
− 前記成長方向(R)においてGaN層(5,8,11)それぞれの後ろに、AlGaN層(7,10,15)もしくはAlN層(7,10,15)またはその両方が続いている、
請求項1から請求項4のいずれか一項に記載の方法。 - 前記AlGaN層(7,10,15)の少なくとも1層におけるGaの濃度が、少なくとも5%から最大で10%の範囲内である、
請求項6または請求項7に記載の方法。 - 前記AlGaN層(4)層内において、アルミニウム濃度が成長方向(R)に最大95%から少なくとも15%に段階的に減少する、
請求項1から請求項8のいずれか一項に記載の方法。 - 前記AlGaN遷移層(4)は、前記AlNバッファ層(3)および前記第1のGaN層(5)に直接隣接している、
請求項1から請求項9のいずれか一項に記載の方法。
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DE102009047881.7A DE102009047881B4 (de) | 2009-09-30 | 2009-09-30 | Verfahren zur Herstellung einer epitaktisch hergestellten Schichtstruktur |
DE102009047881.7 | 2009-09-30 |
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JP2013506980A (ja) | 2013-02-28 |
JP2015181180A (ja) | 2015-10-15 |
CN105551932A (zh) | 2016-05-04 |
EP2483914B1 (de) | 2017-09-06 |
KR101808197B1 (ko) | 2017-12-12 |
US8828768B2 (en) | 2014-09-09 |
JP6463813B2 (ja) | 2019-02-06 |
WO2011039181A1 (de) | 2011-04-07 |
DE102009047881B4 (de) | 2022-03-03 |
US20130065342A1 (en) | 2013-03-14 |
CN105551932B (zh) | 2019-04-09 |
US20140329350A1 (en) | 2014-11-06 |
CN102576656A (zh) | 2012-07-11 |
JP2018022909A (ja) | 2018-02-08 |
US9184337B2 (en) | 2015-11-10 |
KR20120081177A (ko) | 2012-07-18 |
DE102009047881A1 (de) | 2011-04-21 |
JP5748758B2 (ja) | 2015-07-15 |
CN102576656B (zh) | 2016-01-20 |
EP2483914A1 (de) | 2012-08-08 |
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