JP6194651B2 - Information processing device - Google Patents

Information processing device Download PDF

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JP6194651B2
JP6194651B2 JP2013126535A JP2013126535A JP6194651B2 JP 6194651 B2 JP6194651 B2 JP 6194651B2 JP 2013126535 A JP2013126535 A JP 2013126535A JP 2013126535 A JP2013126535 A JP 2013126535A JP 6194651 B2 JP6194651 B2 JP 6194651B2
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endpoint
power
root complex
notification
switch
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JP2015001867A (en
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正太郎 宮本
正太郎 宮本
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富士ゼロックス株式会社
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Description

  The present invention relates to an information processing apparatus.

  In an information processing apparatus having various devices, there is known a technique for shutting off the power of a device and shifting to a power saving state (Patent Documents 1 to 5).

JP 2009-176294 A JP 2006-159678 A JP 2012-168589 A JP 2012-176611 A JP 2005-225172 A

  The present invention provides a technique for shutting off the power supply of the first endpoint while supplying power to the second endpoint in an information processing apparatus having a plurality of endpoints in the PCI Express standard.

  The present invention relates to an endpoint in the PCI Express standard, which includes a plurality of endpoints including a first endpoint and a second endpoint, a root complex that controls the plurality of endpoints, the root complex, A switch that relays data transfer to and from a plurality of endpoints, and the route complex has notification means for notifying the first endpoint of the plurality of endpoints of power-off. The root complex has control means for controlling the switch so as to disconnect the link with the first endpoint after the notification, and the first endpoint is configured to Notification means for notifying the root complex that preparation has been completed, Complex, after the notification, the switch, to provide an information processing apparatus having a power shutoff means for shutting off the power supply of the first endpoint.

  The first end point may include a detection unit that detects the disconnection of the link, and the notification unit may perform the notification after the detection unit detects the disconnection of the link.

  The first end point may include processing means for performing a preparation process for power shutdown when the detection means detects the disconnection of the link.

  The notification means may perform the notification after the preparation process is completed.

  The detection unit may start polling the root complex upon receiving the power-off notification and detect the link disconnection based on the polling.

  The switch and the first endpoint are connected via a non-PCI Express signal line, and the switch shuts off the power of the first endpoint by a signal supplied via the signal line. May be.

  When the second endpoint receives a communication unit that communicates with an external device, a storage unit that stores data, and a data accumulation command according to the notification of power-off, the second endpoint receives the command from the external device via the communication unit. The received data is stored in the storage means, and when the switch receives a data output command after the power of the first endpoint is shut off, the data stored in the storage means is You may output to a complex.

  The root complex assigns identification numbers to a plurality of buses between the root complex, the switch, and a plurality of endpoints to which power is supplied among the plurality of endpoints, and the switch includes the first endpoint. The identification number may be reassigned after the power source is shut off.

  The first endpoint has a register for storing data, and the root complex has the power supply to the register through the link with the link between the switch and the first endpoint established. The notification of power shutdown may be performed by writing data indicating the notification of shutdown.

According to the first aspect of the present invention, in the PCI Express standard, the power source of the first endpoint can be shut off while the power source is supplied to the second endpoint.
According to the second aspect of the present invention, the power supply can be shut off after the link disconnection is detected.
According to the third aspect of the present invention, when the power supply of the first endpoint is shut off, it is possible to perform a preparation process for power shutoff.
According to the invention which concerns on Claim 4, a power supply can be interrupted | blocked after a preparation process is completed.
According to the fifth aspect of the present invention, link disconnection can be detected based on polling.
According to the sixth aspect of the invention, the power supply of the first endpoint can be shut off without affecting the operation of the PCI Express standard.
According to the seventh aspect of the present invention, loss of data from an external device can be prevented.
According to the invention which concerns on Claim 8, the malfunction of the operation | movement resulting from the discontinuity of an identification number can be prevented.
According to the ninth aspect of the present invention, it is possible to notify the power shutdown via the register.

The figure which shows the structure of the information processing apparatus 1 which concerns on one Embodiment. 3 is a sequence chart showing an outline of the operation of the information processing apparatus 1. The figure which illustrates assignment of a bus number. 10 is a flowchart showing a specific example of the operation of the route complex 31. 7 is a flowchart showing a specific example of the operation of the endpoint 34. 7 is a flowchart showing an operation mode switching process of the endpoint 33. 6 is a flowchart showing processing of data received by the endpoint 33.

1. Configuration FIG. 1 is a diagram illustrating a configuration of an information processing apparatus 1 according to an embodiment. The information processing apparatus 1 is, for example, an image forming apparatus (more specifically, an apparatus having functions as a facsimile, a scanner, and a printer). The information processing apparatus 1 is not limited to an image forming apparatus, and may be a general-purpose personal computer, for example. The information processing apparatus 1 includes a CPU 10, a memory 20, and a PCI device group 30. The CPU 10 is a processing device that performs various processes (calculations) in order to control each component of the information processing apparatus 1. The memory 20 is a storage device that functions as a work area when the CPU 10 executes a program.

  The PCI device group 30 is an input / output device group and a control device group thereof according to a predetermined standard, in this example, PCI Express (PCI Express, sometimes referred to as PCIe). The PCI device group 30 includes a root complex 31, a switch 32, an end point 33, and an end point 34. The root complex 31 is a control device that controls other devices included in the PCI device group 30. The root complex 31 is connected to the CPU 10 via the system bus and to the memory 20 via the memory bus. The switch 32 is a device that relays a signal from the root complex 31 to the end point. A plurality of endpoints are connected to the switch 32. In this example, two endpoints, endpoint 33 and endpoint 34, are connected. The endpoint is an input / output device. For example, the end point 33 is a communication device that performs communication via a network, and the end point 34 is a display device. In FIG. 1, only one switch and two endpoints are shown for the sake of simplicity. However, a plurality of switches may be connected to the root complex 31, and one switch includes three switches. Two or more endpoints may be connected. Further, a switch may be further connected to the lower stage of the switch.

  In order to meet the demand for power saving, it may be required to shut off the power of another endpoint while supplying power to one endpoint. However, in PCI Express, there is a problem that the power supply of one endpoint cannot be cut off while power is supplied from the root complex to other endpoints. In the present embodiment, the power of the endpoint 34 is cut off while the power is supplied to the endpoint 33.

  The root complex 31 includes a notification unit 311, a control unit 312, a power cutoff unit 314, and an allocation unit 315. The switch 32 includes link control means 321 and power supply cutoff means 322. The end point 33 includes a communication unit 331, a storage unit 332, a storage control unit 333, and an output unit 334. The end point 34 includes a notification unit 341, a detection unit 342, and a processing unit 343.

  The notification unit 311 notifies the end point 34 of power-off. The control means 312 controls the switch 32 to disconnect the link with the end point 34 after this notification. The detection means 342 detects this link breakage. When the detection unit 342 detects that the link has been disconnected, the processing unit 343 performs a preparation process for power-off. The notification means 341 notifies the root complex 31 that the preparation for power shutdown has been completed. After this notification, the power shut-off means 314 causes the switch 32 to shut off the power of the endpoint 34.

  The communication unit 331 communicates with an external device. The storage unit 332 stores data. When the storage control unit 333 receives a data storage command in response to the power-off command, the storage control unit 333 stores the data received from the external device via the communication unit 331 in the storage unit 332. When the output unit 334 receives a data output command after the switch 32 shuts off the power supply of the endpoint 34, the output unit 334 outputs the data stored in the storage unit 332 to the root complex 31.

  The assigning unit 315 assigns identification numbers to a plurality of buses among the root complex 31, the switch 32, and a plurality of endpoints to which power is supplied among the plurality of endpoints. The assigning means 315 reassigns this identification number after the switch 32 shuts off the power supply of the endpoint 34.

  In this example, the root complex 31, the switch 32, the endpoint 33, and the endpoint 34 each have a processor and a memory (or a register) as hardware elements (all not shown). These processors operate according to a given program or input signal, so that the above functions are implemented in each device.

2. Operation FIG. 2 is a sequence chart showing an outline of the operation of the information processing apparatus 1. The sequence in FIG. 2 is triggered by a predetermined event, for example, an event that a predetermined time has elapsed since the information processing apparatus 1 was last operated by the user. In FIG. 2 and subsequent figures, the root complex, the switch, and the endpoint are denoted as RC, SW, and EP, respectively.

  In step S <b> 10, the root complex 31 issues a power-off notification (or a notification of transition to the energy saving mode) to an endpoint that shuts off the power (endpoint 34 in this example). Further, following the notification of power shutdown, the root complex 31 issues a command to shift to the accumulation mode to an endpoint that does not shut off the power (end point 33 in this example). The accumulation mode is an operation mode in which data received from an external device is not output to the root complex 31 but is accumulated in the internal memory of the endpoint.

  When the notification of power-off is received, the end point 34 starts polling the root complex 31 (step S11). This polling is performed in order to detect that the link with the root complex 31 is disconnected (that is, the link state is disabled). The endpoint 34 determines that the link is maintained while the response to the polling is returned (that is, the link state is enabled), and the response is returned within a predetermined time for the polling. If it is not received, it is determined that the link is disconnected.

  When receiving the instruction to shift to the accumulation mode, the endpoint 33 shifts its own operation mode to the data accumulation mode (step S12). In the data accumulation mode, the endpoint 33 stores the data received from the external device in the storage unit 332.

  When issuing a power-off notification, the root complex 31 issues a command to the switch 32 to disconnect the link with the end-point that shuts off the power (end-point 34 in this example) (step S13).

  Upon receiving the link disconnection command, the switch 32 disconnects the link with the end point (in this example, the end point 34) designated by the command (step S14). When the link with the endpoint 34 is broken, the root complex 31 does not respond to polling from the endpoint 34. Therefore, the end point 34 detects that the link with the root complex 31 is disconnected (step S15). When it is detected that the link is disconnected, the end point 34 executes a process for shifting to the energy saving mode (energy saving transition sequence) (step S16). The shift process to the energy saving mode includes, for example, a process of saving data used when returning from the energy saving mode to the normal mode in the nonvolatile memory. When the transition process to the energy saving mode is completed, the endpoint 34 notifies the route complex 31 that the transition process to the energy saving mode is completed (step S17). At this point, since the link between the root complex 31 and the end point 34 has already been disconnected, this notification is transmitted via a signal line other than the PCI Express standard. Specifically, a signal line other than the PCI Express standard is provided between the endpoint 34 and the switch 32, and a notification that the process of shifting to the energy saving mode is completed is transmitted via this signal line. The

  Upon receiving the notification that the process of shifting to the energy saving mode has been completed, the root complex 31 switches the command for shutting down the power of the endpoint (endpoint 34 in this example) that has completed the process of shifting to the energy saving mode. (Step S18). When receiving a command to cut off the power from the route complex 31, the switch 32 cuts off the power of the designated endpoint (step S19).

  When a command to shut off the power is issued to the switch 32, the route complex 31 reassigns the bus number (identification number) according to a predetermined algorithm (step S20). In the PCI device group 30, a bus between two devices, in this example, a bus between the root complex 31 and the switch 32, a bus between the switch 32 and the endpoint 33, and a switch 32 and the endpoint 34 Each bus is assigned a bus number. The bus number is used in the control based on the PCI Express standard.

  FIG. 3 is a diagram illustrating assignment of bus numbers. FIG. 3A illustrates the assignment of bus numbers before the power of the endpoint 34 is shut off. In this example, a bus number “1” is assigned to the bus between the root complex 31 and the switch 32, a bus number “2” is assigned to the internal bus of the switch 32, and a bus is assigned to the bus between the switch 32 and the endpoint 34. The number “3” is assigned to the bus between the switch 32 and the end point 33, and the bus number “4” is assigned thereto.

  When the link between the switch 32 and the end point 34 is disconnected in this state, the bus number “3” becomes a missing number. If the bus numbers are discontinuous, a malfunction may occur in the operation of the PCI device group 30. Therefore, in the present embodiment, such a problem is prevented by reassigning the bus number after the link is disconnected.

  FIG. 3B illustrates the assignment of bus numbers after the power of the endpoint 34 is shut off. In this example, a bus number “1” is assigned to the bus between the root complex 31 and the switch 32, a bus number “2” is assigned to the internal bus of the switch 32, and a bus is assigned to the bus between the switch 32 and the endpoint 33. The number “3” is assigned to each.

  Refer to FIG. 2 again. When the bus number is reassigned, the root complex 31 issues a storage mode release notification (that is, a notification of transition to the normal mode) to an endpoint that does not shut off the power (in this example, the endpoint 33) (step S1). S21).

  Upon receiving the notification of canceling the accumulation mode, the endpoint 33 sequentially outputs (transfers) the data accumulated in the internal memory to the root complex 31 (in order from the first received data) (step S22). The root complex 31 performs processing according to the data supplied from the end point 33.

  According to this example, the power supply to a specific endpoint (endpoint 34 in the above example) is cut off while power is supplied to another endpoint (endpoint 33 in the above example). Further, at this time, the occurrence of problems due to the discontinuity of the bus numbers is prevented. The above is the outline of the operation of the information processing apparatus 1. Hereinafter, an operation example of each apparatus will be described in more detail.

  FIG. 4 is a flowchart showing a specific example of the operation of the root complex 31 and the switch 32. The flow in FIG. 4 is started when, for example, the CPU 10 instructs to shut off the power supply of the end point 34 (to shift the end point 34 to the energy saving mode).

  In step S <b> 101, the root complex 31 determines whether there is an endpoint that shuts off the power. When it is determined that there is an end point for shutting off the power (S101: YES), the root complex 31 shifts the process to step S102. When it is determined that there is no end point for shutting off the power (S101: NO), the root complex 31 proceeds to step S103.

  In step S102, the root complex 31 sets the value of the flag indicating the power shutdown (that is, the transition to the energy saving mode) to “on” in the configuration space of the endpoint (the endpoint 34 in this example) that shuts off the power. rewrite. The configuration space refers to a register space (or memory space) included in each device. A part of the configuration space is used in the PCI Express standard, but there is a free area that is not used in the PCI Express standard. Here, the value of the power-off flag is written in the free area.

  In step S103, the root complex 31 determines whether there is an endpoint that does not shut off the power. If it is determined that there is an endpoint that does not shut off the power (S103: YES), the root complex 31 moves the process to step S104. If it is determined that there is no endpoint that does not shut off the power (S103: NO), the root complex 31 proceeds to step S106.

  In step S <b> 104, the root complex 31 determines whether communication is performed until power-off is completed (that is, during energy saving transition). If it is determined that communication is performed even during the energy saving transition (S104: YES), the route complex 31 proceeds to step S105. If it is determined that communication is not performed during the energy saving transition (S104: NO), the route complex 31 proceeds to step S106.

  In step S105, the root complex 31 rewrites the value of the flag indicating the accumulation mode to “on” in the configuration space of the end point (end point 33 in this example) that does not shut off the power.

  In step S106, the root complex 31 has a flag value for disconnecting (disabling) the link between the switch 32 and the endpoint (in this example, the endpoint 34) that shuts off the power supply in the configuration space of the switch 32. Is replaced with a value indicating disconnection (for example, “off”).

  In step S107, the root complex 31 indicates that the level of the signal input to the port of the signal line supplied from the endpoint that shuts off the power supply has been transferred to the energy saving mode (for example, high level). ) If it is indicated that the shift to the energy saving mode is completed (S107: YES), the route complex 31 shifts the process to step S110. If it is indicated that the shift to the energy saving mode is not completed (S107: NO), the route complex 31 shifts the process to step S108.

  In step S108, the root complex 31 determines whether the time-out period has elapsed and the level of the input signal indicates that the transition to the energy saving mode has not been completed (for example, low level). When the time-out period has elapsed and it is indicated that the transition to the energy saving mode has not been completed (S108: YES), the root complex 31 returns an error to the CPU 10. If the timeout period has not elapsed (S108: NO), the root complex 31 proceeds to step S109.

  In step S109, the root complex 31 waits for a predetermined period (in this example, 10 microseconds). After waiting, the root complex 31 shifts the process to step S107 again.

  In step S110, the root complex 31 accesses the general-purpose input / output (GPIO) of the switch 32 and instructs the switch 32 to shut off the power supply of the endpoint to be shifted to the energy saving mode. In step S111, the root complex 31 searches for a bus in the PCI device group 30 and reassigns a bus number. In step S112, the root complex 31 sets the value of the flag indicating the transition to the accumulation mode to “off” (that is, in the normal mode (in the configuration space of the endpoint 33 in this example) to be shifted to the accumulation mode. Rewrite to “(accumulation mode canceled)”.

  FIG. 5 is a flowchart showing a specific example of the operation of the endpoint 34. In step S201, the endpoint 34 determines whether an instruction (command) has been received. If it is determined that the command has been received (S201: YES), the endpoint 34 proceeds to step S202. When it is determined that the command has not been received (S201: NO), the endpoint 34 waits until the command is received.

  In step S202, the endpoint 34 determines whether the received command is a power-off command. If it is determined that the received command is a power-off command (S202: YES), the endpoint 34 moves the process to step S203. If it is determined that the received command is not a power-off command (S202: NO), the endpoint 34 performs processing according to the received command (step S207).

  In step S203, the end point 34 determines whether the link with the root complex 31 has been disconnected. Specifically, the endpoint 34 polls the root complex 31 and determines that the link is maintained if there is a response to the polling, and determines that the link is disconnected if there is no response. When it is determined that the link has been disconnected (S203: YES), the endpoint 34 proceeds to step S204. When it is determined that the link is maintained (S203: NO), the endpoint 34 waits until it detects the disconnection of the link.

  In step S <b> 204, the end point 34 executes power-off preparation processing (the above-described energy saving transition sequence). In step S205, the end point 34 sets the level of the signal supplied to the signal line provided with the root complex 31 for notifying that the power-off preparation process has been completed. The level is changed to a level (for example, high level) indicating that the preparation process is completed. In step S206, the endpoint 34 waits for the power to be cut off.

  FIG. 6 is a flowchart showing a specific example of the operation of the endpoint 33, specifically, operation mode switching processing. The flow in FIG. 6 is started, for example, when the CPU 10 calls the operation mode switching processing of the endpoint 33 (that is, the operation mode switching is instructed).

  In step S301, the endpoint 33 determines whether the accumulation mode flag is turned on in its configuration space. If it is determined that the accumulation mode flag is on (S301: YES), the endpoint 33 proceeds to step S304. When it is determined that the accumulation mode flag is off (S301: NO), the endpoint 33 shifts the processing to step S302.

  In step S302, the endpoint 33 sets the operation mode to the normal mode. Specifically, the register value indicating the operation mode is rewritten to indicate the normal mode. In step S303, the endpoint 33 copies the data stored in its own internal memory space to the memory space that is open to the root complex 31 (that is, accessible from the root complex 31). The root complex 31 can acquire data from this memory space.

  In step S304, the endpoint 33 sets the operation mode to the accumulation mode. Specifically, the register value indicating the operation mode is rewritten to indicate the accumulation mode. When the process of step S303 or S304 ends, the endpoint 33 ends the flow of FIG. That is, the caller is notified that the operation mode switching process has been completed.

  FIG. 7 is a flowchart showing a specific example of the operation of the endpoint 33, specifically, processing of data received from an external device. The flow in FIG. 7 is started when the data transfer process is called from another process of the endpoint 33 (that is, the data transfer is instructed), for example.

  In step S401, the endpoint 33 determines whether the operation mode is the accumulation mode. The operation mode is determined based on a register value indicating the operation mode. When it is determined that the operation mode is the accumulation mode (S401: YES), the endpoint 33 shifts the process to step S403. When it is determined that the operation mode is the normal mode (S401: NO), the endpoint 33 shifts the process to step S402.

  In step S <b> 402, the endpoint 33 writes the data received from the external device in the memory space that is open to the root complex 31.

  In step S <b> 403, the endpoint 33 writes the data received from the external device in the internal memory space of the endpoint 33.

3. Modifications The present invention is not limited to the above-described embodiments, and various modifications can be made. Hereinafter, some modifications will be described. Two or more of the following modifications may be used in combination.

  Some of the functions or processes described in the embodiments may be omitted. For example, the bus number reassignment process may be omitted. Depending on the device, there may be no problem even if the bus numbers are discontinuous. In another example, data accumulation at the endpoint 33 may not be performed. That is, the end point 33 may transfer data as usual even when the end point 34 is in the middle of power-off.

DESCRIPTION OF SYMBOLS 1 ... Information processing apparatus, 10 ... CPU, 20 ... Memory, 30 ... PCI apparatus group, 31 ... Route complex, 32 ... Switch, 33 ... End point, 34 ... End point, 311 ... Notification means, 312 ... Control means, 313: Notification means, 314: Power-off means, 315 ... Assignment means, 321 ... Link control means, 322 ... Power-off means, 331 ... Communication means, 332 ... Storage means, 333 ... Storage control means, 334 ... Output means, 341 ... notification means, 342 ... detection means, 343 ... processing means

Claims (7)

  1. A plurality of endpoints in the PCI Express standard including a first endpoint and a second endpoint;
    A root complex that controls the plurality of endpoints;
    A switch that relays data transfer between the root complex and the plurality of endpoints;
    The switch and the first endpoint are connected via a signal line other than the PCI Express standard,
    The root complex has first notification means for notifying the first endpoint of the plurality of endpoints of power shutdown,
    The root complex has control means for outputting a command for disconnecting a link with the first endpoint to the switch after the notification of the power shutdown.
    The first endpoint has processing means for performing preparation processing for the power shutdown after receiving the notification of the power shutdown.
    The first endpoint has second notification means for outputting a notification that the preparation for power shutdown has been completed to the root complex via the signal line,
    The root complex has a power shut-off means for outputting a power shut-off command for causing the first endpoint to shut off the power after the notification that the preparation for power shut-off is completed. apparatus.
  2. The first endpoint has detection means for detecting the disconnection of the link;
    The cutting of the link Ru is detected by the detection means, the processing means performs preparation processing for the power-off,
    2. The information processing apparatus according to claim 1, wherein when the preparation process is completed, the second notification unit outputs a notification that the preparation for power-off is completed.
  3. 3. The information according to claim 2 , wherein the detection unit starts polling the root complex upon receiving the power-off notification, and detects the disconnection of the link based on the polling. Processing equipment.
  4. The information processing apparatus according to any one of claims 1 to 3 , wherein the switch shuts off the power supply of the first endpoint by a signal supplied via the signal line.
  5. Subsequent to the notification of the power shutdown, the first notification means outputs a command to shift to the accumulation mode to the second endpoint,
    After the power shutdown unit outputs the power shutdown command, the root complex has output command unit for outputting a data output command to the second endpoint,
    The second endpoint is
    A communication means for communicating with an external device;
    Storage means for storing data;
    Have
    When receiving a command to shift to the accumulation mode, the data received from the external device via the communication means is stored in the storage means,
    Upon receiving the output command of the data, the data stored in the storage unit, information processing apparatus according to any of claims 1 to 4 and outputs to the root complex.
  6. The root complex assigns identification numbers to a plurality of buses between the root complex, the switch, and the endpoints to which power is supplied among the plurality of endpoints,
    The information processing apparatus according to any one of claims 1 to 5 , wherein the switch reassigns the identification number after the power shut-off unit transmits the power shut-off command.
  7. The first endpoint has a register for storing data;
    The root complex writes the data indicating the power-off notification to the register via the link in a state where the link between the switch and the first endpoint is established. The information processing apparatus according to any one of claims 1 to 6 , wherein:
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US9798377B2 (en) 2014-10-08 2017-10-24 Apple Inc. Methods and apparatus for recovering errors with an inter-processor communication link between independently operable processors
US10042794B2 (en) 2015-06-12 2018-08-07 Apple Inc. Methods and apparatus for synchronizing uplink and downlink transactions on an inter-device communication link
US10572390B2 (en) 2016-02-29 2020-02-25 Apple Inc. Methods and apparatus for loading firmware on demand
US10591976B2 (en) 2016-11-10 2020-03-17 Apple Inc. Methods and apparatus for providing peripheral sub-system stability
US20180129269A1 (en) * 2016-11-10 2018-05-10 Apple Inc. Methods and apparatus for providing individualized power control for peripheral sub-systems
US10346226B2 (en) 2017-08-07 2019-07-09 Time Warner Cable Enterprises Llc Methods and apparatus for transmitting time sensitive data over a tunneled bus interface
CN108307463B (en) * 2018-01-30 2019-04-02 江苏信源达科技有限公司 Mode switching method, system and access control system
US10585699B2 (en) 2018-07-30 2020-03-10 Apple Inc. Methods and apparatus for verifying completion of groups of data transactions between processors

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JP2006159678A (en) * 2004-12-08 2006-06-22 Canon Inc Recording device in serial bus
US8141092B2 (en) * 2007-11-15 2012-03-20 International Business Machines Corporation Management of an IOV adapter through a virtual intermediary in a hypervisor with functional management in an IOV management partition
JP2009140081A (en) * 2007-12-04 2009-06-25 Shinko Electric Ind Co Ltd Information processing apparatus and method
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