JP6171280B2 - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device Download PDF

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JP6171280B2
JP6171280B2 JP2012170397A JP2012170397A JP6171280B2 JP 6171280 B2 JP6171280 B2 JP 6171280B2 JP 2012170397 A JP2012170397 A JP 2012170397A JP 2012170397 A JP2012170397 A JP 2012170397A JP 6171280 B2 JP6171280 B2 JP 6171280B2
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resin composition
semiconductor device
semiconductor chip
composition layer
semiconductor
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JP2014029958A (en
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中村 茂雄
茂雄 中村
弘久 奈良橋
弘久 奈良橋
玄迅 真子
玄迅 真子
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味の素株式会社
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32135Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93Batch processes
    • H01L2224/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00
    • H01L2225/10All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices having separate containers
    • H01L2225/1005All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1023All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being an insulating substrate
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00
    • H01L2225/10All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices having separate containers
    • H01L2225/1005All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1041Special adaptations for top connections of the lowermost container, e.g. redistribution layer, integral interposer
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00
    • H01L2225/10All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices having separate containers
    • H01L2225/1005All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047Details of electrical connections between containers
    • H01L2225/1058Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Description

  The present invention relates to a semiconductor device manufacturing method and a semiconductor device manufactured by the manufacturing method.

  In recent years, the demand for small high-performance portable terminals such as smartphones and tablet PCs is increasing. There is a demand for further enhancement in function and size of a semiconductor device used in such a small high-performance portable terminal. In order to solve such a problem, for example, a multi-chip package sealed so as to enclose two or more semiconductor chips, or a package on which a plurality of multi-chip packages are joined together. A structure called a package (PoP) has attracted attention. As a configuration of such a package-on-package, for example, there is a form in which another package is mounted on a predetermined package and electrically connected to each other.

  In manufacturing the package as described above, as a method of mounting a semiconductor chip on the mounting substrate, for example, the electrode of the semiconductor chip is mounted on the mounting substrate in a so-called face-up state, facing the side opposite to the mounting substrate side. And mounting the semiconductor chip electrode and the mounting substrate electrode with bonding wires, and mounting the semiconductor chip electrode facing the mounting substrate side in a so-called face-down state. Flip chip mounting that directly connects the electrodes is known. In the case of flip chip mounting, bump electrodes called bumps are formed on the electrodes on the semiconductor chip side, and the bumps and electrodes on the mounting substrate side are joined.

  Furthermore, the mounting substrate on which the semiconductor chip is mounted is a semiconductor chip mounted by a method such as a transfer molding method using an epoxy molding compound (sealing resin), a vacuum hot press method for pressing a sealing film made of a sealing resin, A package is formed by forming a mold (cured body) for sealing the bonding wires and bumps (see Patent Document 1).

International Publication No. 2010/001597

  However, with a conventionally used mold mold material (sealing resin), the conductor layer cannot be formed on the surface. Therefore, it is necessary to directly connect the electrode exposed from the via hole of one package and the protruding electrode (for example, solder ball) of the other package after providing an opening (via hole) for exposing the electrode to the mold. was there. For this reason, it is necessary to precisely align the electrodes of both multichip packages. However, the conventional mold material for the package cannot form a conductor layer on the surface of the mold. Since there is no choice but to arrange the electrodes so that they are located immediately above the electrodes on the mounting substrate, and the number of electrodes is limited, the packages that can be mounted are limited.

Further, when the mold is formed by the transfer mold method, a molding die is required and a large amount of sealing resin is required, so that the manufacturing cost increases.
Furthermore, in the sealing process by the vacuum hot press method using the sealing film, it takes a long time to perform the lamination and thermosetting of the sealing film, and it is difficult to control conditions such as pressure and temperature. In some cases, the properties of the mold to be formed become non-uniform, and voids are generated particularly in the voids immediately below the mounted semiconductor chip, thereby deteriorating the electrical characteristics of the package. Moreover, when sealing a thin semiconductor chip, it is necessary to set the pressure in the vacuum hot press method to be relatively low. However, in this case, it is technically difficult to control the pressure. In some cases, the semiconductor chip may be damaged due to excessive pressure.

  The present invention has been made in view of the above problems, and an object thereof is to provide a method of manufacturing a semiconductor device that can solve the above problems.

As a result of intensive studies, the present inventors have found that the above problems can be solved by using a predetermined sealing film, and have completed the present invention.
That is, the present invention provides the following [1] to [18].
[1] A step of providing a mounting substrate having a semiconductor chip mounting surface, and a plurality of semiconductor chips mounted on the semiconductor chip mounting surface by flip chip connection and / or wire bonding connection;
A sealing film having a support and a resin composition layer provided on the support, the sealing film further comprising a cover film provided on the resin composition layer;
The step of temporarily attaching the sealing film by bonding the resin composition layer while peeling the cover film on the semiconductor chip mounting surface side;
Embedding the semiconductor chip in the resin composition layer so as to cover the semiconductor chip by heating and pressurizing from the support side under reduced pressure conditions;
A step of curing the resin composition layer embedded with the semiconductor chip by heating to form a cured body for sealing the semiconductor chip.
[2] The method for manufacturing a semiconductor device according to [1], wherein the resin composition layer has a minimum melt viscosity of 50 poise to 10,000 poise.
[3] The method for manufacturing a semiconductor device according to [1] or [2], wherein the resin composition layer includes an inorganic filler, an epoxy resin, and a curing agent.
[4] The method for manufacturing a semiconductor device according to any one of [1] to [3], wherein the resin composition layer has a thickness of 30 μm to 300 μm.
[5] The method for manufacturing a semiconductor device according to any one of [1] to [4], wherein the support is a polyethylene terephthalate film, a polyethylene terephthalate film with a release treatment layer, or a metal foil.
[6] After the step of embedding the semiconductor chip in the resin composition layer, the method further includes a step of peeling the support body before the step of forming a cured body for sealing the semiconductor chip. ] The manufacturing method of the semiconductor device as described in any one of [5].
[7] The step of embedding the semiconductor chip in the resin composition layer is performed by heating and pressurizing from the support side under reduced pressure conditions or normal pressure with a metal plate or a metal roll. The method for manufacturing a semiconductor device according to any one of [1] to [6], further including a smoothing step.
[8] burying the semiconductor chip on the resin composition layer, the following under reduced pressure pressure 26.7 hPa, heated at 90 ° C. to 180 ° C., a pressure of 1kgf / cm 2 ~18kgf / cm 2 20 The method for manufacturing a semiconductor device according to any one of [1] to [7], wherein the method is performed by adding the second to 400 seconds.
[9] The step of curing the resin composition layer to form a cured body for sealing the semiconductor chip is performed by heating at 100 ° C. to 240 ° C. for 15 minutes to 300 minutes, [1] to [8] The method for manufacturing a semiconductor device according to any one of [8].
[10] The method for manufacturing a semiconductor device according to any one of [1] to [9], further including a step of forming a conductor layer on the cured body.
[11] The method for manufacturing a semiconductor device according to [10], wherein the step of forming the conductor layer includes a plating step.
[12] A semiconductor device that can be obtained by the method for manufacturing a semiconductor device according to any one of [1] to [11],
A mounting substrate on which a plurality of semiconductor chips are mounted by flip chip connection and / or wire bonding connection on the semiconductor chip mounting surface;
A semiconductor device comprising: a cured body that embeds and seals the semiconductor chips so as to cover a plurality of the semiconductor chips.
[13] The semiconductor device according to [12], wherein the plurality of semiconductor chips are flip-chip connected to the mounting substrate, and the cured body fills a gap between the semiconductor chip and the mounting substrate.
[14] The semiconductor device according to [12] or [13], further including a conductor layer provided on the cured body.
[15] The semiconductor device according to [14], further including an electronic component mounted so as to be electrically connected to the conductor layer.
[16] The semiconductor device according to [15], wherein the electronic component is a package including a semiconductor chip.
[17] The semiconductor device according to [16], wherein the electronic component is a multi-chip package including two or more semiconductor chips.
[18] The semiconductor device according to [15], wherein the electronic component is a stacked semiconductor device.

According to the semiconductor device of the present invention, since the conductor layer (wiring layer) is directly provided immediately above the cured body (mold) for sealing the semiconductor chip, another semiconductor device electrically connected to the conductor layer is provided. A wiring pattern can be provided so as to match the arrangement of the electrodes. Therefore, since it can be mounted on the semiconductor device of the present invention without changing the arrangement of the electrodes of the mounted semiconductor device, it is easy to mount a wide variety of semiconductor devices, for example, a semiconductor device having a structure like a package on package The design can be easily changed, and the electrode can also be provided in the region immediately above the sealed semiconductor chip. Therefore, the semiconductor device can be further miniaturized, highly integrated, and highly functionalized.
According to the method for manufacturing a semiconductor device of the present invention, a semiconductor device having the above-described configuration and effects can be manufactured efficiently and with a high yield by a simple process.

FIG. 1 is a schematic plan view transparently showing the internal configuration of the semiconductor device. FIG. 2 is a schematic cross-sectional view taken along the dashed line II-II shown in FIG. FIG. 3 is a schematic cross-sectional view of a singulated semiconductor device. FIG. 4 is a schematic cross-sectional view of a stacked semiconductor device. FIG. 5 is a schematic cross-sectional view (1) for explaining the method of manufacturing the semiconductor device. FIG. 6 is a schematic cross-sectional view (2) for explaining the method of manufacturing the semiconductor device. FIG. 7 is a schematic cross-sectional view (3) for explaining the method for manufacturing the semiconductor device. FIG. 8 is a schematic cross-sectional view (4) for explaining the method for manufacturing the semiconductor device. FIG. 9 is a schematic cross-sectional view (5) for explaining the method of manufacturing the semiconductor device. FIG. 10 is a schematic cross-sectional view (6) for explaining the method for manufacturing the semiconductor device. FIG. 11 is a schematic cross-sectional view (7) for explaining the method for manufacturing the semiconductor device.

  Hereinafter, the present invention will be described in detail. In the following description, the present invention may be described with reference to the drawings, but the present invention is not limited to this. It should be noted that the drawings only schematically show the shapes, sizes, and arrangements of the components to the extent that the invention can be understood. Each component can be appropriately changed without departing from the gist of the present invention. In each drawing used for the following description, the same components are denoted by the same reference numerals, and redundant description may be omitted.

<Configuration example of semiconductor device>
A configuration example of a semiconductor device according to an embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a schematic plan view of a semiconductor device. FIG. 2 is a schematic cross-sectional view showing a cross section taken at the position of the dashed line II-II shown in FIG. FIG. 3 is a schematic cross-sectional view of a singulated semiconductor device.

  The semiconductor device according to the present embodiment has a semiconductor chip mounting surface, a mounting substrate on which a plurality of semiconductor chips are mounted by flip chip connection and / or wire bonding connection, and a plurality of semiconductor chip mounting surfaces. A hardened body that embeds and seals the semiconductor chip so as to cover the semiconductor chip.

As shown in FIGS. 1 and 2, only two of the semiconductor chips 30 mounted on the mounting substrate 20 will be described as a representative. Actually, the semiconductor device 10 has a structure in which a plurality of individualized semiconductor devices 12 when separated into individual pieces are arranged in a matrix and integrally connected.
The semiconductor device 10 shown in FIGS. 1 and 2 and the singulated semiconductor device 12 shown in FIG. 3 have a structure for manufacturing the stacked semiconductor device 14 shown in FIG. I have.
Hereinafter, specific configuration examples of the semiconductor device 10 and the individualized semiconductor device 12 will be described.

(Mounting board)
The semiconductor device 10 has a mounting substrate 20. In this configuration example, the mounting substrate 20 is a so-called wiring board having a plate-like shape having two main surfaces facing each other and having a conductor layer patterned (circuit formed) on one side or both sides. Examples of the main body include a silicon substrate, a glass epoxy substrate, a metal substrate, a polyester substrate, a polyimide substrate, a BT resin substrate, and a thermosetting polyphenylene ether substrate. More specific examples of the mounting substrate 20 include a multilayer printed wiring board and a flexible printed wiring board.

  One of the two main surfaces of the mounting substrate 20 is a semiconductor chip mounting surface 20a. The semiconductor chip mounting surface 20a is provided with a plurality of semiconductor chip mounting areas 20aa on which the semiconductor chip 30 is mounted and wiring and electrode pads to which the semiconductor chip 30 is electrically connected are provided. In this configuration example, the plurality of semiconductor chip mounting areas 20aa are arranged at regular intervals in a matrix shape, and a dicing line DL is set between the semiconductor chip mounting areas 20aa.

The area of the semiconductor chip mounting area 20aa is set to be larger than the area when viewed from one side in the thickness direction of the semiconductor chip 30 to be mounted (hereinafter sometimes referred to as “in plan view”). In the example, it has a square shape, and a plurality of first electrode pads 22a are arranged along the outer peripheral edge thereof. A plurality of second electrode pads 22b are arranged in a matrix inside the first electrode pads 22a. The first electrode pad 22 a and the second electrode pad 22 b are electrically connected by a connection wiring 24.
As shown in FIG. 3, the semiconductor chip mounting surface 20a is formed on the main surface opposite to the semiconductor chip mounting surface 20a of the mounting substrate 20 of the singulated semiconductor device 12 by wiring provided in a through hole (not shown). A plurality of bumps 28 are provided which are electrically connected to the connection wiring 24 provided in. The bumps 28 are external terminals used for mounting the singulated semiconductor device 12 on a substrate (for example, a mother board) or the like. The bumps 28 are preferably, for example, solder balls (hereinafter the same applies to “bumps”).

(Semiconductor chip)
The semiconductor device 10 has a plurality of semiconductor chips 30. In the present embodiment, the plurality of semiconductor chips 30 are plate-like bodies having a square shape in plan view, and a plurality of bumps 32 are arranged in a matrix on one main surface. The plurality of semiconductor chips 30 have the same size and the same configuration. The functions of the plurality of semiconductor chips 30 may be the same or different from each other.

  The semiconductor chips 30 are arranged in a matrix so as to be spaced apart from each other at equal intervals in the semiconductor chip mounting areas 20aa, and the bumps 32 are electrically connected to the second electrode pads 22b provided in the semiconductor chip mounting area 20aa. Has been.

  That is, in this configuration example, the semiconductor chip 30 is mounted on the mounting substrate 20 by flip chip connection, that is, by face-down mounting. However, the present invention is not limited to this, and the semiconductor chip 30 is connected by wire bonding, It may be mounted face up.

(Hardened body)
The semiconductor device 10 includes a cured body 44 that embeds and seals the semiconductor chip 30 so as to cover the plurality of semiconductor chips 30. The thickness of the cured body 44 is larger than the thickness of the semiconductor chip 30, and covers and seals the entire surface of the semiconductor chip 30 and the exposed mounting substrate 20. That is, the cured body 44 is provided so as to cover the semiconductor chip 30, the first electrode pad 22 a, the second electrode pad 22 b, and the connection wiring 24.

When the semiconductor chip 30 is mounted on the mounting substrate 20 by wire bonding connection, the cured body 44 is provided so as to seal all bonding wires in addition to the entire surface of the semiconductor chip 30.
When the semiconductor chip 30 is flip-chip connected to the mounting substrate 20, the cured body 44 fills the gap between the semiconductor chip 30 and the mounting substrate 20 and seals the entire surface of the semiconductor chip 30. Since the conductor layer 50 is provided on the cured body 44, the upper surface thereof is a flat surface. The cured body 44 is provided with a plurality of via holes 48 that expose at least a portion of the first electrode pad 22a.

(Conductor layer)
A conductor layer 50 is provided on the cured body 44. The conductor layer 50 is a wiring layer including a plurality of wirings 52. The wiring 52 included in the conductor layer 50 extends so that one end side thereof is electrically connected to the first electrode pad 22a of the mounting substrate 20 through the via hole 48 and the other end side is present on the cured body 44. Exist. The terminal portion on the other end side of the wiring 52 is, for example, an electrode pad 52a so that a bump 132 (details will be described later, see FIG. 4) of the electronic component 100 further mounted on the semiconductor device 10 can be connected.

  In this configuration example, the wiring 52 extends from the via hole 48 toward the inside of the semiconductor chip mounting region 20aa in a plan view. However, the present invention is not limited to this, and the wiring 52 starts from the via hole 48. It can extend in any direction. For example, the wiring 52 may extend in a direction from the via hole 48 toward the outer peripheral end of the semiconductor chip mounting region 20aa.

  The conductor material used for the conductor layer 50 is not particularly limited. The conductor material used for the conductor layer 50 is preferably one or more selected from the group consisting of gold, platinum, silver, copper, aluminum, cobalt, chromium, zinc, nickel, titanium, tungsten, iron, tin, and indium. Contains metal. The conductor layer 50 may be composed of either a single metal film or an alloy film. As the alloy film, for example, an alloy of two or more metals selected from the above group (for example, nickel chromium alloy, copper A film formed from a nickel alloy and a copper titanium alloy). Above all, from the viewpoint of versatility, cost, ease of patterning, etc., chromium, nickel, titanium, aluminum, zinc, gold, silver or copper single metal film, or nickel chromium alloy, copper nickel alloy, copper titanium alloy alloy A film is preferable, a single metal film of chromium, nickel, titanium, aluminum, zinc, gold, silver or copper, or an alloy film of nickel chromium alloy is more preferable, and a single metal film of copper is further preferable.

  The conductor layer 50 may have a single layer structure or a multilayer structure in which two or more single metal films or alloy films made of different types of metals or alloys are laminated. When the conductor layer 50 has a multilayer structure, the layer in contact with the resin composition layer is preferably composed of a single metal film of chromium, zinc or titanium, or an alloy film of nickel chromium alloy.

Here, with reference to FIG. 3, the configuration of the individualized semiconductor device 12 according to the embodiment of the present invention will be described. FIG. 3 is a schematic cross-sectional view of the singulated semiconductor device 12.
The individualized semiconductor device 12 is a semiconductor device that is cut out from the semiconductor device 10 and separated into individual pieces by grinding the cured body 44 and the mounting substrate 20 along the dicing line DL shown in FIGS. 1 and 2. is there. The components of the individualized semiconductor device 12 are the same as those of the semiconductor device 10 already described, and thus detailed description thereof is omitted.

<Configuration example of stacked semiconductor device>
With reference to FIG. 4, a configuration example of the stacked semiconductor device according to the embodiment of the present invention will be described. FIG. 4 is a schematic cross-sectional view of a stacked semiconductor device. In this configuration example, a configuration example of a semiconductor device having a package-on-package structure in which the electronic component 100 is mounted on the individual semiconductor device 12 will be described.

The stacked semiconductor device 14 having a package-on-package structure includes a singulated semiconductor device 12 that is separated by cutting the semiconductor device 10 described above along the dicing line DL.
The singulated semiconductor device 12 has a semiconductor chip mounting surface 20a. In this example, the mounting substrate 20 on which one semiconductor chip 30 is mounted by flip chip connection and the semiconductor chip 30 are mounted on the semiconductor chip mounting surface 20a. And a hardened body 44 for embedding and sealing the semiconductor chip 30 so as to cover it.

  One of the two main surfaces of the mounting substrate 20 is a semiconductor chip mounting surface 20a. On the semiconductor chip mounting surface 20a, there is set a semiconductor chip mounting area 20aa on which a semiconductor chip 30 is mounted and wiring and electrode pads are electrically connected to the semiconductor chip. A plurality of first electrode pads 22a are arranged along the outer peripheral edge of the semiconductor chip mounting region 20aa. A plurality of second electrode pads 22b are arranged in a matrix on the inner side of the first electrode pads 22a. The first electrode pad 22 a and the second electrode pad 22 b are electrically connected by a connection wiring 24.

  The main surface of the mounting substrate 20 opposite to the semiconductor chip mounting surface 20a is electrically connected to the connection wiring 24 provided on the semiconductor chip mounting surface 20a by wiring provided in a through hole (not shown). A plurality of bumps 28 are provided. The bumps 28 are external terminals used for mounting the stacked semiconductor device 14 on a substrate (for example, a motherboard).

  The bumps 32 of the semiconductor chip 30 are electrically connected to the second electrode pads 22b provided in the semiconductor chip mounting area 20aa.

  The individualized semiconductor device 12 includes a cured body 44 that embeds and seals the semiconductor chip 30 so as to cover the semiconductor chip 30. The thickness of the cured body 44 is larger than the thickness of the semiconductor chip 30, and covers and seals the entire surface of the semiconductor chip 30 and the exposed mounting substrate 20.

  The semiconductor chip 30 is flip-chip connected to the mounting substrate 20. The cured body 44 fills the gap between the semiconductor chip 30 and the mounting substrate 20 and seals the entire surface of the semiconductor chip 30. Since the conductor layer 50 is provided on the cured body 44, the upper surface thereof is a flat surface. The cured body 44 is provided with a plurality of via holes 48 that expose at least a portion of the first electrode pad 22a.

  A conductor layer 50 is provided on the surface of the cured body 44. The wiring 52 included in the conductor layer 50 extends so that one end side thereof is electrically connected to the first electrode pad 22a of the mounting substrate 20 through the via hole 48 and the other end side is present on the cured body 44. Exist. A terminal portion on the other end side of the wiring 52 is an electrode pad 52a.

  The electronic component 100 is mounted on the cured body 44 provided with the conductor layer 50 of the singulated semiconductor device 12. Specifically, the bump 132 that is an external terminal of the electronic component 100 is electrically connected to the electrode pad 52 a of the singulated semiconductor device 12.

  In this configuration example, the electronic component 100 is a so-called multichip package. Hereinafter, the configuration of the electronic component 100 will be described.

  The electronic component 100 has a mounting substrate 120. In this configuration example, the mounting substrate 120 is a plate-like body having two opposing main surfaces, and is, for example, a printed wiring board. One of the two main surfaces of the mounting substrate 120 is a semiconductor chip mounting surface 120a. On the semiconductor chip mounting surface 120a, there is set a semiconductor chip mounting area 120aa on which the first semiconductor chip 130A is mounted and wiring and electrode pads to which the first semiconductor chip 130A is electrically connected are provided. A plurality of first electrode pads 132a are provided on the upper surface of the first semiconductor chip 130A. That is, the first semiconductor chip 130A is mounted face up. A second semiconductor chip 130B is mounted on the first semiconductor chip 130A so that the first electrode pads 132a are exposed. A plurality of second electrode pads 132b are provided on the upper surface of the second semiconductor chip 130B. That is, the second semiconductor chip 130B is mounted face up.

  The area of the semiconductor chip mounting region 120aa is set to be larger than the area of the first semiconductor chip 130A to be mounted in plan view. In this configuration example, the area is a square shape, and a plurality of the semiconductor chip mounting areas 120aa are arranged along the outer periphery. The first electrode pads 122a are arranged, and the second electrode pads 122b are arranged on the outer peripheral side of the first electrode pads 122a.

  The first electrode pad 122a and the first electrode pad 132a of the first semiconductor chip 130A are connected by a first bonding wire 124A. The second electrode pad 122b and the second electrode pad 132b of the second semiconductor chip 130B are connected by a second bonding wire 124B.

  On the main surface of the mounting substrate 120 opposite to the semiconductor chip mounting surface 120a, a wiring layer (first layer) provided on the semiconductor chip mounting surface 120a is formed by wiring provided in a through hole (not shown) that penetrates the mounting substrate 120. A plurality of bumps 132 that are electrically connected to the first electrode pad 122a and the second electrode pad 122b are provided.

  In this configuration example, the first electrode pad 132a of the first semiconductor chip 130A is connected to the first electrode pad 122a of the mounting substrate 120, and the second electrode pad 132b of the second semiconductor chip 130B is the second electrode of the mounting substrate 120. Although the configuration connected to the pad 122b has been described, for example, the first electrode pad 132a and the second electrode pad 132b may be electrically connected by a bonding wire, or the first electrode of the first semiconductor chip 130A. The pad 132a may be connected to the second electrode pad 122b of the mounting substrate 120, and the second electrode pad 132b of the second semiconductor chip 130B may be connected to the first electrode pad 122a of the mounting substrate 120.

  In this configuration example, both the first semiconductor chip 130A and the second semiconductor chip 130B are mounted on the mounting substrate 20 by wire bonding connection, that is, face-up mounting. However, the present invention is not limited to this, The first semiconductor chip 130A and the second semiconductor chip 130B may be flip-chip connected, that is, face-down mounted.

  The electronic component 100 includes a cured body 144 that embeds and seals the first semiconductor chip 130A and the second semiconductor chip 130B so as to cover the first semiconductor chip 130A and the second semiconductor chip 130B. The thickness of the cured body 144 is larger than the thickness of the stacked first semiconductor chip 130A and second semiconductor chip 130B, and the first semiconductor chip 130A and second semiconductor chip 130B, the first bonding wire 124A, the first 2 The bonding wire 124B and the exposed mounting substrate 20 are covered and sealed.

  In this embodiment, the configuration example in which the electronic component 100 is a multi-chip package including two semiconductor chips (130A and 130B) in a single package has been described, but the present invention is not limited to this, and the electronic component 100 may be a package including a semiconductor chip (one piece) like the already described individualized semiconductor device 12, may be a semiconductor chip itself, or a multichip including two or more semiconductor chips. It may be a package.

When the electronic component 100 is a multi-chip package, the mounting mode of the plurality of semiconductor chips included in the electronic component 100 is not particularly limited. In the illustrated example, the mode in which the two semiconductor chips 130A and 130B) are stacked on each other has been described. However, for example, a plurality of semiconductor chips may be mounted on the semiconductor chip mounting surface 120a.
Further, the electronic component 100 itself may be a stacked semiconductor device. That is, a stacked semiconductor device that is stacked in two or more stages may be configured using the semiconductor device 10 and the individualized semiconductor device 12 that have already been described.

<Method for Manufacturing Semiconductor Device>
With reference to FIGS. 5 to 11, a method for manufacturing the semiconductor device according to the present embodiment will be described. 5 to 11 are schematic cross-sectional views (1) to (7) for explaining the method of manufacturing the semiconductor device, as shown in FIG.

(Process for preparing mounting board)
As shown in FIG. 5, a mounting board 20 is prepared. A plurality of semiconductor chip mounting surfaces 20 a are set on the mounting substrate 20. A plurality of semiconductor chips 30 are mounted on each of the plurality of semiconductor chip mounting surfaces 20a by flip chip connection and / or wire bonding connection.

(Process for preparing a sealing film)
Next, the sealing film 40 is prepared. In this configuration example, the sealing film 40 has a laminated structure in which three films (layers) are laminated. With reference to FIG. 6, the structural example of the sealing film 40 is demonstrated. FIG. 6 is a schematic cross-sectional view of a sealing film 40 for explaining a method for manufacturing a semiconductor device.

  As shown in FIG. 6, the sealing film 40 includes a support 42 and a resin composition layer 44 </ b> X provided on the support 42. In this configuration example, the sealing film 40 is further provided with a cover film 46 on the resin composition layer 44X.

(Resin composition layer)
The sealing film 40 has a resin composition layer 44X having heat fluidity and solid properties at room temperature.

The minimum melt viscosity of the resin composition layer 44X is preferably 50 poise to 10000 poise, more preferably 100 poise to 8000 poise, and still more preferably 500 poise to 5000 poise. A method for measuring the minimum melt viscosity will be described later.
When the minimum melt viscosity is within such a range, the fluidity of the resin composition constituting the resin composition layer 44X can be improved. Therefore, the gap between the mounting substrate 20 and the semiconductor chip 30 can be filled without any gap, particularly in the case of mounting the semiconductor chip 30 by flip chip connection.

  The resin composition that can form the resin composition layer 44X is a resin composition that has a thermosetting resin and / or polymer as a main component, is softened by heating, and has a film-forming ability. The material is not particularly limited as long as the material has required characteristics such as heat resistance and electrical characteristics by curing.

  The resin composition layer 44X preferably includes an inorganic filler, an epoxy resin, and a curing agent. Hereinafter, the inorganic filler, epoxy resin, and curing agent that can be used as the material of the resin composition layer 44X will be described.

(Inorganic filler)
The resin composition layer 44X preferably includes an inorganic filler with a high content in order to keep the coefficient of thermal expansion of the cured body 44 obtained by thermosetting the resin composition layer 44X low. Specifically, the content of the inorganic filler in the resin composition layer 44X is preferably 60% by mass or more when the nonvolatile component in the resin composition layer 44X is 100% by mass. Since the thermal expansion coefficient of the cured body 44 can be sufficiently reduced, the content of the inorganic filler in the resin composition layer 44X is 65 when the nonvolatile component in the resin composition layer 44X is 100% by mass. More preferably, it is more than 70 mass%, and still more preferably 70 mass% or more.

The difference (S A −S B ) between the peel strength (S A ) of the support 42 with respect to the resin composition layer 44X and the peel strength (S B ) of the cover film 46 with respect to the resin composition layer 44X is set within a predetermined range. For example, even if the inorganic filler content of the resin composition layer 44X is increased, the resin is hardly peeled off when the cover film is peeled off in the auto cutter device. Therefore, the difference (S A −S B ) between the peel strength (S A ) of the support 42 with respect to the resin composition layer 44X and the peel strength (S B ) of the cover film 46 with respect to the resin composition layer 44X is within a predetermined range. In the case where it is inside, the content of the inorganic filler in the resin composition layer 44X is 72% by mass or more, 74% by mass or more, and 76% when the nonvolatile component in the resin composition layer 44X is 100% by mass. It can be increased to mass% or more, 78 mass% or more, 80 mass% or more, or 82 mass% or more.

  The upper limit of the content of the inorganic filler in the resin composition layer 44X is the non-volatile component in the resin composition layer 44X from the viewpoint of the mechanical strength of the cured body 44 obtained by thermosetting the resin composition layer 44X. When it is 100% by mass, it is preferably 95% by mass or less, more preferably 90% by mass or less, and still more preferably 85% by mass or less.

  Examples of the inorganic filler include silica, alumina, barium sulfate, talc, clay, mica powder, aluminum hydroxide, magnesium hydroxide, calcium carbonate, magnesium carbonate, magnesium oxide, boron nitride, aluminum borate, barium titanate, Examples include strontium titanate, calcium titanate, magnesium titanate, bismuth titanate, titanium oxide, barium zirconate, and calcium zirconate. Of these, silica such as amorphous silica, fused silica, crystalline silica, and synthetic silica is particularly suitable. Moreover, spherical silica is preferable as the silica. These inorganic fillers may be used alone or in combination of two or more.

  The average particle size of the inorganic filler is preferably in the range of 0.01 μm to 4 μm, more preferably in the range of 0.05 μm to 2 μm, and still more preferably 0.1 μm to 1 μm. If it is set as such a range, since the fluidity | liquidity of a resin composition can be improved, embedding property and filling property can be improved more. The average particle size of the inorganic filler can be measured by a laser diffraction / scattering method based on Mie scattering theory. Specifically, the particle size distribution of the inorganic filler can be created on a volume basis by a laser diffraction particle size distribution measuring device, and the median diameter can be measured as the average particle diameter. The measurement sample is preferably a sample in which an inorganic filler is dispersed in water using ultrasonic waves. As a laser diffraction type particle size distribution measuring apparatus, LA-500 manufactured by Horiba, Ltd. can be used.

  Inorganic filler is one kind of aminosilane coupling agent, epoxysilane coupling agent, mercaptosilane coupling agent, silane coupling agent, organosilazane compound, titanate coupling agent, etc. for improving moisture resistance. Or it is preferable to process with 2 or more types of surface treating agents. A commercial item can be used for the inorganic filler. As the inorganic filler, for example, “KBM403” (3-glycidoxypropyltrimethoxysilane) manufactured by Shin-Etsu Chemical Co., Ltd., “KBM803” (3-mercaptopropyltrimethoxysilane) manufactured by Shin-Etsu Chemical Co., Ltd., Shin-Etsu "KBE903" (3-aminopropyltriethoxysilane) manufactured by Chemical Industry Co., Ltd. "KBM573" (N-phenyl-3-aminopropyltrimethoxysilane) manufactured by Shin-Etsu Chemical Co., Ltd., manufactured by Shin-Etsu Chemical Co., Ltd. “SZ-31” (hexamethyldisilazane) and the like.

(Epoxy resin)
Examples of the epoxy resin include bisphenol A type epoxy resin, bisphenol F type epoxy resin, bisphenol S type epoxy resin, bisphenol AF type epoxy resin, dicyclopentadiene type epoxy resin, trisphenol epoxy resin, naphthol novolac epoxy resin, phenol novolac. Type epoxy resin, tert-butyl-catechol type epoxy resin, naphthalene type epoxy resin, glycidylamine type epoxy resin, glycidyl ester type epoxy resin, cresol novolac type epoxy resin, biphenyl type epoxy resin, linear aliphatic epoxy resin, alicyclic Epoxy resin, heterocyclic epoxy resin, spiro ring-containing epoxy resin, cyclohexanedimethanol type epoxy resin, naphthylene ether type epoxy resin and tri Chiroru type epoxy resins. These epoxy resins may be used individually by 1 type, or may use 2 or more types together.

  The epoxy resin preferably contains an epoxy resin having two or more epoxy groups in one molecule. When the amount of nonvolatile components of the epoxy resin is 100% by mass, at least 50% by mass or more is preferably an epoxy resin having two or more epoxy groups in one molecule. In particular, an epoxy resin having two or more epoxy groups in one molecule and being liquid at a temperature of 20 ° C. (hereinafter referred to as “liquid epoxy resin”) and having three or more epoxy groups in one molecule. And a solid epoxy resin at a temperature of 20 ° C. (hereinafter referred to as “solid epoxy resin”). By using a liquid epoxy resin and a solid epoxy resin in combination as the epoxy resin, the resin composition layer 44X having excellent flexibility can be obtained. For this reason, the sealing film 40 having the resin composition layer 44X is excellent in handleability. Moreover, the breaking strength of the cured body 44 formed by curing the resin composition layer 44X is also improved.

  As the liquid epoxy resin, bisphenol A type epoxy resin, bisphenol F type epoxy resin, phenol novolac type epoxy resin, or naphthalene type epoxy resin are preferable, and naphthalene type epoxy resin is more preferable. Specific examples of the liquid epoxy resin include “HP4032” (naphthalene type epoxy resin), “HP4032D” (naphthalene type epoxy resin), “EXA4032SS” (naphthalene type epoxy resin), “EXA4850-150” manufactured by DIC Corporation. (Epoxy resin having fatty chain in main chain), “EXA4850-1000” (epoxy resin having fat chain in main chain), “EXA4816” (epoxy resin having fat chain in main chain), “EXA4822” (Epoxy resin having a fatty chain in the main chain), “jER828EL” (bisphenol A type epoxy resin), “jER807” (bisphenol F type epoxy resin), “jER152” (phenol novolac type epoxy) manufactured by Mitsubishi Chemical Corporation Resin), "YL7410" (bifunctional aliphatic epoxy) Fat), “YL7175-500” (epoxy resin having a fatty chain in the main chain), “YL7175-1000” (epoxy resin having a fatty chain in the main chain), “ZX1059” manufactured by Nippon Steel Chemical Co., Ltd. (Bisphenol type epoxy resin) and the like. These may be used individually by 1 type, or may use 2 or more types together. In particular, since the embedding of the cured body 44 can be improved and warpage can be reduced, it is preferable to use an epoxy resin having a flexible fatty chain in the main chain.

  Examples of solid epoxy resins include tetrafunctional naphthalene type epoxy resins, cresol novolac type epoxy resins, dicyclopentadiene type epoxy resins, trisphenol epoxy resins, naphthol novolac epoxy resins, biphenyl type epoxy resins, and naphthylene ether type epoxy resins. A tetrafunctional naphthalene type epoxy resin, a biphenyl type epoxy resin, or a naphthylene ether type epoxy resin is more preferable. Examples of the solid epoxy resin include “HP-4700” (tetrafunctional naphthalene type epoxy resin), “N-690” (cresol novolak type epoxy resin), “N-695” (cresol novolak) manufactured by DIC Corporation. Type epoxy resin), "HP-7200" (dicyclopentadiene type epoxy resin), "EXA7311" (naphthylene ether type epoxy resin), "EXA7310" (naphthylene ether type epoxy resin), "EXA7311-G3" (naphthy Renether type epoxy resin), “EPPN-502H” (trisphenol epoxy resin), “NC7000L” (naphthol novolak epoxy resin), “NC3000H” (biphenyl type epoxy resin), “NC3000” manufactured by Nippon Kayaku Co., Ltd. (Biphenyl type epoxy resin), NC3000L "(biphenyl type epoxy resin)," NC3100 "(biphenyl type epoxy resin)," ESN475 "(naphthol novolak type epoxy resin) manufactured by Tohto Kasei Co., Ltd.," ESN485 "(naphthol novolak type epoxy resin), Mitsubishi Chemical "YX4000H" (biphenyl type epoxy resin), "YX4000HK" (bixylenol type epoxy resin), etc. manufactured by Co., Ltd. are listed.

  When the liquid epoxy resin and the solid epoxy resin are used in combination as the epoxy resin, the quantitative ratio thereof (liquid epoxy resin: solid epoxy resin) is in the range of 1: 0.1 to 1: 3 by mass ratio. preferable. By making the quantity ratio of the liquid epoxy resin and the solid epoxy resin in such a range, i) suitable adhesiveness, ii) sufficient flexibility can be obtained, and handleability is improved. iii) When the cured body 44 is used, an effect such as a sufficient breaking strength can be obtained. Since the effects i) to iii) can be obtained, the quantitative ratio of liquid epoxy resin to solid epoxy resin (liquid epoxy resin: solid epoxy resin) is 1: 0.5 to 1 in terms of mass ratio. : More preferably within the range of 2.

  The content of the epoxy resin is preferably 3% by mass to 30% by mass, more preferably 5% by mass to 25% by mass, and more preferably 8% by mass to 20% by mass with respect to 100% by mass of the nonvolatile component in the resin composition layer 44X. % Is more preferable, and 10% by mass to 20% by mass is particularly preferable.

(Curing agent)
The curing agent is not particularly limited as long as it has a function of curing the epoxy resin, and examples thereof include phenol-based curing agents, active ester-based curing agents, benzoxazine-based curing agents, and cyanate ester-based curing agents. A hardening | curing agent may be used individually by 1 type, or may use 2 or more types together.

  As a phenol type hardening | curing agent, a biphenyl type hardening | curing agent, a naphthalene type hardening | curing agent, a phenol novolak type hardening | curing agent, a naphthylene ether type hardening | curing agent, and a nitrogen-containing phenol type hardening | curing agent are preferable from a heat resistant and water-resistant viewpoint. Further, from the viewpoint of adhesion (peeling strength) with the semiconductor chip 30, the wiring of the mounting substrate 20, electrode pads, and the like, a nitrogen-containing phenol-based curing agent is preferable, and a triazine skeleton-containing phenol-based curing agent is more preferable. Especially, since heat resistance, water resistance, and adhesiveness with the conductor layer 50 can be ensured, it is preferable to use a triazine skeleton-containing phenol novolac resin as a curing agent.

  Examples of phenolic curing agents include biphenyl type curing agents MEH-7700, MEH-7810, MEH-7785 (manufactured by Meiwa Kasei Co., Ltd.), naphthalene type curing agents NHN, CBN, GPH (Nippon Kayaku Co., Ltd.) )), SN170, SN180, SN190, SN475, SN485, SN495, SN375, SN395 (manufactured by Nippon Steel Chemical Co., Ltd.), EXB9500 (manufactured by DIC Corporation), TD2090 of a phenol novolac type curing agent (DIC Corporation) )), Naphthylene ether type curing agent EXB-6000 (manufactured by DIC Corporation), triazine skeleton-containing phenolic curing agents LA3018, LA7052, LA7054, LA1356 (manufactured by DIC Corporation), and the like.

  As the curing agent, an active ester curing agent is also preferable from the viewpoint of adhesion to the semiconductor chip 30, the wiring of the mounting substrate 20, the electrode pads, and the like. When an active ester curing agent is used as the curing agent, when the cured body 44 is formed, a conductor layer (wiring layer) 50 having sufficient peel strength can be formed on the surface thereof. Examples of the active ester curing agent include “EXB-9460” and “HPC8000” manufactured by DIC Corporation, “DC808” and “YLH1030” manufactured by Mitsubishi Chemical Corporation.

  Examples of the benzoxazine-based curing agent include “HFB2006M” manufactured by Showa Polymer Co., Ltd., “Pd” and “Fa” manufactured by Shikoku Kasei Kogyo Co., Ltd.

  Examples of cyanate ester-based curing agents include bisphenol A dicyanate, polyphenol cyanate (oligo (3-methylene-1,5-phenylene cyanate), 4,4′-methylenebis (2,6-dimethylphenyl cyanate), 4,4. '-Ethylidene diphenyl dicyanate, hexafluorobisphenol A dicyanate, 2,2-bis (4-cyanate) phenylpropane, 1,1-bis (4-cyanatephenylmethane), bis (4-cyanate-3,5-dimethyl) Bifunctional cyanate resins such as phenyl) methane, 1,3-bis (4-cyanatephenyl-1- (methylethylidene)) benzene, bis (4-cyanatephenyl) thioether, and bis (4-cyanatephenyl) ether, phenol Novolac and K Examples include polyfunctional cyanate resins derived from sol novolac, prepolymers in which these cyanate resins are partly triazines, etc. Specific examples of cyanate ester curing agents include “PT30” manufactured by Lonza Japan Co., Ltd. “PT60” (both phenol novolac-type polyfunctional cyanate ester resins), “BA230” (prepolymer in which a part or all of bisphenol A dicyanate is triazine-modified), and the like.

  The amount ratio between the epoxy resin and the curing agent is such that the ratio of [total number of epoxy groups of epoxy resin]: [total number of reactive groups of curing agent] is in the range of 1: 0.2 to 1: 2. Is preferable, and the range of 1: 0.5 to 1: 1.5 is more preferable. Here, the reactive group of the curing agent is an active hydroxyl group, an active ester group or the like, and varies depending on the type of the curing agent. Moreover, the total number of epoxy groups of the epoxy resin is a value obtained by dividing the value obtained by dividing the solid mass of each epoxy resin by the epoxy equivalent for all epoxy resins, and the total number of reactive groups of the curing agent is: The value obtained by dividing the solid mass of each curing agent by the reactive group equivalent is the total value for all curing agents. By setting the amount ratio of the epoxy resin and the curing agent in such a range, the heat resistance of the cured body 44 is improved.

The resin composition layer 44X preferably includes the above-described inorganic filler, epoxy resin, and curing agent. From the viewpoint that the peel strength (S A and S B ) of the support 42 and the cover film 46 with respect to the resin composition layer 44X is within a predetermined range, the resin composition layer 44X includes silica as an inorganic filler and epoxy resin. A mixture of liquid epoxy resin and solid epoxy resin (mass ratio of liquid epoxy resin: solid epoxy resin is 1: 0.1 to 1: 3, preferably 1: 0.5 to 1: 2). It is preferable that a nitrogen-containing phenol-based curing agent (preferably a triazine skeleton-containing phenol-based curing agent) or an active ester-based curing agent is included as a curing agent. Even in this case, the preferred content of the inorganic filler, the epoxy resin and the curing agent is as described above. Above all, when the nonvolatile component in the resin composition is 100% by mass, the content of the inorganic filler is included. The amount is 60% by mass to 95% by mass, the content of the epoxy resin is preferably 3% by mass to 30% by mass, the content of the inorganic filler is 60% by mass to 90% by mass, and the epoxy resin The content of is more preferably 5% by mass to 25% by mass. About content of a hardening | curing agent, it is preferable to make it contain so that ratio of the total number of the epoxy groups of an epoxy resin and the total number of the reactive groups of a hardening | curing agent may be 1: 0.2-1: 2, It is more preferable to make it contain so that it may become 1: 0.5-1: 1.5.

  The resin composition layer 44X may further contain additives such as a thermoplastic resin, a curing accelerator, a flame retardant, and rubber particles as necessary.

  Examples of the thermoplastic resin include phenoxy resin, polyvinyl acetal resin, polyimide resin, polyamideimide resin, polyethersulfone resin, and polysulfone resin. A thermoplastic resin may be used individually by 1 type, or may use 2 or more types together.

  The polystyrene equivalent weight average molecular weight of the thermoplastic resin is preferably in the range of 8000 to 70000, more preferably in the range of 10,000 to 60000, and still more preferably in the range of 20000 to 60000. The weight average molecular weight in terms of polystyrene of the thermoplastic resin is measured by a gel permeation chromatography (GPC) method. Specifically, the polystyrene-reduced weight average molecular weight of the thermoplastic resin is LC-9A / RID-6A manufactured by Shimadzu Corporation as a measuring device, and Shodex K-800P / K- manufactured by Showa Denko KK as a column. 804L / K-804L can be measured at a column temperature of 40 ° C. using chloroform or the like as a mobile phase, and can be calculated using a standard polystyrene calibration curve.

  Examples of the phenoxy resin include bisphenol A skeleton, bisphenol F skeleton, bisphenol S skeleton, bisphenolacetophenone skeleton, novolac skeleton, biphenyl skeleton, fluorene skeleton, dicyclopentadiene skeleton, norbornene skeleton, naphthalene skeleton, anthracene skeleton, adamantane skeleton, terpene Examples thereof include phenoxy resins having a skeleton and one or more skeletons selected from the group consisting of a trimethylcyclohexane skeleton. The terminal of the phenoxy resin may be any functional group such as a phenolic hydroxyl group or an epoxy group. A phenoxy resin may be used individually by 1 type, or may use 2 or more types together. Examples of the phenoxy resin include “1256” and “4250” (both bisphenol A skeleton-containing phenoxy resin), “YX8100” (bisphenol S skeleton-containing phenoxy resin), and “YX6954” (bisphenol) manufactured by Mitsubishi Chemical Corporation. In addition, “FX280” and “FX293” manufactured by Toto Kasei Co., Ltd., “YL7553”, “YL6794”, “YL7213”, “YL7290” manufactured by Mitsubishi Chemical Corporation. And “YL7482”.

  Examples of the polyvinyl acetal resin include electrified butyral 4000-2, 5000-A, 6000-C, and 6000-EP manufactured by Denki Kagaku Kogyo Co., Ltd., and the ESREC BH series, BX series, and KS manufactured by Sekisui Chemical Co., Ltd. Series, BL series, BM series and the like.

  Examples of the polyimide resin include “Rika Coat SN20” and “Rika Coat PN20” manufactured by Shin Nippon Rika Co., Ltd. Examples of the polyimide resin include a linear polyimide obtained by reacting a bifunctional hydroxyl group-terminated polybutadiene, a diisocyanate compound and a tetrabasic acid anhydride (see JP-A 2006-37083), a polysiloxane skeleton-containing polyimide ( And modified polyimides such as JP-A No. 2002-12667 and JP-A No. 2000-319386.

  Examples of the polyamide-imide resin include “Bilomax HR11NN” and “Bilomax HR16NN” manufactured by Toyobo Co., Ltd. Examples of the polyamideimide resin include modified polyamideimides such as polysiloxane skeleton-containing polyamideimides “KS9100” and “KS9300” manufactured by Hitachi Chemical Co., Ltd.

  Examples of the polyethersulfone resin include “PES5003P” manufactured by Sumitomo Chemical Co., Ltd.

  Examples of the polysulfone resin include polysulfone “P1700” and “P3500” manufactured by Solvay Advanced Polymers.

  It is preferable that content of a thermoplastic resin is 0.1 mass%-10 mass% with respect to 100 mass% of non-volatile components in the resin composition layer 44X. By setting the content of the thermoplastic resin within this range, the viscosity of the resin composition layer 44X becomes appropriate, and the resin composition layer 44X having a uniform thickness and properties can be formed. Embedding is easy. As for content of a thermoplastic resin, it is more preferable that it is 0.5 mass%-5 mass% with respect to 100 mass% of non-volatile components in the resin composition layer 44X.

  Examples of the curing accelerator include organic phosphine compounds, imidazole compounds, amine adduct compounds, and tertiary amine compounds. The content of the curing accelerator is preferably used in the range of 0.05% by mass to 3% by mass when the total amount of nonvolatile components of the epoxy resin and the curing agent is 100% by mass. A hardening accelerator may be used individually by 1 type, or may use 2 or more types together.

  Examples of the flame retardant include an organic phosphorus flame retardant, an organic nitrogen-containing phosphorus compound, a nitrogen compound, a silicone flame retardant, and a metal hydroxide. A flame retardant may be used individually by 1 type, or may use 2 or more types together. The content of the flame retardant in the resin composition layer 44X is not particularly limited. The content of the flame retardant is preferably 0.5% by mass to 10% by mass and more preferably 1% by mass to 9% by mass with respect to 100% by mass of the nonvolatile component in the resin composition layer 44X. Preferably, it is 1.5 mass%-8 mass%.

  As the rubber particles, for example, rubber particles that do not dissolve in the organic solvent used when forming the resin composition layer 44X and are incompatible with the above-described epoxy resin, curing agent, thermoplastic resin, and the like are used. Such rubber particles are generally prepared by increasing the molecular weight of the rubber component to a level at which it does not dissolve in an organic solvent or resin to form particles.

  Examples of the rubber particles include core-shell type rubber particles, cross-linked acrylonitrile butadiene rubber particles, cross-linked styrene butadiene rubber particles, and acrylic rubber particles. The core-shell type rubber particles are rubber particles having a core layer and a shell layer. For example, a two-layer structure in which an outer shell layer is made of a glassy polymer and an inner core layer is made of a rubbery polymer, or Examples thereof include rubber particles having a three-layer structure in which an outer shell layer is made of a glassy polymer, an intermediate layer is made of a rubbery polymer, and a core layer is made of a glassy polymer. The glassy polymer layer is made of, for example, methyl methacrylate polymer, and the rubbery polymer layer is made of, for example, butyl acrylate polymer (butyl rubber). A rubber particle may be used individually by 1 type, or may use 2 or more types together.

  The average particle size of the rubber particles is preferably in the range of 0.005 μm to 1 μm, more preferably in the range of 0.2 μm to 0.6 μm. The average particle diameter of the rubber particles can be measured using a dynamic light scattering method. In this measurement, for example, rubber particles are uniformly dispersed in an appropriate organic solvent by ultrasonic waves or the like, and the particle size distribution of the rubber particles is determined using a concentrated particle size analyzer (FPAR-1000; manufactured by Otsuka Electronics Co., Ltd.). It can be measured by making it on a mass basis and setting its median diameter as the average particle diameter. The content of the rubber particles is preferably 1% by mass to 10% by mass and more preferably 2% by mass to 5% by mass with respect to 100% by mass of the nonvolatile component in the resin composition layer.

  The resin composition layer 44X may contain other additives as necessary. Examples of the other additives include organic metal compounds such as organic copper compounds, organic zinc compounds, and organic cobalt compounds, and Examples include organic fillers, thickeners, antifoaming agents, leveling agents, adhesion imparting agents, colorants, and resin additives such as curable resins. In addition, the resin composition layer 44X may further contain a reinforcing material such as a glass cloth, an organic cloth, a glass nonwoven fabric, or an organic nonwoven fabric as long as the amount of the resin composition for sealing is sufficient.

  The thickness of the resin composition layer 44 </ b> X laminated on the support 42 is not particularly limited as long as it is a thickness capable of sealing and embedding the semiconductor chip 30 when it becomes the cured body 44. The thickness of the resin composition layer 44X is preferably 30 μm to 300 μm, more preferably 70 μm to 250 μm, and still more preferably 90 μm to 200 μm. The thickness of the resin composition layer 44X is preferably equal to or greater than the thickness of the semiconductor chip 30 (the sum of the thickness of the semiconductor chip 30 and the height of the external terminals such as bumps). 120) It may be in a range of about μm. The resin composition layer 44X may be composed of two or more layers.

  In forming the resin composition layer 44X, for example, a 5 mm square and 0.15 mm thick semiconductor chip 30 is mounted on a 10 mm square mounting substrate 20 by flip chip connection, and the mounting substrate 20 and the semiconductor chip 30 are formed. Assuming the case where the separation distance is 0.07 mm, the gap between the mounting substrate 20 and the semiconductor chip 30 can be obtained by supplying an amount of the resin composition in which the thickness of the resin composition layer 44X is 0.2 mm. The semiconductor chip 30 can be embedded while filling the resin composition. In this case, if the bump volume is ignored, the thickness of the resin composition layer 44X in the region immediately above the semiconductor chip 30 is 0.0175 mm, and the thickness of the resin composition layer 44X on the mounting substrate 20 is 0.2375 mm. It will be about.

[Support]
As the support 42, a film made of a plastic material is preferably used. Examples of the plastic material include polyesters such as polyethylene terephthalate (hereinafter sometimes abbreviated as “PET”) and polyethylene naphthalate (hereinafter sometimes abbreviated as “PEN”), polycarbonate (hereinafter referred to as “PET”). PC ”), acrylic such as polymethyl methacrylate (PMMA), cyclic polyolefin, triacetyl cellulose (TAC), polyether sulfide (PES), polyether ketone, polyimide and the like. As the support 42, a release paper, a copper foil, a metal foil such as an aluminum foil, or the like can be used. As the support 42, a film made of polyethylene terephthalate or polyethylene naphthalate or a metal foil is preferable, and a polyethylene terephthalate film or metal foil is particularly preferable.

  The support 42 may be subjected to a mat treatment or a corona treatment on the surface to be bonded to the resin composition layer 44X. Further, in order to make the support 42 peelable after laminating the mounting substrate 20, a release layer having a release layer is provided on the surface to be bonded to the resin composition layer 44 </ b> X as the support 42. A support 42 is preferably used. The support 42 provided with the release layer is preferably a polyethylene terephthalate film with a release layer, for example, a film on which a release layer such as an alkyd resin release layer is formed.

  A commercially available product may be used as the support 42 provided with the release layer. As the support 42, for example, “SK-1”, “AL-5”, “AL” manufactured by Lintec Co., Ltd., which is a polyethylene terephthalate film having a release layer mainly composed of an alkyd resin release agent. -7 "and the like.

  The release agent used for the release layer that can be formed on the support 42 is not particularly limited as long as the support 42 can be peeled off after the sealing film 40 is laminated on the mounting substrate 20. Suitable release agents include, for example, one or more release agents selected from the group consisting of alkyd resins, polyolefin resins, and urethane resins. In addition, the thickness of a mold release layer is about 0.01 micrometer-1 micrometer normally, Preferably it is 0.01 micrometer-0.2 micrometer.

  The thickness of the support may be usually 10 μm to 150 μm. However, if the thickness of the support 42 is too large, continuous production may be difficult, for example, it may be difficult to convey by vacuum suction in the auto cutter device. Further, when the thickness of the support 42 is too small, handling tends to be difficult, and a phenomenon that the sealing film 40 temporarily attached to the surface of the circuit board is wound (curled) in a roll shape occurs. Continuous production may be difficult. Accordingly, the thickness of the support 42 in the case of using the auto cutter device is preferably in the range of 5 μm to 75 μm, more preferably in the range of 10 μm to 60 μm, and in the range of 20 μm to 50 μm. More preferably, it is particularly preferably in the range of 20 μm to 45 μm. The thickness of the support 42 means the total thickness including the release layer.

[Cover film]
The cover film 46 prevents problems such as damage to the surface of the resin composition layer 44X when the sealing film 40 is set in the auto cutter device, and prevents adhesion of foreign substances such as adhesives and dust. There are functions such as. Examples of the material of the cover film 46 include polyolefins such as polyethylene, polypropylene, and polyvinyl chloride, polyesters such as PET and PEN, polycarbonate (PC), polyimide, and the like, and metal such as release paper, aluminum foil, and copper foil. Examples include foil.

  As with the support 42, the cover film 46 may be subjected to a mat treatment or a corona treatment on the surface to be bonded to the resin composition layer 44 </ b> X. Moreover, the cover film 46 may have a release layer on the surface bonded to the resin composition layer 44X.

  The cover film 46 has a smooth surface, and the thickness thereof is usually preferably in the range of 5 μm to 100 μm, more preferably in the range of 5 μm to 75 μm, and still more preferably in the range of 5 μm to 30 μm.

  The sealing film 40 having the above configuration includes, for example, (1) a step of providing a resin composition layer 44X in contact with the support 42 on the support 42, and (2) a resin formed in the step (1). It can manufacture by the manufacturing method including the process of providing the cover film 46 so that it may join with the composition layer 44X.

  In the said process (1), the resin composition layer 44X can be provided so that it may join with the support body 42 by a well-known method. For example, a resin varnish in which a resin composition is dissolved in a solvent is prepared, this resin varnish is applied to the surface of the support 42 using a coating device such as a die coater, and the resin varnish is dried to thereby form a resin composition layer 44X.

  Solvents used for preparing the resin varnish include, for example, ketones such as acetone, methyl ethyl ketone and cyclohexanone, acetates such as ethyl acetate, butyl acetate, cellosolve acetate, propylene glycol monomethyl ether acetate and carbitol acetate, cellosolve and butylcarbi Examples thereof include carbitols such as Tol, aromatic hydrocarbons such as toluene and xylene, amide solvents such as dimethylformamide, dimethylacetamide and N-methylpyrrolidone. These solvents may be used alone or in combination of two or more.

  The resin varnish can be dried by a known drying method such as heating or hot air blowing. If a large amount of the solvent remains in the resin composition layer 44X, it may cause swelling when the cured body 44 is formed, so that the residual solvent amount in the resin composition layer 44X is usually 10% by mass or less. It is preferably dried so as to be 5% by mass or less.

  The drying condition of the resin varnish affects the minimum melt viscosity temperature of the formed resin composition layer 44X. Although it depends on the composition of the resin composition layer 44X, the minimum melt viscosity temperature of the resin composition layer 44X is preferably in the range of 60 ° C to 170 ° C, more preferably in the range of 70 ° C to 160 ° C, and still more preferably. Is dried so as to be in the range of 80 ° C to 150 ° C. Here, the “minimum melt viscosity temperature” of the resin composition layer 44X refers to the temperature at which the resin composition layer 44X exhibits the minimum melt viscosity. Further, the “minimum melt viscosity” of the resin composition layer 44X refers to the minimum viscosity exhibited by the resin composition layer 44X when the resin of the resin composition layer 44X is melted. Specifically, when the resin composition layer 44X is heated at a constant temperature increase rate to melt the resin, the melt viscosity decreases with an increase in temperature at an initial stage, and thereafter, when a certain temperature is exceeded, the melt viscosity increases with an increase in temperature. Rises. “Minimum melt viscosity” means the melt viscosity at such a minimum point. The minimum melt viscosity temperature of the resin composition layer 44X can be measured by a dynamic viscoelastic method. Specifically, the minimum melt viscosity temperature of the resin composition layer 44X is obtained by performing dynamic viscoelasticity measurement under the conditions of a measurement start temperature of 60 ° C., a heating rate of 5 ° C./min, a frequency of 1 Hz, and a strain of 1 deg. be able to. The dynamic viscoelasticity measurement can be performed using, for example, “Rhesol-G3000” manufactured by UBM Co., Ltd.

  The drying of the resin varnish is preferably performed at a temperature of 50 ° C. to 150 ° C. for 3 minutes to 10 minutes, more preferably at a temperature of 65 ° C. to 140 ° C., depending on the type of solvent and the composition of the resin composition. It is performed for 3 minutes to 10 minutes, more preferably at a temperature of 70 ° C. to 120 ° C. for 3 minutes to 8 minutes. Thus, the resin composition layer 44X can be formed by drying the resin varnish. In addition, as long as said residual solvent amount and / or minimum melt viscosity temperature can be achieved, you may employ | adopt drying temperature and drying time different from the said range.

Since the peel strength (S A and S B ) of the support 42 and the cover film 46 with respect to the resin composition layer 44X can be within a predetermined range, in the above step (2), roll pressing, press pressing, etc. The cover film 46 is preferably laminated on the resin composition layer 44X. (S A -S B ) is not particularly limited as long as resin peeling does not occur when the cover film is peeled off, but is preferably 0.0020 [kgf / cm] or more.

In the laminating process in the step (2), the compression pressure is usually 0.02 kgf / cm 2 to 11 kgf / cm 2 (0.196 × 10 4 N / m 2 to 107.9 × 10 4 N / m 2 ). in the range, preferably in the range from 0.03kgf / cm 2 ~5kgf / cm 2 (0.294 × 10 4 N / m 2 ~78.4 × 10 4 N / m 2), more preferably 0. The range is 04 kgf / cm 2 to 2 kgf / cm 2 (0.392 × 10 4 N / m 2 to 49 × 10 4 N / m 2 ).

In order to make the peel strength (S A and S B ) of the support 42 and the cover film 46 with respect to the resin composition layer 44X within a predetermined range, [the minimum melt viscosity temperature of the resin composition layer 44X −10 ° C.] or less It is preferable to implement a process (2) on temperature conditions. From the viewpoint of obtaining sufficient adhesion between the support 42, the cover film 46, and the resin composition layer 44X, and preventing the resin from peeling when the cover film 46 is peeled off in the auto cutter device, the step (2) is [resin More preferably, it is carried out under the following temperature conditions: [Minimum melt viscosity temperature of the resin composition layer 44X−80 ° C.] to [Minimum melt viscosity temperature of the resin composition layer 44X]. More preferably, it is carried out under a temperature condition in the range of “melt viscosity temperature −30 ° C.”, and [minimum melt viscosity temperature −55 ° C. of resin composition layer 44X] to [minimum melt viscosity temperature −30 of resin composition layer 44X]. It is particularly preferable to carry out under the temperature condition in the range of [° C.].

Although depending on the composition of the resin composition layer 44X, in order to make the peel strength (S A and S B ) of the support 42 and the cover film 46 with respect to the resin composition layer 44X within a predetermined range, in step (1) The resin varnish is dried so that the residual solvent amount in the resin composition layer 44X is in the range of 0.2% by mass to 5% by mass and the minimum melt viscosity temperature of the resin composition layer 44X is in the range of 60 ° C. to 170 ° C. The resin composition layer 44X is formed, and in the step (2), the [minimum melt viscosity temperature of the resin composition layer 44X−80 ° C.] to the [minimum melt viscosity temperature of the resin composition layer 44X−10 ° C.]. Under the conditions of pressure bonding pressure of 0.02 kgf / cm 2 to 11 kgf / cm 2 (0.196 × 10 4 N / m 2 to 107.9 × 10 4 N / m 2 ) In order to join the composition layer 44X, It is preferable to provide the bar film 46. In the step (1), the residual solvent amount in the resin composition 44X is in the range of 0.5 mass% to 4.5 mass% and the minimum melt viscosity temperature of the resin composition layer 44X is. The resin varnish is dried so as to be in the range of 70 ° C. to 160 ° C. to form the resin composition layer 44X, and in the step (2), [minimum melt viscosity temperature of the resin composition layer 44X−55 ° C.] At a temperature in the range of [minimum melt viscosity temperature of the resin composition layer 44X−20 ° C.], the pressure bonding pressure is 0.04 kgf / cm 2 to 2 kgf / cm 2 (0.392 × 10 4 N / m 2 to 49 × 10 4 N / m 2 ), it is more preferable to provide the cover film 46 so as to be bonded to the resin composition layer 44X.

The roll-shaped sealing film 40 can be manufactured by winding the obtained sealing film 40 in a roll after the step (2). In addition, in the roll-shaped sealing film 40, the longitudinal direction corresponds to the MD direction. Therefore, the roll of the sealing film 40, the peel strength in the longitudinal direction, preferably satisfies the relationship of the above S A and S B.

  The manufacturing method of the sealing film 40 which has said structure is the resin composition on the support body 42 by unwinding and conveying the support body 42 wound up by roll shape continuously, and apply | coating and drying a resin varnish. After forming physical layer 44X, it can carry out continuously by providing cover film 46 wound up in the shape of a roll, for example so that it may join with resin composition layer 44X.

(Tacking process)
Next, as shown in FIG. 7, the resin composition layer 44 </ b> X exposed while peeling the cover film 46 is bonded to the semiconductor chip mounting surface 20 a side of the mounting substrate 20 on which the semiconductor chip 30 is mounted. Attach.

  This temporary attachment process can be implemented by a conventionally well-known auto cutter apparatus, for example. In this case, prior to the laminating process in the vacuum laminating apparatus, first, the sealing film 40 is temporarily attached onto the mounting substrate 20 by using an auto cutter apparatus.

  In this case, the cover film 46 is peeled off while the sealing film 40 is transported from the sealing film 40 wound in a roll shape installed in the auto cutter device to the mounting substrate 20. The resin composition layer 44 </ b> X exposed by peeling the cover film 46 is bonded to the mounting substrate 20.

  Subsequently, the sealing film 40, that is, the support 42 and the resin composition layer 44X are cut according to the size of the mounting substrate 20 by an auto cutter device, and thus shaped into the size corresponding to the corresponding mounting substrate 20. The sealing film 40 is temporarily attached to the circuit board.

(Embedding process)
As shown in FIG. 8, the semiconductor chip 30 is then embedded in the resin composition layer 44 </ b> X so as to cover the semiconductor chip 30 by heating and pressurizing from the support 42 side under reduced pressure conditions.
This step is preferably carried out, for example, as 1) a vacuum lamination step using a plate-like body made of heat-resistant rubber having an area larger than the surface area of the mounting substrate 20 provided with the semiconductor chip 30 under reduced pressure conditions. That is, a plate-like body made of a heat-resistant rubber is pressed against the support 42 of the sealing film 40 under reduced pressure, and the resin composition layer 44X of the sealing film 40 is heated and pressurized to obtain the support 42 and The resin composition layer 44X is filled so that the semiconductor chip 30 is embedded in the resin composition layer 44X, and in the case of flip chip connection, the gap between the mounting substrate 20 and the semiconductor chip 30 is filled. Step of molding 44X (molding step), and optionally 2) Further, press support metal plate or laminate metal roll against the support 42, and heat and press to support the resin composition layer 44X And a step of smoothing the surface on the 42 side (smoothing step).

  The molding process and the smoothing process may be an aspect in which the chamber is decompressed in the molding process and the smoothing process is continuously performed while maintaining the decompressed condition. Further, the mounting substrate 20 on which the support 42 and the resin composition layer 44X are vacuum-laminated may be taken out into the atmosphere once after the molding step and before the smoothing step. In this case, the smoothing step may be performed again from the normal pressure to the reduced pressure state, or may be performed under the normal pressure as it is without performing the reduced pressure again.

  The process of embedding the semiconductor chip 30 in the resin composition layer 44X, that is, the molding process is, for example, a vacuum applicator manufactured by Nichigo Morton, a vacuum pressurizing laminator manufactured by Meiki Seisakusho, or a vacuum manufactured by Taisei Laminator Co., Ltd. It can be carried out using a commercially available vacuum laminator such as a laminator.

This molding step is preferably heated at 90 ° C. to 180 ° C. (preferably 100 ° C. to 180 ° C., more preferably 120 ° C. to 150 ° C. from the viewpoint of warpage suppression) under reduced pressure conditions of 26.7 hPa or less, 1kgf / cm 2 ~18kgf / cm 2 ( preferably 3kgf / cm 2 ~15kgf / cm 2 ) can be carried out by adding 20 seconds to 400 seconds pressure (preferably 30 seconds to 300 seconds) of.

  As described above, this molding process is performed by cutting the sealing film 40 into an area of the same extent as the mounting substrate 20 by the auto cutter device, and each of the sealing films 40 is mounted on each mounting substrate 20 on which the semiconductor chip 30 is mounted. It may be carried out after the temporary attachment, and the resin composition layer 44X is laminated by heating and pressurizing from the support 42 side without cutting the sealing film 40, or the roll-shaped sealing film 40 is formed. The sealing film 40 may be cut into a predetermined size after being set on a base roll of a vacuum laminator and laminating the resin composition layer 44X by heating and pressing from the support 42 side.

  In this molding step, lamination is performed under the condition that the thickness of the softened resin composition layer 44X is equal to or greater than the thickness of the semiconductor chip 30, thereby embedding the semiconductor chip 30 on the mounting substrate 20, and mounting substrate 20 and semiconductor chip 30. It is possible to effectively fill the resin composition into the gap.

  The plate-like body made of heat-resistant rubber used in this molding step makes the resin composition layer 44X and the mounting substrate 20 provided with the semiconductor chip 30 in close contact with each other, and effectively performs filling and filling with the resin composition layer 44X. However, since it is flexible and deforms along irregularities such as the semiconductor chip 30 mounted on the mounting substrate 20, the surface of the resin composition layer 44X, that is, the resin composition layer 44X and the support 42 The surface smoothness of the contact surface may be impaired. Therefore, it is good also as implementing a smoothing process, only when there exists a possibility that the smoothness of the resin composition layer 44X may be impaired.

  In the smoothing step, after the molding step, the mounting substrate 20 on which the support 42 and the resin composition layer 44X are laminated, the protective film having a larger area than the sealing film 40 is applied to the metal plate for pressing and / or Or it is performed by smoothing the resin composition layer 44X by heating and pressurizing in a state of being sandwiched between the metal rolls for laminating.

  As a machine used for such a smoothing step, a commercially available laminating machine such as a hot plate type press or a heating and pressing type laminator can be used. In the smoothing step, the resin composition layer 44X is heated and pressurized from the protective film and support 42 side of the mounting substrate 20 on which the support 42 and the resin composition layer 44X are vacuum-laminated by the molding step. By carrying out these heating and pressurizing conditions under the same heating and pressurizing conditions as in the above-described molding step, the contact surface between the resin composition layer 44X and the support 42 can be smoothed.

  By performing the molding process in this way, the semiconductor chip 30 mounted on the mounting substrate 20, the bonding wire, and the gap between the mounting substrate 20 and the semiconductor chip 30 are not generated without using voids. Further, the smoothness of the surface of the cured product can be further improved by further performing a smoothing step in addition to the molding step.

(Hardened body formation process)
Next, as shown in FIG. 9, the mounting substrate 20 on which the support 42 and the resin composition layer 44X are vacuum-laminated is heat-treated to cure the resin composition layer 44X in which the semiconductor chip 30 is embedded. A hardened body 44 that seals the semiconductor chip 30 is used.
The step of forming the cured body 44 that cures the resin composition layer 44X and seals the semiconductor chip 30 is performed by performing a heat treatment under any suitable conditions depending on the material constituting the resin composition layer 44X. be able to.

The formation process of this hardening body 44 can be performed by heat-processing for 15 minutes-300 minutes at 100 to 240 degreeC, for example, and can heat-treat at 120 to 200 degreeC for 20 to 100 minutes. preferable.
This heat treatment may be performed by so-called step cure. That is, the heat treatment can be a multi-stage heat treatment including (1) a pre-curing step under a predetermined condition and (2) a post-curing step under a predetermined condition. Precure conditions are preferably 100 ° C to 130 ° C and 15 minutes to 45 minutes, and postcure conditions are 150 ° C to 220 ° C and preferably 30 minutes to 90 minutes.

  The step of forming the cured body 44 is after the step of embedding the semiconductor chip 30 in the resin composition layer 44X, and the step of forming the cured body 44 for sealing the semiconductor chip 30, that is, before the heat treatment, The process of peeling 42 may further be included. Or you may include the process of peeling the support body 42 after heat processing.

(Process of forming a conductor layer)
Next, a conductor layer (wiring layer) 50 is formed on the formed cured body 44. The conductor layer 50 can be a wiring layer including a desired wiring pattern by any conventionally known suitable forming process such as a semi-additive method. In this embodiment, an example in which the conductor layer 50 is formed by a semi-additive method including a plating step will be described.

As shown in FIG. 10, first, a via hole 48 is formed in the cured body 44. The via hole 48 is a through-hole that penetrates the cured body 44 in the thickness direction and exposes the wiring and the like provided in the mounting substrate 20, that is, the second electrode pad 22b in this configuration example. The via hole 48 can be formed by any conventionally known suitable method in consideration of the characteristics of the cured body 44. As an example of a method for forming the via hole 48, a forming method by laser processing can be given. Formation of the via hole 48 by laser processing can be performed, for example, using Hitachi Via Mechanics Co. CO 2 laser processing machine (LC-2E21B / 1C). The top diameter (diameter) of the via hole is preferably 150 to 250 μm.

  Next, a roughening process is performed on the cured body 44 in which the via hole 48 is formed. This roughening treatment protects the main surface of the mounting substrate 20 opposite to the main surface on which the cured body 44 is provided (the surface opposite to the semiconductor chip mounting surface 20a) in order to protect the mounting substrate 20. It is preferable to cover the tape by applying a tape (not shown).

  A roughening process can be implemented by the conventionally well-known arbitrary suitable method used in the manufacturing process of a printed wiring board, for example. The roughening treatment can be performed, for example, by 1) a step of immersing in the swelling liquid, 2) a step of immersing in the roughening liquid, 3) a step of immersing in the neutralizing liquid, 4) a process including a drying step. 1) The step of immersing in the swelling liquid is a step of immersing the cured body 44 in the swelling liquid at 50 ° C. to 80 ° C. for 2 minutes to 15 minutes (preferably 55 ° C. to 70 ° C. for 4 minutes to 10 minutes). preferable. 2) The step of immersing in the roughening solution is a step of immersing the cured body 44 in the roughening solution at 60 ° C. to 80 ° C. for 5 minutes to 20 minutes (preferably 70 ° C. to 80 ° C. for 8 minutes to 20 minutes). It is preferable. 3) The step of immersing in the neutralizing solution is a step of immersing the cured body 44 in the neutralizing solution at 30 ° C. to 50 ° C. for 3 minutes to 10 minutes (preferably at 35 ° C. to 45 ° C. for 3 minutes to 8 minutes). It is preferable.

  Next, electroless plating is performed, and a copper thin film is preferably formed as a conductor on the entire surface of the hardened body 44 of the mounting substrate 20 that has been subjected to the roughening treatment. Next, a mask pattern for exposing a part of the conductor thin film as a predetermined pattern is formed by patterning on the conductor thin film. Further, electrolytic plating is performed on the entire surface of the mounting substrate 20 including the mask pattern to thicken only a region of the conductor thin film exposed from the mask pattern. Next, after removing the mask pattern by heat treatment (ashing treatment), dissolution treatment (peeling treatment), etc., only the thin film of the conductor that was not thickened because it was covered with the mask pattern is removed by etching or the like. Thus, the conductor layer 50 including the wiring pattern can be formed.

  By these steps, wiring is also formed in the via hole 48, and the conductor layer 50 and the wiring of the mounting substrate 20 are electrically connected.

  When a metal foil such as a copper foil is used as the support 42, the conductor layer 50 can be formed by a subtractive method using this metal foil. Further, the conductor layer 50 can be formed by electrolytic plating using a metal foil as a plating seed layer. The thickness of the conductor layer 50 that can be obtained by such electrolytic plating is generally 3 to 35 μm, preferably 5 to 30 μm. In this way, the conductor layer 50 can be formed.

  As shown in FIG. 11, the structure (semiconductor device 10) obtained by grinding with a conventionally known dicing apparatus having a rotary blade, for example, at the position of the dicing line DL is cut out into individual pieces.

  The cutting process at the dicing line DL may be performed before the formation of the conductor layer 50, or the cured body 44 may be formed for each mounting substrate 20 that is separated into pieces, and the conductor layer 50 may be formed. Further, it may be performed after the electronic component 100 described later is mounted on the conductor layer 50.

  Next, by mounting the bumps 28 on the surface of the mounting substrate 20 opposite to the semiconductor chip mounting surface 20a, the singulated semiconductor device 12 having the configuration already described with reference to FIG. 2 can be obtained. . The mounting of the bumps 28 on the mounting substrate 20 may be performed simultaneously with the mounting of the electronic component 100 described later on the conductor layer 50 or may be performed after the electronic component 100 is mounted on the conductor layer 50.

  As described above, according to the present embodiment, since the conductor layer 50 can be formed immediately above the cured body 44, the electrode of the electronic component (another semiconductor device) that is electrically connected to the conductor layer 50 is used. A wiring pattern can be provided so as to suit the arrangement. Therefore, without changing the arrangement of the electrodes of the electronic component 100 to be mounted, for example, the wiring pattern can be routed in accordance with the arrangement of the electrodes of the electronic component 100 to be mounted. Etc.), and further, an electrode can be provided in the region immediately above the semiconductor chip 30 sealed on the mounting substrate 20, so that the stacked semiconductor device 14 can be further miniaturized and highly integrated. Higher functionality is possible.

<Method for Manufacturing Multilayer Semiconductor Device>
As shown in FIG. 3, an electronic component 100 is mounted on the individualized semiconductor device 12 including the conductor layer 50 while being electrically connected to the conductor layer 50, thereby forming the stacked semiconductor device 14.
When the bump 132 of the electronic component 100 is, for example, a solder ball, the conductor layer 50 included in the semiconductor device 10 or the singulated semiconductor device 12 and the electronic component 100 are obtained by a so-called reflow process using a flux (solder paste). The stacked semiconductor device 14 can be formed by bonding the bumps 132 and electrically connecting them. This reflow step can be performed under any suitable conditions known in the art.

  Hereinafter, the present invention will be specifically described by way of examples. The present invention is not limited to these examples.

<Measurement method and evaluation method>
First, the forms of packages and semiconductor chips, various measurement methods, and evaluation methods used in Examples and Comparative Examples will be described.

(Package form)
Package size: 10mm x 10mm
Mounting board thickness: 0.3mm
Core material: Panasonic R1515A
Solder resist: SR7200G made by Hitachi Chemical
Electrode pad size: 100 μm × 100 μm Gold-plated substrate size: 170 mm × 255 mm
Package layout: 9 pcs (3 × 3 pcs) × 12 Blocks

(Semiconductor chip configuration)
Die size: 5mm x 5mm
Die thickness: 0.15mm
Bump: Solder bump φ80μm
Bump pitch: 150 μm
Number of bumps: 784 (28 x 28)

(Measurement of minimum melt viscosity temperature of resin composition layer)
The minimum melt viscosity temperature of the resin composition layer in the sealing film with a roll-shaped cover film manufactured in Examples and Comparative Examples described later is a dynamic viscoelasticity measuring device (manufactured by UBM Co., Ltd., "Rheosol-G3000"). About 1 g of the resin composition as a sample, using a parallel plate with a diameter of 18 mm, the temperature was increased from a starting temperature of 60 ° C. to 200 ° C. at a heating rate of 5 ° C./minute, and a measurement temperature interval of 2.5 ° C. The temperature at the lowest melt viscosity was measured under the conditions of a frequency of 1 Hz and a strain of 1 deg.

(Evaluation of embeddability)
About the manufactured semiconductor device, using an ultrasonic imaging device (FINESAT manufactured by Hitachi Engineering & Service Co., Ltd.), a cured body directly under the semiconductor chip mounted on the mounting substrate, that is, between the mounting substrate and the semiconductor chip The embedding property of the (resin composition) was evaluated using a 50 MHz / 7 mm probe. The case where a void was not found was evaluated as “good”, and the case where a void was found was evaluated as “impossible”.

(Measurement of peel strength)
The peel strength with respect to the cured body of the conductor layer was measured. The formed conductor layer is cut with a width of 10 mm and a length of 100 mm. One end of the cut is peeled off and is gripped with a gripping tool (TSE Corporation, Autocom type testing machine AC-50C-SL) at room temperature. Then, the load (kgf / cm) when 35 mm was peeled off in the direction perpendicular to the surface of the cured body at a speed of 50 mm / min was measured.
Although details will be described later, Comparative Example 1 was not evaluated because the amount of the resin composition supplied was insufficient and a conductor layer could not be formed by plating. In Comparative Examples 2 and 3, since the solder bump was not embedded in the resin composition, no evaluation was performed.

<Example 1>
(Preparation of resin varnish 1)
Bisphenol type epoxy resin (“ZX1059” manufactured by Nippon Steel Chemical Co., Ltd., 1: 1 (mass ratio) mixture of bisphenol A type epoxy resin and bisphenol F type epoxy resin) 5 parts, bifunctional aliphatic epoxy 5 parts resin (Mitsubishi Chemical Corporation “YL7410”), crystalline bifunctional epoxy resin (Mitsubishi Chemical Corporation “YX4000HK”, epoxy equivalent of about 185), biphenyl type epoxy resin (Nippon Kayaku Co., Ltd.) ) "NC3000H") 10 parts and 5 parts of phenoxy resin ("YL7553BH30" manufactured by Mitsubishi Chemical Corporation, MEK solution with a solid content of 30% by mass) were dissolved in 40 parts of solvent naphtha with stirring. After cooling to room temperature, 15 parts of an active ester compound (“HPC8000-65T” manufactured by DIC Corporation, a toluene solution having a nonvolatile content of 65% by mass with an active group equivalent of about 223), a triazine-containing cresol curing agent (hydroxyl group) Equivalent 151, DIC Corporation "LA-3018-50P") 50% solid methoxypropanol solution 15 parts, curing accelerator (4-dimethylaminopyridine, solid content 2% by weight MEK solution) 6 parts, Flame retardant (“HCA-HQ”, Sanko Co., Ltd., 10- (2,5-dihydroxyphenyl) -10-hydro-9-oxa-10-phosphaphenanthrene-10-oxide, average particle size 2 μm) 2 parts, spherical silica (average particle size of 0.5 μm, A Co., Ltd.) surface-treated with an aminosilane coupling agent (“KBM573” manufactured by Shin-Etsu Chemical Co., Ltd.) Resin varnish 1 was prepared by mixing “SOC2” manufactured by Domatex and 200 parts of carbon per unit area of 0.39 mg / m 2 , and uniformly dispersing with a high-speed rotary mixer.

(Preparation of sealing film)
As a support, a polyethylene terephthalate film (PET film) with an alkyd resin release layer (thickness 38 μm, manufactured by Lintec Corporation, “AL5”) was prepared. The resin varnish 1 obtained in Example 1 above was uniformly applied to the surface of the support on the alkyd resin release layer side with a die coater and dried at 80 ° C. to 120 ° C. (average 100 ° C.) for 8 minutes. By doing so, a resin composition layer was formed. The resin composition layer had a thickness of 200 μm, a residual solvent amount of 2.9% by mass, a minimum melt viscosity of 780 poise, and a temperature of 133 ° C.

(Manufacture of sealing film with roll-shaped cover film)
Next, a polypropylene film having a thickness of 15 μm (the smooth surface side of “Alphan MA-411” manufactured by Oji Specialty Paper Co., Ltd.) was attached to the surface of the resin composition layer at 60 ° C. and wound into a roll. The roll-shaped sealing film with a cover film was slit to a width of 250 mm to obtain two 50-m rolls.

(Temporary attachment process with auto cutter device)
First, a mounting substrate (size 255 mm × 170 mm, thickness 0.3 mm) on which the semiconductor chip described above was mounted on a semiconductor chip mounting surface was prepared.

  The roll-shaped sealing film with a cover film was set in an auto cutter device (manufactured by Shinei Kiko Co., Ltd., “SAC-500”). The sealing film with a cover film was set on the semiconductor chip mounting surface side of the mounting substrate.

The cover film was peeled off while the sealing film with the cover film was unwound and conveyed at a conveyance speed of 5 m / min. The sealing film with the resin composition layer exposed was temporarily attached to the mounting substrate such that the resin composition layer was bonded to the semiconductor chip mounting surface of the mounting substrate. The mounting substrate transport speed at the time of temporary attachment was 2 m / min, the temporary attachment temperature was 100 ° C., the temporary attachment time was 10 seconds, and the temporary attachment pressure was 0.15 kgf / cm 2 .

(Lamination process of sealing film)
The sealing film was laminated on the temporarily mounted mounting substrate using a two-stage vacuum laminator apparatus CVP-700 (trade name, manufactured by Nichigo Morton Co., Ltd.). Lamination is performed by reducing the pressure in the chamber for 45 seconds to reduce the pressure to 13 hPa or less, then pressing with heat resistant rubber at 120 ° C. and a pressure of 0.74 MPa for 90 seconds, and then metal at 120 ° C. and a pressure of 0.9 MPa for 135 seconds. The pressing was performed using a plate.

(Curing process of resin composition)
A cured body (mold) that peels off the PET film as a support from the laminated sealing film, cures the resin composition under curing conditions at 180 ° C. for 30 minutes, and seals the mounted semiconductor chip. Created.

(Process of forming a conductor layer on the cured body)
(1) Via hole formation process By using a CO 2 laser processing machine (LC-2E21B / 1C) manufactured by Hitachi Via Mechanics Co., Ltd., drilling the cured body, the top diameter of the via hole on the surface of the cured body (diameter ) Formed a 200 μm via hole to expose the electrode provided on the mounting substrate.

(2) Roughening treatment After covering the back surface of the mounting substrate with via holes (the surface opposite to the semiconductor chip mounting surface) with a protective tape, it contains diethylene glycol monobutyl ether of Atotech Japan Co., Ltd., which is a swelling liquid. Soaking Dip Securigant P (glycol ether, aqueous solution of sodium hydroxide) at 60 ° C. for 4 minutes, and then as a roughening solution, Concentrate Compact P (KMnO 4 : 60 g) of Atotech Japan Co., Ltd. / L, NaOH: 40 g / L aqueous solution) at 80 ° C. for 8 minutes. Finally, as a neutralizing solution, the solution was reduced to 40% at 40 ° C. in Atotech Japan Co., Ltd. Reduction Sholysin Securigant P (aqueous solution of sulfuric acid). It was immersed for 30 minutes and then dried at 80 ° C. for 30 minutes.

(3) Formation of conductor layer by semi-additive method The mounting substrate on which the via hole is formed is immersed in an electroless plating solution containing PdCl 2 at 40 ° C. for 5 minutes, and then in an electroless copper plating solution at 25 ° C. for 20 minutes. Immerse for a minute. After annealing at 120 ° C. for 30 minutes, a plating resist layer is bonded, and after patterning is performed by exposure and development, copper sulfate electrolytic plating is performed to form a conductor layer having a thickness of 30 μm ( A wiring layer including a wiring pattern) was formed. Next, the plating resist was peeled off, and unnecessary electroless copper plating portions were removed by flash etching to form a wiring pattern. Finally, the protective tape was peeled off, and annealing was performed at 190 ° C. for 60 minutes.

  The embedding property of the formed cured body (resin composition) was evaluated, and the peel strength of the formed conductor layer with respect to the cured body was measured. The results are shown in Table 1 below.

<Example 2>
(Preparation of resin varnish 2)
Bisphenol type epoxy resin (“ZX1059” manufactured by Nippon Steel Chemical Co., Ltd., 1: 1 (mass ratio) mixture of bisphenol A type and bisphenol F type) 5 parts, bifunctional aliphatic epoxy resin (Mitsubishi Chemical Corporation) "YL7410" manufactured by Yokogawa Chemical Co., Ltd.) 5 parts, 10 parts of crystalline bifunctional epoxy resin ("YX4000HK" manufactured by Mitsubishi Chemical Corporation, epoxy equivalent of approximately 185), 10 parts of biphenyl type epoxy resin ("NC3000H" manufactured by Nippon Kayaku Co., Ltd.) 3 parts of bisphenol A type epoxy resin (“jER1007” manufactured by Mitsubishi Chemical Corporation, epoxy equivalent of about 2000) and 2 parts of rubber particles (manufactured by Ganz Kasei Co., Ltd., Staphyloid AC3816N) are stirred into 48 parts of solvent naphtha. The solution was dissolved while heating. After cooling to room temperature, there were 12 parts of a 60% solid content MEK solution of a triazine-containing phenolic curing agent (hydroxyl equivalent 125, “LA-7054” manufactured by DIC Corporation), a naphtholic curing agent (hydroxyl equivalent 215). , "SN-485" manufactured by Nippon Steel Chemical Co., Ltd.) 12 parts of MEK solution with a solid content of 60%, 3 parts of curing accelerator (4-dimethylaminopyridine, MEK solution with a solid content of 2% by mass), flame retardant (“Sanko Co., Ltd.“ HCA-HQ ”, 10- (2,5-dihydroxyphenyl) -10-hydro-9-oxa-10-phosphaphenanthrene-10-oxide, average particle size 2 μm) 2 parts , Spherical silica (average particle size 1.2 μm, manufactured by Admatechs Co., Ltd., “SOC4” manufactured by Shin-Etsu Chemical Co., Ltd., “KBM573”), amount of carbon per unit area 0.47mg / m 2 ) 250 parts were mixed and dispersed uniformly with a high-speed rotary mixer to prepare a resin varnish 2.

(Preparation of sealing film)
As a support, 18 μm carrier copper foil / 3 μm copper foil (manufactured by Mitsui Metal Mining Co., Ltd., trade name: Mitsui Microshin) was prepared. The resin varnish 2 obtained as described above is uniformly applied to the release layer side surface of the support with a die coater and dried at 80 ° C. to 120 ° C. (average 100 ° C.) for 8 minutes to obtain a resin composition. A physical layer was formed. The resin composition layer had a thickness of 200 μm, a residual solvent amount of 2.1 mass%, a minimum melt viscosity of 4500 poise, and a temperature of 98 ° C.

  Production of a sealing film with a roll-shaped cover film, a tacking process using an auto cutter device, and a laminating process of the sealing film were performed in the same manner as Example 1 already described.

(Curing process of resin composition)
Copper foil (with a micro thin 3 μm / carrier copper foil 18 μm attached, first cure at 100 ° C. for 30 minutes, and further cure at 180 ° C. for 60 minutes to cure the resin composition. After making a cured body, only the carrier copper foil was peeled off.

(Process of forming a conductor layer on the cured body)
The remaining copper foil (micro thin 3 μm) was used as a seed layer, so-called M-SAP (modified-semi-additive process), and the thickness of 30 μm (including the seed layer) on the cured body in the same manner as in Example 1. A conductor layer was formed.

  The embedding property of the formed cured body was evaluated, and the peel strength of the formed conductor layer with respect to the cured body was measured. The results are shown in Table 1 below.

<Comparative Example 1>
(Preparation of sealing film)
As a support, a polyethylene terephthalate film (PET film) with an alkyd resin release layer (thickness 38 μm, manufactured by Lintec Corporation, “AL5”) was prepared. The resin varnish 1 obtained in Example 1 above was uniformly applied to the surface of the support on the alkyd resin release layer side with a die coater, and 4.5 to 80 ° C. to 120 ° C. (average 100 ° C.). It was made to dry for minutes and the resin composition layer was formed. The resin composition layer had a thickness of 100 μm, a residual solvent amount of 2.6 mass%, a minimum melt viscosity of 840 poise, and a temperature of 135 ° C.

  The manufacturing process of the sealing film with a roll-shaped cover film, the tacking process with an auto cutter device, the sealing process of the sealing film, the curing process of the resin composition, and the process of forming the conductor layer on the cured body have already been described. The same operation as in Example 1 was performed.

  The embedding property of the formed cured body was evaluated. The results are shown in Table 1 below. In this example, the amount of the resin composition was too small and voids were observed.

<Comparative example 2>
(Preparation of sealing film and production of sealing film with roll-shaped cover film)
The sealing film was prepared similarly to Example 2 already demonstrated, the sealing film with a roll-shaped cover film was manufactured, and the temporary attachment process by an autocutter apparatus was performed.
(Lamination process of sealing film)
The sealing film was laminated on the temporarily mounted mounting substrate using a two-stage vacuum laminator apparatus CVP-700 (trade name, manufactured by Nichigo Morton Co., Ltd.). Lamination is performed by reducing the pressure in the chamber for 45 seconds to reduce the pressure to 13 hPa or less, and then pressing for 90 seconds at 80 ° C. and a pressure of 0.74 MPa, followed by hot pressing at 80 ° C. and a pressure of 0.9 MPa for 135 seconds. It was.

  The step of curing the resin composition and the step of forming a conductor layer on the cured body were performed in the same manner as in Example 1 already described.

  The embedding property of the formed cured body was evaluated. The results are shown in Table 1 below. Under these temperature conditions, voids were observed because the fluidity of the resin composition was insufficient.

<Comparative Example 3>
(Preparation of resin varnish 3)
10 parts of bisphenol type epoxy resin (“ZX1059” manufactured by Nippon Steel Chemical Co., Ltd., 1: 1 mixture of bisphenol A type and bisphenol F type), biphenyl type epoxy resin (“NC3000H” manufactured by Nippon Kayaku Co., Ltd.) 20 parts and 10 parts of phenoxy resin ("YL7553BH30" manufactured by Mitsubishi Chemical Corporation, MEK solution with a solid content of 30% by mass) were dissolved in 40 parts of solvent naphtha with stirring. After cooling to room temperature, 15 parts of a 60% solid MEK solution of a triazine-containing phenolic curing agent (hydroxyl equivalent 125, “LA-7054” manufactured by DIC Corporation), naphtholic curing agent (hydroxyl equivalent 215) , "SN-485" manufactured by Nippon Steel Chemical Co., Ltd.) 10 parts of MEK solution with 60% solid content, 5 parts of curing accelerator (4-dimethylaminopyridine, MEK solution with 2% solid content), flame retardant (Sanko Co., Ltd. "HCA-HQ", 10- (2,5-dihydroxyphenyl) -10-hydro-9-oxa-10-phosphophenanthrene-10-oxide, average particle size 2 μm) 2 parts , Spherical silica (average particle size 0.5 μm, manufactured by Admatechs Co., Ltd., “SOC2”), surface treated with an aminosilane coupling agent (“KBM573” manufactured by Shin-Etsu Chemical Co., Ltd.) 2 parts of carbon (0.39 mg / m 2 ) was mixed and dispersed uniformly with a high-speed rotary mixer to prepare a resin varnish 3.

(Preparation of sealing film)
As a support, a polyethylene terephthalate film (PET film) with an alkyd resin release layer (thickness 38 μm, manufactured by Lintec Corporation, “AL5”) was prepared. The resin varnish 3 obtained above is uniformly applied to the release layer side surface of the support with a die coater and dried at 80 ° C. to 120 ° C. (average 100 ° C.) for 8 minutes to form a resin composition layer. Formed. The resin composition layer had a thickness of 200 μm, a residual solvent amount of 2.8% by mass, a minimum melt viscosity of 11000 poise, and a temperature of 90 ° C.

  The manufacturing process of the sealing film with a roll-shaped cover film, the tacking process with an auto cutter device, the sealing process of the sealing film, the curing process of the resin composition, and the process of forming the conductor layer on the cured body have already been described. The same operation as in Example 1 was performed.

  The embedding property of the formed cured body was evaluated. The results are shown in Table 1 below. Since the minimum melt viscosity of the resin composition was high, generation of voids was observed.

  As apparent from Table 1, according to Example 1 and Example 2, no void was found in the cured body, and the embedding property was good. Moreover, according to the said Example 1 and Example 2, it was favorable also about the peel strength with respect to the hardening body of a conductor layer, and it has confirmed that the conductor layer formed on the hardening body could be used as a wiring layer. In particular, for Example 2, it was confirmed that the peel strength could be further improved by using a copper foil.

DESCRIPTION OF SYMBOLS 10 Semiconductor device 12 Divided semiconductor device 14 Stacked semiconductor device 20, 120 Mounting substrate 20a, 120a Semiconductor chip mounting surface 20aa, 120aa Semiconductor chip mounting region 22a, 122a First electrode pad 22b, 122b Second electrode pad 24 Connection wiring 28, 32, 132 Bump 30 Semiconductor chip 40 Sealing film 42 Support body 44, 144 Cured body 44X Resin composition layer 46 Cover film 48 Via hole 50 Conductor layer (wiring layer)
52 wiring 52a electrode pad 100 electronic component 122 electrode pad 132a first electrode pad 132b second electrode pad 124A first bonding wire 124B second bonding wire 130A first semiconductor chip 130B second semiconductor chip DL dicing line

Claims (18)

  1. Preparing a mounting substrate having a semiconductor chip mounting surface and a plurality of semiconductor chips mounted on the semiconductor chip mounting surface by flip chip connection and / or wire bonding connection;
    A sealing film having a support and a resin composition layer provided on the support, the sealing film further comprising a cover film provided on the resin composition layer;
    The step of temporarily attaching the sealing film by bonding the resin composition layer while peeling the cover film on the semiconductor chip mounting surface side;
    A molding step of embedding the semiconductor chip in the resin composition layer so as to cover the semiconductor chip by heating and pressurizing from the support side under reduced pressure conditions,
    Curing the resin composition layer embedded with the semiconductor chip by heating to form a cured body for sealing the semiconductor chip; and
    A method of manufacturing a semiconductor device, including a step of forming a conductor layer on the cured body by a method including a plating step,
    The resin composition layer comprises (i) an inorganic filler, (ii) an epoxy resin having a flexible fatty chain in the main chain, and (iii) an active ester curing agent, a naphthalene type curing agent, and a naphthylene ether type curing. The manufacturing method of a semiconductor device containing 1 or more types of hardening | curing agents chosen from an agent and a nitrogen-containing phenol type hardening | curing agent .
  2.   The method for manufacturing a semiconductor device according to claim 1, wherein a minimum melt viscosity of the resin composition layer is 50 poise to 10,000 poise.
  3.   The method for manufacturing a semiconductor device according to claim 1, wherein a thickness of the resin composition layer is 30 μm to 300 μm.
  4.   The manufacturing method of the semiconductor device as described in any one of Claims 1-3 whose said support body is a polyethylene terephthalate film, the polyethylene terephthalate film with a mold release process layer, or metal foil.
  5.   The semiconductor as described in any one of Claims 1-4 which further includes the process of peeling the said support body after the said shaping | molding process and before the process used as the hardening body which seals the said semiconductor chip. Device manufacturing method.
  6.   Immediately after the molding step, the method further comprises a step of smoothing the surface of the support side of the resin composition layer by heating and pressurizing from the support side under reduced pressure or normal pressure with a metal plate or metal roll. The manufacturing method of the semiconductor device as described in any one of 1-5.
  7. Said molding step is pressure 26.7hPa following under reduced pressure, heated at 90 ° C. to 180 ° C., is carried out by applying a pressure of 1kgf / cm 2 ~18kgf / cm 2 20 seconds to 400 seconds, claim The manufacturing method of the semiconductor device as described in any one of 1-6.
  8.   The process of hardening the said resin composition layer and setting it as the hardening body which seals the said semiconductor chip is performed by heating at 100 to 240 degreeC for 15 to 300 minutes. A method for manufacturing a semiconductor device according to claim 1.
  9.   The method for manufacturing a semiconductor device according to claim 1, wherein the step of forming the conductor layer is performed by a semi-additive method including the plating step.
  10.   The manufacturing method of the semiconductor device of any one of Claims 1-9 whose peel strength with respect to the said hardening body of the said conductor layer is 0.5 kgf / cm or more.
  11. A mounting substrate on which a plurality of semiconductor chips are mounted by flip chip connection and / or wire bonding connection on the semiconductor chip mounting surface;
    A cured body covering a plurality of the semiconductor chips;
    A conductor layer provided on the cured body,
    The cured body comprises (i) an inorganic filler, (ii) an epoxy resin having a flexible fatty chain in the main chain, and (iii) an active ester curing agent, a naphthalene type curing agent, a naphthylene ether type curing agent, And a semiconductor device which is a cured body obtained by curing a resin composition containing one or more curing agents selected from nitrogen-containing phenol-based curing agents .
  12.   The semiconductor device according to claim 11, wherein a peel strength of the conductor layer with respect to the cured body is 0.5 kgf / cm or more.
  13.   The semiconductor device according to claim 12, wherein a minimum melt viscosity of the resin composition is 50 poise to 10,000 poise.
  14.   The plurality of semiconductor chips are flip-chip connected to the mounting substrate, and the cured body embeds a gap between the semiconductor chip and the mounting substrate. Semiconductor device.
  15.   The semiconductor device according to claim 11, further comprising an electronic component mounted so as to be electrically connected to the conductor layer.
  16.   The semiconductor device according to claim 15, wherein the electronic component is a package including a semiconductor chip.
  17.   The semiconductor device according to claim 16, wherein the electronic component is a multi-chip package including two or more semiconductor chips.
  18.   The semiconductor device according to claim 15, wherein the electronic component is a stacked semiconductor device.
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