JP6101807B2 - 高信頼性メモリコントローラ - Google Patents

高信頼性メモリコントローラ Download PDF

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Publication number
JP6101807B2
JP6101807B2 JP2015536838A JP2015536838A JP6101807B2 JP 6101807 B2 JP6101807 B2 JP 6101807B2 JP 2015536838 A JP2015536838 A JP 2015536838A JP 2015536838 A JP2015536838 A JP 2015536838A JP 6101807 B2 JP6101807 B2 JP 6101807B2
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Prior art keywords
data
memory
address space
reliability
bank
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Japanese (ja)
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JP2015535101A (ja
Inventor
エイチ． ロー ガブリエル
エイチ． ロー ガブリエル
ケイ． スリドハルン ヴィラス
ケイ． スリドハルン ヴィラス
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Advanced Micro Devices Inc
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Advanced Micro Devices Inc
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1044—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices with specific ECC/EDC distribution

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
JP2015536838A 2012-10-11 2013-10-08 高信頼性メモリコントローラ Active JP6101807B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/649,745 US8984368B2 (en) 2012-10-11 2012-10-11 High reliability memory controller
US13/649,745 2012-10-11
PCT/US2013/063881 WO2014058879A1 (en) 2012-10-11 2013-10-08 High reliability memory controller

Publications (2)

Publication Number Publication Date
JP2015535101A JP2015535101A (ja) 2015-12-07
JP6101807B2 true JP6101807B2 (ja) 2017-03-22

Family

ID=49510512

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2015536838A Active JP6101807B2 (ja) 2012-10-11 2013-10-08 高信頼性メモリコントローラ

Country Status (7)

Country Link
US (1) US8984368B2 (en:Method)
EP (1) EP2907030A1 (en:Method)
JP (1) JP6101807B2 (en:Method)
KR (1) KR101626040B1 (en:Method)
CN (1) CN104871137B (en:Method)
IN (1) IN2015DN02935A (en:Method)
WO (1) WO2014058879A1 (en:Method)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9753858B2 (en) 2011-11-30 2017-09-05 Advanced Micro Devices, Inc. DRAM cache with tags and data jointly stored in physical rows
US9009548B2 (en) * 2013-01-09 2015-04-14 International Business Machines Corporation Memory testing of three dimensional (3D) stacked memory
US9798622B2 (en) * 2014-12-01 2017-10-24 Intel Corporation Apparatus and method for increasing resilience to raw bit error rate
US9800271B2 (en) * 2015-09-14 2017-10-24 Qualcomm Incorporated Error correction and decoding
US10013212B2 (en) * 2015-11-30 2018-07-03 Samsung Electronics Co., Ltd. System architecture with memory channel DRAM FPGA module
US10031801B2 (en) * 2015-12-01 2018-07-24 Microsoft Technology Licensing, Llc Configurable reliability for memory devices
KR102766341B1 (ko) * 2016-11-30 2025-02-12 삼성전자주식회사 메모리 모듈, 이를 포함하는 메모리 시스템 및 메모리 시스템의 동작 방법
US20210018952A1 (en) * 2017-06-02 2021-01-21 Ultramemory Inc. Semiconductor module
US11494087B2 (en) 2018-10-31 2022-11-08 Advanced Micro Devices, Inc. Tolerating memory stack failures in multi-stack systems
KR102693213B1 (ko) * 2018-11-30 2024-08-09 에스케이하이닉스 주식회사 메모리 시스템
KR20250099267A (ko) 2019-04-15 2025-07-01 양쯔 메모리 테크놀로지스 씨오., 엘티디. 프로세서 및 동적 랜덤 액세스 메모리를 갖는 본디드 반도체 장치 및 이를 형성하는 방법
JP7311615B2 (ja) * 2019-04-30 2023-07-19 長江存儲科技有限責任公司 プロセッサおよびｎａｎｄフラッシュメモリを有する接合半導体デバイスならびにそれを形成する方法
WO2021158994A1 (en) * 2020-02-07 2021-08-12 Sunrise Memory Corporation Quasi-volatile system-level memory
TWI836184B (zh) 2020-02-07 2024-03-21 美商森恩萊斯記憶體公司 具有低延遲的高容量記憶體電路
US11507301B2 (en) 2020-02-24 2022-11-22 Sunrise Memory Corporation Memory module implementing memory centric architecture
US11656937B2 (en) * 2020-08-25 2023-05-23 Micron Technology, Inc. Techniques for error detection and correction in a memory system

Family Cites Families (50)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5329489A (en) 1988-03-31 1994-07-12 Texas Instruments Incorporated DRAM having exclusively enabled column buffer blocks
US5412787A (en) 1990-11-21 1995-05-02 Hewlett-Packard Company Two-level TLB having the second level TLB implemented in cache tag RAMs
US5848433A (en) 1995-04-12 1998-12-08 Advanced Micro Devices Way prediction unit and a method for operating the same
US5764946A (en) 1995-04-12 1998-06-09 Advanced Micro Devices Superscalar microprocessor employing a way prediction unit to predict the way of an instruction fetch address and to concurrently provide a branch prediction address corresponding to the fetch address
US5845323A (en) 1995-08-31 1998-12-01 Advanced Micro Devices, Inc. Way prediction structure for predicting the way of a cache in which an access hits, thereby speeding cache access time
US5802594A (en) 1995-09-06 1998-09-01 Intel Corporation Single phase pseudo-static instruction translation look-aside buffer
JPH09110582A (ja) 1995-10-11 1997-04-28 Kokusai Chodendo Sangyo Gijutsu Kenkyu Center 結晶製造装置
US6061759A (en) 1996-02-09 2000-05-09 Apex Semiconductor, Inc. Hidden precharge pseudo cache DRAM
US5974506A (en) 1996-06-28 1999-10-26 Digital Equipment Corporation Enabling mirror, nonmirror and partial mirror cache modes in a dual cache system
US20010034808A1 (en) 1996-07-19 2001-10-25 Atsushi Nakajima Cache memory device and information processing system
US5784391A (en) 1996-10-08 1998-07-21 International Business Machines Corporation Distributed memory system with ECC and method of operation
JPH10207726A (ja) * 1997-01-23 1998-08-07 Oki Electric Ind Co Ltd 半導体ディスク装置
US6044478A (en) 1997-05-30 2000-03-28 National Semiconductor Corporation Cache with finely granular locked-down regions
US6073230A (en) 1997-06-11 2000-06-06 Advanced Micro Devices, Inc. Instruction fetch unit configured to provide sequential way prediction for sequential instruction fetches
US6138213A (en) 1997-06-27 2000-10-24 Advanced Micro Devices, Inc. Cache including a prefetch way for storing prefetch cache lines and configured to move a prefetched cache line to a non-prefetch way upon access to the prefetched cache line
US6016533A (en) 1997-12-16 2000-01-18 Advanced Micro Devices, Inc. Way prediction logic for cache array
KR100313996B1 (ko) 1998-01-08 2001-12-28 구자홍 컴퓨터시스템의바이오스데이터저장장치및방법
JP3307579B2 (ja) * 1998-01-28 2002-07-24 インターナショナル・ビジネス・マシーンズ・コーポレーション データ記憶システム
US6038693A (en) 1998-09-23 2000-03-14 Intel Corporation Error correction scheme for an integrated L2 cache
US6314514B1 (en) 1999-03-18 2001-11-06 Ip-First, Llc Method and apparatus for correcting an internal call/return stack in a microprocessor that speculatively executes call and return instructions
US6493800B1 (en) 1999-03-31 2002-12-10 International Business Machines Corporation Method and system for dynamically partitioning a shared cache
US6353910B1 (en) * 1999-04-09 2002-03-05 International Business Machines Corporation Method and apparatus for implementing error correction coding (ECC) in a dynamic random access memory utilizing vertical ECC storage
US6629207B1 (en) 1999-10-01 2003-09-30 Hitachi, Ltd. Method for loading instructions or data into a locked way of a cache memory
US6745310B2 (en) 2000-12-01 2004-06-01 Yan Chiew Chow Real time local and remote management of data files and directories and method of operating the same
US6804162B1 (en) 2001-04-05 2004-10-12 T-Ram, Inc. Read-modify-write memory using read-or-write banks
US6662272B2 (en) 2001-09-29 2003-12-09 Hewlett-Packard Development Company, L.P. Dynamic cache partitioning
US7007210B2 (en) 2002-01-30 2006-02-28 International Business Machines Corporation Method and system for handling multiple bit errors to enhance system reliability
US7234052B2 (en) 2002-03-08 2007-06-19 Samsung Electronics Co., Ltd System boot using NAND flash memory and method thereof
US6832294B2 (en) 2002-04-22 2004-12-14 Sun Microsystems, Inc. Interleaved n-way set-associative external cache
US7054999B2 (en) 2002-08-02 2006-05-30 Intel Corporation High speed DRAM cache architecture
US20050050278A1 (en) 2003-09-03 2005-03-03 Advanced Micro Devices, Inc. Low power way-predicted cache
US7117290B2 (en) 2003-09-03 2006-10-03 Advanced Micro Devices, Inc. MicroTLB and micro tag for reducing power in a processor
US7237098B2 (en) 2003-09-08 2007-06-26 Ip-First, Llc Apparatus and method for selectively overriding return stack prediction in response to detection of non-standard return sequence
US20050228631A1 (en) 2004-04-07 2005-10-13 Maly John W Model specific register operations
US7558920B2 (en) 2004-06-30 2009-07-07 Intel Corporation Apparatus and method for partitioning a shared cache of a chip multi-processor
US7996644B2 (en) 2004-12-29 2011-08-09 Intel Corporation Fair sharing of a cache in a multi-core/multi-threaded processor by dynamically partitioning of the cache
JP4080527B2 (ja) 2005-03-22 2008-04-23 松下電器産業株式会社 キャッシュメモリ制御方法およびキャッシュメモリ制御装置
JP4201783B2 (ja) 2005-08-04 2008-12-24 富士通マイクロエレクトロニクス株式会社 キャッシュメモリ装置、半導体集積回路およびキャッシュ制御方法
US7676730B2 (en) * 2005-09-30 2010-03-09 Quantum Corporation Method and apparatus for implementing error correction coding in a random access memory
US7707463B2 (en) 2005-11-30 2010-04-27 International Business Machines Corporation Implementing directory organization to selectively optimize performance or reliability
US7620875B1 (en) 2006-03-07 2009-11-17 Xilinx, Inc. Error correction code memory system with a small footprint and byte write operation
US7739576B2 (en) * 2006-08-31 2010-06-15 Micron Technology, Inc. Variable strength ECC
US8135935B2 (en) 2007-03-20 2012-03-13 Advanced Micro Devices, Inc. ECC implementation in non-ECC components
US7809980B2 (en) 2007-12-06 2010-10-05 Jehoda Refaeli Error detector in a cache memory using configurable way redundancy
US8589706B2 (en) 2007-12-26 2013-11-19 Intel Corporation Data inversion based approaches for reducing memory power consumption
US20090276587A1 (en) 2008-04-30 2009-11-05 Moyer William C Selectively performing a single cycle write operation with ecc in a data processing system
US8266498B2 (en) 2009-03-31 2012-09-11 Freescale Semiconductor, Inc. Implementation of multiple error detection schemes for a cache
US8327225B2 (en) * 2010-01-04 2012-12-04 Micron Technology, Inc. Error correction in a stacked memory
US8644104B2 (en) * 2011-01-14 2014-02-04 Rambus Inc. Memory system components that support error detection and correction
JP5426711B2 (ja) * 2011-06-08 2014-02-26 パナソニック株式会社 メモリコントローラ及び不揮発性記憶装置

Also Published As

Publication number Publication date
US8984368B2 (en) 2015-03-17
CN104871137B (zh) 2019-02-01
US20140108885A1 (en) 2014-04-17
KR101626040B1 (ko) 2016-06-13
KR20150070252A (ko) 2015-06-24
CN104871137A (zh) 2015-08-26
EP2907030A1 (en) 2015-08-19
WO2014058879A1 (en) 2014-04-17
IN2015DN02935A (en:Method) 2015-09-18
JP2015535101A (ja) 2015-12-07

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