JP6069956B2 - Transistor optimum load characteristic measuring apparatus and transistor optimum load characteristic measuring method - Google Patents

Description

  The present invention relates to a measuring device and measuring method for optimum transistor load characteristics, and can be suitably used for, for example, a device for measuring optimum load characteristics and a method for measuring optimum load characteristics in a frequency band where parasitic components having frequency characteristics cannot be ignored. is there.

  For an amplifier using a transistor or the like used mainly in a high frequency region where wireless communication or wireless power transmission is performed, there is a demand for a method for obtaining an optimum load impedance for a waveform including harmonics.

  In the field of high efficiency amplifiers, various types such as a class F amplifier, an inverse class F amplifier, a class E amplifier, and a class J amplifier have been proposed. These amplifiers share a basic concept. In other words, in the waveform of the voltage applied to the transistor and the waveform of the current flowing into the transistor, during the period when one is a finite value, the other is zero or the minimum value. In this way, high efficiency is achieved by suppressing power consumption in the transistor to zero or to a minimum.

  At this time, the shape of the voltage waveform and the shape of the current waveform are important. These waveforms are represented by the sum of the fundamental wave and its harmonics. Therefore, these waveforms are adjusted by adjusting the load impedance for each of the fundamental wave and each harmonic.

  However, the amplitude and phase of the voltage waveform and current waveform cannot be completely adjusted only by the load impedance. This is because the characteristics of the transistor itself as an equivalent nonlinear current source are involved. This characteristic of a transistor depends on many parameters such as the type, shape, and manufacturing process of the semiconductor. Therefore, in practice, it is difficult to realize an ideal operation for the various types described above, and it is necessary to estimate an optimum load impedance for each individual transistor.

  One method for obtaining the optimum load impedance condition for each individual transistor is a method of optimization by numerical simulation. However, in order to realize this method, a very precise large-signal transistor model that can be used in numerical simulation is required, which is very difficult in practice.

  As another method, there is a method of adjusting various impedances experimentally. However, in the microwave band, the system becomes very complicated and expensive, and at present, the adjustment to the third harmonic at most is the limit.

  Non-Patent Literature 1 (Frederick H. Raab, “Class-E, Class-C, Class-F Power Amplifiers Based Up a Number of Harmonics”, IEEE TRANSACTION SONNON E. , AUGUST 2001.), mathematically analyzing and calculating the voltage and current waveforms in the transistor, the efficiency increases gradually with increasing harmonic order. It is known to go.

JP 2012-027034 A

Frederick H.M. Raab, “Class-E, Class-C, Class-F Power Amplifiers Based Up a Finite Number of Harmonics”, IEEE TRANSACTIONS ON MICROWAVE AND QUALITY. 49, NO. 8, AUGUST 2001.

  According to the present invention, even a third-order or higher harmonic can be adjusted by a relatively simple measuring device and measuring method. Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

  The means for solving the problem will be described below using the numbers used in the (DETAILED DESCRIPTION). These numbers are added to clarify the correspondence between the description of (Claims) and (Mode for Carrying Out the Invention). However, these numbers should not be used to interpret the technical scope of the invention described in (Claims).

  According to one embodiment, a transistor optimum load characteristic measuring apparatus and a transistor optimum load characteristic measuring method are characterized by converting a transistor characteristic into a parasitic component characteristic depending on a frequency of an input signal and an intrinsic part characteristic other than the parasitic component characteristic. The optimum load for the parasitic component characteristic and the intrinsic part characteristic is measured separately, and the transistor optimum load characteristic is calculated based on the measurement results.

  According to the one embodiment, the optimum load characteristic of the transistor to be measured is measured in a frequency band lower than the operating frequency band where the intrinsic part characteristic independent of the frequency is originally expected, and the frequency-dependent parasitic component Since the characteristics are measured separately and the optimum load characteristics of the transistor are calculated from these measured values, it is possible to use a relatively simple measuring device. Also, based on these measurement results, a load circuit having optimum characteristics can be designed.

FIG. 1 is a functional block diagram showing the configuration of a transistor optimum load characteristic measuring apparatus according to an embodiment of the present invention. FIG. 2A is a block circuit diagram showing a more detailed configuration of the connection unit 10 in the transistor optimum load characteristic measuring apparatus according to the first embodiment of the present invention. FIG. 2B is a block circuit diagram showing a more detailed configuration of the connection circuit unit 11 in the connection unit 10 according to the first embodiment of the present invention. FIG. 3A is a graph showing an example of results obtained by measuring waveforms at the drain-source voltage Vds and the drain current Id using the transistor optimum load characteristic measuring apparatus according to the first embodiment of the present invention. FIG. 3B is a Smith chart showing an example of a result of measuring a change in transistor load characteristics with frequency using the transistor optimum load characteristic measuring apparatus according to the first embodiment of the present invention. FIG. 3C is a graph showing another example of the result of measuring the waveforms at the drain-source voltage Vds and the drain current Id using the transistor optimum load characteristic measuring apparatus according to the first embodiment of the present invention. . FIG. 3D is a Smith chart showing another example of a result of measuring a change in transistor load characteristics with frequency using the transistor optimum load characteristic measuring apparatus according to the first embodiment of the present invention. FIG. 4 is a graph showing the characteristics of a prototyped amplifier based on the transistor load characteristic measurement results obtained by using the transistor optimum load characteristic measuring apparatus and transistor optimum load characteristic measuring method according to the first embodiment of the present invention. It is. FIG. 5A shows the result of measuring the waveforms of the drain-source voltage Vds and the drain current Id measured using the transistor optimum load characteristic measuring apparatus and transistor optimum load characteristic measuring method according to the first embodiment of the present invention. It is a graph which shows an example. FIG. 5B is a Smith chart showing an example of a result of measuring a change in transistor load characteristic with frequency, measured using the transistor optimum load characteristic measuring apparatus and transistor optimum load characteristic measuring method according to the first embodiment of the present invention. It is. FIG. 6A is a block circuit diagram showing a configuration of the connection circuit unit 11 in the transistor optimum load characteristic measuring apparatus according to the second embodiment of the present invention. FIG. 6B is a block circuit diagram showing a configuration of the connection circuit unit 11 in the transistor optimum load characteristic measuring apparatus according to the third embodiment of the present invention.

  With reference to the accompanying drawings, a mode for carrying out a measuring apparatus and a measuring method for optimum transistor load characteristics according to the present invention will be described below.

(First embodiment)
The principle on which the present invention is based will be described. The characteristics of the transistor can be considered by dividing it into a parasitic component characteristic depending on the frequency of the input signal and an intrinsic part characteristic other than the parasitic component characteristic. In the present invention, the parasitic component characteristic and the optimum load characteristic with respect to the intrinsic part characteristic are measured separately, and then the optimum load characteristic of the transistor is calculated based on these measurement results.

  More specifically, an input signal adjusted so that the transistor performs a large signal nonlinear operation is generated and input to the input side of the transistor. At the same time, another signal including a fundamental wave and a harmonic wave synchronized with the input signal is generated and input to the output side of the transistor. At this time, the current waveform and voltage waveform of the transistor are directly measured using an oscilloscope or the like connected to the output side of the transistor.

  Such a measurement method is difficult to realize in the expected operating frequency band such as the current GHz (gigahertz) band, but can be sufficiently realized in a frequency band such as a lower MHz (megahertz) band. is there. Furthermore, in a relatively low frequency band such as the MHz band, parasitic component characteristics such as capacitance and inductance appearing inside a transistor operating at a high frequency can be ignored, so that other intrinsic part characteristics can be obtained. In other words, since the intrinsic part of the transistor can be expressed as a nonlinear current source whose characteristics do not depend on the frequency, optimization can be achieved even in the measurement in the MHz band. That is, the measurement result obtained in this way can be regarded as intrinsic part characteristics in the GHz band.

  On the other hand, the parasitic component characteristics of a transistor in a frequency band such as the GHz band can be measured using a network analyzer or the like. This measurement result is obtained in the form of, for example, an S parameter group, and a mathematical method for converting the S parameter group into a Y parameter group is known. By adding the parasitic component characteristics converted into the Y parameter group format to the intrinsic part characteristics in the frequency band such as the GHz band, the transistor characteristics in the expected operating frequency band can be obtained.

  Here, it should be noted that conventional equipment can be used as it is as an oscilloscope or network analyzer.

  Therefore, the transistor optimum load characteristic measuring method according to the first embodiment of the present invention includes the following steps. First, a transistor as a characteristic measurement target is prepared and connected to a transistor optimum load characteristic measurement apparatus. Next, among the characteristics of the transistor, the optimum load characteristic with respect to the intrinsic part characteristic is measured. Further, among the characteristics of the transistor, the parasitic component characteristics are measured. Note that either the measurement of the optimum load characteristic with respect to the intrinsic part characteristic or the measurement of the parasitic component characteristic may be performed first, or a part of the existing measurement result may be used. Finally, based on the measurement result of the optimum load characteristic with respect to the intrinsic part characteristic and the measurement result of the parasitic component characteristic, the parameters of the load circuit suitable for the transistor are calculated.

  The transistor optimum load characteristic measuring apparatus used for performing the transistor optimum load characteristic measuring method according to the first embodiment of the present invention will be described. Here, a case where characteristics in a GHz band of a transistor to be measured are obtained will be described as a specific example.

  FIG. 1 is a functional block diagram showing the configuration of a transistor optimum load characteristic measuring apparatus according to an embodiment of the present invention. The transistor optimum load characteristic measuring apparatus shown in FIG. 1 includes a connection unit 10, an input signal generation unit 20, a measurement unit 30, and a calculation unit 40.

  FIG. 2A is a block circuit diagram showing a more detailed configuration of the connection unit 10 in the transistor optimum load characteristic measuring apparatus according to the first embodiment of the present invention. 2A includes a first connection terminal 101, a second connection terminal 102, a third connection terminal 103, a first input terminal 104, a second input terminal 105, and a first output terminal 106. And a second output terminal 107 and a connection circuit unit 11.

  The connection relationship of the components of the connection unit 10 illustrated in FIG. 2A will be described. The first connection terminal 101 is connected to the first input terminal 104. The second connection terminal 102, the second input terminal 105, the first output terminal 106, and the second output terminal 107 are connected to the connection circuit unit 11. The third connection terminal 103 is grounded. The connection circuit unit 11 is grounded.

  The first connection terminal 101 is connected to the gate of the transistor 1. The second connection terminal 102 is connected to the drain of the transistor 1. The third connection terminal 103 is connected to the source of the transistor 1. Note that the connection relationship of the first to third connection terminals 101 to 103 can be appropriately exchanged depending on the polarity of the transistor 1, the change of the grounding method, and the like.

  The first input terminal 104 and the second input terminal 105 are connected to the input signal generation unit 20. The first output terminal 106 and the second output terminal 107 are connected to the measurement unit 30.

  A voltage between the second connection terminal 102 and the ground is referred to as a drain-source voltage Vds. A voltage between the first input terminal 104 and the ground is referred to as a first input voltage Va. A voltage between the second input terminal 105 and the ground is referred to as a second input voltage Vb. A current flowing into the drain is referred to as a drain current Id.

  The first input voltage Va may be, for example, the sum of a direct current component va0 and an alternating current component va × sin (ωt). Here, va represents the amplitude of the AC component, ω represents the angular frequency of the fundamental frequency, and t represents time.

  The second input voltage Vb may be, for example, the sum of the direct current component vb0 and the alternating current component Σ (vbi × sin (iωt + θbi)). Here, i represents the harmonic number, vbi represents the amplitude of the i-th harmonic, ω represents the angular frequency of the fundamental frequency, t represents time, and θbi represents the phase of the i-th harmonic component. Represent.

  The load-side impedance is obtained by dividing the drain-source voltage Vds by the reciprocal of the drain current Id. At this time, since a sufficiently large signal is supplied to the input side of the transistor 1 so that the transistor 1 performs a nonlinear operation, the transistor 1 itself outputs an output signal including a fundamental wave and a harmonic. On the other hand, when signals having the same frequency are supplied from the output side, standing waves are generated at the fundamental and harmonic frequencies. Furthermore, by appropriately adjusting the amplitude and phase of the signal supplied from the output side, various reflection coefficients can be realized, and an equivalent impedance can be adjusted. Therefore, the value of the load impedance connected to the transistor 1 can be changed in various ways equivalently including the harmonic region. By doing so, it is possible to find an optimum impedance that realizes high efficiency characteristics and the like.

  FIG. 2B is a block circuit diagram showing a more detailed configuration of the connection circuit unit 11 in the connection unit 10 according to the first embodiment of the present invention. The connection circuit unit 11 illustrated in FIG. 2B includes first to fifth resistors 111 to 115.

  The connection relationship of the components of the connection circuit unit 11 illustrated in FIG. 2B will be described. One end of the first resistor 111 is connected to the second connection terminal 102 and one end of the second resistor 112. The other end of the second resistor 112 is connected to the first output terminal 106 and one end of the third resistor 113. The other end of the third resistor 113 is grounded. The other end of the first resistor 111 is connected to the second input terminal 105 and one end of the fourth resistor 114. The other end of the fourth resistor 114 is connected to the second output terminal 107 and one end of the fifth resistor 115. The other end of the fifth resistor 115 is grounded.

  Among the components shown in FIG. 2B, those not included in the connection circuit unit 11 are the same as those in FIG. 2A, and thus further detailed description is omitted.

  An example in which the optimum load characteristic of the transistor 1 to be measured is actually measured using the transistor optimum load characteristic measuring apparatus according to the first embodiment of the present invention will be described. In this example, an existing 2-output arbitrary waveform generator and network analyzer are used as the input signal generation unit 20, an existing digital oscilloscope is used as the measurement unit 30, and a 2-output arbitrary waveform generator, digital oscilloscope and network are used as the calculation unit 40. A computer controlling the analyzer was used. This computer includes a storage unit for storing a transistor optimum load characteristic measurement program, an output unit for generating and outputting a control signal for controlling a 2-output arbitrary waveform generator, a digital oscilloscope and a network analyzer, and a measurement result obtained by the digital oscilloscope and the network analyzer. Input unit, a storage unit for storing the measurement result, and a calculation unit for performing various calculations based on the measurement result. The transistor optimum load characteristic measurement program generates the transistor optimum load characteristic measurement method according to the first embodiment of the present invention so that it can be executed by a computer, and appropriately controls the operations of the input signal generation unit 20 and the measurement unit 30. And is stored in the storage unit.

  When using existing measurement result data as part of the optimum load characteristic and parasitic component characteristic for the intrinsic part characteristic, the measurement part 30 includes a storage part storing the data, an input part for inputting the data from the outside, and the like. It has.

  In the measurement of the optimum load characteristic with respect to the intrinsic part characteristic, a resistance part is connected in series to the output terminal of the transistor 1, the voltage at both ends of the resistance part is measured, and the drain current Id flowing into the transistor 1 is calculated from the measurement result. ing. Further, the impedance of the fundamental wave and the harmonic wave is calculated by decomposing the voltage waveform and the current waveform into frequency components by signal processing by discrete Fourier transform and calculating “voltage / (− current)” for each frequency. .

  Two examples of results obtained by actually performing such measurement will be introduced with reference to FIGS. 3A to 3D.

  FIG. 3A is a graph showing an example of results obtained by measuring waveforms at the drain-source voltage Vds and the drain current Id using the transistor optimum load characteristic measuring apparatus according to the first embodiment of the present invention. The measurement of FIG. 3A is performed at the fundamental frequency f0 = 20 MHz.

  The graph shown in FIG. 3A includes a first graph V4A and a second I4A. The first graph V4A represents the time change of the drain-source voltage Vds. In the first graph V4A, the horizontal axis represents time, and the vertical axis represents voltage value. The second graph I4A represents the time change of the drain current Id. In the second graph I4A, the horizontal axis represents time, and the vertical axis represents the current value.

  FIG. 3B is a Smith chart showing an example of a result of measuring a change in transistor load characteristics with frequency using the transistor optimum load characteristic measuring apparatus according to the first embodiment of the present invention. The measurement in FIG. 3B is performed under the same conditions as in FIG. 3A, and the fundamental frequency f0 = 20 MHz.

  The Smith chart shown in FIG. 3B includes first to fifth measurement points F14B to F54B. The first measurement point F14B indicates the transistor load characteristic at the fundamental frequency f0. The second measurement point F24B indicates the transistor load characteristic at the second harmonic frequency 2f0. The third measurement point F34B indicates the transistor load characteristic at the third harmonic frequency 3f0. The fourth measurement point F44B indicates the transistor load characteristic at the fourth harmonic frequency 4f0. The fifth measurement point F54B indicates the transistor load characteristic at the fifth harmonic frequency 5f0.

  In the measurements shown in FIGS. 3A and 3B, a drain efficiency of 84% was obtained.

  FIG. 3C is a graph showing another example of the result of measuring the waveforms at the drain-source voltage Vds and the drain current Id using the transistor optimum load characteristic measuring apparatus according to the first embodiment of the present invention. . The measurement of FIG. 3A is performed at the fundamental frequency f0 = 20 MHz.

  The graph shown in FIG. 3C includes a first graph V4C and a second I4C. The first graph V4C represents the time change of the drain-source voltage Vds. In the first graph V4C, the horizontal axis represents time, and the vertical axis represents voltage value. The second graph I4C represents the time change of the drain current Id. In the second graph I4C, the horizontal axis represents time, and the vertical axis represents the current value.

  FIG. 3D is a Smith chart showing another example of a result of measuring a change in transistor load characteristics with frequency using the transistor optimum load characteristic measuring apparatus according to the first embodiment of the present invention. The measurement in FIG. 3D is performed under the same conditions as in FIG. 3C, and the fundamental frequency f0 = 20 MHz.

  The Smith chart shown in FIG. 3D includes first to fifth measurement points F14D to F54D. The first measurement point F14D indicates the transistor load characteristic at the fundamental frequency f0. The second measurement point F24D indicates the transistor load characteristic at the second harmonic frequency 2f0. The third measurement point F34D indicates the transistor load characteristic at the third harmonic frequency 3f0. The fourth measurement point F44D indicates the transistor load characteristic at the fourth harmonic frequency 4f0. The fifth measurement point F54D indicates the transistor load characteristic at the fifth harmonic frequency 5f0.

  In the measurements shown in FIGS. 3C and 3D, a drain efficiency of 86% was obtained.

  For example, the parasitic component characteristics are measured as follows. A 2-port network analyzer is connected as the input signal generator 20. When the second connection terminal 102 is reconnected to the second input terminal 105 in the connection unit 10 to which the transistor 1 is connected, a two-terminal pair circuit including the first input terminal 104, the second input terminal 105, and the ground is obtained. By connecting the first port of the network analyzer to the first input terminal 104 and connecting the second port of the network analyzer to the second input terminal 105, the 2-port S parameter of the transistor 1 is measured. Specifically, the reference wave output from the first port of the network analyzer is input to the first input terminal 104, the reflected power output from the first input terminal 104 is measured, and the S11 parameter is calculated from the measurement result. . Similarly, the reference wave is input to the first input terminal 104, the passing power output from the second input terminal 105 is measured, and the S21 parameter is calculated. The reference wave output from the second port of the network analyzer is input to the second input terminal 105, the reflected power output from the second input terminal 105 is measured, and the S22 parameter is calculated from the measurement result. Similarly, the reference wave is input to the second input terminal 105, the passing power output from the first input terminal 104 is measured, and the S12 parameter is calculated.

  Note that the switching of the connection relationship between the connection unit 10 and the input signal generation unit 20 that is required when measuring each of the S parameters is preferably performed appropriately by control performed by the calculation unit 40.

  FIG. 4 is a graph showing the characteristics of a prototyped amplifier based on the transistor load characteristic measurement results obtained by using the transistor optimum load characteristic measuring apparatus and transistor optimum load characteristic measuring method according to the first embodiment of the present invention. It is. The graph shown in FIG. 4 includes first to fourth graphs G1 to G4.

  The first graph G1 represents the change with the input power of the gain in the amplifier according to the first embodiment of the present invention. In the first graph G1, the horizontal axis represents input power, and the vertical axis represents gain. The second graph G2 represents a change with the input power of the output power in the amplifier according to the first embodiment of the present invention. In the second graph G2, the horizontal axis represents input power, and the vertical axis represents output power. The third graph G3 represents the change with the input power of the efficiency in the amplifier according to the first embodiment of the invention. In the third graph G3, the horizontal axis represents input power, and the vertical axis represents efficiency. The fourth graph G4 represents the change with the input power of the power added efficiency in the amplifier according to the first embodiment of the present invention. In the fourth graph G4, the horizontal axis represents input power, and the vertical axis represents power added efficiency.

  As parameters common to the first to fourth graphs G1 to G4, the fundamental frequency f0 is 1.88 GHz, the drain-source voltage Vds is 3.7 V, and the gate-source voltage Vgs is −1. 0.0V.

  As can be read from the third graph G3 shown in FIG. 4, in this example, a high efficiency load characteristic with a maximum efficiency of 77% was confirmed by actual measurement.

  However, in this example, it was confirmed that the prototype load circuit was deviated from the optimized design value. Therefore, in order to estimate the degree of characteristic degradation due to deviation from the design value of the prototype load circuit, we calculated the load circuit characteristics taking this deviation into account, and measured the results for the characteristics. Shown in 5A and FIG. 5B.

  FIG. 5A shows the result of measuring the waveforms of the drain-source voltage Vds and the drain current Id measured using the transistor optimum load characteristic measuring apparatus and transistor optimum load characteristic measuring method according to the first embodiment of the present invention. It is a graph which shows an example. The measurement of FIG. 5A is performed at the fundamental frequency f0 = 20 MHz.

  The graph shown in FIG. 5A includes a first graph V8A and a second I8A. The first graph V8A represents the time change of the drain-source voltage Vds. In the first graph V8A, the horizontal axis represents time, and the vertical axis represents voltage value. The second graph I8A represents the time change of the drain current Id. In the second graph I8A, the horizontal axis represents time, and the vertical axis represents the current value.

  FIG. 5B is a Smith chart showing an example of a result of measuring a change in transistor load characteristic with frequency, measured using the transistor optimum load characteristic measuring apparatus and transistor optimum load characteristic measuring method according to the first embodiment of the present invention. It is. The measurement in FIG. 5B is performed under the same conditions as in FIG. 5A, and the fundamental frequency is f0 = 20 MHz.

  The Smith chart shown in FIG. 5B includes first to fifth measurement points F18B to F58B. The first measurement point F18B indicates the transistor load characteristic at the fundamental frequency f0. The second measurement point F28B indicates the transistor load characteristic at the second harmonic frequency 2f0. The third measurement point F38B indicates the transistor load characteristic at the third harmonic frequency 3f0. The fourth measurement point F48B indicates the transistor load characteristic at the fourth harmonic frequency 4f0. The fifth measurement point F58B indicates the transistor load characteristic at the fifth harmonic frequency 5f0.

  From the measurement results shown in FIGS. 5A and 5B, it was confirmed that the drain efficiency was reduced from 86% to 80%. As a result, it is predicted that further improvement in efficiency can be expected by correcting the load circuit.

  As described above, according to the transistor optimum load characteristic measuring apparatus and the transistor optimum load characteristic measuring method according to the first embodiment of the present invention, the optimum condition for an arbitrary transistor can be derived experimentally and simply. It becomes possible. Moreover, it is possible to simply evaluate the obtained measurement result.

(Second Embodiment)
A transistor optimum load characteristic measuring apparatus according to a second embodiment of the present invention will be described. The transistor optimum load characteristic measuring apparatus according to the second embodiment of the present invention has the configuration of the connection circuit unit 11 in the transistor optimum load characteristic measuring apparatus according to the first embodiment of the present invention shown in FIGS. 2A and 2B. Equal to the change. Since the other components of the transistor optimum load characteristic measuring apparatus according to the second embodiment of the present invention are the same as those of the transistor optimum load characteristic measuring apparatus according to the first embodiment, further detailed description will be given. Omitted.

  FIG. 6A is a block circuit diagram showing a configuration of the connection circuit unit 11 in the transistor optimum load characteristic measuring apparatus according to the second embodiment of the present invention. The connection circuit unit 11 illustrated in FIG. 6A includes first to third resistors 111 to 113.

  A connection relationship of the components of the connection circuit unit 11 illustrated in FIG. 6A will be described. One end of the first resistor 111 is connected to the second connection terminal 102, the first output terminal 106, and one end of the second resistor 112. Here, the first output terminal 106 is connected to a line connecting one end of the first resistor 111 and the second connection terminal 102 via a current probe. The other end of the second resistor 112 is connected to the second output terminal 107 and one end of the third resistor 113. The other end of the third resistor 113 is grounded. The other end of the first resistor 111 is connected to the second input terminal 105.

  In the transistor optimum load characteristic measuring method according to the second embodiment of the present invention, the drain current Id is directly measured using a current probe. Other details are the same as in the case of the first embodiment of the present invention, and a description thereof will be omitted.

(Third embodiment)
A transistor optimum load characteristic measuring apparatus according to a third embodiment of the present invention will be described. The transistor optimum load characteristic measuring apparatus according to the third embodiment of the present invention has the configuration of the connection circuit unit 11 in the transistor optimum load characteristic measuring apparatus according to the first embodiment of the present invention shown in FIGS. 2A and 2B. Equal to the change. The other components of the transistor optimum load characteristic measuring apparatus according to the third embodiment of the present invention are the same as those of the transistor optimum load characteristic measuring apparatus according to the first embodiment, so that further detailed description will be given. Omitted.

  FIG. 6B is a block circuit diagram showing a configuration of the connection circuit unit 11 in the transistor optimum load characteristic measuring apparatus according to the third embodiment of the present invention. The connection circuit unit 11 shown in FIG. 6B is equivalent to the connection circuit unit 11 according to the first embodiment of the present invention shown in FIG. 2B, to which an amplifier 116 and a bias circuit 12 are added. The other components of the connection circuit unit 11 shown in FIG. 6B are the same as those in the first embodiment of the present invention shown in FIG.

  The components of the bias circuit 12 shown in FIG. 6B will be described. The bias circuit 12 includes a capacitor 121, an inductor 122, and a DC voltage source 123.

  The connection relationship of the components of the connection circuit unit 11 illustrated in FIG. 6B will be described. The second input terminal 105 is connected to the input unit of the amplifier 116. An output portion of the amplifier 116 is connected to one end portion of the capacitor 121. The other end of the capacitor 121 is connected to one end of the inductor 122, the other end of the first resistor 111, and one end of the fourth resistor 114. The other end of the inductor 122 is connected to one end of the DC voltage source 123. The other end of the DC voltage source 123 is grounded. Since other connection relationships of the components of the connection circuit unit 11 shown in FIG. 6B are the same as those in the first embodiment of the present invention shown in FIG. 2B, further detailed description is omitted.

  The transistor optimum load characteristic measuring apparatus according to the third embodiment of the present invention is particularly suitable for measuring the optimum load characteristic of a high voltage transistor. Since the transistor optimum load characteristic measuring method according to the third embodiment of the present invention is the same as that of the first embodiment of the present invention, further detailed description is omitted.

  The invention made by the inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say. In addition, the features described in the embodiments can be freely combined within a technically consistent range.

DESCRIPTION OF SYMBOLS 1 Transistor 10 Connection part 101 1st connection terminal 102 2nd connection terminal 103 3rd connection terminal 104 1st input terminal 105 2nd input terminal 106 1st output terminal 107 2nd output terminal 11 Connection circuit part 111-115 Resistance 116 Amplifier DESCRIPTION OF SYMBOLS 12 Bias circuit 121 Capacitor 122 Inductor 123 DC voltage source 20 Input signal generation part 30 Measurement part 40 Calculation part

Claims (7)

An input signal generation unit that generates a first input signal to be input to an input side of an arbitrary transistor that is a characteristic measurement target, and generates a second input signal to be input to an output side of the transistor;
Among the characteristics of the transistor, a measurement unit that measures the optimum load characteristic for the intrinsic part characteristic other than the parasitic component characteristic that depends on the frequency of the input signal,
A calculation unit that calculates the characteristic of the transistor from the measurement value of the parasitic component characteristic and the measurement value of the optimum load characteristic with respect to the intrinsic part characteristic;
The first input signal is:
A fundamental frequency lower than the operating frequency of the transistor;
The transistor has a sufficiently large voltage amplitude to perform non-linear operation;
The second input signal is
A fundamental wave component having the fundamental frequency;
A harmonic component having a frequency that is an integral multiple of the fundamental frequency,
The measurement unit has a drain-source voltage of the transistor in a measurement state in which the first input signal is input to the input side of the transistor and the second input signal is input to the output side of the transistor. And the drain current of the transistor,
The computing unit is
The load side impedance is calculated from the drain-source voltage and the drain current,
A transistor optimum load characteristic measurement device that calculates the optimum load characteristic for the intrinsic part characteristic of the transistor from the load side impedance. In the transistor optimum load characteristic measuring device according to claim 1,
In the measurement state, the first input signal and the second input signal are synchronized. The transistor optimum load characteristic measurement device. In the transistor optimum load characteristic measuring device according to claim 1 or 2,
Further comprising a connection for connecting the transistor to the input signal generator and the measurement unit;
The connecting portion is
A first connection terminal, a second connection terminal and a third connection terminal connecting the gate, drain and source of the transistor;
A first input unit comprising a connection circuit unit connected to the second connection terminal;
The input side of the connecting portion is
A first input terminal conducted to the first connection terminal;
A second input terminal connected to the second input part of the connection circuit part,
The output side of the connecting portion is
A first output terminal connected to a first output portion of the connection circuit portion;
A second output terminal connected to the second output part of the connection circuit part,
The connection circuit section is
A first impedance unit connected between the first input unit and the second input unit;
A transistor optimum load characteristic measuring apparatus comprising: a second impedance unit that is electrically connected to the first impedance and connected between the first output unit and the second output unit. In the transistor optimum load characteristic measuring device according to any one of claims 1 to 3,
The computing unit is
A transistor optimum load characteristic measuring apparatus comprising a design unit for calculating an impedance of a load circuit suitable for the transistor based on a calculation result of the characteristic. Generating a first input signal having a fundamental frequency lower than an operating frequency of an arbitrary transistor whose characteristic is to be measured, and a voltage amplitude sufficiently large for the transistor to perform a nonlinear operation;
Generating a second input signal including a fundamental component of the fundamental frequency and a harmonic component having an integer multiple of the fundamental frequency;
Measuring the drain-source voltage of the transistor in a measurement state in which the first input signal is input to the input side of the transistor and the second input signal is input to the output side of the transistor;
Measuring the drain current in the measurement state;
Calculating a load side impedance from the drain-source voltage and the drain current;
Calculating an optimum load characteristic for the intrinsic part characteristic of the transistor from the load-side impedance;
A transistor optimum load characteristic measurement method comprising: calculating the characteristic of the transistor from the optimum load characteristic with respect to the intrinsic part characteristic and a parasitic component characteristic. In the transistor optimum load characteristic measuring method according to claim 5,
In the measurement state, the first input signal and the second input signal are synchronized. A transistor optimum load characteristic measurement method. The transistor optimum load characteristic measuring method according to claim 5 or 6,
Said calculating is
A transistor optimum load characteristic measuring method, further comprising: calculating an impedance of a load circuit suitable for the transistor based on a calculation result of the characteristic.

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