JP6019937B2 - Manufacturing method of semiconductor device - Google Patents

Description

The present invention relates to a method of manufacturing a semiconductor equipment having a thin portion formed by electrochemical etching.

  Conventionally, as a semiconductor sensor having a thin portion, that is, a diaphragm, a piezoresistive pressure sensor, an acceleration sensor, or the like is known. For example, Patent Document 1 proposes that a diaphragm is formed by an electrochemical etching process on a semiconductor wafer in order to accurately control the thickness of the diaphragm that affects the detection accuracy.

  Here, Patent Document 1 proposes a configuration of a semiconductor device including two backflow prevention diodes. One diode is a backflow prevention diode during electrochemical etching, and the other diode is a backflow prevention diode during circuit operation. These diodes are formed as a lateral PNP transistor structure so that current flows near the surface of a wafer formed by forming an N-type epitaxial layer on a P-type semiconductor substrate.

  Further, a high-concentration n-type buried layer is formed in advance at the interface between the semiconductor substrate and the epitaxial layer. This is because each diode is formed by a bipolar process in the manufacturing process. The buried layer serves to prevent leakage current flowing from the diode region of the epitaxial layer to the semiconductor substrate side when a bias is applied to the wafer in the electrochemical etching process.

Japanese Patent No. 3564898

  In recent years, with the increase in accuracy, higher functionality, and higher integration of semiconductor sensors, one-chip integrated sensors for digital signal processing are becoming mainstream. For this reason, when manufacturing a semiconductor sensor, it is beginning to form a device by a manufacturing process of a CMOS process instead of a bipolar process.

  Here, since the semiconductor sensor proposed in Patent Document 1 is manufactured by adding an electrochemical etching process to the bipolar process, it is difficult to achieve high functionality and high integration. Therefore, it is conceivable to add an electrochemical etching process to the CMOS process in order to increase the functionality and integration of the semiconductor sensor.

  However, the diode structure formed by the CMOS process is a structure in which, for example, an N-type well region is formed in the surface layer portion of a P-type semiconductor substrate and a PN region is formed in the surface layer portion of the well region. A buried layer is not provided in the semiconductor substrate used in the process. For this reason, when the diode formed in the CMOS process is used in the forward direction, a leak current is generated from the well region to the semiconductor substrate via the parasitic PNP transistor formed in the thickness direction of the semiconductor substrate.

  Usually, in an electrochemical etching process, for example, when a semiconductor substrate is etched to a depletion layer formed in a PN junction portion between a P-type semiconductor substrate and an N-type well region formed in a surface layer portion of the semiconductor substrate, the etching is performed. A potential difference is generated between the liquid and the N-type well region. As a result, current flows in the etching solution, and etching stops.

  However, when the diode structure is formed on the semiconductor substrate in the CMOS process, the backflow prevention diode during electrochemical etching is used in the forward direction in the electrochemical etching process. For this reason, because of the influence of the above-described leakage current, a current flows in the etching solution even if the etching is not completed, and thus normal electrochemical etching cannot be performed as in the bipolar process. Therefore, there is a problem that the accuracy of the thickness of the diaphragm is deteriorated and a highly accurate semiconductor sensor cannot be realized.

The present invention has been made in view of the above point, be configured to include a diode formed in a CMOS process, the eye to provide a method of manufacturing a semiconductor equipment provided with a precision diaphragm formed by electrochemical etching Target.

In order to achieve the above object, the invention according to claim 1 operates based on the diaphragm (23) formed thinly by electrochemical etching and the operating power supply applied to the operating power supply terminal (7). In addition, a sensing unit (13) for detecting a physical quantity applied to the diaphragm (23) and a semiconductor device manufacturing method formed on the semiconductor substrate (11) are characterized by the following points.

That is, a diode element (17) for preventing backflow is formed on the semiconductor substrate (11) by a CMOS process, and a resistance element (16) is formed on the semiconductor substrate (11). Subsequently, a first energization path (14) for supplying an etching power from the outside via the resistance element (16) is formed in a portion of the semiconductor substrate (11) where the diaphragm (23) is formed. In addition, a second energization path (15) is formed for electrically connecting the portion of the semiconductor substrate (11) where the diaphragm (23) is formed and the operating power supply terminal (7).

Then, after forming the first energization path (14) and the second energization path (15), the diaphragm (23) of the semiconductor substrate (11) from the first energization path (14) through the resistance element (16) A diaphragm (23) is formed by supplying an etching power to the part and performing electrochemical etching on the semiconductor substrate (11) .

  According to this, even when an etching power source is supplied to the semiconductor substrate (11) from the outside through the first energization path (14) and the resistance element (16) during the electrochemical etching, the structure of the resistance element (16) is obtained. The resulting parasitic transistor does not occur in the semiconductor substrate (11). Even if the diode element (17) is formed by a CMOS process, it does not operate in the forward direction because it operates for backflow prevention during electrochemical etching.

  As described above, even in the configuration including the diode element (17) formed by the CMOS process, the leakage current from the structure of the diode element (17) to the semiconductor substrate (11) can be prevented during the electrochemical etching. . Further, since the leak current does not flow to the semiconductor substrate (11) during electrochemical etching, a structure in which a highly accurate diaphragm (23) is formed can be obtained.

  In addition, the code | symbol in the bracket | parenthesis of each means described in this column and the claim shows the correspondence with the specific means as described in embodiment mentioned later.

1 is a diagram showing an overall configuration of a semiconductor device according to a first embodiment of the present invention. It is sectional drawing of the semiconductor substrate in which the semiconductor sensor part of FIG. 1 was formed. It is the figure which showed the cross-section of the diode element of FIG. 1, and an equivalent circuit. FIG. 2 is a diagram showing a manufacturing process of the semiconductor device of FIG. 1. It is the figure which showed the circuit structure of the semiconductor sensor part which concerns on 3rd Embodiment of this invention. It is the figure which showed the circuit structure of the semiconductor sensor part which concerns on 4th Embodiment of this invention. It is sectional drawing of the semiconductor substrate in which the semiconductor sensor part of FIG. 6 was formed.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, the same or equivalent parts are denoted by the same reference numerals in the drawings. The P− type and P + type shown in the following embodiments correspond to the first conductivity type of the present invention, and the N− type and N + type correspond to the second conductivity type of the present invention.

(First embodiment)
Hereinafter, a first embodiment of the present invention will be described with reference to the drawings. The semiconductor device according to the present embodiment is configured as a semiconductor piezoresistive pressure sensor that detects, for example, the pressure of a pressure medium as a physical quantity.

  As shown in FIG. 1, the semiconductor device includes a semiconductor sensor unit 1, an operational amplifier 2 (Amp), an analog-digital conversion circuit 3 (ADC), a digital correction arithmetic circuit 4, a memory 5 (ROM), And an output interface 6. Further, the semiconductor device has an operation power supply terminal 7 (Vcc), a piezoresistive island potential terminal 8 (VN +), an electrochemical etching power supply terminal 9 (Vin), and an output terminal for electrical connection with the outside. 10 (Vout). These are formed on the semiconductor substrate 11 shown in FIG.

  The semiconductor sensor unit 1 is configured to detect the pressure of the pressure medium. Specifically, as shown in FIG. 1, the semiconductor sensor unit 1 includes a constant current source 12, a sensing unit 13, a first energization path 14, a second energization path 15, a resistance element 16, and a diode element 17. And. In other words, it can be said that the semiconductor substrate 11 includes these components.

  The constant current source 12 is a circuit unit that generates a constant current based on the operation power supply applied to the operation power supply terminal 7. The constant current source 12 is provided in a path between the operation power supply terminal 7 and the sensing unit 13.

  The sensing unit 13 is a circuit unit configured to detect a pressure based on a constant current supplied from the constant current source 12 and to output a signal corresponding to the detected pressure. The sensing unit 13 includes a Wheatstone bridge circuit configured by connecting four piezoresistors 18 in a square shape. One pair of diagonal points of the Wheatstone bridge circuit are connected to a constant current source 12 and a reference potential (GND), respectively. A signal corresponding to the physical quantity is output from the other pair of diagonal points of the bridge circuit.

  As shown in FIG. 2, the sensing unit 13 is formed on a P− type semiconductor substrate 11. An N-type piezoresistive island 20 is formed on the surface layer portion on the one surface 19 side of the semiconductor substrate 11. The piezoresistive island 20 is a well region. Further, the other surface 21 side of the semiconductor substrate 11 is electrochemically etched to form a recess 22, and a part of the piezoresistive island 20 is exposed from the recess 22. The piezoresistive island 20 exposed from the recess 22 is a thin diaphragm 23.

  Then, four P + type piezoresistors 18 are formed on the surface layer portion of the piezoresistive island 20 at a connection portion between the diaphragm 23 and the piezoresistive island 20 so as to be separated from each other. Each piezoresistor 18 is electrically connected by a wiring (not shown) formed on the one surface 19 side of the semiconductor substrate 11.

  Further, an N + type highest potential region 24 is formed in the surface layer portion of the piezoresistive island 20 so as to be separated from the piezoresistor 18. The highest potential region 24 is electrically connected to the piezoresistive island potential terminal 8, and a predetermined voltage is applied via the piezoresistive island potential terminal 8 so as to be the highest potential during normal operation of the semiconductor sensor unit 1. . In FIG. 1, the maximum potential region 24 is shown, and the range of the piezoresistive island 20 is shown by a broken line.

  The first energization path 14 is a wiring path that connects the electrochemical etching power supply terminal 9 and the highest potential region 24. Specifically, the first energizing path 14 is a wiring path for supplying an etching power from the outside to a portion of the semiconductor substrate 11 where the diaphragm 23 is formed during the electrochemical etching of the semiconductor substrate 11.

  The second energization path 15 is a wiring path that connects the operation power supply terminal 7 and the highest potential region 24. The second energization path 15 is a path different from the wiring path connecting the operation power supply terminal 7 and the Wheatstone bridge circuit.

  The resistance element 16 is an element used when supplying the etching power to the highest potential region 24 in the semiconductor substrate 11 during the electrochemical etching of the semiconductor substrate 11. The resistance element 16 is provided in the first energization path 14, one end side of the resistance element 16 is connected to the electrochemical etching power supply terminal 9 through the first energization path 14, and the other end side is connected through the first energization path 14. Are connected to the highest potential region 24 of the semiconductor substrate 11.

  Such a resistance element 16 is formed on an insulating film (not shown) formed on the semiconductor substrate 11 as shown in FIG. In the present embodiment, a thin film fuse resistor is used as the resistance element 16. The thin film fuse resistor is formed of, for example, CrSi or polysilicon.

  The diode element 17 is used for backflow prevention for preventing current from flowing from the semiconductor substrate 11 to the sensing unit 13 via the second energization path 15 based on an etching power source applied to the semiconductor substrate 11 during electrochemical etching. As a role. The diode element 17 is provided in the second energization path 15 as shown in FIG.

  The diode element 17 is formed on the semiconductor substrate 11 by a CMOS process. As shown in FIG. 2, the diode element 17 is formed in an N− type well region 25 formed in the surface layer portion around the piezoresistive island 20 of the semiconductor substrate 11. In the surface layer portion of the well region 25, an N + type region 26 and a P + type region 27 formed so as to be separated from the N + type region 26 and sandwich the N + type region 26 are formed. One P + type region 27 is electrically connected to the operating power supply terminal 7 via the second energization path 15, and the other P + type region 27 and N + type region 26 are the highest via the second energization path 15. It is electrically connected to the potential region 24.

  That is, as shown in FIG. 3, the diode element 17 is configured as a PNP transistor, and this PNP transistor operates as a diode. As shown in FIG. 3, when the diode element 17 formed in the CMOS process is operated to flow a current in the forward direction, the leakage current IL is not limited by the parasitic PNP transistor generated in the thickness direction of the semiconductor substrate 11. Flows.

  The operational amplifier 2 shown in FIG. 1 is a circuit unit for amplifying an analog signal input from the semiconductor sensor unit 1 with a predetermined amplification factor. The operational amplifier 2 is configured by various circuits such as an operational amplifier.

  The analog-digital conversion circuit 3 is a circuit unit that converts the analog signal amplified by the operational amplifier 2 into a digital signal and outputs the digital signal. The digital correction calculation circuit 4 is a circuit unit that operates using parameter data stored in advance in the memory 5, and performs predetermined correction on the digital signal input from the analog-digital conversion circuit 3.

  The output interface 6 is an interface circuit for outputting the digital signal corrected by the digital correction arithmetic circuit 4 to the outside via the output terminal 10.

  Among the above components, each circuit such as the constant current source 12, the resistance element 16, the diode element 17, the operational amplifier 2, the analog-digital conversion circuit 3, the digital correction arithmetic circuit 4, the memory 5, and the output interface 6 is a semiconductor substrate. 11 is formed around the piezoresistive island 20.

  The above is the overall configuration of the semiconductor device according to the present embodiment. In such a semiconductor device configuration, when the pressure of the pressure medium is applied to the diaphragm 23, the diaphragm 23 is deformed, so that the piezoresistor 18 is also deformed. As a result, the resistance value of the piezoresistor 18 increases or decreases, and the output voltage of the Wheatstone bridge circuit increases in proportion to the pressure. This voltage is amplified by the analog / digital conversion circuit 3, corrected by the digital correction calculation circuit 4, and output through the output interface 6.

  Here, during circuit operation, a voltage based on the operating power supply is applied to the highest potential region 24 via the diode element 17 or a predetermined voltage is applied via the electrochemical etching power supply terminal 9. As a result, the highest potential region 24 becomes the highest potential in the semiconductor sensor unit 1. Accordingly, since a bias is applied between the maximum potential region 24 and the piezoresistor 18 in the piezoresistive island 20, a leakage current from the piezoresistor 18 can be suppressed.

  Next, a method for manufacturing a semiconductor device will be described. First, a P-type semiconductor wafer is prepared. Many portions to be semiconductor devices are formed on the semiconductor wafer. Subsequently, a mask such as a resist is disposed on the surface of the semiconductor wafer, and N-type impurities such as P (phosphorus) are ion-implanted. Further, another mask is disposed on the surface of the semiconductor wafer, and N-type impurities such as As (arsenic) and P-type impurities such as B (boron) are ion-implanted.

  Thereafter, the semiconductor wafer is processed at a high temperature to thermally diffuse the impurities, thereby forming the piezoresistive island 20 and the well region 25, which are N− type well regions, and the P + type piezoresistor 18 and the P + type region. 27, and N + type highest potential region 24 and N + type region 26 are formed. That is, the diode element 17 for backflow prevention is formed in the part which becomes the semiconductor substrate 11 among semiconductor wafers by a CMOS process. In the CMOS process in which elements and the like are formed in a portion that becomes the semiconductor substrate 11 of the semiconductor wafer, other circuit portions such as the constant current source 12 and the operational amplifier 2 are also formed.

  Thereafter, an insulating film (not shown) is formed on the surface of the semiconductor wafer. Then, wiring such as the resistance element 16, the first energization path 14, the second energization path 15 and the like is formed on the insulating film. Further, the operation power supply terminal 7, the piezoresistive island potential terminal 8, the electrochemical etching power supply terminal 9, and the output terminal 10 are formed.

  A thin film fuse resistor is formed as the resistance element 16, but the resistance value of the thin film fuse resistor is reduced. This is because a current flows through the resistance element 16 when the electrochemical etching is stopped when the semiconductor wafer is electrochemically etched, and a voltage drop of the resistance element 16 due to this current is suppressed.

  Here, wiring for applying an etching power source to the electrochemical etching power source terminal 9 is also formed on the scribe line of the semiconductor wafer. Then, the wiring is formed so that this wiring and the power terminal 9 for electrochemical etching are connected. By the manufacturing process so far, the structure on the one surface 19 side of the semiconductor substrate 11 is completely completed.

  Subsequently, as shown in FIG. 4, a protective film 28 is formed on the back surface side of the semiconductor wafer, and an area corresponding to a portion to be the diaphragm 23 in the semiconductor wafer is opened. FIG. 4 shows one of many semiconductor devices formed on a semiconductor wafer.

  Then, the wiring formed on the scribe line of the semiconductor wafer is connected to the positive electrode terminal of the power supply circuit (not shown), and the counter electrode (GND electrode) (not shown) is connected to the negative electrode terminal of the power supply circuit, and the semiconductor wafer and the counter electrode are hydroxylated. Electrochemical etching is performed in an etching solution such as potassium.

  Specifically, the etching power is supplied to the electrochemical etching power supply terminal 9 of each semiconductor device through the wiring formed on the scribe line of the semiconductor wafer. As a result, a voltage based on the etching power supply is applied to the semiconductor wafer via the first energization path 14 and the resistance element 16. In this state, the N− type piezoresistive island 20 and the P− type semiconductor wafer are reversely biased, and the second energization path 15 is connected to the semiconductor wafer. Since the backflow preventing diode element 17 is provided, no current flows from the second energizing path 15 to the constant current source 12 side even when an etching power supply is applied to the electrochemical etching power supply terminal 9.

  On the other hand, since a voltage is applied to the piezoresistive island 20 in the semiconductor wafer, a depletion layer spreads at the pn junction between the piezoresistive island 20 and the semiconductor wafer. Since the spread of the depletion layer controls the thickness of the diaphragm 23 to be left by the etching process, the thickness of the diaphragm 23 can be accurately controlled.

  As the etching of the P-type semiconductor wafer progresses and the N-type piezoresistive island 20 is exposed, the reverse bias state disappears, so that a current flows from the electrochemical etching power supply terminal 9 to the counter electrode in the etching solution, and the etching solution Etching stops when a potential difference is generated between the N-type piezoresistive island 20 and the N-type piezoresistive island 20.

  Thereafter, the protective film 28 on the back side of the semiconductor wafer is removed, and the semiconductor wafer is divided into individual semiconductor devices by dicing cutting along the scribe lines. Thus, the semiconductor device is completed. The protective film 28 may be left on the semiconductor wafer.

As described above, in this embodiment, the diode element 17 is formed by the CMOS process, and the etching power is supplied to the semiconductor substrate 11 via the resistance element 16 . The diaphragm 23 is formed by electrochemical etching.

  As a result, even when an etching power source is supplied to the semiconductor substrate 11 from the outside through the first current path 14 and the resistance element 16 during the electrochemical etching, the parasitic transistor due to the structure of the resistance element 16 is generated in the semiconductor substrate 11. It can be prevented from occurring.

  Further, although the diode element 17 is formed by a CMOS process, it does not operate in the forward direction because it operates to prevent backflow during electrochemical etching. Therefore, the leakage current IL can be prevented from flowing from the diode element 17 to the semiconductor substrate 11 during the electrochemical etching, and the thickness accuracy of the diaphragm 23 can be prevented from being affected. For this reason, the highly accurate diaphragm 23 can be formed.

  When the semiconductor device is actually operated, a current flowing in the path of the power supply terminal for operation 7, the diode element 17, the resistance element 16, and the power supply terminal for electrochemical etching 9 and a leakage current generated in the parasitic PNP transistor of the diode element 17 A large current flows in the sum with IL. However, since the resistance value of the resistance element 16 is reduced, this current can be suppressed.

(Second Embodiment)
In the present embodiment, parts different from the first embodiment will be described. In the present embodiment, the resistive element 16 is disconnected in the semiconductor device. The disconnection is a state where the resistance element is physically destroyed and the electrical conduction is interrupted.

  Thereby, during a normal operation in which the sensing unit 13 detects a physical quantity, it is possible to prevent a current flowing from the operating power supply terminal 7 to the electrochemical etching power supply terminal 9 via the diode element 17 and the resistance element 16. For this reason, it is possible to prevent current consumption from increasing due to current flowing through the resistance element 16 provided in the first energization path 14.

  The resistive element 16 is disconnected after the diaphragm 23 is formed on the semiconductor substrate 11 by electrochemical etching. As a method of disconnecting the resistive element 16, there are a trimming method using a laser, a method of destroying the resistive element 16 by passing a large current between the piezoresistive island potential terminal 8 and the power supply terminal 9 for electrochemical etching. is there.

  Even if the resistance value of the resistance element 16 is increased to a certain level of, for example, several kΩ or more, if the thickness of the diaphragm 23 is accurately determined by electrochemical etching, the resistance element 16 does not need to be disconnected.

(Third embodiment)
In the present embodiment, parts different from the first and second embodiments will be described. As shown in FIG. 5, an Al wiring (AL) is provided as the resistance element 16 provided in the first energization path 14. The Al wiring (AL) is formed on the semiconductor substrate 11 by a method such as vapor deposition or sputtering via an insulating film (not shown).

  Since the Al wiring has a very small resistance, there is an advantage that there is almost no voltage drop. For this reason, the current consumed by the resistance element 16 can be reduced. In addition, it is possible to apply a highly accurate voltage to the piezoresistive island 20 during electrochemical etching. As described in the second embodiment, the Al wiring may be disconnected after the electrochemical etching is completed.

(Fourth embodiment)
In the present embodiment, parts different from the first to third embodiments will be described. In the present embodiment, as shown in FIG. 6, the diode element 17 has a MOS structure.

  Specifically, as shown in FIG. 7, the diode element 17 includes an N + type source region 29 and an N + type drain region 30 formed on the surface layer portion of the semiconductor substrate 11, and an illustration on the semiconductor substrate 11. A gate electrode 31 formed on the gate insulating film. The gate electrode 31 is formed above the channel region 32 between the source region 29 and the drain region 30.

  According to such a configuration, a current flows through the diode element 17 by controlling the channel formed in the channel region 32 based on the voltage applied to the gate electrode 31. That is, in this embodiment, the diode element 17 has an N-channel type MOS structure.

  Thus, by making the diode element 17 have the MOS structure, the current flowing through the diode element 17 flows along the channel formed in the channel region 32, that is, along the surface direction of the one surface 19 of the semiconductor substrate 11. Thereby, it is possible to prevent the leakage current IL from leaking in the thickness direction of the semiconductor substrate 11.

  The diode element 17 can be formed by the above-described CMOS process. Specifically, the source region 29 and the drain region 30 are formed by ion implantation of N-type impurities into the surface layer portion of the semiconductor wafer and thermal diffusion. Further, a gate insulating film is formed in a predetermined region of the semiconductor wafer, and a gate electrode 31 is formed on the gate insulating film, that is, above the channel region 32.

  As described in the second embodiment, the resistance element 16 according to this embodiment may be disconnected after the electrochemical etching is completed, or the Al wiring described in the third embodiment may be used as the resistance element 16. good.

(Other embodiments)
The configurations of the semiconductor devices described in the above embodiments are examples, and the present invention is not limited to the configurations described above, and other configurations that can realize the present invention may be employed. For example, the sensing unit 13 provided in the diaphragm 23 is not limited to detecting pressure, and may be configured to detect, for example, acceleration as a physical quantity. Moreover, as a use of a semiconductor device, it can be used for vehicles, medical equipment, and the like.

7 Operation power supply terminal 11 Semiconductor substrate 13 Sensing unit 14 First energization path 15 Second energization path 16 Resistance element 17 Diode element 23 Diaphragm 29 Source region 30 Drain region 31 Gate electrode 32 Channel region

Claims (4)

Sensing that detects the physical quantity applied to the diaphragm (23) while operating based on the diaphragm (23) formed thin by electrochemical etching and the operating power supply applied to the operating power supply terminal (7) Part (13) is a method of manufacturing a semiconductor device formed on a semiconductor substrate (11),
Forming a backflow preventing diode element (17) on the semiconductor substrate (11) by a CMOS process;
Forming a resistance element (16) on the semiconductor substrate (11);
Forming a first energization path (14) for supplying an etching power from the outside to the portion of the semiconductor substrate (11) where the diaphragm (23) is formed via the resistance element (16); ,
Forming a second energization path (15) for electrically connecting the portion of the semiconductor substrate (11) where the diaphragm (23) is formed and the power supply terminal for operation (7);
After forming the first energization path (14) and the second energization path (15), the diaphragm of the semiconductor substrate (11) from the first energization path (14) through the resistance element (16). Supplying the etching power to a portion to be (23) and performing the electrochemical etching on the semiconductor substrate (11) to form the diaphragm (23);
A method for manufacturing a semiconductor device, comprising: The method of manufacturing a semiconductor device according to claim 1 , further comprising a step of disconnecting the resistance element (16) after the step of forming the diaphragm (23). In the step of forming the resistive element (16), wherein the resistive element (16), a method of manufacturing a semiconductor device according to claim 1 or 2, characterized in that form either a thin film fuse resistor or Al wiring . In the step of preparing the semiconductor substrate (11), a semiconductor substrate of the first conductivity type is prepared as the semiconductor substrate (11).
In the step of forming the diode element (17), a second conductivity type source region (29) and a second conductivity type drain region (30) are formed in the surface layer portion of the semiconductor substrate (11), and these sources are formed. By forming a gate electrode (31) above the channel region (32) between the region (29) and the drain region (30), the channel region (32) is based on the voltage applied to the gate electrode (31). the method of manufacturing a semiconductor device according to any one of claims 1 to 3 channels to be formed and forming a diode element (17) of the MOS structures are controlled.

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