JP5980494B2 - Heat treatment method - Google Patents

Description

  The present invention relates to a heat treatment method for heating a substrate by irradiating a semiconductor wafer, a glass substrate for a liquid crystal display device or the like (hereinafter simply referred to as “substrate”) with flash light from a flash lamp.

  Conventionally, a lamp annealing apparatus using a halogen lamp has been generally used in an ion activation process of a semiconductor wafer after ion implantation. In such a lamp annealing apparatus, ion activation of a semiconductor wafer is performed by heating (annealing) the semiconductor wafer to a temperature of about 1000 ° C. to 1100 ° C., for example. In such a heat treatment apparatus, the temperature of the substrate is raised at a rate of several hundred degrees per second by using the energy of light irradiated from the halogen lamp.

  On the other hand, in recent years, as semiconductor devices have been highly integrated, it is desired to reduce the junction depth as the gate length becomes shorter. However, even when ion activation of a semiconductor wafer is performed using the above-described lamp annealing apparatus that raises the temperature of the semiconductor wafer at a speed of several hundred degrees per second, ions such as boron and phosphorus implanted in the semiconductor wafer are heated. It was found that the phenomenon of deep diffusion occurs. When such a phenomenon occurs, there is a concern that the junction depth becomes deeper than required, which hinders good device formation.

  For this reason, the surface of the semiconductor wafer into which ions have been implanted by irradiating the surface of the semiconductor wafer with flash light using a xenon flash lamp (hereinafter simply referred to as “flash lamp” means xenon flash lamp). Has been proposed (for example, Patent Documents 1 and 2) in which the temperature is raised only for a very short time (several milliseconds or less). The emission spectral distribution of the flash lamp ranges from the ultraviolet region to the near infrared region, has a shorter wavelength than the conventional halogen lamp, and almost coincides with the fundamental absorption band of a silicon semiconductor wafer. Therefore, when the semiconductor wafer is irradiated with flash light from the flash lamp, it is possible to raise the temperature of the semiconductor wafer rapidly with little transmitted light. Further, it has been found that if the flash light is irradiated for a very short time of several milliseconds or less, only the vicinity of the surface of the semiconductor wafer can be selectively heated. For this reason, if the temperature is raised for a very short time by a xenon flash lamp, only the ion activation can be performed without diffusing ions deeply.

JP 2004-55821 A JP 2004-88052 A

  As mentioned above, heat treatment equipment using xenon flash lamps is essentially an annealing equipment suitable for shallow junction heat treatment, but in recent years, using xenon flash lamps, ion activation of junctions slightly deeper than conventional ones is possible. There is also a desire to do this. In order to activate deeper junctions than before, the flash lamp emission time is set longer than before, so that not only the surface (shallow region) of the semiconductor wafer but also deeper regions are heated by heat conduction. A method to do this is conceivable. As a result, ion activation in a deeper region from the surface of the semiconductor wafer, that is, deep junction activation can be performed.

  However, if the xenon flash lamp emission time is lengthened to increase the temperature to a deep region, the surface temperature of the semiconductor wafer will rise more than necessary, and as a result, a large thermal stress will act on the surface, causing wafer warpage. In the worst case, there is a problem that wafer cracking occurs due to rapid thermal expansion.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a heat treatment method capable of activating deep bonding without causing warpage or cracking in a substrate.

In order to solve the above problems, the invention of claim 1 is directed to a heat treatment method for heating a semiconductor substrate by irradiating flash light from a flash lamp onto a semiconductor substrate into which ions are implanted. Te wherein a first irradiation step of irradiating the flash light having a first peak intensity in the entire area of the surface of the semiconductor substrate, the semiconductor substrate in the first than the irradiation time of the long second irradiation time A second irradiation step of irradiating flash light having a second peak intensity that is weaker than the first peak intensity over the entire surface, and the flash irradiated in at least a part of the second irradiation step light is superimposed with a flash light emitted by the first irradiation step in the entire region of the surface of the semiconductor substrate, flushing of the first irradiation step and the second irradiation step The temperature was raised to the activation temperature or more of the processing temperature of the ions and the surface temperature is injected into the semiconductor substrate of the semiconductor substrate by light irradiation, the surface temperature of the semiconductor substrate by flash irradiation of at least the second irradiation step The first irradiation step and the second irradiation step are started at the same time while maintaining the activation temperature or higher for a predetermined time or longer.

The invention of claim 2 is the heat treatment method according to claim 1 , wherein the first irradiation time is 1.0 millisecond and the second irradiation time is 3.0 milliseconds. It is characterized by.

According to the first and second aspects of the present invention, the flash light having the first peak intensity to be irradiated at the first irradiation time and the first irradiation to be performed at the second irradiation time longer than that . Since the flash light having the second peak intensity that is weaker than the peak intensity is superimposed and irradiated onto the substrate, deep junction activation can be performed without causing warpage or cracking of the substrate.

It is a sectional side view which shows the structure of the heat processing apparatus which concerns on this invention. It is sectional drawing which shows the gas path of the heat processing apparatus of FIG. It is sectional drawing which shows the structure of a holding | maintenance part. It is a top view which shows a hot plate. It is a sectional side view which shows the structure of the heat processing apparatus of FIG. It is a figure which shows the drive circuit of a xenon flash lamp. It is a figure which shows the arrangement configuration of the some flash lamp in 1st Embodiment. It is a block diagram which shows the structure of a control part. It is a figure which shows transition of the light intensity in the surface of a semiconductor wafer. It is a figure which shows transition of the surface temperature of the semiconductor wafer from light emission start. It is a figure which shows the arrangement configuration of the some flash lamp in 2nd Embodiment. It is a figure which shows the arrangement configuration of the some flash lamp in 3rd Embodiment. It is a figure which shows an example of transition of the light intensity when the light emission start timing of the flash lamp from which pulse width differs is shifted. It is a figure which shows the other example of transition of the light intensity when the light emission start timing of the flash lamp from which pulse width differs is shifted.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

<1. First Embodiment>
First, the overall configuration of the heat treatment apparatus according to the present invention will be outlined. FIG. 1 is a side sectional view showing a configuration of a heat treatment apparatus 1 according to the present invention. The heat treatment apparatus 1 is a flash lamp annealing apparatus that irradiates a substantially circular semiconductor wafer W as a substrate with flash (flash light) and heats the semiconductor wafer W.

  The heat treatment apparatus 1 includes a substantially cylindrical chamber 6 that accommodates a semiconductor wafer W, and a lamp house 5 that houses a plurality of flash lamps FL. Further, the heat treatment apparatus 1 includes a control unit 3 that controls each operation mechanism provided in the chamber 6 and the lamp house 5 to execute the heat treatment of the semiconductor wafer W.

  The chamber 6 is provided below the lamp house 5 and includes a chamber side 63 having a substantially cylindrical inner wall and a chamber bottom 62 covering the lower part of the chamber side 63. A space surrounded by the chamber side 63 and the chamber bottom 62 is defined as a heat treatment space 65. An upper opening 60 is formed above the heat treatment space 65, and a chamber window 61 is attached to the upper opening 60 to be closed.

  The chamber window 61 constituting the ceiling portion of the chamber 6 is a disk-shaped member made of quartz, and transmits flash light emitted from the lamp house 5 to the heat treatment space 65. The chamber bottom 62 and the chamber side 63 constituting the main body of the chamber 6 are formed of, for example, a metal material having excellent strength and heat resistance such as stainless steel, and a ring on the upper side of the inner side surface of the chamber side 63. 631 is formed of an aluminum (Al) alloy or the like having durability superior to stainless steel against deterioration due to light irradiation.

  Further, in order to maintain the airtightness of the heat treatment space 65, the chamber window 61 and the chamber side portion 63 are sealed by an O-ring. That is, the O-ring is sandwiched between the lower surface peripheral portion of the chamber window 61 and the chamber side portion 63, the clamp ring 90 is brought into contact with the upper peripheral portion of the chamber window 61, and the clamp ring 90 is attached to the chamber side portion 63. The chamber window 61 is pressed against the O-ring by screwing.

  The chamber bottom 62 has a plurality (in this embodiment) for supporting the semiconductor wafer W from the lower surface (surface opposite to the side irradiated with light from the lamp house 5) through the holding portion 7. 3) support pins 70 are provided upright. The support pin 70 is made of, for example, quartz and is fixed from the outside of the chamber 6 and can be easily replaced.

The chamber side 63 has a transfer opening 66 for carrying in and out the semiconductor wafer W, and the transfer opening 66 can be opened and closed by a gate valve 185 that rotates about a shaft 662. In a portion of the chamber side 63 opposite to the transfer opening 66, an inert gas such as nitrogen (N ₂ ) gas, helium (He) gas, argon (Ar) gas, etc. Alternatively, an introduction path 81 for introducing oxygen (O ₂ ) gas or the like is formed, one end of which is connected to an air supply mechanism (not shown) via a valve 82, and the other end is formed inside the chamber side portion 63. Connected to the gas introduction buffer 83. A discharge passage 86 for discharging the gas in the heat treatment space 65 is formed in the transfer opening 66 and is connected to an exhaust mechanism (not shown) through a valve 87.

  FIG. 2 is a cross-sectional view of the chamber 6 cut along a horizontal plane at the position of the gas introduction buffer 83. As shown in FIG. 2, the gas introduction buffer 83 is formed over about ３ of the inner periphery of the chamber side 63 on the opposite side of the transfer opening 66 shown in FIG. Then, the processing gas guided to the gas introduction buffer 83 is supplied into the heat treatment space 65 from the plurality of gas supply holes 84.

  The heat treatment apparatus 1 also includes a substantially disc-shaped holding unit 7 that holds the semiconductor wafer W in a horizontal position inside the chamber 6 and performs preheating of the held semiconductor wafer W before irradiation with flash light. And a holding unit elevating mechanism 4 that elevates the unit 7 with respect to the chamber bottom 62 which is the bottom surface of the chamber 6. 1 includes a substantially cylindrical shaft 41, a moving plate 42, guide members 43 (three arranged around the shaft 41 in the present embodiment), a fixed plate 44, a ball screw 45, It has a nut 46 and a motor 40. A substantially circular lower opening 64 having a smaller diameter than the holding portion 7 is formed in the chamber bottom 62 which is the lower portion of the chamber 6, and the stainless steel shaft 41 is inserted through the lower opening 64 to hold the holding portion. 7 (strictly speaking, the hot plate 71 of the holding unit 7) is connected to the lower surface of the holding unit 7 to support it.

  A nut 46 that is screwed into the ball screw 45 is fixed to the moving plate 42. The moving plate 42 is slidably guided by a guide member 43 that is fixed to the chamber bottom 62 and extends downward, and is movable in the vertical direction. Further, the moving plate 42 is connected to the holding unit 7 via the shaft 41.

  The motor 40 is installed on a fixed plate 44 attached to the lower end of the guide member 43, and is connected to the ball screw 45 via the timing belt 401. When the holding part 7 is raised and lowered by the holding part raising / lowering mechanism 4, the motor 40 as the driving part rotates the ball screw 45 under the control of the control part 3, and the moving plate 42 to which the nut 46 is fixed follows the guide member 43. Move vertically. As a result, the shaft 41 fixed to the moving plate 42 moves along the vertical direction, and the holding unit 7 connected to the shaft 41 moves between the delivery position of the semiconductor wafer W shown in FIG. 1 and the semiconductor wafer W shown in FIG. Move up and down smoothly between the processing positions.

  On the upper surface of the moving plate 42, a mechanical stopper 451 having a substantially semi-cylindrical shape (a shape obtained by cutting the cylinder in half along the longitudinal direction) is provided so as to extend along the ball screw 45. If the upper limit of the mechanical stopper 451 is struck against the end plate 452 provided at the end of the ball screw 45, the moving plate 42 is prevented from rising abnormally. Thereby, the holding part 7 does not rise above a predetermined position below the chamber window 61, and the collision between the holding part 7 and the chamber window 61 is prevented.

  The holding unit lifting mechanism 4 has a manual lifting unit 49 that manually lifts and lowers the holding unit 7 when performing maintenance inside the chamber 6. The manual elevating part 49 has a handle 491 and a rotating shaft 492. By rotating the rotating shaft 492 via the handle 491, the ball screw 45 connected to the rotating shaft 492 is rotated via the timing belt 495 to hold the holding part. 7 can be moved up and down.

  A telescopic bellows 47 that surrounds the shaft 41 and extends downward is provided below the chamber bottom 62, and its upper end is connected to the lower surface of the chamber bottom 62. On the other hand, the lower end of the bellows 47 is attached to the bellows lower end plate 471. The bellows lower end plate 471 is attached by being screwed to the shaft 41 by a flange-shaped member 411. The bellows 47 is contracted when the holding portion 7 is raised with respect to the chamber bottom 62 by the holding portion lifting mechanism 4, and the bellows 47 is expanded when the holding portion 7 is lowered. When the holding unit 7 moves up and down, the airtight state in the heat treatment space 65 is maintained by the expansion and contraction of the bellows 47.

  FIG. 3 is a cross-sectional view showing the configuration of the holding unit 7. The holding unit 7 is installed on a hot plate (heating plate) 71 that preheats the semiconductor wafer W (so-called assist heating), and an upper surface of the hot plate 71 (a surface on the side where the holding unit 7 holds the semiconductor wafer W). The susceptor 72 is provided. As described above, the shaft 41 that moves up and down the holding unit 7 is connected to the lower surface of the holding unit 7. The susceptor 72 is made of quartz (or may be aluminum nitride (AIN) or the like), and a pin 75 for preventing displacement of the semiconductor wafer W is provided on the upper surface thereof. The susceptor 72 is installed on the hot plate 71 with its lower surface in surface contact with the upper surface of the hot plate 71. Thus, the susceptor 72 diffuses the thermal energy from the hot plate 71 and transmits it to the semiconductor wafer W placed on the upper surface of the susceptor 72, and can be removed from the hot plate 71 and cleaned during maintenance.

  The hot plate 71 includes an upper plate 73 and a lower plate 74 made of stainless steel. A resistance heating wire 76 such as a nichrome wire for heating the hot plate 71 is disposed between the upper plate 73 and the lower plate 74, and is filled with a conductive nickel (Ni) solder and sealed. The end portions of the upper plate 73 and the lower plate 74 are bonded by brazing.

  FIG. 4 is a plan view showing the hot plate 71. As shown in FIG. 4, the hot plate 71 includes a disc-shaped zone 711 and an annular zone 712 that are concentrically arranged in a central portion of a region facing the held semiconductor wafer W, and a zone 712. There are four zones 713 to 716 obtained by equally dividing a peripheral substantially annular region into four equal parts in the circumferential direction, and a slight gap is formed between the zones. The hot plate 71 is provided with three through holes 77 through which the support pins 70 are inserted, every 120 ° on the circumference of the gap between the zone 711 and the zone 712.

  In each of the six zones 711 to 716, heaters are individually formed so that mutually independent resistance heating wires 76 circulate, and each zone is individually formed by a heater built in each zone. Heated. The semiconductor wafer W held by the holding unit 7 is heated by heaters built in the six zones 711 to 716. Each of the zones 711 to 716 is provided with a sensor 710 that measures the temperature of each zone using a thermocouple. Each sensor 710 passes through the inside of a substantially cylindrical shaft 41 and is connected to the control unit 3.

  When the hot plate 71 is heated, the resistance heating wire disposed in each zone is set so that the temperature of each of the six zones 711 to 716 measured by the sensor 710 becomes a predetermined temperature. The amount of power supplied to 76 is controlled by the control unit 3. The temperature control of each zone by the control unit 3 is performed by PID (Proportional, Integral, Derivative) control. In the hot plate 71, the temperature of each of the zones 711 to 716 is continuously measured until the heat treatment of the semiconductor wafer W (when plural semiconductor wafers W are continuously processed, the heat treatment of all the semiconductor wafers W) is completed. Then, the power supply amount to the resistance heating wire 76 disposed in each zone is individually controlled, that is, the temperature of the heater built in each zone is individually controlled, and the temperature of each zone becomes the set temperature. Maintained. The set temperature of each zone can be changed by an offset value set individually from the reference temperature.

  The resistance heating wires 76 respectively disposed in the six zones 711 to 716 are connected to a power supply source (not shown) via a power line passing through the inside of the shaft 41. On the way from the power supply source to each zone, the power lines from the power supply source are arranged so as to be electrically insulated from each other inside a stainless tube filled with an insulator such as magnesia (magnesium oxide). The The interior of the shaft 41 is open to the atmosphere.

  Next, the lamp house 5 includes a light source composed of a plurality of (30 in this embodiment) xenon flash lamps FL inside the housing 51, and a reflector 52 provided so as to cover the light source, It is configured with. A lamp light emission window 53 is attached to the bottom of the casing 51 of the lamp house 5. The lamp light radiation window 53 constituting the floor of the lamp house 5 is a plate-like member made of quartz. By installing the lamp house 5 above the chamber 6, the lamp light emission window 53 faces the chamber window 61. The lamp house 5 heats the semiconductor wafer W by irradiating the semiconductor wafer W held by the holding unit 7 in the chamber 6 with flash light from the flash lamp FL via the lamp light emission window 53 and the chamber window 61. .

  The plurality of flash lamps FL are rod-shaped lamps each having a long cylindrical shape. In the first embodiment, each of the plurality of flash lamps FL is planar so that the longitudinal directions thereof are parallel to each other along the main surface of the semiconductor wafer W held by the holding unit 7 (that is, along the horizontal direction). Is arranged. Therefore, the plane formed by the arrangement of the flash lamps FL is also a horizontal plane.

  FIG. 6 is a diagram showing a drive circuit for the xenon flash lamp FL. The xenon flash lamp FL includes a rod-shaped glass tube (discharge tube) 92 in which xenon gas is sealed and an anode and a cathode connected to a capacitor 93 are disposed at both ends thereof, and an outer peripheral surface of the glass tube 92. And a trigger electrode 91 provided on the top. A predetermined voltage is applied to the capacitor 93 by the power supply unit 95, and electric charges corresponding to the applied voltage are accumulated. A coil 94 is provided in a circuit connecting the capacitor 93 and the glass tube 92 electrode.

  Since xenon gas is electrically an insulator, even if electric charges are accumulated in the capacitor 93, no electricity flows in the glass tube 92 in a normal state. However, when the trigger switch SW is turned on and a high voltage is applied to the trigger electrode 91 to break the insulation, the electricity stored in the capacitor 93 instantaneously flows into the glass tube 92 and the Joule heat at that time The xenon gas is heated to emit light. That is, the light emission start timing of the xenon flash lamp FL is determined by the timing at which the trigger switch SW is switched from the OFF state to the ON state. In such a xenon flash lamp FL, the electrostatic energy stored in the capacitor 93 in advance is converted into an extremely short light pulse of 0.1 to 10 milliseconds, so that compared to a continuously lit light source. It has the feature that it can irradiate extremely strong light. As the trigger switch SW, an electrical switch element such as a thyristor is used.

  Incidentally, in the first embodiment, 30 flash lamps FL are provided, and one drive circuit as shown in FIG. 6 is provided for each flash lamp FL. The light emission time of the xenon flash lamp FL is determined by the capacitance of the capacitor 93 and the inductance of the coil 94. The period of the pulse of the flash light emitted from the flash lamp FL, that is, the light emission time of the flash lamp FL per one flash irradiation is proportional to the 1/2 power of the product of the capacitance of the capacitor 93 and the inductance of the coil 94. As the capacitance of the capacitor 93 is increased and the inductance of the coil 94 is increased, the light emission time of the flash lamp FL is increased.

  In the first embodiment, two types of lamp drive circuits having different inductances of the coil 94 are used, and each of the 30 flash lamps FL is connected to one of the two types of drive circuits. FIG. 7 is a diagram showing an arrangement configuration of a plurality of flash lamps FL in the first embodiment. As shown in FIG. 7, each of the 30 flash lamps FL is connected to either the short pulse circuit SP or the long pulse circuit LP. The short pulse circuit SP is a drive circuit using the capacitor 93 having a capacity of 750 μF and the coil 94 having an inductance of 260 μH in the configuration of FIG. The long pulse circuit LP is a drive circuit using the capacitor 93 having a capacity of 750 μF and the coil 94 having an inductance of 2200 μH in the configuration of FIG. The flash lamp FL1 connected to the short pulse circuit SP has a light emission time of about 1.0 millisecond, and the flash lamp FL2 connected to the long pulse circuit LP (hatched in FIG. 7 for ease of understanding). The light emission time is about 3.0 milliseconds. That is, the long pulse circuit LP includes a coil 94 having a larger inductance than the short pulse circuit SP, and the flash lamp connected to the long pulse circuit LP is longer than the light emission time of the flash lamp FL1 connected to the short pulse circuit SP. FL2 has a longer emission time.

  Here, in the first embodiment, as shown in FIG. 7, the flash lamps FL1 and the flash lamps FL2 are alternately arranged in a line. That is, 30 flash lamps FL (flash lamp FL1 and flash lamp FL2 are simply collectively referred to as “flash lamp FL” when it is not necessary to separately specify flash lamp FL1 and flash lamp FL2) are divided into two groups of 15 lamps. One of the lamp groups (first lamp group) is connected to the short pulse circuit SP, and the other lamp group (second lamp group) is connected to the long pulse circuit LP, and the flash constituting the first lamp group. The lamps FL1 and the flash lamps FL2 constituting the second lamp group are alternately arranged. In FIG. 7, for convenience of illustration, 15 flash lamps FL1 are connected to one short pulse circuit SP, and 15 flash lamps FL2 are connected to one long pulse circuit LP. One flash lamp FL is provided with one drive circuit, and each of the short pulse circuit SP and the long pulse circuit LP in FIG. 7 is a comprehensive description of 15 drive circuits.

  In addition, the reflector 52 is provided above the plurality of flash lamps FL so as to cover all of them. The basic function of the reflector 52 is to reflect flash light emitted from the plurality of flash lamps FL toward the holding unit 7. The reflector 52 is formed of an aluminum alloy plate, and the surface (the surface facing the flash lamp FL) is roughened by blasting to exhibit a satin pattern. The roughening process is performed when the surface of the reflector 52 is a perfect mirror surface, and a regular pattern is generated in the intensity of the reflected light from the plurality of flash lamps FL, so that the surface temperature distribution of the semiconductor wafer W is obtained. This is because the uniformity of the is reduced.

  The control unit 3 controls the various operation mechanisms provided in the heat treatment apparatus 1. FIG. 8 is a block diagram illustrating a configuration of the control unit 3. The configuration of the control unit 3 as hardware is the same as that of a general computer. That is, the control unit 3 stores a CPU 31 that performs various arithmetic processes, a ROM 32 that is a read-only memory that stores basic programs, a RAM 33 that is a readable / writable memory that stores various information, control software, data, and the like. The magnetic disk 34 to be placed is connected to a bus line 39.

  The bus line 39 is electrically connected to a motor 40 and a trigger control circuit 38 of the holding unit lifting mechanism 4 that lifts and lowers the holding unit 7 in the chamber 6. The trigger control circuit 38 is connected to each trigger switch SW of the plurality of flash lamps FL, and controls ON / OFF of each trigger switch SW. The CPU 31 of the control unit 3 executes control software stored in the magnetic disk 34 to control the motor 40 and adjust the height position of the holding unit 7, and each of the plurality of flash lamps FL is predetermined. The trigger control circuit 38 is controlled so that the light is emitted at the timing, that is, the trigger switch SW is turned on at a predetermined timing.

  Further, the display unit 21 and the input unit 22 are electrically connected to the bus line 39. The display unit 21 is configured using, for example, a liquid crystal display or the like, and displays various information such as processing results and recipe contents. The input unit 22 is configured using, for example, a keyboard, a mouse, and the like, and receives input of commands, parameters, and the like. The operator of the apparatus can input commands and parameters from the input unit 22 while confirming the contents displayed on the display unit 21. Note that the display unit 21 and the input unit 22 may be integrated to form a touch panel.

  In addition to the above configuration, the heat treatment apparatus 1 is used for various cooling purposes in order to prevent excessive temperature rise of the chamber 6 and the lamp house 5 due to the heat energy generated from the flash lamp FL and the hot plate 71 during the heat treatment of the semiconductor wafer W. It has the structure of For example, water-cooled tubes (not shown) are provided on the chamber side 63 and the chamber bottom 62 of the chamber 6. The lamp house 5 has an air cooling structure provided with a gas supply pipe 55 and an exhaust pipe 56 for exhausting heat by forming a gas flow therein (see FIG. 1). Air is also supplied to the gap between the chamber window 61 and the lamp light emission window 53 to cool the lamp house 5 and the chamber window 61.

  Next, a processing procedure of the semiconductor wafer W in the heat treatment apparatus 1 will be briefly described. Here, the semiconductor wafer W to be processed is a semiconductor substrate to which an impurity (ion) is added by an ion implantation method, and the activation of the added impurity is performed by a flash heating process by the heat treatment apparatus 1.

  First, the holding unit 7 is lowered from the processing position shown in FIG. 5 to the delivery position shown in FIG. The “processing position” is a position of the holding unit 7 when the semiconductor wafer W is irradiated with flash light from the flash lamp FL, and is a position in the chamber 6 of the holding unit 7 shown in FIG. Further, the “delivery position” is the position of the holding unit 7 when the semiconductor wafer W is carried in and out of the chamber 6, and is the position of the holding unit 7 shown in FIG. The reference position of the holding unit 7 in the heat treatment apparatus 1 is the processing position. Before the processing, the holding unit 7 is located at the processing position, and this is lowered to the delivery position at the start of processing. As shown in FIG. 1, when the holding portion 7 is lowered to the delivery position, the holding portion 7 comes close to the chamber bottom portion 62, and the tip of the support pin 70 penetrates the holding portion 7 and protrudes above the holding portion 7.

  Next, when the holding unit 7 is lowered to the delivery position, the valve 82 and the valve 87 are opened, and normal temperature nitrogen gas is introduced into the heat treatment space 65 of the chamber 6. Subsequently, the gate valve 185 is opened to open the transfer opening 66, and the semiconductor wafer W after ion implantation is transferred into the chamber 6 through the transfer opening 66 by a transfer robot outside the apparatus, and a plurality of support pins 70. Placed on top.

  The purge amount of nitrogen gas into the chamber 6 when the semiconductor wafer W is loaded is about 40 liters / minute, and the supplied nitrogen gas is moved from the gas introduction buffer 83 in the direction of the arrow AR4 shown in FIG. Then, the exhaust gas is exhausted by utility exhaust via the discharge path 86 and the valve 87 shown in FIG. A part of the nitrogen gas supplied to the chamber 6 is also discharged from an outlet (not shown) provided inside the bellows 47. In each step described below, nitrogen gas is continuously supplied to and exhausted from the chamber 6, and the supply amount of the nitrogen gas is variously changed according to the processing process of the semiconductor wafer W.

  When the semiconductor wafer W is loaded into the chamber 6, the transfer opening 66 is closed by the gate valve 185. The holding unit lifting mechanism 4 raises the holding unit 7 from the delivery position to a processing position close to the chamber window 61. In the process in which the holding unit 7 is lifted from the delivery position, the semiconductor wafer W is transferred from the support pins 70 to the susceptor 72 of the holding unit 7 and is placed and held on the upper surface of the susceptor 72. When the holding unit 7 moves up to the processing position, the semiconductor wafer W placed on the susceptor 72 is also held at the processing position.

  Each of the six zones 711 to 716 of the hot plate 71 is heated to a predetermined temperature by a heater (resistive heating wire 76) individually incorporated in each zone (between the upper plate 73 and the lower plate 74). ing. When the holding unit 7 rises to the processing position and the semiconductor wafer W comes into contact with the holding unit 7, the semiconductor wafer W is preheated by the heater built in the hot plate 71 and the temperature gradually rises.

  Preheating for about 60 seconds is performed at this processing position, and the temperature of the semiconductor wafer W rises to a preset preheating temperature T1. The preheating temperature T1 is set to about 200 ° C. to 800 ° C., preferably about 350 ° C. to 550 ° C., in which impurities added to the semiconductor wafer W are not likely to diffuse due to heat. Further, the distance between the holding unit 7 and the chamber window 61 can be arbitrarily adjusted by controlling the rotation amount of the motor 40 of the holding unit lifting mechanism 4.

  After the preheating time of about 60 seconds elapses, flash light is irradiated from the flash lamp FL of the lamp house 5 toward the semiconductor wafer W under the control of the control unit 3 while the holding unit 7 is positioned at the processing position. Specifically, the control unit 3 controls the trigger control circuit 38 to simultaneously turn on the trigger switches SW of the short pulse circuit SP and the long pulse circuit LP connected to all the flash lamps FL. At this time, a part of the flash light emitted from the flash lamp FL goes directly to the holding part 7 in the chamber 6, and the other part is once reflected by the reflector 52 and then goes into the chamber 6. Flash heating of the semiconductor wafer W is performed by irradiation of the flash light. Since the flash heating is performed by flash irradiation from the flash lamp FL, the surface temperature of the semiconductor wafer W can be increased in a short time.

  Here, in the first embodiment, the flash lamps FL1 having a relatively short light emission time and the flash lamps FL2 having a long light emission time are alternately arranged in a line (FIG. 7). That is, the flash lamp FL1 and the flash lamp FL2 having different pulse widths (flash light pulse periods) are arranged adjacent to each other. For this reason, the flash light emitted from the flash lamp FL1 and the flash light emitted from the flash lamp FL2 are uniformly overlapped with each other in the entire region of the surface of the semiconductor wafer W held by the holding portion 7 at the processing position. As a result, the light intensity from the start of light emission on the surface of the semiconductor wafer W (when the trigger switch SW is turned on) changes as shown in FIG. In the figure, the dotted line indicates the intensity of the flash light emitted from the flash lamp FL1 with a short pulse width, and the alternate long and short dash line indicates the intensity of the flash light emitted from the flash lamp FL2 with a long pulse width. The combined light intensity is indicated by a solid line.

  Although the flash light emitted from the flash lamp FL1 having a short pulse width shows a strong peak intensity, the intensity is attenuated in a short time. On the contrary, the flash light irradiated from the flash lamp FL2 having a long pulse width maintains the light intensity for a relatively long time although the peak intensity is lower than that of the flash lamp FL1. As a result of superimposing the flash light emitted from the flash lamps FL1 and FL2, as shown in FIG. 9, the flash light irradiation from the flash lamp FL1 is dominant immediately after the start of light emission, thereby obtaining a strong peak intensity. Thereafter, after the flash light intensity from the flash lamp FL1 is attenuated, the flash light irradiation from the flash lamp FL2 becomes dominant, and a certain light intensity is maintained for a relatively long time.

  FIG. 10 is a diagram showing the transition of the surface temperature of the semiconductor wafer W from the start of light emission. Immediately after the start of light emission, the surface of the semiconductor wafer W is rapidly processed at a processing temperature T2 (1000 ° C. to 1100 ° C.) higher than the ion activation temperature by flash light having a strong peak intensity mainly emitted from the flash lamp FL1 having a short pulse width. Temperature). After that, the temperature is gradually lowered after maintaining a temperature higher than the activation temperature for a relatively long time by the heat retaining effect by the flash light having a gentle peak mainly emitted from the flash lamp FL2 having a long pulse width. As a result, even a relatively deep region from the surface of the semiconductor wafer W can be raised to an activation temperature or higher, and deep junction activation can be performed. On the other hand, the temperature of the surface (shallow region) of the semiconductor wafer W does not rise more than necessary, and warping and cracking of the semiconductor wafer W can be prevented.

  In this way, not only the shallow junction of the semiconductor wafer W but also a relatively deep junction is activated. Note that although the flash lamp FL2 has a relatively long light emission time of about 3.0 milliseconds, it is extremely short compared to the time required for the thermal diffusion of the added impurity, and therefore the surface of the semiconductor wafer W (shallow region). However, no impurity diffusion occurs.

  In addition, by preheating the semiconductor wafer W by the holding unit 7 before the flash heating, the surface temperature of the semiconductor wafer W can be quickly raised to the processing temperature T2 by flash irradiation from the flash lamp FL.

  After the flash heating is finished and the standby for about 10 seconds at the processing position, the holding unit 7 is lowered again to the delivery position shown in FIG. 1 by the holding unit lifting mechanism 4, and the semiconductor wafer W is transferred from the holding unit 7 to the support pins 70. Is passed. Subsequently, the transfer opening 66 closed by the gate valve 185 is opened, and the semiconductor wafer W placed on the support pins 70 is unloaded by a transfer robot outside the apparatus, and the semiconductor wafer W is flushed in the heat treatment apparatus 1. The heat treatment is completed.

  As described above, nitrogen gas is continuously supplied to the chamber 6 during the heat treatment of the semiconductor wafer W in the heat treatment apparatus 1, and the supply amount is about 30 liters / minute when the holding unit 7 is located at the processing position. When the holding unit 7 is located at a position other than the processing position, the rate is about 40 liters / minute.

  As described above, in the first embodiment, the flash lamps FL1 having a short pulse width and the flash lamps FL2 having a long pulse width are alternately arranged in a line (FIG. 7). If the pulse width of 30 flash lamps FL is constant as in the prior art, the temperature of the shallow region is required to increase the temperature from the surface of the semiconductor wafer W to the deeper region than the activation temperature. As described above, the wafer is warped or cracked due to the thermal stress when the temperature is too high. On the contrary, when the shallow region on the surface of the semiconductor wafer W is heated to an appropriate temperature, the deep region does not reach the activation temperature, and the deep junction cannot be activated.

  If the flash lamps FL1 having a short pulse width and the flash lamps FL2 having a long pulse width are alternately arranged in a line as in the present embodiment, the strong peak intensity irradiated from the flash lamp FL1 on the entire surface of the semiconductor wafer W is increased. The flash light and the flash light having a gentle peak emitted from the flash lamp FL2 are uniformly overlapped, and the deep region is heated above the activation temperature without heating the shallow region of the semiconductor wafer W more than necessary. It is possible to activate the deep junction without causing the semiconductor wafer W to warp or crack.

<2. Second Embodiment>
Next, a second embodiment of the present invention will be described. The overall configuration of the heat treatment apparatus of the second embodiment is substantially the same as the apparatus configuration of the first embodiment shown in FIGS. It is the same as the embodiment. The heat treatment apparatus according to the second embodiment is different from the first embodiment in the arrangement of the flash lamp FL.

  FIG. 11 is a diagram illustrating an arrangement configuration of a plurality of flash lamps FL in the second embodiment. In the second embodiment, the flash lamp FL1 and the flash lamp FL2 are arranged so as to cross like a cross. That is, the plurality of flash lamps FL are divided into the same number of two lamp groups, and one of the lamp groups (first lamp group) is connected to the short pulse circuit SP and the other lamp group (second lamp group). Is connected to the long pulse circuit LP. The flash lamps FL1 constituting the first lamp group are arranged on a plane so as to be parallel to each other along the horizontal direction. The flash lamps FL2 constituting the second lamp group are also arranged on a plane so as to be parallel to each other along the horizontal direction. Then, the arrangement surface of the first lamp group and the arrangement surface of the second lamp group are arranged so that the flash lamps FL1 and the flash lamps FL2 intersect in a cross pattern. The short pulse circuit SP and the long pulse circuit LP are the same as those in the first embodiment, and the remaining configuration other than the arrangement of the flash lamp FL is the same as that in the first embodiment. Further, the vertical relationship of the arrangement of the flash lamp FL1 and the flash lamp FL2 may be either top.

  Even in the crossed arrangement as in the second embodiment, the flash light emitted from the flash lamp FL1 and the flash light emitted from the flash lamp FL2 are formed on the entire surface of the semiconductor wafer W held in the holding unit 7 at the processing position. They overlap each other uniformly. As a result, the light intensity from the start of light emission on the surface of the semiconductor wafer W changes as shown in FIG. 9, and the surface temperature of the semiconductor wafer W changes as shown in FIG. That is, as in the second embodiment, if the flash lamp FL1 having a short pulse width and the flash lamp FL2 having a long pulse width are arranged so as to cross in a cross pattern, the entire surface of the semiconductor wafer W is irradiated from the flash lamp FL1. The flash light having a strong peak intensity and the flash light having a gentle peak emitted from the flash lamp FL2 are uniformly overlapped to activate a deep region without heating the shallow region of the surface of the semiconductor wafer W more than necessary. The temperature can be raised to a temperature equal to or higher than the activation temperature, and deep bonding can be activated without causing the semiconductor wafer W to warp or crack.

<3. Third Embodiment>
Next, a third embodiment of the present invention will be described. The overall configuration of the heat treatment apparatus of the third embodiment is also substantially the same as the apparatus configuration of the first embodiment shown in FIGS. It is the same as the embodiment. The heat treatment apparatus of the third embodiment is different from the first embodiment in the shape and arrangement of the flash lamp FL.

  FIG. 12 is a diagram showing an arrangement configuration of a plurality of flash lamps FL in the third embodiment. In the first and second embodiments, the flash lamp FL is a rod lamp provided with a cylindrical glass tube 92, but in the third embodiment, the flash lamp FL is a point light source lamp (for example, a spherical lamp). A plurality of flash lamps FL, which are point light source lamps, are divided into the same number of two lamp groups, and one of the lamp groups (first lamp group) is connected to the short pulse circuit SP and the other lamp group (second lamp group). The point that the lamp group) is connected to the long pulse circuit LP is the same as in the first and second embodiments. In the third embodiment, the flash lamps FL1 and the flash lamps FL2 are alternately arranged in both the vertical direction and the horizontal direction. That is, the flash lamp FL1 and the flash lamp FL2 are arranged in a checkered pattern. The short pulse circuit SP and the long pulse circuit LP are the same as those of the first embodiment, and the remaining configuration other than the shape and arrangement of the flash lamp FL is the same as that of the first embodiment.

  Even in the lamp arrangement as in the third embodiment, the flash light emitted from the flash lamp FL1 and the flash light emitted from the flash lamp FL2 are applied to the entire surface of the semiconductor wafer W held in the holding unit 7 at the processing position. They overlap each other uniformly. As a result, the light intensity from the start of light emission on the surface of the semiconductor wafer W changes as shown in FIG. 9, and the surface temperature of the semiconductor wafer W changes as shown in FIG. That is, as in the third embodiment, if the flash lamp FL1 having a short pulse width and the flash lamp FL2 having a long pulse width are arranged in a checkered pattern, the entire surface of the semiconductor wafer W is irradiated from the flash lamp FL1. The flash light having a strong peak intensity and the flash light having a gentle peak emitted from the flash lamp FL2 are uniformly overlapped, and an activation temperature can be obtained even in a deep region without heating the shallow region of the surface of the semiconductor wafer W more than necessary. The temperature can be increased as described above, and deep bonding can be activated without causing the semiconductor wafer W to warp or crack.

<4. Modification>
While the embodiments of the present invention have been described above, the present invention can be modified in various ways other than those described above without departing from the spirit of the present invention. For example, in each of the above embodiments, the light emission start timing of the flash lamp FL1 and the light emission start timing of the flash lamp FL2 are set at the same time, but these may be shifted. FIG. 13 is a diagram showing the transition of the light intensity on the surface of the semiconductor wafer W when the light emission start timing of the flash lamp FL1 with a short pulse width is made earlier than the flash lamp FL2 with a long pulse width. Specifically, the control unit 3 controls the trigger control circuit 38 to turn on the trigger switch SW of the short pulse circuit SP connected to the flash lamp FL1, and then the long pulse circuit LP connected to the flash lamp FL2. Turn on the trigger switch SW.

  On the other hand, FIG. 14 is a diagram showing the transition of the light intensity on the surface of the semiconductor wafer W when the light emission start timing of the flash lamp FL1 having a short pulse width is made slower than that of the flash lamp FL2 having a long pulse width. Specifically, the control unit 3 controls the trigger control circuit 38 to turn on the trigger switch SW of the long pulse circuit LP connected to the flash lamp FL2, and then the short pulse circuit SP connected to the flash lamp FL1. Turn on the trigger switch SW. In FIG. 13 and FIG. 14, as in FIG. 9, the dotted line indicates the intensity of the flash light emitted from the flash lamp FL1 with a short pulse width, and the alternate long and short dash line is applied from the flash lamp FL2 with a long pulse width. The intensity of the flash light is shown, and the light intensity obtained by superimposing both is indicated by a solid line. Further, the arrangement of the flash lamps FL may be any of the first to third embodiments.

  As shown in FIG. 13 or FIG. 14, even if the emission start timing of the flash lamp FL1 and the emission start timing of the flash lamp FL2 are shifted, the flash light with a strong peak intensity emitted from the flash lamp FL1 and the flash lamp FL2 are emitted. The flash light having a gentle peak overlaps, and a deep region can be heated to an activation temperature or higher without heating a shallow region on the surface of the semiconductor wafer W more than necessary. It is possible to activate deep bonding without causing cracks. Furthermore, the depth of the region where the temperature is raised to the activation temperature or higher and the surface temperature of the semiconductor wafer W can be appropriately adjusted according to the time for shifting the light emission start timing, and the variation of the heat treatment pattern can be made abundant. it can.

  Further, the arrangement of the flash lamps FL is not limited to the patterns shown in FIGS. 7, 11 and 12, and various patterns can be adopted. However, an arrangement in which a flash lamp FL1 having a short pulse width or a flash lamp FL2 having a long pulse width is unevenly distributed (for example, in FIG. 7, only the flash lamp FL1 is arranged on the right half of the drawing and only the flash lamp FL2 is arranged on the left half). Then, a region where only the flash light having a strong peak intensity is irradiated on the surface of the semiconductor wafer W and a region where only the flash light having a gentle peak is irradiated are generated, and the activation process becomes non-uniform. Therefore, over the entire surface of the semiconductor wafer W, the flash light having a strong peak intensity emitted from the flash lamp FL1 and the flash light having a gentle peak emitted from the flash lamp FL2 are uniformly overlapped. It is preferable to use the lamp arrangement as described above.

  In each of the above embodiments, the number of flash lamps FL1 and flash lamps FL2 is the same. However, the number is not limited to this, and any number may be large. That is, the first lamp group constituted by a part of the plurality of flash lamps is connected to the short pulse circuit SP, and the second lamp group constituted by the remaining part is connected to the long pulse circuit LP. I just need it.

  In the short pulse circuit SP and the long pulse circuit LP of each of the above embodiments, the power supply unit 95 in the configuration of FIG. 6 is configured by a constant voltage power source, and a predetermined constant voltage is supplied to the capacitor 93. The power supply unit 95 of each of the short pulse circuit SP and the long pulse circuit LP is constituted by a variable power supply so that a desired voltage can be applied to the capacitor 93 and the charge voltage stored in the capacitor 93 is not limited to this. It may be made variable. With this configuration, the charge voltage stored in the capacitor 93 can be freely set by the short pulse circuit SP and the long pulse circuit LP by making the value of the power supply voltage applied from the power supply unit 95 variable. The discharge amount in each short pulse circuit SP and long pulse circuit LP can be changed by any combination of the charge voltages of the short pulse circuit SP and the long pulse circuit LP. Thereby, the intensity of light discharged from the flash lamp FL1 connected to the short pulse circuit SP and the intensity of light discharged from the flash lamp FL2 connected to the long pulse circuit LP can be made variable. In combination with making the light emission time variable as described above, it is possible to more freely select giving the required amount of heat to the semiconductor wafer W for the required time, and a desired depth region on the surface of the semiconductor wafer W according to the required process Can be activated freely.

  The flash lamp FL is not limited to a xenon flash lamp, and may be a krypton flash lamp.

  In each of the above embodiments, the hot plate 71 is used as the assist heating unit. However, a plurality of lamp groups (for example, a plurality of halogen lamps) are provided below the holding unit 7 that holds the semiconductor wafer W, You may make it perform assist heating by the light irradiation from.

  In each of the above embodiments, the semiconductor wafer is irradiated with light to perform the ion activation process. However, the present invention is not limited to this, and a configuration in which a cobalt silicide layer or a nickel silicide layer is formed. By using the heat treatment apparatus according to the present invention, a sufficiently thick silicide layer can be formed. Furthermore, the substrate to be processed by the heat treatment apparatus according to the present invention is not limited to a semiconductor wafer. For example, the glass substrate on which various silicon films such as a silicon nitride film and a polycrystalline silicon film are formed may be processed by the heat treatment apparatus according to the present invention. As an example, an amorphous silicon film made amorphous by ion implantation of silicon into a polycrystalline silicon film formed on a glass substrate by a CVD method is formed, and a silicon oxide film serving as an antireflection film is further formed thereon. Form. In this state, the entire surface of the amorphous silicon film is irradiated with light by the heat treatment apparatus according to the present invention, so that a polycrystalline silicon film obtained by polycrystallizing the amorphous silicon film can be formed.

  Further, a heat treatment according to the present invention is applied to a TFT substrate having a structure in which a base silicon oxide film and a polysilicon film obtained by crystallizing amorphous silicon are formed on a glass substrate, and the polysilicon film is doped with impurities such as phosphorus and boron. It is also possible to activate the impurities implanted in the doping process by irradiating light with an apparatus.

DESCRIPTION OF SYMBOLS 1 Heat processing apparatus 3 Control part 4 Holding part raising / lowering mechanism 5 Lamp house 6 Chamber 7 Holding part 52 Reflector 53 Lamp light emission window 61 Chamber window 65 Heat treatment space 71 Hot plate 72 Susceptor FL, FL1, FL2 Flash lamp LP Long pulse circuit SP Short Pulse circuit W Semiconductor wafer

Claims (2)

A heat treatment method for heating a semiconductor substrate by irradiating flash light from a flash lamp onto a semiconductor substrate into which ions are implanted ,
A first irradiation step of irradiating flash light having a first peak intensity to the entire region of the surface of the semiconductor substrate in a first irradiation time;
A second irradiation of a flash light having a second peak intensity weaker than the first peak intensity over the entire region of the surface of the semiconductor substrate during a second irradiation time longer than the first irradiation time. Irradiation process;
With
The flash light irradiated in at least a part of the second irradiation step is overlapped with the flash light irradiated in the first irradiation step in the entire region of the surface of the semiconductor substrate .
The first irradiation step and the temperature was raised to the second irradiation the semiconductor substrate activation temperature above the processing temperature ions of the surface temperature is injected into the semiconductor substrate of the flash light irradiation step, at least the second irradiation step Maintaining the surface temperature of the semiconductor substrate by flash light irradiation of the above activation temperature or more for a predetermined time or more,
The heat treatment method, wherein the first irradiation step and the second irradiation step are started simultaneously. The heat treatment method according to claim 1,
The heat treatment method according to claim 1, wherein the first irradiation time is 1.0 millisecond, and the second irradiation time is 3.0 milliseconds.

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