JP5907084B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
- Publication number
- JP5907084B2 JP5907084B2 JP2013018640A JP2013018640A JP5907084B2 JP 5907084 B2 JP5907084 B2 JP 5907084B2 JP 2013018640 A JP2013018640 A JP 2013018640A JP 2013018640 A JP2013018640 A JP 2013018640A JP 5907084 B2 JP5907084 B2 JP 5907084B2
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- JP
- Japan
- Prior art keywords
- lead frame
- frame material
- film material
- mask
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
本発明の第1実施形態について図面を参照しつつ説明する。図1に示されるように、半導体装置は、アイランド10上に半導体素子20が搭載され、半導体素子20が端子部11と電気的に接続されると共にモールド樹脂30に封止されて構成されている。なお、本実施形態では、アイランド10が本発明の搭載部に相当している。
本発明は上記した実施形態に限定されるものではなく、特許請求の範囲に記載した範囲内において適宜変更が可能である。
11 端子部
20 半導体素子
30 モールド樹脂
100 リードフレーム材
100a 一面
100b 他面
110 第1フォトレジスト(第1マスク)
120 第2フォトレジスト(第2マスク)
130 フィルム材
Claims (3)
- 一面(100a)および前記一面と反対側の他面(100b)を有するリードフレーム材(100)を用意する工程と、
前記リードフレーム材の一面に第1マスク(110)を形成する工程と、
前記リードフレーム材の他面に第2マスク(120)を形成する工程と、
前記第2マスクを所定形状にパターニングする工程と、
前記第2マスクを用いて前記リードフレーム材の他面側からハーフエッチングを行う工程と、
前記ハーフエッチングで除去された部分を埋め込むように、前記リードフレーム材の他面に接着力を変更可能なフィルム材(130)を配置する工程と、
前記第1マスクを所定形状にパターニングする工程と、
前記第1マスクを用いて前記リードフレーム材の一面側からエッチングを行い、搭載部(10)および端子部(11)を形成する工程と、
前記搭載部に前記半導体素子(20)を搭載する工程と、
前記フィルム材が露出するように、前記半導体素子をモールド樹脂(30)にて封止する工程と、
前記フィルム材の接着力を弱めて当該フィルム材を前記搭載部および前記端子部から除去する工程と、を行うことを特徴とする半導体装置の製造方法。 - 前記リードフレーム材は供給ロール(60a)から供給されて巻取りロール(60b)で巻取られるようになっており、
前記フィルム材を配置する工程では、前記リードフレーム材と前記フィルム材とを重ねた状態で、前記供給ロールと前記巻取りロールとの間に配置された一対の押し付けロール(80a、80b)の間を通過させる際に前記フィルム材を前記リードフレーム材に押し付けることによって圧接し、
前記半導体素子を搭載する工程の前に、前記リードフレーム材から前記フィルム材にて連結された1チップ分の前記端子部および前記搭載部を切り出すことを特徴とする請求項1に記載の半導体装置の製造方法。 - 前記フィルム材として紫外線硬化性樹脂フィルムを用い、
前記除去する工程では、前記フィルム材に紫外線を照射して当該フィルム材の接着力を弱めることを特徴とする請求項1または2に記載の半導体装置の製造方法。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2013018640A JP5907084B2 (ja) | 2013-02-01 | 2013-02-01 | 半導体装置の製造方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2013018640A JP5907084B2 (ja) | 2013-02-01 | 2013-02-01 | 半導体装置の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2014150182A JP2014150182A (ja) | 2014-08-21 |
JP5907084B2 true JP5907084B2 (ja) | 2016-04-20 |
Family
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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JP2013018640A Expired - Fee Related JP5907084B2 (ja) | 2013-02-01 | 2013-02-01 | 半導体装置の製造方法 |
Country Status (1)
Country | Link |
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JP (1) | JP5907084B2 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2023101044A1 (ko) * | 2021-11-30 | 2023-06-08 | 해성디에스 주식회사 | 프리 몰드 기판 및 프리 몰드 기판의 제조 방법 |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4272299B2 (ja) * | 1999-06-03 | 2009-06-03 | アピックヤマダ株式会社 | リードフレームばたつき防止機構及びリードフレーム検査装置 |
JP3664077B2 (ja) * | 2000-12-27 | 2005-06-22 | 松下電器産業株式会社 | リードフレームへのテープ貼り付け方法 |
JP4526714B2 (ja) * | 2001-01-29 | 2010-08-18 | 日東電工株式会社 | リードフレーム積層物および半導体装置の製造方法 |
JP4091050B2 (ja) * | 2005-01-31 | 2008-05-28 | 株式会社三井ハイテック | 半導体装置の製造方法 |
JP2007157846A (ja) * | 2005-12-01 | 2007-06-21 | Mitsui High Tec Inc | 半導体装置の製造方法 |
JP5077980B2 (ja) * | 2006-03-06 | 2012-11-21 | 日東電工株式会社 | 半導体装置の製造方法 |
JP5629969B2 (ja) * | 2008-09-29 | 2014-11-26 | 凸版印刷株式会社 | リードフレーム型基板の製造方法と半導体装置の製造方法 |
-
2013
- 2013-02-01 JP JP2013018640A patent/JP5907084B2/ja not_active Expired - Fee Related
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2023101044A1 (ko) * | 2021-11-30 | 2023-06-08 | 해성디에스 주식회사 | 프리 몰드 기판 및 프리 몰드 기판의 제조 방법 |
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JP2014150182A (ja) | 2014-08-21 |
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