JP5895338B2 - Power supply control circuit, electronic device, and power supply control method - Google Patents

Description

  The technology disclosed in the present application relates to a power supply control circuit that performs switching control in a current mode, an electronic device, and a power supply control method.

  As power supply devices capable of high-speed response, power supply devices that control output voltage by performing switching control based on a comparison between a ripple component of a feedback voltage and a reference voltage are known (Patent Documents 1 and 2, etc.). This is a so-called comparator type power supply device.

JP 2010-35316 US Publication No. 2005-0028269

  However, in a comparator type power supply device in a general technique, a switching operation is performed when the ripple component of the feedback voltage falls below the reference voltage as the output voltage decreases. The timing of the switching operation is an asynchronous operation performed in accordance with the output voltage fluctuation.

  Therefore, when a plurality of power supply devices are mixedly mounted on a device, each power supply device performs a switching operation asynchronously with respect to another power supply device without adjusting the timing of the switching operation. For this reason, the timing of the switching operation of each power supply device varies, and noise due to the switching operation may occur in a wide frequency band.

  In general, the comparator type power supply device compares the reference voltage with the peak value or the bottom value of the ripple component of the feedback voltage. In this case, the peak value or the bottom value of the ripple component of the output voltage is controlled to a voltage value corresponding to the reference voltage. On the other hand, the ripple component of the output voltage may be different depending on the operating conditions. In the comparator type power supply device, the output voltage obtained by averaging the ripple components may be controlled to a different voltage value depending on the operating conditions. This is a problem because the accuracy of the output voltage may not be ensured.

  The technology disclosed in the present application has been made in view of the problems of the background art, and provides a power supply control circuit, an electronic device, and a power supply control method that have improved high-speed response in current mode switching control. For the purpose.

A power supply control circuit according to a technique disclosed in the present application includes an amplifier that outputs an amplified signal based on a difference voltage between a feedback voltage corresponding to a voltage output from one end of an inductance element and a reference voltage, and an amplified signal. A signal generation circuit that outputs a first control signal, a current-voltage conversion circuit that detects a current flowing through a transistor connected to the other end of the inductance element, converts the detected current into a voltage, and an output of the current-voltage conversion circuit A comparison circuit that compares the signal and the amplified signal and outputs a second control signal; and a third control signal that turns on the transistor in response to a rising transition of the clock signal and turns off the transistor based on the second control signal. a flip-flop circuit for outputting an oscillation circuit for outputting a first clock signal having a fixed period, the fixed period the first clock signal Than the period from the third rising transition of the control signal in the operation of the transistor in the ON state until the rising transition of the first clock signal, rising at the elapsed period is short from the rising transition of the third control signal, and the third control A clock circuit that outputs a second clock signal having a rising transition that rises in a fixed predetermined period from the rising transition of the signal, and selects either the first clock signal or the second clock signal based on the first control signal And a selection circuit that outputs the clock signal to the flip-flop circuit, and the signal generation circuit has a first voltage value obtained by differentiating the voltage of the amplified signal according to a predetermined time constant higher than the first specified value. The first control signal for causing the selection circuit to select the second clock signal as the clock signal is output.

Further, according to the power supply control method according to the technique disclosed in the present application, the step of outputting the amplified signal based on the difference voltage between the feedback voltage corresponding to the voltage output from one end of the inductance element and the reference voltage; A step of outputting a first control signal based on the amplified signal, a step of detecting a current flowing through a transistor connected to the other end of the inductance element, a step of converting the detected current into a voltage, and a conversion of the detected current into a voltage Comparing the amplified signal with the amplified signal and outputting a second control signal; and a third control signal for turning on the transistor in response to the rising transition of the clock signal and for turning off the transistor based on the second control signal. and outputting, and outputting a first clock signal having a fixed period, preparative fixed period by the first clock signal Njisuta than a period of from rising transition of the third control signal at the operation of the ON state until the rising transition of the first clock signal, rising at the elapsed period is short from the rising transition of the third control signal, and the third control A step of outputting a second clock signal having a rising transition that rises in a fixed predetermined period from the rising transition of the signal, and a first that is obtained by differentiating the voltage of the amplified signal according to a predetermined time constant based on the first control signal Outputting the first clock signal as a clock signal if the voltage value is less than or equal to the first specified value; and outputting the second clock signal as a clock signal if the first voltage value is higher than the first specified value. And have.

  According to the power supply control circuit, the electronic device, and the power supply control method according to the technique disclosed in the present application, while ensuring the accuracy of the output voltage by switching control at a fixed frequency according to the current flowing through the inductance element, It is possible to provide a power supply control circuit, an electronic device, and a power supply control method capable of achieving high-speed response during response.

It is a circuit diagram of the switching power supply of an embodiment. It is an operation | movement waveform diagram of the switching power supply at the time of load increase. It is an operation | movement waveform diagram of the switching power supply at the time of load sudden reduction. It is a circuit diagram which illustrates the specific example of a selection circuit. FIG. 5 is an operation waveform diagram of the selection circuit illustrated in FIG. 4. It is a circuit diagram which illustrates the specific example of a time measuring circuit. FIG. 4 is a circuit diagram illustrating a specific example of a phase compensation circuit. It is a circuit diagram which illustrates the specific example of IV converter. It is a figure which shows control of the gain in IV converter. It is a block diagram which shows the electronic device carrying the switching power supply 1. FIG.

  FIG. 1 is a circuit diagram of a switching power supply 1 exemplified as an embodiment according to the present application. The switching power supply 1 includes a pMOS transistor Q1, an nMOS transistor Q2, an inductor L, a capacitor C, a switch SW1, an error amplifier 11, a selection circuit 12, a phase compensation circuit 13, an IV converter 14, and a comparator. 15, an oscillation circuit 16, a timing circuit 17, an AND circuit 18, and a D flip-flop (hereinafter referred to as D-FF) circuit 19.

  The pMOS transistor Q1 and the nMOS transistor Q2 are connected between the power supply voltage Vcc and the ground voltage, the power supply voltage Vcc is supplied to the source terminal of the pMOS transistor Q1, and the ground voltage is supplied to the source terminal of the nMOS transistor Q2. A control line PgL is connected to the gate terminals of the pMOS transistor Q1 and the nMOS transistor Q2. A control signal Pg propagates to the control line PgL. The drain terminals of the pMOS transistor Q1 and the nMOS transistor Q2 are connected by a connection line LxL. The connection line LxL and the output line VoL are connected via an inductor L. A capacitor C having one end connected to the ground voltage is connected to the output line VoL. The output voltage Vo is supplied from the output line VoL.

  The resistors R1 and R2 are connected in series between the output line VoL and the ground voltage. A connection for connecting the resistor R1 and the resistor R2 is a reference line VfbL. The resistor R1 is connected between the output line VoL and the reference line VfbL, and the resistor R2 is connected between the reference line VfbL and the ground voltage. A reference voltage Vfb obtained by dividing the output voltage Vo is supplied from the reference line VfbL.

  The reference line VfbL is connected to the inverting input terminal of the error amplifier 11, and the reference voltage Vr is input to the non-inverting input terminal. An error line VeaL is connected to the output terminal of the error amplifier 11 to output an error voltage Vea. The error voltage Vea is a result of amplifying the difference voltage of the reference voltage Vfb with respect to the reference voltage Vr. The lower the reference voltage Vfb is compared to the reference voltage Vr, the higher the error voltage Vea. The higher the reference voltage Vfb is compared to the reference voltage Vr, the lower the error voltage Vea.

  The phase compensation circuit 13 is connected between a reference line VfbL connected to the inverting input terminal of the error amplifier 11 and an error line VeaL connected to the output terminal of the error amplifier 11. In the phase compensation circuit 13, the frequency band for which phase compensation is performed is switched according to the control signal CMP3.

  The selection circuit 12 is connected to the error line VeaL, the control line CMP1L, the control line CMP2L, and the control line CMP3L. The control signal CMP1 is output to the control line CMP1L, the control signal CMP2 is output to the control line CMP2L, and the control signal CMP3 is output to the control line CMP3L in accordance with the error voltage Vea input from the error line VeaL. A change in the error voltage Vea is detected, and the control signal CMP1, the control signal CMP2, and the control signal CMP3 are controlled according to the direction of the change. When the output voltage Vo output to the output line VoL of the switching power supply 1 is maintained at a predetermined voltage without transient fluctuation or is not more than a prescribed fluctuation even when transient fluctuation occurs, the error voltage Vea fluctuates. Even if it does or does not fluctuate, the rate of fluctuation per hour (hereinafter referred to as slew rate) is below the specified value. In this case, the control signal CMP1 is at a low level, the control signal CMP2 is at a high level, and the control signal CMP3 is at a high level. When the output voltage Vo fluctuates more than a specified value in a decreasing direction and the slew rate of the error voltage Vea exceeds a positive specified value, the control signal CMP1 changes to a high level and the control signal CMP3 changes to a low level. The control signal CMP2 is at a high level. When the output voltage Vo fluctuates more than a specified value in an increasing direction and the slew rate of the error voltage Vea exceeds a negative specified value, the control signal CMP2 changes to a low level, and at the same time, the control signal CMP3 changes to a low level. . The control signal CMP1 is at a low level.

  The IV converter 14 is connected to the control line CMP1L and the control line CMP2L, and receives the control signal CMP1 and the control signal CMP2. A conversion signal Vse is output to the conversion line VseL. The IV converter 14 detects the inductor current Il flowing through the inductor L. The conversion signal Vse is a signal converted into a voltage value corresponding to the inductor current Il. The higher the inductor current Il, the higher the voltage value of the conversion signal Vse. The lower the inductor current Il, the lower the voltage value of the conversion signal Vse. The IV converter 14 controls a gain that is a conversion coefficient of the conversion signal Vse according to the control signal CMP1 and the control signal CMP2.

  The inverting input terminal of the comparator 15 is connected to the conversion line VseL, and the non-inverting input terminal is connected to the error line VeaL. A control line PrL is connected to the output terminal of the comparator 15 to output a control signal Pr. The comparator 15 compares the voltage values of the error voltage Vea and the conversion signal Vse. When the conversion signal Vse exceeds the voltage value of the error voltage Vse, the control signal Pr changes from high level to low level. Since the conversion signal Vse is proportional to the inductor current Il, in order for the control signal Pr to transition to a low level, the conversion signal Vse increases as the error voltage Vea increases. That is, the inductor current Il increases.

  The clock line CK1L is connected to the output terminal of the oscillation circuit 16, and the clock signal CK1 is output. The clock signal CK1 oscillates at a predetermined clock cycle T1.

  A control line PgL is connected to the input terminal of the timer circuit 17. A clock line CK2L is connected to the output terminal to output a clock signal CK2. The clock signal CK2 changes from the low level to the high level after a predetermined time has elapsed since the high level transition of the control signal Pg. The low level transition of the control signal Pg causes a low level transition.

  The switch SW1 is controlled to select either the clock line CK1L or the clock line CK2L by the control signal CMP1.

  One of the input terminals of the AND circuit 18 is connected by selecting either the clock line CK1L or the clock line CK2L by the switch SW1, and the other input terminal is connected by the control line CMP2L. A clock line CKL is connected to the output terminal to output a clock signal CK. The AND circuit 18 is controlled by a control signal CMP2. The AND circuit 18 controls whether the CK terminal of the D-FF circuit 19 is connected to the clock line CK1L or the clock line CK2L, or fixed to a low level. When the control signal CMP2 is at a high level, the clock line CKL is connected to either the clock line CK1L or the clock line CK2L selected by the switch SW1. When the control signal CMP2 is at low level, the CK terminal of the D-FF circuit 19 is fixed at low level.

  When the output voltage Vo is maintained at a predetermined voltage, or when the transient fluctuation is less than the specified value, the control signal CMP1 is at a low level. In this case, the switch SW1 connects the clock line CK1L to the AND circuit 18. When the transient fluctuation of the output voltage Vo is a fluctuation more than a specified value in the voltage lowering direction, the control signal CMP1 becomes a high level. In this case, the switch SW1 connects the clock line CK2L to the AND circuit 18. Since the control signal CMP2 is at a high level, the clock line CK2L signal selected by the switch SW1 is output to the clock line CKL. When the transitional fluctuation of the output voltage Vo is a fluctuation exceeding the specified value in the increasing direction, the control signal CMP2 becomes low level. In this case, the clock line CKL is fixed at a low level.

  A ground voltage is connected to the terminal D of the D-FF circuit 19, and a low level is always input. A clock line CKL is connected to the terminal CK. A control line PrL is connected to the terminal PRB. A control line PgL is connected to the terminal Q.

  When the control signal Pr transitions to a low level, the D-FF circuit 19 is preset and the control signal Pg transitions to a high level. The gate terminals of the pMOS transistor Q1 and the nMOS transistor Q2 are set to the high level. As a result, the pMOS transistor Q1 is turned off and the nMOS transistor Q2 is turned on. Supply of the power supply voltage Vcc to the inductor L is stopped by turning off the pMOS transistor Q1. On the other hand, the nMOS transistor Q2 is turned on, and the electromagnetic energy accumulated in the inductor L is released toward the output line VoL. This is a so-called regenerative state. The control signal Pg transitions to the low level because the conversion signal Vse exceeds the voltage value of the error voltage Vea. That is, when the inductor current Il exceeds the current value corresponding to the error voltage Vea set according to the output voltage Vo, the switching power supply 1 enters a regenerative state. The switching power supply 1 performs peak current control.

  When the clock signal CK transitions to a high level, the ground voltage connected to the terminal D of the D-FF circuit 19 is taken in as a low level signal and output from the terminal Q. The control signal Pg output from the control line PgL connected to the terminal Q of the D-FF circuit 19 transitions to a low level. The gate terminals of the pMOS transistor Q1 and the nMOS transistor Q2 are set to the low level. As a result, the pMOS transistor Q1 is turned on and the nMOS transistor Q2 is turned off. The power supply voltage Vcc is supplied to the inductor L by turning on the pMOS transistor Q1.

  A signal input to the terminal CK of the D-FF circuit 19 is controlled by the switch SW1. When the clock signal CK1 output from the oscillation circuit 16 at a constant cycle is input by the switch SW1, the switching power supply 1 performs a switching operation at a fixed cycle. When the clock signal CK <b> 2 whose low level continues for a predetermined time is input from the timer circuit 17 by the switch SW <b> 1, the switching power supply 1 performs a switching operation with a fixed off time.

  FIG. 2 shows a case where the load suddenly increases as an example in which the transient fluctuation of the output voltage Vo fluctuates more than a specified value in the voltage drop direction. FIG. 4 is an operation waveform diagram of the switching power supply 1. Before the sudden increase in load, the control signal CMP1 is at a low level and the control signal CMP2 is at a high level. Therefore, the clock line CKL is connected to the clock line CK1L, and the switching power supply 1 performs a switching operation at a clock cycle T1, which is a fixed period of the clock signal CK1 output from the oscillation circuit 16.

  When the load increases rapidly, the error voltage Vea increases at a slew rate that exceeds a specified value as the output voltage Vo decreases. Since the error voltage Vea is input to the non-inverting input terminal of the comparator 15, the control signal Pr output from the comparator 15 becomes low level. The voltage value of the conversion signal Vse increases. The conversion signal Vse is a signal converted into a voltage value according to the inductor current Il by the IV converter 14. Therefore, the peak current of the inductor current Il increases.

  In a general circuit using a switching operation at a fixed frequency, the timing when the off period ends and the next on period starts is after the clock cycle T1 from the start of the previous on period. The on period is started again by the high-level transition of the clock signal CK1 output from the oscillation circuit 16 (a waveform denoted as a fixed frequency in FIG. 2). When the transient fluctuation of the output voltage Vo occurs in the voltage drop direction, the error voltage Vea may not follow the sudden change of the output voltage Vo because the phase compensation circuit 13 exists. It can be considered that the error voltage Vea is maintained at a low value at the beginning of the sudden decrease of the output voltage Vo. In this case, the conversion signal Vse is compared with a low value error voltage Vea. As a result, the control signal Pr output from the comparator 15 transitions to a low level when the conversion signal Vse is low. That is, the off-period of the switching power supply is started in a state where the peak current of the inductor current Il is not sufficiently high, and there is a possibility that a switching operation with a sufficiently large duty cannot be obtained. During this time, it becomes a period during which the response of the switching power supply cannot follow the sudden increase in load. If the value of the error voltage Vea increases and the value of the conversion signal Vse does not exceed the value of the error voltage Vea even if the ON period continues during the clock cycle T1, the switching power supply reaches the maximum duty and power Supply is maximized.

  In the switching power supply 1, it is detected that the slew rate of the error voltage Vea becomes more than a positive regulation with a transient voltage drop exceeding the regulation of the output voltage Vo due to a sudden increase in load or the like. As a result, the control signal CMP1 changes from the low level to the high level. The switch SW1 is switched, and the clock line CK2L is connected to the clock line CKL. The clock signal CK is switched to the clock signal CK2 output from the timer circuit 17. The switching power supply 1 performs switching operation with a fixed off time.

  FIG. 2 illustrates a case where the transition of the error voltage Vea is detected at the timing when the clock signal CK1 and the clock signal CK2 simultaneously transition to the high level, and the clock signal CK switches from the clock signal CK1 to the clock signal CK2. In a switching power supply controlled at a fixed frequency, the ON period starts when the clock signal CK1 transitions to a high level, so that the power supply is the earliest timing for the switching power supply controlled at a fixed frequency.

  It is assumed that the off period Toff2 generated by the timer circuit 17 is sufficiently shorter than the switching cycle T1 in the fixed frequency control. At the beginning of the sudden decrease in the output voltage Vo, the error voltage Vea may be maintained at a low value. The conversion signal Vse is compared with a low value error voltage Vea, and the control signal Pr output from the comparator 15 transitions to a low level when the conversion signal Vse is low. However, in the switching power supply 1, since the off period Toff2 is set to a short time, the on period is started again after a short time has elapsed. The duty of the switching operation at this time is larger than that in the case of fixed frequency control. The period during which power supply from the power supply voltage Vcc to the inductor L is stopped can be shortened, and a decrease in the output voltage Vo can be suppressed.

  When the switching operation is performed with the fixed off time, the on period is determined according to the voltage difference between the error voltage Vea and the conversion signal Vse. Since the off period Toff2 is fixed, the switching cycle is adjusted according to the voltage difference between the error voltage Vea and the conversion signal Vse. In the initial stage of voltage drop of the output voltage Vo, when the error voltage Vea is low and the voltage difference from the conversion signal Vse is small, the ON period is short and the duty is small, but the switching frequency is high. Thereafter, when the error voltage Vea increases and the voltage difference from the conversion signal Vse increases, the ON period becomes longer and the switching frequency becomes lower, but the duty increases. As a result, compared with the case of fixed frequency control used in a general circuit, the switching frequency is short at the initial stage of fluctuation of the output voltage Vo, the duty is then increased, and power can be effectively supplied to the load. As a result, it is possible to improve response characteristics with respect to a decrease in the output voltage Vo.

  FIG. 3 shows a case where the load suddenly decreases as an example in which the transient fluctuation of the output voltage Vo fluctuates more than a specified value in the voltage rising direction. FIG. 4 is an operation waveform diagram of the switching power supply 1. Before the sudden decrease in load, the control signal CMP1 is at a low level and the control signal CMP2 is at a high level. Therefore, the clock line CKL is connected to the clock line CK1L, and the switching power supply 1 performs a switching operation at the clock cycle T1.

  When the load suddenly decreases, the error voltage Vea decreases at a slew rate that exceeds a specified value as the output voltage Vo increases. Since the error voltage Vea is input to the non-inverting input terminal of the comparator 15, the voltage value of the conversion signal Vse at which the control signal Pr output from the comparator 15 becomes low level decreases. The conversion signal Vse is a signal converted into a voltage value according to the inductor current Il by the IV converter 14. Therefore, the peak current of the inductor current Il decreases.

  In a general circuit using a switching operation at a fixed frequency, a high level transition of the clock signal CK1 occurs every clock cycle T1, and an on period occurs. In other words, during the period in which the output voltage Vo rises above the specified value, the on period is between the time when the value of the conversion signal Vse reaches the value of the error voltage Vea (indicated as a fixed frequency in FIG. 3). Waveform). Due to this switching operation, there is a period in which the response of the switching power supply does not follow the sudden decrease in load, and power is supplied from the power supply voltage Vcc to the inductor L and the output voltage Vo rises.

  In the switching power supply 1, it is detected that the slew rate of the error voltage Vea becomes greater than a negative regulation as the transient voltage increases beyond the regulation of the output voltage Vo. At this time, the control signal CMP2 transits to a low level and the clock signal CK is masked. The clock signal CK output from the AND circuit 18 is fixed at a low level. As a result, the switching power supply 1 is maintained in the off state, and power supply to the output voltage Vo is stopped. The switching power supply 1 remains off until the control signal CMP2 transitions to a high level. Therefore, the switching power supply 1 can stop the power supply to the load, and the response characteristic of the output voltage Vo with respect to the sudden decrease in the load can be improved.

  Further, the control signal CMP3 is input to the phase compensation circuit 13. The control signal CMP3 is at a high level when the output voltage Vo is maintained at a predetermined voltage or when the transient fluctuation is below a specified level. At this time, the frequency band of the phase compensation circuit 13 takes a predetermined value required to ensure the stability of the system in the steady state of the switching power supply 1. When the transient fluctuation of the output voltage Vo fluctuates more than a specified value in the voltage decreasing direction or increasing direction, the control signal CMP3 transits to a low level. The frequency band of the phase compensation circuit 13 is switched to a higher frequency band. Since the response of the error voltage Vea becomes faster, it is possible to quickly respond to the transient fluctuation of the output voltage Vo. The slew rate of the error voltage Vea increases with respect to the transient fluctuation of the output voltage Vo, and a high-speed response is possible. As a result, it is possible to improve the response characteristics of the output voltage Vo to a sudden load change.

  The IV converter 14 is supplied with a control signal CMP1. The control signal CMP1 transitions to a high level when the transitional fluctuation of the output voltage Vo is more than a specified fluctuation in the voltage decreasing direction. As a result, the gain set by the IV converter 14 becomes a small value as compared with the case where the output voltage Vo is maintained at a predetermined voltage or the transient fluctuation is equal to or less than the prescribed fluctuation. Since the gain decreases, the value of the conversion signal Vse output after conversion with respect to the current value of the inductor current Il decreases. As a result of comparison with the error voltage Vea by the comparator 15, the peak current value of the inductor current Il is controlled to a large current value. The on period becomes longer, the power supply capability to the load is improved, and the response characteristic to the transient reduction of the output voltage Vo can be improved.

  When the transitional fluctuation of the output voltage Vo is a fluctuation exceeding the specified value in the voltage increasing direction, the control signal CMP1 transits to the low level and the control signal CMP2 transits to the low level. The gain set by the IV converter 14 becomes a large value as compared with the case where the output voltage Vo is maintained at a predetermined voltage or the transient fluctuation is equal to or less than the prescribed fluctuation. Since the gain increases, the value of the conversion signal Vse output after conversion with respect to the current value of the inductor current Il increases. As a result of comparison with the error voltage Vea by the comparator 15, the peak current value of the inductor current Il is controlled to a small current value. The on-period is shortened, and the response characteristics with respect to the transient increase of the output voltage Vo can be improved.

  FIG. 4 is a circuit diagram illustrating a specific example of the selection circuit 12. The selection circuit 12 includes a differentiation circuit 21 and a selection control circuit 22.

  The differentiation circuit 21 includes a capacitor Csr and a resistor Rsr, and is connected between the error line VeaL and the reference voltage Va. The capacitor Csr is connected between the error line VeaL and the differential line VsrL, and the resistor Rsr is connected between the differential line VsrL and the reference voltage Va. Here, the differential line VsrL is a connection point between the capacitor Csr and the resistor Rsr. When the output voltage Vo is in a steady state, the error voltage Vea input to the differentiating circuit 21 does not fluctuate, so the differential signal Vsr generated on the differential line VsrL is equal to the reference voltage Va. Even when the error voltage Vea fluctuates, if the fluctuation is less than the specified value, the change of the differential signal Vsr generated on the differential line VsrL is not detected by the selection control circuit 22 described later. .

  The selection control circuit 22 includes comparators CMP1 and CMP2, an inverter circuit 23, and a NOR circuit 24.

  The reference voltage Vb is input to the inverting input terminal of the comparator CMP1, and the differential line VsrL is connected to the non-inverting input terminal and the differential signal Vsr is input. The reference voltage Vb is connected so as to be added to the reference voltage Va. A value obtained by adding the reference voltage Vb to the reference voltage Va is input to the inverting input terminal of the comparator CMP1. A control line CMP1L is connected to the output terminal to output a control signal CMP1. If the output voltage Vo is maintained at a predetermined voltage or if the transient fluctuation is equal to or less than the prescribed fluctuation, the differential signal Vsr does not exceed the voltage obtained by adding the reference voltage Vb to the reference voltage Va, and the control is performed. The signal CMP1 is at a low level.

  The reference voltage Vc is input to the inverting input terminal of the comparator CMP2, and the differential line VsrL is connected to the non-inverting input terminal and the differential signal Vsr is input. The reference voltage Vc is wired so as to be subtracted from the reference voltage Va. A value obtained by subtracting the reference voltage Vb from the reference voltage Va is input to the inverting input terminal of the comparator CMP2. A control line CMP2L is connected to the output terminal to output a control signal CMP2. When the output voltage Vo is maintained at a predetermined voltage, or when the transient fluctuation is equal to or less than the prescribed fluctuation, the differential signal Vsr does not exceed the voltage obtained by subtracting the reference voltage Vb from the reference voltage Va, and the control signal CMP2 is at a high level.

  The control line CMP1L is connected to the first input terminal of the NOR circuit 24, and the control signal CMP1 is input. The output terminal of the inverter circuit 23 is input to the second input terminal. A control line CMP2L is connected to an input terminal of the inverter circuit 23, and a control signal CMP2 is input thereto. An inverted signal of the control signal CMP2 is input to the second input terminal. A control line CMP3 is connected to the output terminal to output a control signal CMP3.

  FIG. 5 is an operation waveform diagram of the selection circuit illustrated in FIG. In the region (I), a case where the transient fluctuation of the output voltage Vo is a fluctuation more than a specified value in the voltage drop direction is illustrated. At this time, the error voltage Vea increases. The differential signal Vsr is a pulse signal higher than the voltage obtained by differentiating the fluctuation of the error voltage Vea and adding the reference voltage Vb to the reference voltage Va. As a result, the control signal CMP1 changes from the low level to the high level, and at the same time, the control signal CMP3 changes from the high level to the low level. Thereafter, the voltage of the differential signal Vsr decreases toward the reference voltage Va according to the time constant of the differentiating circuit 21. When the differential signal Vsr falls below the voltage obtained by adding the reference voltage Vb to the reference voltage Va, the control signal CMP1 changes to the low level, and at the same time, the control signal CMP3 changes to the high level.

  In the region (II), a case where the transient fluctuation of the output voltage Vo is a fluctuation more than a specified value in the increasing direction is illustrated. At this time, the error voltage Vea decreases. The differential signal Vsr is a lower pulse signal obtained by differentiating the fluctuation of the error voltage Vea and subtracting the reference voltage Vc from the reference voltage Va. As a result, the control signal CMP2 changes from the high level to the low level, and at the same time, the control signal CMP3 changes from the high level to the low level. Thereafter, the voltage of the differential signal Vsr increases toward the reference voltage Va according to the time constant of the differentiating circuit 21. When the differential signal Vsr exceeds the voltage obtained by subtracting the reference voltage Vc from the reference voltage Va, the control signal CMP2 transits to a high level, and at the same time, the control signal CMP3 transits to a high level.

  When the transitional fluctuation of the output voltage Vo is a fluctuation exceeding the specified value in the decreasing or increasing direction of the voltage, the error voltage Vea fluctuates beyond the specified value. The differentiation circuit 21 detects a variation in the error voltage Vea as a differentiation result, and outputs a differentiation signal Vsr to the selection control circuit 22. The selection control circuit 22 detects the fluctuation direction of the output voltage Vo by comparing the differential signal Vsr with a reference voltage. The selection control circuit 22 transitions the control signal CMP1 to a high level when the transient fluctuation of the output voltage Vo fluctuates more than a specified value in the voltage drop direction and the error voltage Vea increases more than a specified value. When the transient fluctuation of the output voltage Vo fluctuates more than a specified value in the increasing direction and the error voltage Vea decreases more than a specified value, the control signal CMP2 is transited to a low level. In the case of fluctuations in both directions, the control signal CMP3 is transited to a low level.

  FIG. 6 is a circuit diagram illustrating a specific example of the timer circuit 17. The timer circuit 17 includes an inverter circuit 31, an nMOS transistor Q3, a constant current source CS0 for passing a constant current I1, a capacitor C1, and a comparator 32. The control line PgL is connected to the input terminal of the inverter circuit 31 and the control signal Pg is input. An inverted signal of the control signal Pg is output to the gate terminal of the nMOS transistor Q3. The ground voltage is connected to the source terminal of the nMOS transistor Q3, and the line CtL is connected to the drain terminal. Here, the voltage generated on the line CtL is the terminal voltage VCt. Capacitor C1 is connected between line CtL and a reference voltage. The reference voltage Vt is input to the inverting input terminal of the comparator 32, and the line CtL is connected to the non-inverting input terminal to input the terminal voltage VCt.

  When the control signal Pg input to the timer circuit 17 is at a low level, the constant current I1 flows to the ground voltage via the nMOS transistor Q3. Therefore, the capacitor C1 is always discharged, and the terminal voltage VCt is compared with the reference voltage Vt. Is low. Therefore, the clock signal CK2 that is the output signal of the comparator 32 is at a low level. When the control signal Pg changes from the low level to the high level, the nMOS transistor Q3 changes from the on state to the off state. Charging of the capacitor C1 is started by the constant current I1, and the terminal voltage VCt rises according to the constant current I1. After a lapse of a predetermined period from the high level transition of the control signal Pg, the terminal voltage VCt becomes higher than the reference voltage Vt. The voltage difference input to the comparator 32 is inverted, and the clock signal CK2 changes from the low level to the high level. The capacitor C1 is charged by the constant current I1 output from the constant current source CS0, and the terminal voltage VCt that increases in accordance with the charging is compared with the reference voltage Vt, whereby the clock signal CK2 is clocked during the low level period. Since the constant current I1, the capacitance value of the capacitor C1, and the reference voltage Vt are fixed, the low level period of the clock signal CK2 is a constant time. Thereby, a fixed off period is timed.

  FIG. 7 is a circuit diagram illustrating a specific example of the phase compensation circuit 13. The phase compensation circuit 13 includes capacitors C2 and C3 connected between the reference line VfbL and the error line VeaL, and a switch SW2. Capacitor C2 and capacitor C3 are connected in parallel between reference line VfbL and error line VeaL. One end of the capacitor C2 is connected to the error line VeaL via the switch SW2. The switch SW2 is controlled by a control signal CMP3. When the control signal CMP3 is at a high level, the switch SW2 is short-circuited, and one end of the capacitor C2 and the error line VeaL are connected. When the control signal CMP3 is at a low level, the switch SW2 is opened, and one end of the capacitor C2 and the error line VeaL are opened.

  When the control signal CMP3 is at a low level, the switch SW2 is opened and the capacitor C2 is disconnected from the phase compensation circuit 13. The phase compensation circuit 13 includes a capacitor C3. The capacitance value of the phase compensation circuit 13 becomes low. Therefore, when the transient fluctuation of the output voltage Vo is a fluctuation more than the specified value in the voltage decreasing or increasing direction, it is possible to respond to a high frequency band. Therefore, it becomes possible to speed up the response of the feedback operation by the error amplifier 11 to the fluctuation of the output voltage Vo due to the sudden load change.

  FIG. 8 is a circuit diagram illustrating a specific example of the IV converter 14. The IV converter 14 includes pMOS transistors Q4 and Q5, nMOS transistors Q6 and Q7, resistors R3, R4, and R5, and an operational amplifier 33. The gate terminal of the pMOS transistor Q4 whose source terminal is connected to the power supply voltage Vcc is connected to the control line PgL. The drain terminal is connected to the inverting input terminal of the operational amplifier 33 and the source terminal of the pMOS transistor Q5. The non-inverting input terminal of the operational amplifier 33 is connected to the connection line LxL. The output terminal is connected to the gate terminal of the pMOS transistor Q5. The drain terminal of the pMOS transistor Q5 is connected to the conversion line VseL. The operational amplifier 33 controls the pMOS transistor Q5 so that the drain voltage of the pMOS transistor Q4 is substantially equal to the voltage of the connection line LxL. As a result, the pMOS transistor Q5 and the pMOS transistor Q1 have their source, drain, and gate terminals biased to the same voltage. When the gate length is the same, the current flowing through each transistor is proportional to the gate width of each transistor. Therefore, the detection current Ise flowing through the pMOS transistor Q5 is a current proportional to the inductor current Ilx flowing through the inductor L via the pMOS transistor Q1. The inductor current Ilx can be detected by the detection current Ise. The inductor current Ilx is a current that flows from the power supply voltage Vcc to the inductor L via the pMOS transistor Q1 due to the low level transition of the control signal Pg. That is, the inductor current Ilx is the inductor current Il when the pMOS transistor Q1 is on. Due to the high level transition of the control signal Pg, the pMOS transistor Q1 is turned off and the current value becomes 0A. When the clock signal CK transits to a high level, the control signal Pg transits to a low level, and the pMOS transistor Q1 is turned on again.

  The resistors R3, R4, and R5 are connected in series between the conversion line VseL and the ground voltage. The drain terminal of the nMOS transistor Q6 is connected to a connection connecting the resistor R3 and the resistor R4, one end of which is connected to the conversion line VseL. The source terminal of the nMOS transistor Q6 is connected to the ground voltage, and the control terminal CMP1L is connected to the gate terminal. Also, the drain terminal of the nMOS transistor Q7 is connected to the connection connecting the resistors R4 and R5, one end of which is connected to the resistor R3. The ground terminal is connected to the source terminal of the nMOS transistor Q7, and the control line CMP2L is connected to the gate terminal. The other end of the resistor R5 having one end connected to the resistor R4 is connected to the installation voltage.

  FIG. 9 is a diagram illustrating gain control in the IV converter 14. In the IV converter 14, when the output voltage Vo is maintained at a predetermined voltage, or when the transient fluctuation is equal to or less than the prescribed fluctuation, the input control signal CMP 1 is low level and the control signal CMP 2 is high level. It is. At this time, the nMOS transistor Q6 is turned off and the nMOS transistor Q7 is turned on. Therefore, the detection current Ise flows to the ground voltage via the resistors R3, R4 and the nMOS transistor Q7. The resistance value between the conversion line VseL and the ground voltage is equal to the resistance value obtained by adding the resistance R3 and the resistance R4 (R3 + R4). This is set as a reference gain (R3 + R4).

  When the transitional fluctuation of the output voltage Vo is a fluctuation exceeding the specified value in the voltage lowering direction, the input control signals CMP1 and CMP2 are both at a high level. At this time, the nMOS transistors Q6 and Q7 are both turned on. The detection current Ise flows to the ground voltage via the resistor R3 and the nMOS transistors Q6 and Q7. The resistance value between the conversion line VseL and the ground voltage becomes a resistance R3, which becomes a gain (R3). The gain is smaller than the reference gain (R3 + R4). The peak current value of the inductor current Ilx is higher when the error voltage Vea is the same as compared with the case of the reference gain. Since the inductor current Ilx rises according to the time during which the power supply voltage Vcc is supplied to the inductor L, the on period becomes longer when the gain is small. The power supply capability to the load can be increased, and the response characteristics with respect to the transient reduction of the output voltage Vo can be improved.

  When the transitional fluctuation of the output voltage Vo is a fluctuation exceeding the specified value in the increasing direction, the input control signals CMP1 and CMP2 are both at a low level. At this time, the nMOS transistors Q6 and Q7 are both turned off. The detection current Ise flows to the ground voltage via the resistors R3, R4, and R5 connected in series. The resistance value between the conversion line VseL and the ground voltage is equal to the resistance value obtained by adding the resistors R3, R4, and R5. This is the gain (R3 + R4 + R5). The gain is larger than the reference gain (R3 + R4). Then, when the error voltage Vea is the same, the peak current value of the inductor current Ilx is lower than that of the reference gain. In this case, the ON period is shortened. By limiting the power supply to the load, it is possible to improve the response characteristics against a transient increase in the output voltage Vo.

  FIG. 10 is a block diagram showing an electronic device 100 in which the switching power supply 1 is mounted. Examples of the electronic device 100 include a portable device system, a personal computer, a mobile phone, and a digital camera. The electronic device 100 includes a battery 200, a switching power supply 1, and a load circuit 300. The battery 200 supplies a power supply voltage Vcc to the switching power supply 1. For example, a lithium ion battery or a plurality of lithium ion battery units connected in series. The load circuit 300 is, for example, an analog circuit, a digital circuit, a microprocessor, a light emitting element, a display element, a sensor, or the like. The switching power supply 1 receives the power supply voltage Vcc output from the battery 200, converts it to an output voltage Vo having a predetermined voltage value, and supplies the output voltage Vo to the load circuit 300.

  As described above in detail, according to the embodiment, the selection circuit 12 controls the signal input to the terminal CK of the D-FF circuit 19 by controlling the switch SW1. As a result, when the transient fluctuation of the output voltage Vo is a fluctuation more than a specified value in the voltage drop direction, the timer circuit 17 is selected as the AND circuit 18 and the clock signal CK becomes a signal with a fixed off time. The switching power supply 1 performs a switching operation by fixed off-time control. Compared with the case of fixed frequency control, the response characteristic with respect to a transient drop of the output voltage Vo due to a sudden increase in load or the like is improved, and the drop of the output voltage Vo is suppressed.

  On the other hand, when the transitional fluctuation of the output voltage Vo is more than a specified fluctuation in the increasing direction, the clock signal CK output from the AND circuit 18 is fixed at a low level. The switching power supply 1 continues to be in an off state, and the switching power supply 1 can stop power feeding to the load. Thereby, the response characteristic with respect to the increase of the output voltage Vo can be improved.

  Further, according to the phase compensation circuit 13 of the present invention, when the output voltage Vo is maintained at a predetermined voltage or the transient fluctuation is not more than a specified value, the frequency band of the phase compensation circuit 13 takes a predetermined value. . When the transient fluctuation of the output voltage Vo is a fluctuation exceeding the specified value in the voltage decreasing or increasing direction, the frequency band of the phase compensation circuit 13 is switched, and it becomes possible to respond to a higher frequency band compared to a predetermined value. . As a result, it is possible to improve the response characteristics of the output voltage Vo to a sudden load change.

  Further, according to the IV converter 14 of the present invention, when the transient fluctuation of the output voltage Vo is a fluctuation more than a specified value in the voltage lowering direction, the gain is set smaller than the case of the reference gain. As a result, the peak current of the inductor current Ilx increases with respect to the same error voltage Vea. The on-period of the switching power supply 1 becomes longer, and the response characteristics with respect to the transient decrease of the output voltage Vo can be improved.

  On the other hand, when the transitional fluctuation of the output voltage Vo is a fluctuation exceeding the specified value in the increasing direction, the gain is set larger than the reference gain. As a result, the peak current of the inductor current Ilx decreases with respect to the same error voltage Vea. The ON period of the switching power supply 1 is shortened, and the response characteristics with respect to the transient increase of the output voltage Vo can be improved.

Needless to say, the present invention is not limited to the above-described embodiment, and various improvements and modifications can be made without departing from the spirit of the present invention.
For example, the selection circuit 12 may directly input the output voltage Vo instead of the error voltage Vea. Further, when the switch SW1 is connected to the timing circuit 17 simultaneously with the high level transition of the control signal CMP1, the timing circuit 17 can be set to transition from the low level to the high level. Thereby, the pMOS transistor Q1 can be turned on simultaneously with switching.

The inductor L is an example of an inductance element, the reference voltage Vfb is an example of a feedback voltage, the error voltage Vea is an example of a difference voltage, the error amplifier 11 is an example of an amplifier, the IV converter 14 is an example of a detector, and the selection circuit 12 is a differentiation circuit. The switch SW1 is an example of a first selection circuit, the clock signal CK is an example of a trigger signal, the AND circuit 18 is an example of a mask circuit, and the switch SW2 is an example of a second selection circuit.
Further, an error amplifier 11 as an example of an amplifier, an IV converter 14 as an example of a detector, a selection circuit 12 as an example of a differentiation circuit, an oscillation circuit 16 as an example of an oscillation circuit, and a timing circuit as an example of a timing circuit. 17 and a circuit including at least the switch SW1 as an example of the first selection circuit is an example of a power supply control circuit. Further, an example of a power supply control circuit including an AND circuit 18 which is an example of a mask circuit will be disclosed.

DESCRIPTION OF SYMBOLS 1 Switching power supply 11 Error amplifier 12 Selection circuit 13 Phase compensation circuit
14 IV converter 15 Comparator 16 Oscillator circuit 17 Clock circuit 18 AND circuit 19 D-FF circuit 100 Electronic device 200 Battery 300 Load circuit Q1, Q2 Transistor L Inductor Co Capacitor SW1 Switch

Claims (7)

An amplifier that outputs an amplified signal based on a difference voltage between a feedback voltage corresponding to a voltage output from one end of the inductance element and a reference voltage;
A signal generation circuit that outputs a first control signal based on the amplified signal;
A current-voltage conversion circuit that detects a current flowing in a transistor connected to the other end of the inductance element and converts the detected current into a voltage;
A comparison circuit for comparing the output signal of the current-voltage conversion circuit with the amplified signal and outputting a second control signal;
A flip-flop circuit that outputs a third control signal that turns on the transistor in response to a rising transition of a clock signal and turns off the transistor based on the second control signal;
An oscillation circuit for outputting a first clock signal having a fixed period;
From the period from the rising transition of the third control signal to the rising transition of the first clock signal in the operation of turning on the transistor at the fixed period by the first clock signal, from the rising transition of the third control signal A timing circuit that outputs a second clock signal having a rising transition that rises at a short time when the elapsed time of the third control signal rises and rises in a fixed predetermined period from the rising transition of the third control signal;
A selection circuit that selects either the first clock signal or the second clock signal based on the first control signal and outputs the selected clock signal to the flip-flop circuit as the clock signal;
Have
The signal generation circuit causes the selection circuit to select the second clock signal as the clock signal when a first voltage value obtained by differentiating the voltage of the amplified signal according to a predetermined time constant is higher than a first specified value. A power supply control circuit that outputs the first control signal. The comparison circuit outputs the second control signal that falls when the voltage value of the output signal of the current-voltage conversion circuit becomes higher than the voltage value of the amplified signal,
The power supply control circuit according to claim 1, wherein the flip-flop circuit turns off the transistor in response to a falling transition of the second control signal.   And a mask circuit for fixing the output of the clock signal to the flip-flop circuit at a low level when the first voltage value is lower than a second specified value which is a value lower than the first specified value. The power supply control circuit according to claim 1 or 2. The amplifier is
A phase compensation circuit for compensating the phase of the amplified signal;
In the phase compensation circuit, when the first voltage value is higher than the first specified value or lower than the second specified value, the first voltage value is not more than the first specified value and not less than the second specified value. The power supply control circuit according to claim 3 , wherein the phase of the amplified signal is compensated in a frequency band higher than a case frequency band. The current-voltage conversion circuit is
When the first voltage value is higher than the first specified value, the current-voltage conversion coefficient is lower than the first current-voltage conversion coefficient when the first voltage value is equal to or lower than the first specified value and equal to or higher than the second specified value. 5. The power supply control circuit according to claim 3 , wherein when the first voltage value is lower than the second specified value, the current-voltage conversion coefficient is higher than the first current-voltage conversion coefficient. 6. A transistor having a source terminal connected to the power supply voltage line and a drain terminal connected to one end of the inductance element;
An amplifier that outputs an amplified signal based on a voltage difference between a feedback voltage corresponding to a voltage output from the other end of the inductance element and a reference voltage;
A signal generation circuit that outputs a first control signal based on the amplified signal;
A current-voltage conversion circuit that detects a current flowing from the power supply voltage line to the source terminal of the transistor and converts the detected current into a voltage;
A comparison circuit for comparing the output signal of the current-voltage conversion circuit with the amplified signal and outputting a second control signal;
A flip-flop circuit that outputs a third control signal that turns on the transistor in response to a rising transition of a clock signal and turns off the transistor based on the second control signal;
An oscillation circuit for outputting a first clock signal having a fixed period;
From the period from the rising transition of the third control signal to the rising transition of the first clock signal in the operation of turning on the transistor at the fixed period by the first clock signal, from the rising transition of the third control signal A timing circuit that outputs a second clock signal having a rising transition that rises at a short time when the elapsed time of the third control signal rises and rises in a fixed predetermined period from the rising transition of the third control signal;
A selection circuit that selects either the first clock signal or the second clock signal based on the first control signal and outputs the selected clock signal to the flip-flop circuit as the clock signal;
Have
The signal generation circuit causes the selection circuit to select the second clock signal as the clock signal when a first voltage value obtained by differentiating the voltage of the amplified signal according to a predetermined time constant is higher than a first specified value. An electronic apparatus that outputs the first control signal. Outputting an amplified signal based on a difference voltage between a feedback voltage corresponding to a voltage output from one end of the inductance element and a reference voltage;
Outputting a first control signal based on the amplified signal;
Detecting a current flowing in a transistor connected to the other end of the inductance element, and converting the detected current into a voltage;
Comparing the amplified signal with a signal obtained by converting the detected current into a voltage, and outputting a second control signal;
Outputting a third control signal that turns on the transistor in response to a rising transition of a clock signal and turns off the transistor based on the second control signal;
Outputting a first clock signal having a fixed period;
From the period from the rising transition of the third control signal to the rising transition of the first clock signal in the operation of turning on the transistor at the fixed period by the first clock signal, from the rising transition of the third control signal Outputting a second clock signal having a rising transition that rises when the elapsed period of time is short and rises in a fixed predetermined period from the rising transition of the third control signal;
When the first voltage value obtained by differentiating the voltage of the amplified signal according to a predetermined time constant based on the first control signal is equal to or less than a first specified value, the first clock signal is output as the clock signal. And a step of outputting the second clock signal as the clock signal when the first voltage value is higher than the first prescribed value.

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