JP5872132B2 - Inverter control circuit, grid-connected inverter system equipped with this inverter control circuit - Google Patents

Description

  The present invention relates to an inverter control circuit for controlling a three-phase inverter circuit with a PWM signal, a grid-connected inverter system provided with the inverter control circuit, a program for realizing the inverter control circuit, and a recording medium recording the program About.

  Conventionally, a grid-connected inverter system has been developed in which DC power generated by a solar cell or the like is converted into AC power and supplied to a three-phase power system. In a grid interconnection inverter system, a full bridge type three-phase inverter circuit is generally used. The full-bridge three-phase inverter circuit connects three switching elements connected in series (hereinafter referred to as “arms”) in parallel, and from the connection point between the switching elements of each arm, the U phase, It includes a bridge circuit from which three outputs corresponding to the V phase and W phase are extracted. Then, phase voltage signals (sine wave voltage signals whose phases are shifted from each other by 2π / 3) are converted into PWM signals, and each arm of the three-phase inverter circuit is converted using each PWM signal. By controlling the on / off operation of the switching element, the AC voltage signal output from the three-phase inverter circuit to each of the U-phase, V-phase, and W-phase is controlled.

  FIG. 17 is a block diagram for explaining an example of a grid-connected inverter system provided with a conventional inverter control circuit.

  In the figure, the inverter circuit 2 in the inverter system A ′ is constituted by a full bridge type three-phase inverter circuit. A DC voltage input from the DC power supply 1 is applied to each arm of the bridge circuit in the inverter circuit 2, while a total of six switching elements provided for each arm are supplied from the inverter control circuit 6 ′. Six input PWM signals are input, and the ON / OFF operation of each switching element is controlled by the PWM signal to correspond to each phase from the inverter circuit 2 to the U phase, V phase, and W phase. The pulsed AC voltage signal is output.

  The signal lines input from the inverter control circuit 6 ′ to the inverter circuit 2 are shaded with six lines, and the number of the hatched lines indicates the number of the signal lines. Accordingly, FIG. 17 shows that six PWM signals corresponding to the six switching elements are input to the inverter circuit 2 from the inverter control circuit 6 ′.

  High frequency components including switching noise are removed from the three pulsed AC voltage signals output from the inverter circuit 2 by the filter circuit 3, respectively, and converted into a sinusoidal AC voltage signal. Then, three sinusoidal AC voltage signals (AC voltage signals corresponding to the U-phase, V-phase, and W-phase phases) are adjusted in amplitude by the transformer circuit 4 and output to the corresponding phase of the system 5. In the inverter system A ′, the three phase voltage signals output from the transformer circuit 4 to the system 5 must be linked to the AC voltage signals of the corresponding phases of the system 5. Therefore, the inverter control circuit 6 ′ basically generates a phase voltage control signal for each phase that is an output control target based on the phase voltage signal for each phase of the system 5, and as shown in FIG. The voltage control signal is compared with a predetermined carrier signal (triangular wave signal) to generate a PWM signal.

  In FIG. 18, when the phase of the U phase is used as a reference, the PWM signal PSu for the switching element of the arm corresponding to the U phase of the inverter circuit 2 by comparing the U phase voltage control signal Su and the carrier signal Sc. The principle of generating is shown. Since two switching elements are connected in series to the arm corresponding to the U phase of the inverter circuit 2, the PWM signal PSu shown in the figure becomes a PWM signal for one switching element, and the level of the PWM signal PSu is inverted. The PWM signal becomes a PWM signal for the other switching element.

  In addition, the phase voltage control signal of the V phase is advanced by 2π / 3 from the phase voltage control signal Su of the U phase, and the phase voltage control signal of the W phase is 4π / phase of the phase voltage control signal Su of the U phase. If it is advanced by 3, the pattern waveform of the PWM signal PSv for the switching element of the arm corresponding to the V phase is obtained by advancing the phase of the PWM signal PSu by 2π / 3, and the switching of the arm corresponding to the W phase is performed. The pattern waveform of the PWM signal PSw for the element is obtained by advancing the phase of the PWM signal PSu by 4π / 3.

  FIG. 18 shows the principle of generating a PWM signal by the so-called triangular wave comparison method. The level range (amplitude peak-to-peak value) Dc of the carrier signal Sc is changed to the level range (amplitude peak-to-peak value) of the phase voltage control signal Su. ) The pulse signal duty ratio is changed to a PWM signal PSu changed according to the positive / negative amplitude value of the phase voltage control signal Su by comparing with the level of the carrier signal Sc and the phase voltage control signal Su. It is a method to do.

  As is well known, in the PWM signal for the bridge type inverter circuit, it is necessary to provide a dead time so that the pair of switching elements of each arm are not turned on at the same time (so that each arm is not short-circuited). It is necessary to provide a margin. For this reason, a range Dum that can be modulated is provided in the level range Dc of the carrier signal Sc, and the phase voltage control signal Su must be changed within the modifiable range Dum.

  When the third harmonic is superimposed on the phase voltage control signal, as shown in FIG. 19, the peak-to-peak value Pu0 of the phase voltage control signal is smaller than the case where the third harmonic is not superimposed (Pu) (in FIG. 19). The phase voltage control signal in which the waveform Xu does not superimpose the third harmonic, and the phase voltage control signal in which the waveform Xu0 superimposes the third harmonic). When the phase voltage signal of each phase of U phase, V phase, and W phase is balanced, even if the third harmonic is included in each phase voltage signal, the third harmonic is U-V, V-W, and W. It is not included in the line voltage signal (see waveform Xuv in FIG. 19) between the lines of −U, and is not output to the system 5. Therefore, in the inverter control circuit 6 ', the voltage utilization factor of the carrier signal Sc in the PWM signal generation by the triangular wave comparison method is increased by using the phase voltage control signal on which the third harmonic is superimposed as the output control target of each phase. Yes.

  In FIG. 17, the inverter control circuit 6 ′ includes a command value signal generation circuit 61 ′ and a PWM signal generation circuit 62 ′. The command value signal generation circuit 61 ′ superimposes the above-described third-order harmonics of each phase. The phase voltage control signal is generated as an output control target signal (hereinafter referred to as “command value signal”), and the PWM signal generation circuit 62 ′ is configured to output each phase input from the command value signal generation circuit 61 ′. This is a circuit that generates six PWM signals by the triangular wave comparison method using the command value signals Xu0, Xv0, and Xw0.

  The phase voltage control signal generation circuit 611 ′ in the command value signal generation circuit 61 ′ is a circuit that generates the above-described phase voltage control signal for each phase, and the third harmonic superimposing circuit 612 ′ is the phase voltage control signal. This is a circuit that generates command value signals Xu0, Xv0, Xw0 by superimposing the third harmonics of the phase voltage control signals Xu, Xv, Xw of each phase output from the generation circuit 611 ′. Note that the phase voltage control signal generation circuit 611 ′ uses the output voltage (DC) of the DC power source 1 detected by the DC voltage sensor 7 in order to set the output control target to the actual phase voltage signal of each phase of the system 5. The phase voltage control of each phase using the phase current (AC) flowing in each phase of the system 5 detected by the current sensor 8 and the line voltage (AC) of the system 5 detected by the line voltage sensor 9. Signals Xu, Xv, and Xw are generated.

  In the grid-connected inverter system, the switching element of the inverter circuit 2 is turned on / off to convert DC power into AC power, so the power consumption for the on / off operation of the switching element is a loss of power conversion (generally “ This is called “switching loss”. For this reason, conventionally, in order to increase the power conversion efficiency in the inverter circuit 2, for example, it has been proposed to reduce the switching loss by reducing the frequency of the carrier signal in the PWM signal generation circuit 62 ′ or switching the frequency. Has been.

JP 2007-228745 A

  As shown in FIG. 18, the conventional method for generating a PWM signal using a triangular wave comparison method changes the command value signals Xu0, Xv0, and Xw0 within the modifiable range Dum of the level range Dc of the carrier signal Sc. Therefore, the PWM signal always has a pulse in each cycle. In particular, when third-order harmonics are superimposed on the phase voltage control signals Xu, Xv, Xw as the command value signals Xu0, Xv0, Xw0, the lines U-V, V-W and W-U output to the system 5 In order to prevent the third-order harmonics from being included in the line voltage signal between them, margins are provided at both ends of the level range Dc of the carrier signal Sc, and the command value signals Xu0, Xv0, Xw0 at the center of the level range Dc. Therefore, each period of the PWM signal always includes a pulse.

  Therefore, conventionally, by reducing the frequency of the carrier signal, the period of the PWM signal is lengthened, and the switching loss is reduced based on the idea of reducing the number of pulses (switching frequency of the switching element) within a certain period. Yes.

  However, if the frequency of the carrier signal is reduced in all periods, PWM modulation is not appropriately performed in a period in which the amount of change in the output current value of the inverter circuit 2 is large, and there is a disadvantage in that the stability of the output current value decreases. . In addition, when the frequency of the carrier signal is switched in a specific period, the frequency of the PWM signal changes in accordance with the switching, and the frequency band of the switching noise to be removed fluctuates. Inconveniently, it is necessary to design the circuit so as to be able to remove switching noise in the entire range of the changing frequency band.

  The present invention has been conceived under the circumstances described above, and provides a period in which no pulse is periodically generated in the PWM signal of each phase, thereby periodically stopping the switching operation of the switching element. An object of the present invention is to provide an inverter control circuit that can reduce switching loss.

  In order to solve the above problems, the present invention takes the following technical means.

The inverter control circuit provided by the first aspect of the present invention controls the driving of a plurality of switching means in the three-phase inverter circuit by a PWM signal, and supplies the power to the power system. 1 cycle waveform becomes zero in the 1/3 cycle period, and in the following 1/3 cycle period, the waveform becomes a sine wave waveform in the interval from 0 to 2π / 3, A first command value signal in which the phase of the sine wave is a waveform in the interval of π / 3 to π in the remaining 1/3 period, and the phase is 2π / 3 with respect to the first command value signal Command value signal generating means for generating a second command value signal that has advanced and a third command value signal that is delayed by 2π / 3 in phase with respect to the first command value signal; PWM signal generating means for generating PWM signal based on The command value signal generating means includes a signal that detects a three-phase current output from the three-phase inverter circuit, a signal that detects a DC voltage input to the three-phase inverter circuit, and the power A phase voltage control signal generating means for generating three phase voltage control signals based on a signal for detecting a line voltage of each transmission of the system; and a line voltage control which is a differential signal of the three phase voltage control signals. Control signal converting means for generating a signal, signal generating means for generating the first to third command value signals by switching between the line voltage control signal and a zero signal whose value is always zero. It is characterized by having.

In a preferred embodiment of the present invention, the signal generating means converts the command value signal of each phase from the phase voltage control signal of the phase to the phase voltage control signal of which the phase order is one order before the phase and the phase. the phase voltage control signal after the one from the two line voltage control signal obtained by subtracting respectively the zero signal and of generating a combined signal to a maximum value of these signals.

  In a preferred embodiment of the present invention, the signal generating means sets the command value signal of each phase to a period of 1/3 period as zero, and a period of 1/3 period as a phase voltage control signal of the phase. The line voltage control signal obtained by subtracting the phase voltage control signal whose phase sequence is one previous from the phase is obtained, and the phase sequence from the phase voltage control signal of the phase is changed to the phase sequence from the phase. It is generated as a line voltage control signal obtained by subtracting the next phase voltage control signal.

The inverter control circuit provided by the second aspect of the present invention controls the driving of a plurality of switching means in the three-phase inverter circuit by a PWM signal, and supplies the power to the power system. 1 cycle waveform becomes zero in the 1/3 cycle period, and in the following 1/3 cycle period, the waveform becomes a sine wave waveform in the interval from 0 to 2π / 3, A first command value signal in which the phase of the sine wave is a waveform in the interval of π / 3 to π in the remaining 1/3 period, and the phase is 2π / 3 with respect to the first command value signal Command value signal generating means for generating a second command value signal that has advanced and a third command value signal that is delayed by 2π / 3 in phase with respect to the first command value signal; PWM signal generating means for generating PWM signal based on And the command value signal generating means detects a three-phase current output from the three-phase inverter circuit, detects a DC voltage input to the three-phase inverter circuit, and A phase voltage control signal generating means for generating three phase voltage control signals based on a signal for detecting a line voltage of each transmission of the power system; and each of the three-phase inverter circuits from the three phase voltage control signals Signal generating means for generating the first to third command value signals for the phase, and the signal generating means is configured to output the first command signal during a period in which the first command value signal is zero. The first phase voltage control signal is subtracted from the first phase voltage control signal of the phase corresponding to the value signal to obtain the first command value signal, and the second of the phase corresponding to the second command value signal The first phase voltage control signal from the phase voltage control signal. The second command value signal is subtracted to obtain the third command value signal by subtracting the first phase voltage control signal from the third phase voltage control signal of the phase corresponding to the third command value signal. In the period of 1/3 period following the zero period, the second phase voltage is obtained by subtracting the third phase voltage control signal from the first phase voltage control signal to obtain the first command value signal. The third phase voltage control signal is subtracted from the control signal to obtain the second command value signal, and the third phase voltage control signal is subtracted from the third phase voltage control signal to obtain the third command value signal. In the remaining period of 1/3 cycle, the second phase voltage control signal is subtracted from the first phase voltage control signal to obtain the first command value signal, and the second phase voltage control signal Subtracting the second phase voltage control signal from the second phase voltage control signal. And a command value signal, characterized in that said third said from the phase voltage control signal by subtracting the second phase voltage control signal third command value signal.

In a preferred embodiment of the present invention, the PWM signal generating means adjusts the three command value signals to a predetermined carrier signal, and matches the minimum value of each command value signal to the minimum value of the carrier signal. The PWM signal is generated by comparison.

The grid interconnection inverter system provided by the third aspect of the present invention includes the inverter control circuit provided by the first or second aspect of the present invention.

According to a fourth aspect of the present invention, there is provided a program for controlling the driving of a plurality of switching means in a three-phase inverter circuit by a PWM signal to supply power to the power system. A program for causing a computer to function as an inverter control circuit for controlling an output, wherein a waveform of one cycle becomes zero in a period of 1/3 period, and a phase is changed from 0 to 2π in a period of 1/3 period. And a first command value signal in which the phase of the sine wave becomes a waveform in the interval from π / 3 to π in the remaining 1/3 period, and the first command value signal. A command for generating a second command value signal whose phase is advanced by 2π / 3 with respect to the value signal and a third command value signal having a phase delayed by 2π / 3 with respect to the first command value signal Value signal generation means and previous A PWM signal generating means for generating a PWM signal based on the command value signal, the command value signal generating means detecting a three-phase current output from the three-phase inverter circuit ; Phase voltage control signal generation that generates three phase voltage control signals based on a signal that detects a DC voltage input to the three-phase inverter circuit and a signal that detects a line voltage of each transmission of the power system Switching means, a control signal converting means for generating a line voltage control signal which is a difference signal of the three phase voltage control signals, the line voltage control signal, and a zero signal whose value is always zero. Signal generating means for generating the first to third command value signals.

The recording medium provided by the fifth aspect of the present invention is a computer-readable recording medium on which the program provided by the fourth aspect of the present invention is recorded.

  According to the present invention, since the command value signal is zero for a period of one third of the cycle, the PWM signal generated based on the command value signal is kept at a low level during synchronization. Therefore, the switching means of the three-phase inverter circuit does not perform switching during the period. Thereby, the frequency | count of switching can be reduced and the power conversion efficiency of the said three-phase inverter circuit can be improved.

  Other features and advantages of the present invention will become more apparent from the detailed description given below with reference to the accompanying drawings.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings.

  First, the basic concept of the present invention for reducing the switching loss of a three-phase inverter circuit will be described.

  In the conventional inverter system A ′ shown in FIG. 17, the command value signal Xu 0, so that the line voltage signals between the lines UV, VW and WU output to the system 5 are balanced. Xv0 and Xw0 are set. Specifically, phase voltage signals Vu, Vv, and Vw to be output to the U-phase, V-phase, and W-phase of the system 5 are Vu = A · sin (ωt) and Vv = A · sin (ωt + 2π / 3) When Vw = A · sin (ωt + 4π / 3), signals having the same waveform as the phase voltage signal obtained by superimposing the third harmonic on the phase voltage signals Vu, Vv, Vw are command value signals Xu0, Xv0. , Xw0 is set. Then, the command value signals Xu0, Xv0, Xw0 are compared with a triangular carrier signal to generate a PWM signal.

  As described above, in the PWM signal generation circuit 62 ′ of the inverter system A ′, the levels of the command value signals Xu0, Xv0, and Xw0 are compared with the center of the level range of the triangular carrier signal to compare the levels of both signals. Therefore, a pulse always occurs in each period of the PWM signal. Even if the level values of the command value signals Xu0, Xv0, and Xw0 are matched to the minimum value of the level range of the triangular carrier signal and the levels of both signals are compared, the command value signals Xu0, Xv0, and Xw0 are sine. Since it is a wave signal, there is no period without a pulse in the PWM signal.

In the present invention, the command value signal of each phase is not a signal that changes symmetrically in the positive and negative directions with reference to 0 [v] like a sine wave signal,
(1) A line voltage signal between the lines U-V, V-W and W-U output to the system 5 becomes a balanced signal. (2) Asymmetry that changes only in the positive direction with reference to 0 [v]. And a signal satisfying the condition that a period of 0 [v] is included in a part of each cycle, and the minimum value (0 [v]) of the level range of the command value signal is set to a triangular wave The PWM signal of each phase is generated by comparing the levels of both signals in accordance with the minimum value of the level range of the carrier signal.

  According to the above method, since no pulse is generated in the PWM signal during the period of 0 [v] of the command value signals Xu0, Xv0, Xw0, the on / off operation of the switching element in the three-phase inverter circuit is stopped during that period. Can be made. Therefore, since the switching element in the three-phase inverter circuit periodically stops the on / off operation, the switching loss can be reduced accordingly.

  Next, signals that satisfy the above conditions (1) and (2) will be described.

When the phase voltage signals Vu, Vv, and Vw are Vu = A · sin (ωt), Vv = A · sin (ωt + 2π / 3), and Vw = A · sin (ωt + 4π / 3), respectively, the line voltage signal Vuv, Vvw, Vwu are Vuv = Vu−Vv = √ (3) · A · sin (ωt−π / 6), Vvw = Vv−Vw = √ (3) · A · sin (ωt + 3π / 6), V wu = Vw−Vu = √ (3) · A · sin (ωt + 7π / 6). A vector diagram showing the relationship between the phase voltage signals Vu, Vv, Vw and the line voltage signals Vuv, Vvw, Vwu is as shown in FIG.

This figure shows the state when the X axis is the phase reference (θ = 0 °) and the vector Pu corresponding to the U-phase phase voltage signal Vu coincides with the X axis. The vectors Pu, Pv, and Pw are vectors corresponding to the phase voltage signals Vu, Vv, and Vw, and the vectors Puv, Pvw, and Pwu are vectors corresponding to the line voltage signals Vuv, Vvw, and Vwu, respectively. The vectors Pvu, Pwv, and Puw are obtained by reversing the directions of the vectors Puv, Pvw, and Pwu, respectively. Accordingly, the line voltage signals Vvu, Vwv, and Vuw corresponding to the vectors Pvu, Pwv, and Puw are obtained by shifting the phase of the line voltage signals Vuv, Vvw, and Vwu by π, and Vvu = −Vuv = √ (3 ) · A · sin (ωt + 5π / 6), Vwv = −Vvw = √ (3) · A · sin (ωt + 9π / 6), Vuw = −Vwu = √ (3) · A · sin (ωt + π / 6) .

  The condition (1) is that the vectors Pu, Pv, and Pw maintain a phase difference of 2π / 3 in FIG. 1 and rotate at an angular velocity ω counterclockwise around the neutral point N. It corresponds to. Generally, since the neutral point N is set to a reference voltage of 0 [v], the U-phase, V-phase, and W-phase voltage signals Vu, Vv, Vw are on the Y axis of the vectors Pu, Pv, Pw. As described above, sine wave signals whose phases are shifted from each other by 2π / 3 are obtained.

  Examining the above condition (2), as a method of changing the phase voltage signals Vu, Vv, Vw only in the positive direction based on 0 [v], the maximum of the circle C around which the tips of the vectors Pu, Pv, Pw circulate is obtained. A method is conceivable in which the lower point d3 (the position of −A on the Y axis) is set to a reference voltage of 0 [v]. However, in this method, the phase voltage signals Vu, Vv, and Vw become 0 [v] only at the moment when the tips of the vectors Pu, Pv, and Pw pass the point d3. The phase voltage signals Vu, Vv, Vw cannot be periodically held at 0 [v] for a certain period only by changing the position of.

  Therefore, in order to hold the phase voltage signals Vu, Vv, and Vw periodically at 0 [v] for a certain period, a partial area on the circle C is set as a reference area R of 0 [v], and the vectors Pu, Pv , Pw must maintain the phase voltage signals Vu, Vv, Vw at 0 [v] during the period in which the reference region R is added.

  Since the phase voltage signals Vu, Vv, and Vw are changed only in the positive direction, the reference region R of 0 [v] is one of the three vectors Pu, Pv, and Pw in FIG. When passing through R, the other two vectors must be set so as to pass above the reference region R in the Y direction. Further, at the moment when a vector passing through the reference region R passes through the reference region R, another vector enters the reference region R so that any one of the three vectors Pu, Pv, Pw always moves in the reference region R. Must be.

  Therefore, when a reference line L of 0 [v] parallel to the X axis is provided so as to cross the circle C with respect to the circle C, and the position of the reference line L satisfying the above condition is obtained, as shown in FIG. , The position passes through the points d1 and d2. Points d1 and d2 correspond to the tip positions of the vector Pv and the vector Pw when the circle C is rotated counterclockwise by π / 2 in FIG. In terms of the rotational position of the vector Pu, the point d1 is a position rotated to θ = 7π / 6, and the point d2 is a position rotated to θ = 11π / 6. Therefore, in the present invention, the reference area R of 0 [v] is set to the area from the points d1 to d2 of the circle C.

As shown in FIG. 1, for example, when the vector Pu rotates around the neutral point N as the center of rotation, the vector Pv always has a position of the opening angle + 2π / 3 with respect to the vector Pu. The vector Pw always moves so as to maintain the position of the opening angle −2π / 3 with respect to the vector Pu, that is, the tips of the vectors Pu, Pv, and Pw are always equilateral triangles T (FIG. 2) .

  Since the rotation of the vector Pu with respect to the neutral point N is relative, when the neutral point N is rotated around the tip of the vector Pu, the positional relationship of the vectors Pv and Pw with respect to the vector Pu becomes the vectors Pu and Pv. As long as the positional relationship in which the regular triangle T is formed by the tips of Pw is maintained, the condition (1) is satisfied. The conventional rotation of the vectors Pu, Pv, Pw can be understood as the rotation of the tip positions of the vectors Pu, Pv, Pw when the equilateral triangle T is rotated at the speed of ωt around the center of gravity (neutral point N). The rotation of the vectors Pu, Pv, and Pw according to the present invention is as shown in FIG. 2 at the tip positions of the vectors Pu, Pv, and Pw when the regular triangle T is rotated on the reference line L at the speed of ωt. It can be understood as a rotation.

  FIG. 2 shows the rotational positions of the vectors Pu, Pv, and Pw when the equilateral triangle T is rotated once from the position of θ = −π / 6, and (a) to (d) are θ = −π, respectively. / 6, θ = 3π / 6, θ = 7π / 6, θ = 11π / 6. Note that the position of θ = 0 is a position where the vector Pu coincides with the X axis, as shown in FIG.

  As shown in the figure, between (a) and (b), the regular triangle T rotates around the tip w of the vector Pw, and between (b) and (c), the regular triangle T is the vector Pv. The regular triangle T rotates around the tip u of the vector Pu between (c) and (d). In FIG. 2, the regular triangle T does not rotate smoothly so as to roll the circle C, but the regular triangle T is always held, and the three vectors Pu, Pv, and Pw are always in the region where the reference voltage is 0 [v] or more. The above conditions (1) and (2) are satisfied. Accordingly, the waveform of the phase voltage signal (hereinafter referred to as “phase voltage signals Vu1, Vv1, Vw1”) obtained by rotating the vectors Pu, Pv, Pw as shown in FIG. 2 is set as the command value signal. Also, line voltage signals Vuv, Vvw, Vwu balanced in the system 5 can be output.

  Next, the waveforms of the U-phase, V-phase, and W-phase voltage signals Vu1, Vv1, and Vw1 will be described with reference to FIGS.

  The waveforms of the phase voltage signals of the U phase, V phase, and W phase are determined by the positions of the tips of the vectors Pu, Pv, and Pw, respectively. In the case of FIG. 1, the neutral point N is fixed to the reference voltage 0 [v], and the tips of the vectors Pu, Pv, and Pw rotate about the neutral point N, respectively. The waveforms of the phase voltage signals Vu, Vv, Vw of each phase are calculated by the equation of A · sin (θ) based on the magnitude A and the phase θ of the vectors Pu, Pv, Pw, respectively.

  In the case of FIG. 2, when the reference voltage 0 [v] is set to the reference line L and the vertex of the regular triangle T (the tip of the vector Pu, Pv, Pw) is in contact with the reference line L, the regular triangle is centered on that vertex. Since T rotates, the position of the reference voltage 0 [v] changes every time the regular triangle T rotates 2π / 3. Therefore, when obtaining the movement trajectory of the tip of the vectors Pu, Pv, Pw, the position of the reference voltage 0 [v] is changed every time the equilateral triangle T rotates 2π / 3, and the changed reference voltage 0 [v] is obtained. It is necessary to obtain the movement trajectory for the position.

  For example, the waveform of the U-phase phase voltage signal Vu1 is determined by the position of the tip of the vector Pu with respect to the position of the reference voltage 0 [v]. According to FIG. 2, the period (a) to (b) ( In the period of θ from −π / 6 to 3π / 6), since the tip of the vector Pw is set to the reference voltage 0 [v], the waveform of the U-phase phase voltage signal Vu1 goes from the w point to the u point. A waveform at the tip of the vector E1 when the vector E1 is rotated from the position (a) to the position (b) (see the thick line B1 in FIG. 2). In the period from (b) to (c) (the period in which θ is 3π / 6 to 7π / 6), the leading end of the vector Pv is set to the reference voltage 0 [v]. Is a waveform at the tip of the vector E2 when the vector E2 from the v point to the u point is rotated from the position (b) to the position (c) (see the one-dot chain line B2 in FIG. 2). Further, during the period from (c) to (d) (the period in which θ is 7π / 6 to 11π / 6), the leading end of the vector Pu is set to the reference voltage 0 [v], and therefore the U-phase phase voltage signal Vu1. Is fixed at a reference voltage of 0 [v].

  FIG. 3 is obtained by rotating the vector diagram of FIG. 1 by −π / 6 to obtain the state of FIG. The waveform of the thick line B1 in FIG. 2 is a waveform obtained by rotating the vector E1 around 0 to 2π / 3 around the tip of the vector Pw. This waveform has the same phase (θ = The vector Puw having 0) is the same as the waveform when rotated from 0 to 2π / 3. That is, the waveform of the line voltage signal Vuw is the same as that at −π / 6 to 3π / 6. The waveform of the alternate long and short dash line B2 in FIG. 2 is a waveform obtained by rotating the vector E2 around π / 3 to π around the tip of the vector Pv. This waveform is counterclockwise to the vector diagram shown in FIG. In the state rotated by 2π / 3, the vector having the same phase (θ = π / 3) as the vector E2, that is, the vector Puv of θ = −π / 3 in FIG. It is the same as the waveform when rotating. That is, the waveform of the line voltage signal Vuv is the same as that at 3π / 6 to 7π / 6.

  Therefore, the waveform of one cycle of the U-phase phase voltage signal Vu1 is the line voltage signal Vuw (−π / 6 to 3π / 6), the line voltage signal Vuv (3π / 6 to 7π / 6), and 0 [v ] (7π / 6 to 11π / 6).

The waveforms of one cycle of the V-phase and W-phase voltage signals Vv1 and Vw1 can be obtained by the same method. Although the details are omitted, the waveform of one cycle of the V-phase phase voltage signal Vv1 is the line voltage signal Vvw at −π / 6 to 3π / 6, 0 [v], 7π at 3π / 6 to 7π / 6. In / 6 to 11π / 6, it is given as a composite wave of the line voltage signal Vvu. The waveform of one cycle of the W-phase phase voltage signal Vw1 is 0 [v] at -π / 6 to 3π / 6, and the line voltage signal Vwv at 7π / 6 to 7π / 6, 7π / 6 to 11π / 6 is given as a composite wave of the line voltage signal Vwu.

  To summarize the above, the waveforms of the phase voltage signals Vu1, Vv1, and Vw1 of the U-phase, V-phase, and W-phase are as shown in the table of FIG. 4, and the specific waveforms are as shown in FIG. Become. 5A shows the waveforms of the line voltage signals Vuv, Vvw and Vwu, and FIG. 5B shows the line voltage signals Vvu (= −Vuv), Vwv (= −Vvw) and Vuw (= −). Vwu), and (c) shows the waveforms of the phase voltage signals Vu1, Vv1, and Vw1.

  According to FIGS. 4 and 5, the vectors Pu, Pv, and Pw respectively corresponding to the U phase, the V phase, and the W phase are arranged counterclockwise in the order of U, V, and W phases as shown in FIG. In this case, the line voltage signals used for forming the waveform of the U-phase phase voltage signal Vu1 are the U-W line voltage signal Vuw and the U-V line voltage signal Vuv. These line voltage signals are obtained by subtracting the W-phase voltage signal Vw immediately before the U-phase and the V-phase voltage signal Vv immediately after the U-phase from the U-phase voltage signal Vu. It is a line voltage signal obtained in this way.

  The line voltage signals used for forming the waveform of the V phase voltage signal Vv1 are the VU line voltage signal Vvu and the VW line voltage signal Vvw. These line voltage signals are obtained by subtracting the U-phase voltage signal Vu immediately before the V-phase and the W-phase voltage signal Vw immediately after the V-phase from the V-phase voltage signal Vv, respectively. It is a line voltage signal obtained in this way. The line voltage signals used to form the waveform of the W-phase phase voltage signal Vw1 are the W-V line voltage signal Vwv and the W-U line voltage signal Vwu. These line voltage signals are obtained by subtracting the V-phase voltage signal Vv immediately preceding the W-phase and the U-phase voltage signal Vu immediately following the W-phase from the W-phase voltage signal Vw, respectively. It is a line voltage signal obtained in this way.

  That is, the line voltage signal used for forming the waveform of the phase voltage signal of each phase is the phase voltage signal immediately before the phase and the phase voltage immediately after the phase from the phase voltage signal of the phase. It can be said that two line voltage signals obtained by subtracting the voltage signals respectively.

  When the waveform of the phase voltage signals Vu1, Vv1, and Vw1 shown in FIG. 5C is set as the command value signal, for example, the waveform of the line voltage signal Vuv between U and V output to the system 5 is Vuv = It is obtained from Vu1−Vv1 by adding the waveform of the phase voltage signal Vu1 in FIG. 5C and the waveform obtained by inverting the phase voltage signal Vv1.

  In the period of 3π / 6 to 7π / 6, the phase voltage signal Vv1 is at the 0 level, so that the waveform of the line voltage signal Vuv is the same as the waveform of the phase voltage signal Vu1. That is, it becomes the same as the waveform of the line voltage signal Vuv. Further, during the period of 7π / 6 to 11π / 6, the phase voltage signal Vu1 is at the 0 level, so the waveform of the line voltage signal Vuv is the same as the waveform obtained by inverting the waveform of the phase voltage signal Vv1. That is, it is the same as the waveform obtained by inverting the waveform of the line voltage signal Vvu (the waveform of the line voltage signal Vuv). According to FIG. 1, since the line voltage signal Vuv is an orthogonal projection of the vector Puv onto the Y-axis, it is represented by √ (3) · A · sin (ωt−π / 6). In the period of 11π / 6, the waveform of the line voltage signal Vuv is √ (3) · A · sin (ωt−π / 6).

  On the other hand, in the period of −π / 6 to 3π / 6, the waveform of the line voltage signal Vuv is obtained by Vuw−Vvw. According to FIG. 1, since Vuw = √ (3) · A · sin (ωt + π / 6) and Vvw = √ (3) · A · sin (ωt + 3π / 6), the waveform of the line voltage signal Vuv is Vuw−Vvw = √ (3) · A · {sin (ωt + π / 6) −sin (ωt + 3π / 6)}. The portion of sin (ωt + π / 6) −sin (ωt + 3π / 6) is deformed as shown in the following equation (1) when ωt = θ.

  Therefore, the waveform of the line voltage signal Vuv is √ (3) · A · sin (ωt−π / 6) similarly to the period of 3π / 6 to 11π / 6 even in the period of −π / 6 to 7π / 6. , −π / 6 to 11π / 6, the waveform of the line voltage signal Vuv is given by √ (3) · A · sin (ωt−π / 6). The waveforms of the line voltage signals Vvw and Vwu are obtained in the same manner, and the vectors corresponding to the line voltage signals Vvw and Vwu are the vector Pvw and the vector Pwu, respectively. Therefore, the line voltage signal Vvw becomes √ (3) · A · sin (ωt + π / 2), and the line voltage signal Vwu becomes √ (3) · A · sin (ωt + 7π / 6).

  As described above, even if the waveform of the phase voltage signals Vu1, Vv1, Vw1 shown in FIG. 5C is set as the command value signal, the line voltage signals Vuv, Vvw, Vwu balanced in the system 5 are output. Can do.

Next, an inverter control circuit that generates the command value signal described above and outputs a PWM signal based on the command value signal to the inverter circuit 2 will be described.

FIG. 6 is a block diagram for explaining an example of a grid-connected inverter system including the first embodiment of the inverter control circuit according to the present invention.

  The grid-connected inverter system A1 includes a DC power source 1, an inverter circuit 2, a filter circuit 3, a transformer circuit 4, a commercial power system 5, an inverter control circuit 6, a DC voltage sensor 7, a current sensor 8, and a line voltage sensor 9. ing. The DC power source 1 is connected to the inverter circuit 2. The inverter circuit 2 is a three-phase inverter, and the inverter circuit 2, the filter circuit 3, the transformer circuit 4, and the commercial power system 5 are in this order by the output lines of the output voltages of the U phase, the V phase, and the W phase, Connected in series. An inverter control circuit 6 is connected to the inverter circuit 2. The grid interconnection inverter system A1 converts the DC power generated by the DC power source 1 into AC power by the inverter circuit 2 and supplies the AC power to the commercial power system 5.

  The DC power source 1 generates DC power and includes a solar cell that converts sunlight energy into electrical energy.

  The inverter circuit 2 is a full-bridge type three-phase inverter, and the DC power input from the DC power source 1 is converted into AC by turning on / off the switching element included based on the PWM signal input from the inverter control circuit 6. Convert to electricity.

  FIG. 7 is a diagram for explaining the inverter circuit 2.

  The inverter circuit 2 is obtained by bridge-connecting six switching elements Tr1 to Tr6. Feedback diodes D1, D2, D3, D4, D5, and D6 are connected in parallel to the switching elements Tr1, Tr2, Tr3, Tr4, Tr5, and Tr6, respectively. As the switching element, for example, a semiconductor switching element such as a bipolar transistor, a field effect transistor, or a thyristor is used, and FIG. 7 shows an example using a transistor.

  Switching element Tr1 and switching element Tr2 connected in series (hereinafter referred to as “first arm”), switching element Tr3 and switching element Tr4 connected in series (hereinafter referred to as “second arm”), switching element Tr5 and switching element A DC voltage Vdc output from the DC power source 1 is supplied to both ends of a series connection (hereinafter referred to as “third arm”) of the Tr 6 so that the connection points a, b, U-phase, V-phase, and W-phase phase voltage signals are output from c.

  The six switching elements Tr <b> 1 to Tr <b> 6 are each controlled to be turned on / off by a PWM signal output from the inverter control circuit 6. Specifically, the inverter control circuit 6 outputs three sets of PWM signals having different pulse widths, with two sets of PWM signals whose phases are inverted to each other as one set. Assuming that each set of PWM signals is (PS11, PS12), (PS21, PS22), (PS31, PS32), the PWM signals PS11, PS12 are respectively the control terminals of the switching elements Tr1 and Tr2 (in FIG. The PWM signals PS21 and PS22 are respectively input to the control terminals of the switching element Tr3 and the switching element Tr4, and the PWM signals PS31 and PS32 are respectively input to the control terminals of the switching element Tr5 and the switching element Tr6.

  The filter circuit 3 is a low-pass filter including a reactor and a capacitor. The filter circuit 3 removes switching noise included in the AC voltage output from the inverter circuit 2. The transformer circuit 4 boosts or steps down the AC voltage output from the filter circuit 3 to substantially the same level as the voltage of the commercial power system 5 (hereinafter referred to as “system voltage”).

  The DC voltage sensor 7 detects a DC voltage output from the DC power supply 1. The detected DC voltage signal is input to the inverter control circuit 6. The current sensor 8 detects a current of each phase output from the transformer circuit 4. The detected current signal is input to the inverter control circuit 6. The line voltage sensor 9 detects a line voltage signal of each phase of the commercial power system 5. The detected line voltage signal is input to the inverter control circuit 6.

  The inverter control circuit 6 generates a PWM signal for controlling the on / off operation of the switching element of the inverter circuit 2. The inverter control circuit 6 receives a DC voltage signal from the DC voltage sensor 7, a current signal from the current sensor 8, and a line voltage signal from the line voltage sensor 9, and outputs a PWM signal to the inverter circuit 2.

  The inverter control circuit 6 includes a command value signal generation circuit 61 and a PWM signal generation circuit 62. The command value signal generation circuit 61 generates the command value signal described above and outputs it to the PWM signal generation circuit 62. In the present embodiment, command value signals generated by the command value signal generation circuit 61 are Xu1, Xv1, and Xw1.

  The command value signal generation circuit 61 includes a phase voltage control signal generation circuit 611, a control signal conversion circuit 612, and a signal generation circuit 613.

  The phase voltage control signal generation circuit 611 has a DC voltage signal input from the DC voltage sensor 7, a current signal input from the current sensor 8, a line voltage signal input from the line voltage sensor 9, and a preset voltage signal. Based on the target DC voltage and the target reactive current, the phase voltage control signals Xu, Xv, Xw for controlling the phase voltage of each phase are generated and output to the control signal conversion circuit 612.

  The phase voltage control signal generation circuit 611 includes a phase detection circuit 611a, a PI control circuit 611b, a three-phase / two-phase conversion circuit 611c, a stationary coordinate conversion circuit 611d, a PI control circuit 611e, a rotational coordinate conversion circuit 611f, and a two-phase / three-phase. A phase conversion circuit 611g is provided.

  The phase detection circuit 611a detects the phase of the system voltage from the line voltage signal input from the line voltage sensor 9, and outputs it to the stationary coordinate conversion circuit 611d, the rotation coordinate conversion circuit 611f, and the signal generation circuit 613. The PI control circuit 611b performs PI control and outputs a correction value signal Xd of the difference between the DC voltage signal input from the DC voltage sensor 7 and the target DC voltage. The three-phase / two-phase conversion circuit 611c converts the three-phase current signal input from the current sensor 8 into a two-phase current signal and outputs it. The stationary coordinate conversion circuit 611d receives a two-phase current signal from the three-phase / two-phase conversion circuit 611c, and receives the phase of the system voltage from the phase detection circuit 611a. The stationary coordinate conversion circuit 611d converts the two-phase current signal into a phase difference component and an in-phase component with respect to the phase of the system voltage and outputs the converted signal. The so-called αβ conversion for converting three phases to two phases and the so-called dq conversion for converting rotating coordinates to stationary coordinates are well known, and therefore detailed description thereof will be omitted.

  The PI control circuit 611e performs PI control and outputs a correction value signal Xq of the difference between the reactive current signal that is a phase difference component output from the stationary coordinate conversion circuit 611d and the target reactive current. The rotation coordinate conversion circuit 611f receives the correction value signal Xd output from the PI control circuit 611b as an in-phase component, receives the correction value signal Xq output from the PI control circuit 611e as a phase difference component, and receives a system from the phase detection circuit 611a. Input voltage phase. The rotational coordinate conversion circuit 611f converts the correction value signal Xd and the correction value signal Xq into two-phase control signals Xα and Xβ and outputs them. The two-phase / three-phase conversion circuit 611g converts the control signals Xα and Xβ input from the rotational coordinate conversion circuit 611f into three-phase phase voltage control signals Xu, Xv, and Xw and outputs the converted signals. Since so-called inverse αβ transformation that transforms two phases into three phases and so-called inverse dq transformation that transforms stationary coordinates into rotational coordinates are also well known, detailed description thereof will be omitted.

  The configuration of the phase voltage control signal generation circuit 611 is not limited to this, and any configuration that generates the phase voltage control signals Xu, Xv, and Xw may be used. For example, a phase voltage control signal may be generated so as to control a two-phase current signal without performing a static coordinate conversion, or a three-phase current signal may be converted without converting a three-phase into a two-phase. The phase voltage control signal may be generated so that control is performed as it is.

  The control signal conversion circuit 612 converts the phase voltage control signals Xu, Xv, and Xw input from the phase voltage control signal generation circuit 611 into line voltage control signals Xuv, Xvw, and Xwu, and outputs them to the signal generation circuit 613. . The control signal conversion circuit 612 converts the control signal by generating the difference signal between Xu and Xv as Xuv, the difference signal between Xv and Xw as Xvw, and the difference signal between Xw and Xu as Xwu.

  It is not always necessary to generate the phase voltage control signal in order to generate the line voltage control signal. Instead of the phase voltage control signal generation circuit 611 and the control signal conversion circuit 612, a circuit that directly generates a line voltage control signal may be provided to directly generate the line voltage control signal.

  The signal generation circuit 613 receives command value signals Xu1, Xv1, Xvw from the line voltage control signals Xuv, Xvw, Xwu input from the control signal conversion circuit 612 and the signals Xvu, Xwv, Xuw obtained by inverting these polarities. Generate and output Xw1. The control signal conversion circuit 612 also generates and outputs line voltage control signals Xvu, Xwv, Xuw, and the signal generation circuit 613 inputs six line voltage control signals Xuv, Xvw, Xwu, Xvu, Xwv, Xuw. You may be made to do.

  The signal generation circuit 613 calculates Xu1, Xv1, and Xw1 using the following equation (2) according to the phase of the U-phase phase voltage signal of the system voltage input from the phase detection circuit 611a.

  FIG. 8 is a diagram for explaining the waveform of the command value signal Xu1 output from the signal generation circuit 613. The waveform Xu is the waveform of the phase voltage control signal Xu and matches the waveform of the phase voltage signal targeted for the U phase of the system voltage. The waveform Xuv indicates the waveform of the line voltage control signal Xuv, and the waveform Xuw indicates the waveform of the signal Xuw obtained by inverting the polarity of the line voltage control signal Xwu.

As shown in the figure, the command value signal Xu1 becomes a signal Xuw during a period of −π / 6 ≦ θ ≦ 3π / 6, where θ is the phase of the U-phase phase voltage signal of the system voltage, and 3π / 6 ≦ The period of θ ≦ 7π / 6 is the line voltage control signal Xuv, and the period of 7π / 6 ≦ θ ≦ 11π / 6 is zero. In other words, the waveform Xu1 shown in the figure is a waveform of the same waveform Vu1 shown in FIG. 5 (c). Similarly, the command value signal Xv1 becomes the line voltage control signal Xvw during the period of −π / 6 ≦ θ ≦ 3π / 6, and becomes zero during the period of 3π / 6 ≦ θ ≦ 7π / 6, and 7π / 6 ≦ θ. During the period of ≦ 11π / 6, the signal Xvu is obtained by inverting the polarity of the line voltage control signal Xuv. The command value signal Xw1 is zero during the period of −π / 6 ≦ θ ≦ 3π / 6, and becomes a signal Xwv obtained by inverting the polarity of the line voltage control signal Xvw during the period of 3π / 6 ≦ θ ≦ 7π / 6. , 7π / 6 ≦ θ ≦ 11π / 6 is the line voltage control signal Xwu.

  The two-phase / three-phase conversion circuit 611g calculates the phase voltage control signals Xu, Xv, Xw from the control signals Xα, Xβ using the following equation (3). In addition, the control signal conversion circuit 612 calculates line voltage control signals Xuv, Xvw, Xwu from the phase voltage control signals Xu, Xv, Xw using the following equation (4). The following formula (5) is calculated from the following formula (3) and the following formula (4).

  The following formula (6) is calculated from the formula (5) and the formula (2). Therefore, the two-phase / three-phase conversion circuit 611g, the control signal conversion circuit 612, and the signal generation circuit 613 are combined into one, and the command value signals Xu1, Xv1, Xw1 may be directly calculated and output.

  Returning to FIG. 6, the PWM signal generation circuit 62 receives each phase from the carrier signal generated therein and the command value signals Xu 1, Xv 1, Xw 1 of each phase input from the command value signal generation circuit 61. A PWM signal is generated and output to the inverter circuit 2.

  FIG. 9A is a diagram for explaining a method of generating a PWM signal from a command value signal and a carrier signal. In FIG. 5A, the command value signal is indicated by waveform F, the carrier signal is indicated by waveform C, and the PWM signal is indicated by waveform P. The PWM signal generation circuit 62 generates, as a PWM signal, a pulse signal that becomes high level when the command value signal is larger than the carrier signal and becomes low level when the command value signal is equal to or lower than the carrier signal. Accordingly, in FIG. 9A, the waveform P is at a high level during a period when the waveform F is greater than the waveform C, and the waveform P is at a low level during a period when the waveform F is equal to or less than the waveform C.

  In the present embodiment, the carrier signal is generated so as to change in a range of 0 level or more of the command value signal so that the minimum value of the command value signal matches the minimum value of the carrier signal.

  The U-phase, V-phase, and W-phase switching elements of the inverter circuit 2 perform on / off operations based on the U-phase, V-phase, and W-phase PWM signals, respectively. The PWM signal generation circuit 62 also generates a pulse signal obtained by inverting the U-phase, V-phase, and W-phase pulse signals, and outputs the pulse signal to the inverter circuit 2 as a reverse-phase PWM signal. The switching elements connected in series to the U-phase, V-phase, and W-phase switching elements of the inverter circuit 2 are respectively referred to as the U-phase, V-phase, and W-phase switching elements based on the reverse-phase PWM signals. On the other hand, it operates on and off.

  The PWM signal may be generated by a method other than the method based on the comparison between the command value signal and the carrier signal. For example, the pulse width can be calculated from the line voltage control signal using the PWM hold method, and the PWM signal can be generated based on the pulse width for the phase voltage converted from the pulse width for the calculated line voltage.

  Next, the operation of the inverter control circuit 6 will be described.

In the present embodiment, the command value signal generation circuit 61 outputs command value signals Xu1, Xv1, and Xw1 having waveforms shown in FIG. 5C, and the PWM signal generation circuit 62 generates a PWM signal based on the command value signal. Generated and output to the inverter circuit 2. The phase voltage signals Vu1, Vv1, and Vw1 output from the inverter circuit 2 have the waveforms shown in FIG. 5C. The line voltage signal that is a differential signal of the phase voltage signals Vu1, Vv1, and Vw1 is shown in FIG. Since the line voltage signals Vuv, Vvw, Vwu are balanced in the system 5 shown in FIG. Therefore, the AC power output from the inverter circuit 2, the switching noise is removed by the filter circuit 3, it is boosted by the transformer circuit 4 is supplied to the commercial power system 5.

  In the present embodiment, the command value signal has a period of one third of the cycle being zero. During this period, since the command value signal is in a state equal to or lower than the carrier signal, the PWM signal is kept at a low level. Therefore, the switching element of the inverter circuit 2 to which the PWM signal is input does not perform switching during the period. Thereby, the frequency | count of switching of the switching element of the inverter circuit 2 can be reduced, switching loss can be reduced, and the power conversion efficiency of the inverter circuit 2 can be improved. Further, since the frequency of the carrier signal is not changed, the filter circuit 3 may be designed as one that can remove the switching noise of the frequency.

  In the inverter control circuit 6 of the present embodiment, since the phase voltage control signal generation circuit 611 and the PWM signal generation circuit 62 are common to those of the conventional inverter control circuit 6 ′, the third harmonic superposition is performed in the conventional inverter control circuit 6 ′. This can be realized simply by replacing the circuit 612 ′ with the control signal conversion circuit 612 and the signal generation circuit 613.

  FIG. 9 (b) is for comparison with FIG. 9 (a), and a command value signal (a third harmonic is added to the phase voltage control signal) input to the PWM signal generation circuit 62 ′ of the conventional inverter control circuit 6 ′. A waveform F ′ of a waveform (see waveform Xu0 in FIG. 19), a waveform C of a carrier signal, and a waveform P ′ of a PWM signal are shown.

  In FIGS. 4A and 4B, an arrow L at the left end indicates the amplitude of the carrier signal C, and represents a settable range of the length of the high level period of the PWM signal. However, when the high level period is too long or too short, the accuracy of the length of the high level period cannot be maintained due to the dead time added when generating the PWM signal. Therefore, a margin is provided in order to make the range where the accuracy cannot be maintained an unusable range. The solid-line arrows M1 and M2 at the right end in FIGS. 4A and 4B represent a range for tolerance. As shown in FIG. 6A, in this embodiment, in order not to exceed the carrier signal during the period when the command value signal is zero, the tolerance when the high-level period is short (the region indicated by the arrow M2). Is not provided. Even if it does in this way, the precision deterioration by dead time will be a level which does not become a problem.

  The dotted arrows N at the right end in FIGS. 4A and 4B represent an available range that is a range obtained by excluding the range for tolerance from the settable range of the length of the high level period. That is, the length of the high level period of the PWM signal can be set within this range. As shown in the figure, the range of arrow N in (a) is wider than the range of arrow N in (b) by the range of arrow M2. Therefore, in this embodiment, the voltage utilization factor is improved over the conventional one.

  In addition, when the conventional inverter control circuit 6 ′ is used, all three phases of the inverter circuit 2 are switched. Therefore, the common potential obtained by adding the potentials of the three phases is the output voltage (hereinafter referred to as “DC voltage” However, in this embodiment, since the potential of one phase is always zero, the common potential varies only in the voltage range twice as large as the DC voltage. . Therefore, in the present embodiment, noise due to EMI generated in proportion to the common potential is smaller than that of the conventional one.

  Although the case where digital signal processing is performed has been described in the above embodiment, the present invention can also be applied to the case where analog signal processing is performed.

FIG. 10 is a block diagram for explaining an example of a grid-connected inverter system including the second embodiment of the inverter control circuit according to the present invention. In the figure, the same or similar elements as those in the first embodiment are denoted by the same reference numerals.

  In the grid-connected inverter system A2, the DC voltage sensor 7, the current sensor 8, and the line voltage sensor 9 are analog sensors, and the measured analog signal is input to the command value signal generation circuit 61 as it is. The command value signal generation circuit 61 includes a phase voltage control signal generation circuit 611 that is an analog processing device, a control signal conversion circuit 612, and a signal generation circuit 613, and the command value signals Xu2, Xv2, and Xw2 that are analog signals are received. Generated and output to the PWM signal generation circuit 62. The PWM signal generation circuit 62 generates a PWM signal based on the command value signals Xu2, Xv2, and Xw2, and outputs the PWM signal to the inverter circuit 2.

The signal generation circuit 613 uses the input line voltage control signals Xuv, Xvw, Xwu, the inverted signals Xvu, Xwv, Xuw, and the zero signal whose value is always zero to generate a command value signal Xu2, Xv2 and Xw2 are generated. For example, Xu2 is generated by inputting Xuv, Xuw, and a zero signal to the comparator and extracting the maximum signal. The generated command value signal Xu2 has the same waveform as the waveform Vu1 shown in FIG. Similarly, Xv2 is generated from Xvw, Xvu, and zero signal, and Xw2 is generated from Xwu, Xwv, and zero signal.

  Also in this embodiment, the same effect as the first embodiment can be obtained.

  The command value signals Xu2, Xv2, and Xw2 may be generated using the full-wave rectified signals Xuv ′, Xvw ′, and Xwu ′ of the line voltage control signals Xuv, Xvw, and Xwu.

  FIG. 11 is a diagram for explaining a method of generating command value signals Xu2, Xv2, and Xw2 using full-wave rectified signals Xuv ′, Xvw ′, and Xwu ′. FIG. 12 is a diagram for explaining the configuration of the signal generation circuit 613 for using this method.

  As shown in FIG. 12, the signal generation circuit 613 includes a full-wave rectification circuit 613a and a signal selection circuit 613b. The full-wave rectification circuit 613a performs full-wave rectification on the input line voltage control signals Xuv, Xvw, and Xwu, and outputs full-wave rectification signals Xuv ′, Xvw ′, and Xwu ′. In FIG. 11A, the broken line indicates the line voltage control signal Xuv, and the solid line indicates the full wave rectified signal Xuv ′ obtained by full wave rectifying the line voltage control signal Xuv. In FIG. 11B, the broken line indicates the line voltage control signal Xwu, and the solid line indicates the full wave rectified signal Xwu ′ obtained by full wave rectifying the line voltage control signal Xwu.

  The signal selection circuit 613b generates and outputs command value signals Xu2, Xv2, and Xw2 from the full-wave rectification signals Xuv ′, Xvw ′, and Xwu ′ input from the full-wave rectification circuit 613a. The signal selection circuit 613b outputs a command value signal by switching the signal to be output according to the phase of the system voltage. FIG. 11C shows the command value signal Xu2 output from the signal selection circuit 613b. Assuming that the phase of the U phase of the system voltage is the reference phase, the full-wave rectified signal Xwu ′ is output when the reference phase is between −π / 6 and π / 2, and when the reference phase is between π / 2 and 7π / 6. A full-wave rectified signal Xuv ′ is output, and a zero signal is output when the reference phase is between 7π / 6 and 11π / 6. The signal output in this way becomes the command value signal Xu2. Similarly, the command value signal Xv2 is output by switching the full-wave rectified signals Xvw ′, Xuv ′ and the zero signal, and the command value signal Xw2 is generated by switching the full-wave rectified signals Xwu ′, Xvw ′ and the zero signal. Output by switching and outputting.

  In the first and second embodiments, the command value signal is generated using the line voltage control signal, but the present invention is not limited to this. For example, the phase voltage of each phase may coincide with the potential on the negative electrode side of the DC power supply 1 (hereinafter referred to as “DC negative electrode potential”) every one-third cycle.

  FIG. 13 is a flowchart for explaining a control method for controlling the phase voltage of each phase to coincide with the DC negative potential of the DC power supply 1 every one-third cycle.

  In this control method, the phase to be fixed to the DC negative electrode potential is determined in advance based on the reference phase. For example, when the reference phase is −π / 3 (= −60 °) to π / 3 (= 60 °), the U phase is fixed at the DC negative electrode potential, and the reference phase is changed from π / 3 (= 60 °) to π. The W phase is fixed at the DC negative potential during (= 180 °), and the V phase is fixed at the DC negative potential during the reference phase from π (= 180 °) to 5π / 3 (= 300 °). deep.

  First, the phase voltage of each phase is determined (S1), and the phase set to the DC negative electrode potential is determined based on the reference phase (S2). Next, a voltage amount Vn for setting the phase to the DC negative electrode potential is calculated (S3), and Vn is added to the other two phases (S4). The calculated phase voltage of each phase is output (S5).

  The U-phase, V-phase, and W-phase voltages are Vu, Vv, and Vw, respectively, and the changed phase voltages are Vu ′, Vv ′, and Vw ′, respectively. When the reference phase is between −60 ° and 60 °, the U phase is fixed at the DC negative electrode potential, so Vn = −Vu. Therefore, Vu ′ = 0, Vv ′ = Vv−Vu, and Vw ′ = Vw−Vu. When the reference phase is between 60 ° and 180 °, the W phase is fixed at the DC negative electrode potential, so Vn = −Vw. Therefore, Vu ′ = Vu−Vw, Vv ′ = Vv−Vw, and Vw ′ = 0. When the reference phase is between 180 ° and 300 °, the V phase is fixed at the DC negative electrode potential, so Vn = −Vv. Therefore, Vu ′ = Vu−Vv, Vv ′ = 0, and Vw ′ = Vw−Vv.

  Assuming that the U-phase, V-phase, and W-phase line voltages are Vuv, Vvw, and Vwu, respectively, Vuv = Vu′−Vv ′, Vvw = Vv′−Vw ′, and Vwu = Vw′−Vu ′. When the reference phase is between −60 ° and 60 °, Vuv = Vu′−Vv ′ = 0− (Vv−Vu) = Vu−Vv, and when the reference phase is between 60 ° and 180 °, Vuv = Vu′−Vv. '= (Vu−Vw) − (Vv−Vw) = Vu−Vv, and when the reference phase is between 180 ° and 300 °, Vuv = Vu′−Vv ′ = (Vu−Vv) −0 = Vu−Vv Become. That is, Vuv = Vu−Vv for the entire period. Similarly, Vvw = Vv−Vw, Vwu = Vw−Vu, and each line voltage, which is the difference between the phase voltages after the change, matches the difference between the original phase voltages. Therefore, each line voltage output from the inverter circuit 2 can be synchronized with the system voltage.

  FIG. 14 is a vector transition diagram showing the control method. When the reference phase is between -60 ° and 60 °, the tip of the vector indicating the phase voltage of the U phase (thick arrow in the figure) is fixed to the DC negative potential, and the reference phase is between 60 ° and 180 °. , The tip of a vector (thin line arrow in the figure) indicating the phase voltage of the W phase is fixed at the DC negative electrode potential, and the vector (V) indicating the phase voltage of the V phase is between 180 ° and 300 °. The tip of the dotted arrow in the figure is fixed at the DC negative potential.

An inverter control circuit for realizing the control method will be described below.

FIG. 15 is a block diagram for explaining an example of a grid-connected inverter system including the third embodiment of the inverter control circuit according to the present invention. In the figure, the same or similar elements as those in the first embodiment are denoted by the same reference numerals.

  The inverter control circuit 6 of the grid-connected inverter system A3 is different from that of the first embodiment in that a signal generation circuit 614 is provided instead of the control signal conversion circuit 612 and the signal generation circuit 613.

  The signal generation circuit 614 generates command value signals Xu3, Xv3, and Xw3 using the phase voltage control signals Xu, Xv, and Xw that are input. The signal generation circuit 614 sets the command value signals Xu3, Xw3, and Xv3 to zero every third cycle in this order, and sets the phase voltage control signal of the phase set to zero from the phase voltage control signal of each phase. By using the reduced signal as the command value signal, the control method shown in FIG. 13 is realized.

  FIG. 16 is a flowchart for explaining processing performed in the signal generation circuit 614.

  First, the reference phase θ is initialized (S11). Next, a phase voltage control signal for each phase is input (S12), and a reference phase is determined (S13). When −π / 3 ≦ θ <π / 3, the command value signal Xu3 is set to zero, Xu is subtracted from the phase voltage control signal Xv to become the command value signal Xv3, and the command is obtained by subtracting Xu from the phase voltage control signal Xw. The value signal Xw3 is set (S14). If π / 3 ≦ θ <π, Xw3 is set to zero, Xw is subtracted from Xw to be Xu3, and Xv is subtracted from Xw to be Xv3 (S15). When π ≦ θ <5π / 3, Xv3 is set to zero, Xv is subtracted from Xu to Xu3, and Xv is subtracted from Xw to Xw3 (S16). Each command value signal is output to the PWM signal generation circuit 62 (S17), the reference phase θ is increased (S18), and the process returns to step S12.

  When implementing this embodiment, it is necessary to consider the phase change accompanying harmonic control.

  Also in this embodiment, the same effect as the first embodiment can be obtained.

  In addition, although the said embodiment demonstrated the case where the inverter control circuit of this invention was used for the grid connection inverter system, it is not restricted to this. The inverter control circuit of the present invention is realized by reading a program for generating a PWM signal in a conventional inverter control circuit by a method described above into a computer from a recording medium such as a ROM recorded in a computer-readable manner and executing the program. May be.

  The inverter control circuit according to the present invention is not limited to the above-described embodiment. The specific configuration of each part of the inverter control circuit according to the present invention can be varied in design in various ways.

It is a vector diagram showing the relationship between phase voltage signals Vu, Vv, Vw and line voltage signals Vwu, Vuv, Vvw. It is a figure which shows a mode that the position of a reference voltage changes by rotating the equilateral triangle formed by the vectors Pu, Pv, and Pw respectively corresponding to phase voltage signal Vu, Vv, Vw on a reference line. FIG. 2 is a diagram obtained by rotating the vector diagram shown in FIG. 1 by π / 6 clockwise. It is a figure which shows the relationship between the phase voltage signal of each phase of U phase, V phase, and W phase which concerns on this invention, and a line voltage signal. It is a figure which shows the waveform of phase voltage signal Vu1, Vv1, Vw1 of each phase of the line voltage signal Vwu, Vuv, Vvw, Vuw, Vvu, Vwv and the U phase, V phase, and W phase which concerns on this invention. It is a block diagram for demonstrating an example of the grid connection inverter system provided with 1st Embodiment of the inverter control circuit which concerns on this invention. It is a figure which shows an example of a full bridge type three-phase inverter circuit. It is a figure for demonstrating the waveform of the command value signal Xu1 which a signal generation circuit outputs. It is a figure for demonstrating the method to produce | generate a PWM signal from a command value signal and a carrier signal. It is a block diagram for demonstrating an example of the grid connection inverter system provided with 2nd Embodiment of the inverter control circuit which concerns on this invention. It is a figure for demonstrating the method of producing | generating a command value signal using a full wave rectification signal. It is a figure for demonstrating the structure of the signal generation circuit for using the method of producing | generating a command value signal using a full wave rectification signal. It is a flowchart for demonstrating the control method for controlling so that the phase voltage of each phase may correspond with DC negative electrode potential of DC power supply for every 1/3 period. FIG. 14 is a vector transition diagram showing the control method shown in FIG. It is a block diagram for demonstrating an example of the grid connection inverter system provided with 3rd Embodiment of the inverter control circuit which concerns on this invention. It is a flowchart for demonstrating the process performed with a signal generation circuit. It is a block diagram for demonstrating an example of the grid connection 3 phase inverter system provided with the conventional inverter control circuit. It is a figure which shows the production | generation principle of the PWM signal by a triangular wave comparison system. It is a figure which shows the waveform of the command value signal which superimposed the waveform of the phase voltage control signal, and the 3rd harmonic on this.

Explanation of symbols

A1, A2, A3 Grid-connected inverter system 1 DC power supply 2 Inverter circuit 3 Filter circuit 4 Transformer circuit 5 Commercial power system 6 Inverter control circuit 61 Command value signal generation circuit 611 Phase voltage control signal generation circuit 611a Phase detection circuit 611b PI control Circuit 611c Three-phase / two-phase conversion circuit 611d Static coordinate conversion circuit 611e PI control circuit 611f Rotation coordinate conversion circuit 611g Two-phase / three-phase conversion circuit 612 Control signal conversion circuit 613, 614 Signal generation circuit 62 PWM signal generation circuit 7 DC voltage Sensor 8 Current sensor 9 Line voltage sensor

Claims (8)

An inverter control circuit that controls driving of a plurality of switching means in the three-phase inverter circuit by a PWM signal and controls an output of the three-phase inverter circuit that supplies power to the power system;
The waveform of one cycle becomes zero in the period of 1/3 cycle, becomes a sine wave waveform in the interval of 0 to 2π / 3 in the period of 1/3 cycle, and the waveform in the remaining 1/3 cycle period. A first command value signal in which the phase of the sine wave is a waveform in a section from π / 3 to π, a second command value signal whose phase is advanced by 2π / 3 with respect to the first command value signal, Command value signal generating means for generating a third command value signal whose phase is delayed by 2π / 3 with respect to the first command value signal;
PWM signal generating means for generating a PWM signal based on the command value signal;
With
The command value signal generating means is
A signal detecting a three-phase current output from the three-phase inverter circuit, a signal detecting a DC voltage input to the three-phase inverter circuit, and a signal detecting a line voltage of each transmission of the power system And phase voltage control signal generating means for generating three phase voltage control signals based on
Control signal conversion means for generating a line voltage control signal which is a differential signal of the three phase voltage control signals;
Signal generating means for generating the first to third command value signals by switching between the line voltage control signal and a zero signal whose value is always zero;
An inverter control circuit comprising:   The signal generation means outputs the command value signal of each phase from the phase voltage control signal of the phase, the phase voltage control signal that is one phase before the phase, and the phase voltage control signal that is one phase after the phase. 2. The inverter control circuit according to claim 1, wherein the inverter control circuit is generated from two line voltage control signals obtained by subtraction and the zero signal as a signal synthesized so as to take a maximum value among these signals.   The signal generation means sets the command value signal of each phase to zero for a period of 1/3 period, and for the subsequent period of 1/3 period to the phase order one phase before the phase from the phase voltage control signal of the phase. The line voltage control signal obtained by subtracting the phase voltage control signal is subtracted from the phase voltage control signal of the relevant phase for the remaining 1/3 cycle period. The inverter control circuit according to claim 1, wherein the inverter control circuit is generated as a line voltage control signal obtained in this way. An inverter control circuit that controls driving of a plurality of switching means in the three-phase inverter circuit by a PWM signal and controls an output of the three-phase inverter circuit that supplies power to the power system;
The waveform of one cycle becomes zero in the period of 1/3 cycle, becomes a sine wave waveform in the interval of 0 to 2π / 3 in the period of 1/3 cycle, and the waveform in the remaining 1/3 cycle period. A first command value signal in which the phase of the sine wave is a waveform in a section from π / 3 to π, a second command value signal whose phase is advanced by 2π / 3 with respect to the first command value signal, Command value signal generating means for generating a third command value signal whose phase is delayed by 2π / 3 with respect to the first command value signal;
PWM signal generating means for generating a PWM signal based on the command value signal;
With
The command value signal generating means is
A signal detecting a three-phase current output from the three-phase inverter circuit, a signal detecting a DC voltage input to the three-phase inverter circuit, and a signal detecting a line voltage of each transmission of the power system And phase voltage control signal generating means for generating three phase voltage control signals based on
Signal generating means for generating the first to third command value signals for each phase of the three-phase inverter circuit from the three phase voltage control signals;
The signal generating means includes
In the period when the first command value signal is zero,
Subtracting the first phase voltage control signal from the first phase voltage control signal of the phase corresponding to the first command value signal to obtain the first command value signal;
Subtracting the first phase voltage control signal from the second phase voltage control signal of the phase corresponding to the second command value signal to obtain the second command value signal;
Subtracting the first phase voltage control signal from the third phase voltage control signal of the phase corresponding to the third command value signal to obtain the third command value signal;
In the period of 1/3 period following the zero period,
Subtracting the third phase voltage control signal from the first phase voltage control signal as the first command value signal,
Subtracting the third phase voltage control signal from the second phase voltage control signal to obtain the second command value signal;
Subtracting the third phase voltage control signal from the third phase voltage control signal to obtain the third command value signal,
In the remaining 1/3 period,
Subtracting the second phase voltage control signal from the first phase voltage control signal as the first command value signal,
Subtracting the second phase voltage control signal from the second phase voltage control signal to obtain the second command value signal,
Subtracting the second phase voltage control signal from the third phase voltage control signal to obtain the third command value signal;
An inverter control circuit characterized by that. The PWM signal generation means generates the PWM signal by comparing the three command value signals with predetermined carrier signals, respectively, so that the minimum value of each command value signal matches the minimum value of the carrier signal. An inverter control circuit according to any one of claims 1 to 4.   A grid-connected inverter system comprising the inverter control circuit according to any one of claims 1 to 5. Computer
A program for controlling the driving of a plurality of switching means in a three-phase inverter circuit by a PWM signal and functioning as an inverter control circuit for controlling the output of the three-phase inverter circuit for supplying power to a power system,
The computer,
The waveform of one cycle becomes zero in the period of 1/3 cycle, becomes a sine wave waveform in the interval of 0 to 2π / 3 in the period of 1/3 cycle, and the waveform in the remaining 1/3 cycle period. A first command value signal in which the phase of the sine wave is a waveform in a section from π / 3 to π, a second command value signal whose phase is advanced by 2π / 3 with respect to the first command value signal, Command value signal generating means for generating a third command value signal whose phase is delayed by 2π / 3 with respect to the first command value signal;
PWM signal generating means for generating a PWM signal based on the command value signal;
To function,
The command value signal generating means is
A signal detecting a three-phase current output from the three-phase inverter circuit, a signal detecting a DC voltage input to the three-phase inverter circuit, and a signal detecting a line voltage of each transmission of the power system And phase voltage control signal generating means for generating three phase voltage control signals based on
Control signal conversion means for generating a line voltage control signal which is a differential signal of the three phase voltage control signals;
Signal generating means for generating the first to third command value signals by switching between the line voltage control signal and a zero signal whose value is always zero;
With
A program characterized by that.   A computer-readable recording medium on which the program according to claim 7 is recorded.

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