JP5855896B2 - Display device using subfield driving method, display method, and program - Google Patents

Description

  The present invention relates to a technique used for a matrix type display device such as a plasma display panel, and more particularly to a sub-field that divides a field for displaying image data into a plurality of sub-fields and adds the plurality of sub-fields to display a gradation. The present invention relates to a display device using a field driving method, a display method, and a program.

  With the development of video processing technology, the demand for image quality performance of display devices is increasing. In particular, the technical progress related to the driving method of the liquid crystal display device, which has been considered to have a problem with the moving image quality, is remarkable, and the moving image quality has been dramatically improved by the double speed driving or black insertion technology. On the other hand, research and development on display technology at a higher frame frequency are also being performed for the purpose of improving gradation expression in a plasma display (hereinafter referred to as PDP) that is excellent in moving image quality.

  Incidentally, a subfield driving method (hereinafter referred to as SF driving method) is known as a gradation display method used in PDP or the like (see, for example, Patent Document 1). In this SF driving method, a field indicating a video display period of one frame is temporally divided into a plurality of sections (subfields, hereinafter referred to as SF), and the display time of each divided SF is weighted. Luminance (emission weight) is allocated, and these SFs are added (time-integrated) with the combination of SFs to emit light to express pixel values and display an image. Specifically, in a display device including a plurality of pixels arranged in a row direction and a column direction, image data is converted into data for each bit, an address period for selecting a pixel, and the selected pixel as a bit weight. The gradation display is performed according to the image data by the SF including the display period in which light is emitted for the corresponding time. As a result, gradation display can be realized by temporal integration of an image reflected in the human eye. For example, one field is divided into 8 SFs, and weights of 1, 2, 4, 8, 16, 32, 64, and 128 are given to the respective SFs, and these SFs are added together so that an image of 256 gradations is added. Display.

Japanese Patent No. 3259253

  However, this SF driving method has an upper limit on the frame frequency. This is schematically expressed as N ≦ 1 / (fT), where N is the number of SFs per frame, T is the time width required to display one SF, and f is the frame frequency. This is because the number of gradations that can be expressed when using a set of SFs having unique emission weights corresponding to the factorial of 2 is the Nth power of 2.

  For example, it is assumed that one frame is divided into eight SFs having emission weights of 128, 64, 32, 16, 8, 4, 2, and 1, and 256 gradation image display is performed depending on whether or not each SF emits light. To do. In this case, in order to double the frame frequency without changing the time given to each SF, it is necessary to reduce the number of SFs for dividing one frame to 4 which is a half. When the frame frequency is increased, the number of SFs is decreased and the number of gradations is decreased. Therefore, an increase in the frame frequency causes a decrease in the number of SFs, that is, a decrease in gradation.

  Accordingly, the present invention has been made to solve the above-described problems, and an object of the present invention is to perform SF driving capable of improving the gradation while maintaining or increasing the frame frequency of the high luminance component related to the moving image quality. It is to provide a display device, a display method, and a program using the method.

In order to achieve the above object, a display device according to the present invention includes a plurality of pixels arranged in a row direction and a column direction, converts image data of an input video into bit data of a predetermined number of bits, and selects the pixels. In a display device that generates a display image from the input image and performs gradation display by processing of a subfield including an address period and a display period in which the selected pixel emits light for a time corresponding to the weight of the bit data , N is a natural number, and a predetermined number of upper bits are extracted based on the respective image data of the first frame of frame number (2n-1) and the second frame of frame number 2n in the input video. a bit processing unit, and a lower bit processor for summing the image data of the first and second frames successive in the input image, the lower Lower order bits of the first predetermined position and the second predetermined position from the image data obtained by subtracting the image data including the upper bits extracted by the upper bit processing unit from the image data added by the bit processing unit And a predetermined number of upper bits extracted from the first frame by the upper bit processing unit and the lower bits at the first predetermined position are combined and extracted from the second frame by the upper bit processing unit. And a combining unit that combines the predetermined number of upper bits and the lower bits of the second predetermined position and outputs the combined image data of two consecutive frames as a display image. .

  Further, in the display device according to the present invention, the combining unit allocates the upper bits extracted based on the first frame of the input video to the upper bits of the first frame of the display video, and the second of the input video. The high-order bits extracted based on the frame are allocated to the high-order bits of the second frame of the display image.

The display device according to the present invention, the upper bit processing unit, from each of the image data of the first and second frames successive in the input image, the higher extraction unit for extracting upper bits of the predetermined number directly, It is provided with.

The display device according to the present invention, the lower bit processing unit, summing the image data of the first and second frames successive in the input image, and a summing unit configured to generate a metadata frame image data, the upper bits An addition unit that adds the upper bits extracted from the first frame and the upper bits extracted from the second frame by the processing unit to generate added image data; and the metaframe image data generated by the summing unit; A subtracting unit that performs subtraction using the added image data generated by the adding unit to generate display error image data.

Further, according to the display method of the present invention, an address period in which image data of an input video is converted into bit data having a predetermined number of bits by a display device including a plurality of pixels arranged in a row direction and a column direction, and the pixels are selected. In a display method for generating a display image from the input image and performing gradation display in processing of a subfield consisting of a display period in which the selected pixel emits light for a time corresponding to the weight of the bit data, A first number for extracting a predetermined number of higher-order bits based on respective image data of the first frame of frame number (2n-1) and the second frame of frame number 2n in the input video , where n is a natural number . a step of a second step of summing the image data of the first and second frames successive in the input image, the second step Extracting the lower-order bits of the first predetermined position and the second predetermined position from the image data obtained by subtracting the image data including the upper bits extracted in the first step from the image data added by the first step. And a fourth step of combining the predetermined number of upper bits extracted from the first frame by the first step and the lower bits at the first predetermined position extracted by the third step; A fifth step of combining the predetermined number of upper bits extracted from the second frame by the first step and the lower bits of the second predetermined position extracted by the third step; the fourth step; And a sixth step of outputting the image data of two consecutive frames synthesized by the step 5 as a display video.

  Furthermore, a display program according to the present invention causes a computer to function as the display device.

  As described above, according to the present invention, it is possible to improve gradation while maintaining or increasing the frame frequency of a high luminance component related to moving image quality.

It is a block diagram which shows the structure of the display apparatus by embodiment of this invention. It is a figure which shows the flow of the image data in a display apparatus. It is a figure explaining the image of the display image output by a display apparatus. It is a figure which shows the flow of the image data in the conventional display apparatus. It is a figure explaining the image of the display image output by the conventional display apparatus. It is a figure explaining a simulation result.

  Hereinafter, embodiments for carrying out the present invention will be described in detail with reference to the drawings. The embodiment of the present invention generates image data larger than a predetermined number of gradations for a display image of SF with a large luminance weight, which is a high luminance component, and treats it with the same frame frequency as the input video. For an SF display image having a small luminance weight, image data larger than a predetermined number of gradations is generated and handled at a frame frequency lower than that of the input image. Here, human visual follow-up has a characteristic that it is fast for an image with a high luminance component and slow for a low luminance component. Therefore, an effect of improving the moving image quality is expected by displaying the SF of the high luminance component at a high frame frequency.

  In the embodiment of the present invention, an image obtained by averaging two temporally adjacent input video frames (hereinafter referred to as a metaframe) is divided into SFs, and luminance weights that are predetermined low luminance components are divided. Determine a small SF. The SF with a small luminance weight in the display video is assumed to have different weights in adjacent frames. For example, the first frame is composed of 4-bit SFs corresponding to the weights of 64, 32, 8, and 1, and the following If the frame is composed of 4-bit SFs corresponding to the weights of 64, 32, 4 and 2, the SFs of bits corresponding to the weights of 8 and 1, which are lower-order SFs having a small luminance weight in each frame, and For the SF of bits corresponding to the weights of 4 and 2, the SF value of the metaframe is given. As a result, the value obtained by adding (adding) both frames (the first frame and the next frame) takes a value closer to the metaframe than when both frames are represented by 4 bits. As described above, in the embodiment of the present invention, the low-luminance component in the metaframe (the actual low-luminance component when the image is viewed at a frame frequency lower than normal) is distributed to the adjacent display video frames. Therefore, the gradation reproducibility of a still image can be improved. Therefore, it is possible to improve the gradation while maintaining the frame frequency of the high luminance component related to the moving image quality.

[Display device]
First, a display device according to an embodiment of the present invention will be described. FIG. 1 is a block diagram illustrating a configuration of a display device, and FIG. 2 is a diagram illustrating a flow of image data in the display device. In the embodiment shown in FIGS. 1 and 2, a still image having a horizontal size of 480 pixels, a vertical size of 260 pixels, and 256 gradations per pixel (8 bits) is defined as one frame. The display device 1 inputs a moving image of 120 frames per second (that is, 120 fps) as an 8-bit image F _i (N) of an input video, and outputs a display video image D (N) divided into five SFs. Shall. In addition, the display device 1 can output 600 SFs per second. Therefore, if the video is 120 fps, 5 SFs can be allocated per frame. The 8-bit image F _i (N) indicates the pixel value of frame number N.

Referring to FIG. 1, this display device 1 includes color reduction units 10-1 and 10-2, upper extraction units 11-1 and 11-2, an averaging unit (summing unit) 12, a color reduction unit 13, and an addition unit 14. The subtracting unit 15 and the combining units 16-1 and 16-2 are provided. The color reduction units 10-1 and 10-2 and the high-level extraction units 11-1 and 11-2 constitute a high-order bit processing unit, and the averaging unit 12, the color reduction unit 13, the addition unit 14, and the subtraction unit 15 constitute a low-order bit processing unit. Is configured. The display device 1 receives two frames of 8-bit images F _i (N) and F _i (N + 1) in the input video, and the upper 3 bits of the SFs constituting the display video have a gradation number of 32. It is composed of data of gradation number 64 (6 bits) and 120 fps larger than (5 bits), and the lower 2 bits SF are data obtained by averaging the input video, and the gradation number 32 (5 bits) Two frames of images D (N) and D (N + 1) composed of data having a larger gradation number 128 (7 bits) and 60 fps are output as display images. After processing the 8-bit images F _i (N) and F _i (N + 1), the display device 1 inputs the two frames of the 8-bit images F _i (N + 2) and F _i (N + 3) in the input video, and inputs 2 frames. Images D (N + 2) and D (N + 3) are generated and output as display images.

The color reduction unit 10-1 receives an 8-bit image F _i (N) of the input video, converts the 8-bit image data into 6-bit image data by color reduction processing, and generates a 6-bit image F ₆ (N). And output to the upper extraction unit 11-1. The configuration of the 6-bit image F ₆ (N) is as shown by d1 in FIG. In d1 of FIG. 2, "1,2,4,8,16,32" indicates the weight of each bit in the 6-bit image _F 6 (N), the number of gradations of the 6-bit image _F 6 (N) is 64 (6 bits). Note that, for the color reduction processing that generates the 6-bit image F ₆ (N), for example, a steavenson & Arche dithering algorithm that deletes lower bits while performing error diffusion is used. Since this color reduction process is known, description thereof is omitted here. In the present invention, the color reduction processing is not limited to the processing by the steavenson & Arche dithering algorithm.

The high-order extraction unit 11-1 receives the 6-bit image F ₆ (N) from the color reduction unit 10-1, extracts the predetermined high-order 3 bits corresponding to the high luminance component, and the low-order 2 bits of the dummy (0) An upper bit image F ₃ (N) composed of a total of 5 bits obtained by combining the extracted upper 3 bits is generated, and the upper bit image F ₃ (N) is output to the adding unit 14 and the combining unit 16-1. The upper 3 bits of data in the upper bit image F ₃ (N) are allocated to the high luminance component of the display video image D (N) generated by the display device 1. The configuration of the upper bit image F ₃ (N) is as shown by d2 in FIG. As shown in d2 of FIG. 2, the upper bit image F ₃ (N) is 120 fps data composed of 5 bits, and the upper 3 bits are the same as the upper 3 bits of the 6-bit image F ₆ (N). is there. The number of gradations of the upper bit image F ₃ (N) is 32 (5 bits).

The color reduction unit 10-2 performs the same processing as the color reduction unit 10-1, inputs an 8-bit image F _i (N + 1) of the input video, and converts 8-bit image data into 6-bit image data by color reduction processing. Then, a 6-bit image F ₆ (N + 1) is generated and output to the upper extraction unit 11-2. The configuration of the 6-bit image F ₆ (N + 1) is as shown by d3 in FIG. In d3 in FIG. 2, "1,2,4,8,16,32" indicates the weight of each bit in the 6-bit image _F 6 (N + 1), the number of gradations of the 6-bit image _F 6 (N + 1) is 64 (6 bits).

The upper extraction unit 11-2 performs the same processing as the upper extraction unit 11-1, inputs the 6-bit image F ₆ (N + 1) from the color reduction unit 10-2, and performs predetermined upper 3 bits corresponding to the high luminance component. extracting, generating a dummy (0) high-order 3 bits and the upper bits image F ₃ constituted by synthesized a total of 5 bits and the extracted low order 2 bits of the _(N + 1), the upper bit image F ₃ a _(N + 1) The data is output to the adding unit 14 and the combining unit 16-2. The data of the upper 3 bits in the upper bit image F ₃ (N + 1) is allocated to the high luminance component of the image D (N + 1) of the display video generated by the display device 1. The configuration of the upper bit image F ₃ (N + 1) is as shown by d4 in FIG. As shown in d4 of FIG. 2, the upper bit image F ₃ (N + 1) is 120 fps data composed of 5 bits, and the upper 3 bits are the same as the upper 3 bits of the 6-bit image F ₆ (N + 1). is there. The upper bit image F ₃ (N + 1) has a gradation number of 32 (5 bits).

The addition unit 14 receives the upper bit image F ₃ (N) from the upper extraction unit 11-1 and also receives the upper bit image F ₃ (N + 1) from the upper extraction unit 11-2, and receives the upper bit image F ₃ ( N) and the upper bit image F ₃ (N + 1) are added (added) to generate an average image F _b (N + 1/2) of two frames, and a subtraction unit for the average image F _b (N + 1/2) of two frames 15 is output. The structure of the average image F _b (N + 1/2) of two frames is as shown by d6 in FIG. As shown in d6 of FIG. 2, the average image F _b (N + 1/2) of 2 frames is 60 fps data composed of 7 bits, and the upper 4 bits are the upper _{3 of the} upper bit image F ₃ (N). This is the result of adding the bit and the upper 3 bits of the upper bit image F ₃ (N + 1), and the lower 3 bits are dummy bits. Further, the number of gradations of the average image F _b (N + 1/2) of two frames is 127 (7 bits).

The averaging unit 12 inputs 8-bit images F _i (N) and F _i (N + 1) of the input video, averages these images, generates an averaged image, and outputs the averaged image to the color reduction unit 13. Specifically, the averaging unit 12 adds (adds) the pixel values of the 8-bit images F _i (N) and F _i (N + 1) and divides by 2 to generate an averaged image.

The color reduction unit 13 receives the averaged image from the averaging unit 12, converts the image data of the 8-bit averaged image into 7-bit image data by the color reduction process, and generates a metaframe F _m (N + 1 / N) of the 7-bit image. 2) is generated and output to the subtraction unit 15. The configuration of the meta frame F _m (N + 1/2) of the 7-bit image is as indicated by d5 in FIG. In d5 of FIG. 2, “1, 2, 4, 8, 16, 32, 64” indicates the weight of each bit in the metaframe F _m (N + 1/2) of the 7-bit image. The meta frame F _m (N + 1/2) is data equivalent to 60 fps composed of 7 bits, and the number of gradations is 128 (7 bits). The color reduction processing for the 7-bit image by the color reduction unit 13 is the same as the color reduction processing for the 6-bit image by the color reduction units 10-1 and 10-2.

The subtraction unit 15 receives the metaframe F _m (N + 1/2) from the color reduction unit 13 and the average image F _b (N + 1/2) of two frames from the addition unit 14, and receives the metaframe F _m (N + 1/1/2). The pixel value of the average image F _b (N + 1/2) of two frames is subtracted from the pixel value of 2) to generate a display error D _m (N + 1/2) and output it to the combining units 16-1 and 16-2. . Here, the meta frame F _m (N + 1/2), the average image F _b (N + 1/2) of two frames, and the display error D _m (N + 1/2) are data of 60 fps composed of 7 bits, The number of gradations is 128 (7 bits). Part of the lower 4 bits of the display error D _m (N + 1/2) is allocated to the low-luminance components of the display video images D (N) and D (N + 1) generated by the display device 1, respectively. It is. The configuration of the display error D _m (N + 1/2) is as shown by d7 in FIG. In d7 of FIG. 2, “1, 2, 4, 8, 16, 32, 64” indicates the weight of each bit in the display error D _m (N + 1/2) of the 7-bit image. The display error D _m (N + 1/2) generated by the subtracting unit 15 has no upper bit component. This is because the display error D _m (N + 1/2) is a result of subtracting the average image F _b (N + 1/2) of two frames from the meta frame F _m (N + 1/2). In this example, there is no data in the bit component having the weight of “16, 32, 64”.

The display error D _m (N + 1/2) generated by the subtracting unit 15 is the current metaframe F that is an ideal image when updated at 60 fps (an actual image when viewing the image at 60 fps). _m (N + 1/2) and the higher-order bit images F ₃ (N) and F ₃ (N + 1) updated at 120 fps are converted into an image updated at 60 fps, and the two-frame average image F _b (N + 1/2) It can be said that the current error between

The synthesizing unit 16-1 receives the upper bit image F ₃ (N) from the upper extracting unit 11-1, and also receives the display error D _m (N + 1/2) from the subtracting unit 15, and receives the upper bit image F ₃ ( The upper 3 bits of the 5 bits constituting N) are used as the upper 3 bits as they are, and the least significant (first) bit and the fourth bit of the 7 bits constituting the display error D _m (N + 1/2) Are combined as lower 2 bits to generate and output a display video image D (N). The configuration of the display video image D (N) is as shown by d8 in FIG. In d8 of FIG. 2, “1, 8, 8, 16, 32” indicates the weight of each bit in the image D (N) of the display video that is a 5-bit image. The number of gradations of the display video image D (N) is 32 (5 bits), but the upper 3 bits are data that realizes the gradation number 64 (6 bits) and are updated at 120 fps, and the lower 2 bits. Is data that realizes the number of gradations 128 (7 bits) and is updated at 60 fps.

The synthesizing unit 16-2 performs the same processing as the synthesizing unit 16-1, inputs the upper bit image F ₃ (N + 1) from the upper extracting unit 11-2, and displays the display error D _m (N + 1 / N) from the subtracting unit 15. 2), the upper 3 bits of the 5 bits constituting the upper bit image F ₃ (N + 1) are directly used as the upper 3 bits, and 2 of the 7 bits constituting the display error D _m (N + 1/2). The first bit and the third bit are combined as the lower 2 bits, and a display video image D (N + 1) is generated and output. The configuration of the display video image D (N + 1) is as shown by d9 in FIG. In d9 of FIG. 2, “2, 4, 8, 16, 32” indicates the weight of each bit in the image D (N + 1) of the display video that is a 5-bit image. The number of gradations of the display video image D (N + 1) is 32 (5 bits), but the upper 3 bits are data that realizes the gradation number 64 (6 bits) and are updated at 120 fps, and the lower 2 bits. Is data that realizes the number of gradations 128 (7 bits) and is updated at 60 fps.

The display device 1 shown in FIG. 1 may not include the color reduction units 10-1 and 10-2. In this case, the upper extraction units 11-1 and 11-2 receive the 8-bit images F _i (N) and F _i (N + 1) of the input video, and extract predetermined upper 3 bits corresponding to the high luminance component. Then, upper bit images F ₃ (N) and F ₃ (N + 1) composed of a total of 5 bits obtained by combining the lower 2 bits of the dummy (0) and the extracted upper 3 bits are generated. That is, the color reduction units 10-1 and 10-2 are resampling processing units that operate as necessary. For example, the color reduction units 10-1 and 10-2 may or may not operate according to user settings.

Further, the display device 1 may not include the color reduction unit 13. In this case, the adding unit 14 adds (adds) the upper bit image F ₃ (N) and the upper bit image F ₃ (N + 1), generates an added image, and outputs the added image to the subtracting unit 15. The subtracting unit 15 receives the metaframe that is the averaged image from the averaging unit 12, and also receives the added image from the adding unit 14, subtracts the pixel value of the added image from the pixel value of the metaframe, and displays a display error D. _m (N + 1/2) is generated. As described above, the display device 1 does not necessarily include the color reduction units 10-1, 10-2, and 13. That is, the color reduction unit 13 is a resampling processing unit that operates as necessary. For example, the color reduction unit 13 may or may not operate depending on user settings.

[Effect of display device]
Next, effects of the display device 1 shown in FIG. 1 will be described. FIG. 4 is a diagram illustrating a flow of image data in a conventional display device, and FIG. 5 is a diagram for explaining an image of a display video output by the conventional display device. Also in the conventional display device, similarly to the display device 1 shown in FIG. 1, a still image having a horizontal size of 480 pixels, a vertical size of 260 pixels, and a gradation number of 256 (8 bits) per pixel is defined as one frame. , A moving image of 120 fps is input as an 8-bit image F _r (N) of the input video, and a display video image D (N) divided into five SFs is output. The 8-bit image F _r (N) indicates the pixel value of frame number N.

Referring to FIG. 4, the conventional display device inputs an 8-bit image F _r (N) of an input video, converts 8-bit image data into 5-bit image data by color reduction processing, and converts the 5-bit image F ₅ (N) is generated. Then, the 5-bit image F ₅ (N) is output as the display video image D (N). In addition, the conventional display device inputs an 8-bit image F _r (N + 1) of an input video, converts 8-bit image data into 5-bit image data by color reduction processing, and converts the 5-bit image F ₅ (N + 1). Generate. Then, the 5-bit image F ₅ (N + 1) is output as a display video image D (N + 1). In the color reduction processing for generating the 5-bit images F ₅ (N) and F ₅ (N + 1), for example, as in the color reduction processing by the color reduction units 10-1, 10-2, and 13 shown in FIG. Steavenson &Arche's dithering algorithm is used to remove the lower bits while spreading.

Referring to FIG. 5, an image D (N) of a display video generated by the conventional display device shown in FIG. 4 is an 8-bit image F _r (N) of the first frame of the input video. Is a 5-bit image F ₅ (N) converted into a 5-bit image obtained by converting an 8-bit image F _r (N + 1) of the second frame of the input video into a 5-bit image. F ₅ (N + 1). These display video images D (N) and D (N + 1) are both 120 fps images, and the number of gradations is 32 (5 bits).

  Generally, the human brain recognizes a still image displayed by switching at a certain frequency as a moving image. However, if the blinking of the pixel is too fast, the blinking cannot be detected, and the integrated luminance value (summed value) is transmitted to the brain, and the resolution in the time direction is limited. This is the temporal integration action of the image reflected in the human eye. The limit of the resolution depends on the area, position, brightness, etc. of the portion of the image being watched, and is usually about 55 Hz in a portion having a higher luminance than the periphery and about 12 Hz in a portion having a lower luminance. Obtained experimentally. By such an eye integration action, in the human brain, for example, two frames of images updated at 120 fps are recognized as one frame of images updated at 60 fps. Therefore, in FIG. 5, the display video image when the display video image D (N) in the first frame and the display video image D (N + 1) in the second frame are summed is an image of 60 fps. The number is 64 (6 bits).

  However, when the luminance changes at a certain frame frequency and the human eye catches it, the luminance change becomes flicker or the like, which may cause image quality interference. In particular, a fake video is displayed when the frame frequency is low in a video including a fast-moving scene. Such a problem can be solved by increasing the frame frequency and increasing the number of gradations, thereby improving the moving image quality. Therefore, in the display device 1 according to the embodiment of the present invention shown in FIG. 1, as described later, a display video image D (N) in the first frame and a display video image D (N + 1) in the second frame are displayed. The image of the display video when combined is an image of 60 fps, but the number of gradations is equivalent to 128 (7 bits), which is larger than the conventional number of gradations 64 (6 bits). That is, by increasing the number of gradations, it is possible to eliminate image quality interference factors such as flicker and avoid false image display.

FIG. 3 is a diagram for explaining the images D (N) and D (N + 1) of the display video output by the display device 1 shown in FIG. As shown in FIG. 3, the upper 3 bits SF in the image D (N) of the display video is data obtained by converting the 8-bit image F _i (N) of the first frame of the input video into a 6-bit image. The lower 2 bits are composed of average data based on 8-bit images F _i (N) and F _i (N + 1) of the first and second frames of the input video. Similarly, the upper 3 bits SF in the image D (N + 1) of the display video is constituted by data extracted by converting the 8-bit image F _i (N + 1) of the second frame of the input video into a 6-bit image, The lower 2 bits are composed of average data based on 8-bit images F _i (N) and F _i (N + 1) of the first and second frames of the input video. Here, referring to FIG. 1, the upper 3 bits of data in the image D (N) of the display image shown in FIG. 3 is obtained by the color reduction unit 10-1, the upper extraction unit 11-1, and the synthesis unit 16-1. The lower two bits of data are generated by the averaging unit 12, the color reduction unit 13, the subtraction unit 15, and the synthesis unit 16-1. Similarly, the upper 3 bits of data D (N + 1) of the display video shown in FIG. 3 are generated by the color reduction unit 10-2, the upper extraction unit 11-2, and the synthesis unit 16-2, and the lower 2 bits thereof. Is generated by the averaging unit 12, the color reduction unit 13, the subtraction unit 15, and the synthesis unit 16-2.

That is, the upper 3 bits SF in the displayed video images D (N) and D (N + 1) have a gradation number 64 (6) larger than the conventional gradation number 32 (5 bits) shown in FIGS. Bit) and updated at 120 fps, the lower 2 bits SF realizes a gradation number 128 (7 bits) larger than the conventional gradation number 32 (5 bits) shown in FIGS. And updated at 60 fps. Therefore, when the display video image D (N) in the first frame and the display video image D (N + 1) in the second frame are added together, the display video image is an image of 60 fps, but the number of gradations is This is equivalent to 128 (7 bits) instead of the conventional 64 (6 bits). The lower 2 bits, which are low luminance components in the displayed video images D (N) and D (N + 1), are the average values of the images F _i (N) and F _i (N + 1) of the first frame and the second frame. Matches the bit.

As described above, in the display device 1 according to the embodiment of the present invention, even when the display image is output at the same frame frequency as the input image, the number of gradations is 64 (6 bits) compared with the conventional display device. A large number of gradations 128 (7 bits) can be realized. As a result, the gradation can be improved while maintaining the frame frequency of the high luminance component related to the moving image quality. Further, the meta frame F _m (N + 1/2) of the 7-bit image generated by the averaging unit 12 and the color reduction unit 13 is an actual image when updated at 60 fps (an image viewed at 60 fps) itself. The lower 2 bits, which are low-luminance components in the displayed video images D (N) and D (N + 1), are generated based on the metaframe F _m (N + 1/2) of the 7-bit image. Thereby, the gradation reproducibility can be improved in the low luminance component. Further, even when a display image is output at a high frame frequency, it is expected that the gradation is increased and the still image reproducibility is improved. That is, it is possible to maintain the frame frequency of the high luminance component that has a dominant influence on the moving image quality and to suppress the gradation deterioration. In addition, the number of necessary SFs can be reduced with the increase in gradation, and as a result, the time corresponding to the reducible SFs can be diverted to other processes such as countermeasures for false contours and higher luminance. Is possible.

ここで、画素数は１フレームあたりの画素数を示し、フレーム数は全フレーム数（１２０）を示す。 〔simulation result〕
Next, a simulation result by a computer when the conventional display device and the display device 1 according to the embodiment of the present invention are used will be described. FIG. 6 is a diagram for explaining a simulation result, and an image of a low luminance component between an input video image and a display video image generated by the conventional display device and the display device 1 according to the embodiment of the present invention. The ratio (error rate) indicating the error is shown. The error rate is calculated by the following equation.

Here, the number of pixels indicates the number of pixels per frame, and the number of frames indicates the total number of frames (120).

  From FIG. 6, in all the moving images in the three types of samples 1 to 3, the error rate when the display device 1 according to the embodiment of the present invention is used is lower than the error rate when the conventional display device is used. You can see that Therefore, according to the display device 1 according to the embodiment of the present invention, still image reproducibility can be improved in a low luminance component.

The present invention has been described with reference to the embodiment. However, the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the technical idea thereof. For example, in the above embodiment, the number of SFs in the image of the display video is set to 5, but the present invention is not limited to 5 SFs. In the embodiment, as shown in FIGS. 1 and 2, the combining unit 16-1 has the least significant (first) bit among the 7 bits constituting the display error D _m (N + 1/2). And the fourth bit as the lower 2 bits to generate a display video image D (N), and the combining unit 16-2 uses the second bit among the 7 bits constituting the display error D _m (N + 1/2). And the image D (N + 1) of the display video is generated with the third bit as the lower 2 bits. In the present invention, for the lower 4 bits of the 7 bits constituting the display error D _m (N + 1/2), the display video images D (N), D ( The bits assigned to the lower 2 bits of N + 1) are not limited, and the bits having the same weight of the display error D _m (N + 1/2) are not assigned to the images D (N) and D (N + 1) of the display video. What should I do? For example, the synthesizing unit 16-1 uses the least significant (first) bit and the third bit of the seven bits constituting the display error D _m (N + 1/2) as the display video image D (N). The lower 2 bits are used, and the combining unit 16-2 uses the second bit and the fourth bit among the 7 bits constituting the display error D _m (N + 1/2) as the lower bits of the display video image D (N + 1). Two bits may be used.

  Note that a normal computer can be used as the hardware configuration of the display device 1 according to the embodiment of the present invention. The display device 1 is configured by a computer including a volatile storage medium such as a CPU and a RAM, a non-volatile storage medium such as a ROM, an interface, and the like. Color reduction units 10-1 and 10-2, upper extraction units 11-1 and 11-2, an averaging unit 12, a color reduction unit 13, an addition unit 14, a subtraction unit 15, and a synthesis unit 16-1 included in the display device 1. Each of the functions 16-2 is realized by causing the CPU to execute a program describing these functions. These programs can also be stored and distributed in a storage medium such as a magnetic disk (floppy (registered trademark) disk, hard disk, etc.), optical disk (CD-ROM, DVD, etc.), semiconductor memory, or the like.

DESCRIPTION OF SYMBOLS 1 Display apparatus 10 and 13 Color reduction part 11 Upper rank extraction part 12 Averaging part 14 Addition part 15 Subtraction part 16 Composition part

Claims (6)

A plurality of pixels arranged in a row direction and a column direction, converting image data of an input video into bit data of a predetermined number of bits, an address period for selecting the pixels, and the selected pixels as weights of the bit data In a display device that generates a display image from the input image and performs gradation display by processing of a subfield including a display period that emits light for a corresponding time,
A high-order bit for extracting a predetermined number of high-order bits based on respective image data of the first frame of frame number (2n-1) and the second frame of frame number 2n in the input video , where n is a natural number A processing unit;
And a lower bit processor for summing the image data of the first and second frames successive in the input image,
The first predetermined position and the second predetermined position are obtained from the image data obtained by subtracting the image data including the upper bits extracted by the upper bit processing unit from the image data added by the lower bit processing unit. The lower bits are extracted, and a predetermined number of upper bits extracted from the first frame by the upper bit processing unit and the lower bits at the first predetermined position are combined, and the upper bit processing unit extracts the lower bits from the second frame. A combining unit that combines the extracted predetermined number of upper bits and the lower bits of the second predetermined position and outputs the combined image data of two consecutive frames as a display image;
A display device comprising: The display device according to claim 1,
The synthesizing unit allocates the upper bits extracted based on the first frame of the input video to the upper bits of the first frame of the display video, and extracts the upper bits extracted based on the second frame of the input video Is assigned to the upper bits of the second frame of the display video. The display device according to claim 1 or 2,
The upper bit processor is
From each of the image data of the first and second frames successive in the input image, the higher extraction unit for extracting upper bits of the predetermined number directly,
A display device comprising: In the display device according to any one of claims 1 to 3,
The lower bit processing unit
Summing the image data of the first and second frames successive in the input image, and a summing unit configured to generate a metadata frame image data,
An addition unit that adds the upper bits extracted from the first frame and the upper bits extracted from the second frame by the upper bit processing unit, and generates added image data;
A subtraction unit that performs subtraction using the metaframe image data generated by the summation unit and the addition image data generated by the addition unit, and generates display error image data;
A display device comprising: By a display device having a plurality of pixels arranged in a row direction and a column direction, image data of an input video is converted into bit data of a predetermined number of bits, an address period for selecting the pixels, and the selected pixels as the bits In a display method of generating a display image from the input image and performing gradation display in the processing of a subfield consisting of a display period that emits light for a time corresponding to the weight of data,
A first number for extracting a predetermined number of higher-order bits based on respective image data of the first frame of frame number (2n-1) and the second frame of frame number 2n in the input video , where n is a natural number . And the steps
A second step of summing the image data of the first and second frames successive in the input image,
The lower-order bits of the first predetermined position and the second predetermined position from the image data obtained by subtracting the image data including the upper bits extracted in the first step from the image data added in the second step A third step of extracting
A fourth step of combining the predetermined number of upper bits extracted from the first frame by the first step and the lower bits at the first predetermined position extracted by the third step;
A fifth step of combining the predetermined number of upper bits extracted from the second frame in the first step and the lower bits in the second predetermined position extracted in the third step;
A sixth step of outputting image data of two consecutive frames synthesized by the fourth step and the fifth step as a display video;
A display method characterized by comprising:   A display program for causing a computer to function as the display device according to any one of claims 1 to 4.

Images