JP5774458B2 - Semiconductor memory and system - Google Patents

Description

  The present invention relates to a semiconductor memory and a system in which the semiconductor memory is mounted.

  There has been proposed a semiconductor memory that detects that a dummy bit line having a charge-up characteristic equivalent to that of a bit line is precharged to a predetermined voltage when the memory cell is accessed, and stops the operation of the bit line precharge circuit. (For example, refer to Patent Document 1-2.)

  There has been proposed a semiconductor memory that determines the operation timing of a sense amplifier or the like according to data read from a dummy memory cell to a dummy bit line when accessing the memory cell (see, for example, Patent Document 2).

  In order to quickly precharge the internal node when the power supply voltage is turned on, a method has been proposed in which charging means having a low charging speed and charging means having a high charging speed are sequentially operated (see, for example, Patent Document 3).

JP-A-1-40437 JP 2002-260384 A JP-A-10-255464

  For example, in a semiconductor memory having a second mode in which memory cell access is permitted and a first mode in which memory cell access is prohibited, bit line precharging is performed during the first mode in order to reduce power consumption. Is stopped. In this type of semiconductor memory, it is necessary to precharge the bit line in a minimum time after returning from the first mode to the second mode in order to improve access efficiency.

  An object of the present invention is to improve the access efficiency by precharging the bit line in a minimum time when returning from the first mode to the second mode where the precharging of the bit line is stopped.

  In one embodiment of the present invention, the semiconductor memory is supplied to the first power supply line by entering a floating state during the first mode in which the real memory cell and the real memory cell are connected and access to the real memory cell is prohibited. The real bit line set to an intermediate voltage between the power supply voltage and the ground voltage, and the connection between the first power supply line and the real bit line during the first mode are released, and access to the real memory cell is permitted. A first precharge circuit for connecting the first power supply line to the real bit line during the second mode; a dummy bit line having the same load as the load of the real bit line; and the first power supply line and the dummy bit during the first mode A second precharge circuit that disconnects the line and connects the first power supply line to the dummy bit line during the second mode, and a reset that sets the dummy bit line to the ground voltage during the first mode. And when the voltage of the dummy bit line rising from the ground voltage by the operation of the second precharge circuit exceeds the intermediate voltage at the time of switching from the first mode to the second mode, the mode is returned to the second mode. And a detection circuit for activating a detection signal indicating the above.

  When returning from the first mode to the second mode, the bit line can be precharged in a minimum time, and access efficiency can be improved.

1 illustrates an example of a semiconductor memory in one embodiment. 2 shows an example of the operation of the semiconductor memory shown in FIG. The example of the semiconductor memory in another embodiment is shown. 4 illustrates an example of a main part of the semiconductor memory illustrated in FIG. 3. 5 shows an example of electrical characteristics of the inverter IV3 shown in FIG. 4 shows an example of an entire block of the semiconductor memory shown in FIG. 4 shows an example of the operation of the semiconductor memory shown in FIG. 4 shows another example of the operation of the semiconductor memory shown in FIG. 4 shows another example of the operation of the semiconductor memory shown in FIG. 3 shows another example of a semiconductor memory. 11 shows an example of the operation of the semiconductor memory shown in FIG. 11 shows another example of the operation of the semiconductor memory shown in FIG. The example of the semiconductor memory in another embodiment is shown. 14 shows an example of a main part of the semiconductor memory shown in FIG. An example of a system in which the above-described semiconductor memory is mounted is shown.

  Hereinafter, embodiments will be described with reference to the drawings. The same reference numerals as the signal names are used for signal lines through which signals are transmitted. A signal with “X” at the end indicates negative logic. Double square marks indicate external terminals. The external terminal is, for example, a semiconductor macro terminal, a pad on a semiconductor chip, or a lead of a package in which the semiconductor chip is accommodated. For the signal supplied via the external terminal, the same symbol as the terminal name is used.

  FIG. 1 shows an example of a semiconductor memory MEM in one embodiment. For example, the memory cell MC is an SRAM (Static Random Access Memory) memory cell. The semiconductor memory MEM may operate in synchronization with the clock signal or may operate asynchronously with the clock signal. The semiconductor memory MEM includes a memory cell MC, a bit line BIT connected to the memory cell MC, a dummy bit line DBIT, a load LD connected to the dummy bit line DBIT, precharge circuits PRE1 and PRE2, a reset circuit RST, and a detection circuit DETC. have. The memory cell MC is an example of a real memory cell. The bit line BIT is an example of a real bit line. A plurality of memory cells MC may be connected to the bit line BIT.

  The load LD is provided to make the load of the dummy bit line DBIT the same as the load of the bit line BIT. For example, the load LD is formed by connecting a dummy memory cell having the same structure as the memory cell MC to the dummy bit line DBIT. Alternatively, the load LD is formed by connecting a transistor having the same size as the transfer transistor in the memory cell MC to the dummy bit line DBIT.

  The precharge circuit PRE1 is arranged between the power supply line VDD and the bit line BIT. The precharge circuit PRE1 stops its operation when the mode signal MD indicates the first mode, releases the connection between the power supply line VDD and the bit line BIT, and stops the supply of the power supply voltage VDD to the bit line BIT. The precharge circuit PRE1 connects the power supply line VDD to the bit line BIT and supplies the power supply voltage VDD to the bit line BIT when the mode signal MD received at the mode terminal indicates the second mode.

  Here, the first mode and the second mode are operation modes of the semiconductor memory MEM. The first mode is an operation mode in which access to the memory cell MC is prohibited, for example, a sleep mode or a low power mode. The second mode is an operation mode in which access to the memory cell MC is permitted, for example, a normal mode. For example, the semiconductor memory MEM transitions to the first mode when the mode signal MD is at a low level, and transitions to the second mode when the mode signal MD is at a high level.

  The precharge circuit PRE2 is arranged between the power supply line VDD and the dummy bit line DBIT. The precharge circuit PRE2 stops operating when the mode signal MD indicates the first mode, disconnects the power supply line VDD and the dummy bit line DBIT, and stops supplying the power supply voltage VDD to the dummy bit line DBIT. To do. The precharge circuit PRE2 connects the power supply line VDD to the dummy bit line DBIT and supplies the power supply voltage VDD to the dummy bit line DBIT when the mode signal MD indicates the second mode.

  The reset circuit RST sets the dummy bit line DBIT to the ground line VSS when the mode signal MD indicates the first mode. The reset circuit RST releases the connection between the dummy bit line DBIT and the ground line VSS when the mode signal MD indicates the second mode.

  The detection circuit DETC detects when the voltage of the dummy bit line DBIT set to the ground voltage VSS rises to the voltage VDD / 2 by the operation of the precharge circuit PRE2 when switching from the first mode to the second mode. Activate the signal DETX. For example, the detection circuit DETC has a CMOS inverter whose input is connected to the dummy bit line DBIT. The voltage VDD / 2 is an intermediate voltage between the power supply voltage VDD and the ground voltage VSS. The activation of the detection signal DETX indicates that the access operation (read operation and write operation) can be performed after switching from the first mode to the second mode. The detection signal DETX is supplied to a circuit that controls the access operation. The detection signal DETX may be output to a controller (such as the CPU in FIG. 15) that accesses the semiconductor memory MEM in order to notify that the access operation can be executed.

  FIG. 2 shows an example of the operation of the semiconductor memory MEM shown in FIG. A shaded frame indicates a period in which each of the precharge circuits PRE1 and PRE2 operates. The first mode is indicated by reference sign MD1, and the second mode is indicated by reference sign MD2. In FIG. 2, the read operation and the write operation executed during the second mode MD2 are not shown. For this reason, the voltage of the bit line BIT is maintained at the power supply voltage VDD during the second mode MD2.

  The precharge circuit PRE1 operates during the second mode MD2, and precharges the bit line BIT to the power supply voltage VDD (FIG. 2 (a)). The second mode MD2 includes a return period RET in which the voltage of the bit line BIT returns from the intermediate voltage VDD / 2 to the power supply voltage VDD. The return period RET is a period from when the mode signal MD changes to high level to when the detection signal DETX is activated to low level.

  The precharge circuit PRE2 operates during the second mode MD2 in order to precharge the dummy bit line DBIT to the power supply voltage VDD (FIG. 2B). The detection circuit DETC sets the detection signal DETX to the low level during the high level period of the dummy bit line DBIT (FIG. 2 (c)).

  When the state of the semiconductor memory MEM transitions from the second mode MD2 to the first mode MD1, the precharge circuits PRE1 and PRE2 stop operating (FIG. 2 (d, e)). Due to the stop of the precharge circuit PRE1, the bit line BIT enters a floating state. The electric charge on the bit line BIT gradually decreases through the leak path on the ground line VSS side, and the voltage of the bit line BIT gradually decreases (FIG. 2 (f)). However, since there is a leak path on the power supply line VDD side in the floating bit line BIT, the voltage of the bit line BIT is finally set to a voltage VDD / 2 intermediate between the power supply voltage VDD and the ground voltage VSS. (FIG. 2 (g)).

  Due to the stop of the precharge circuit PRE2, the dummy bit line DBIT becomes a floating state and is set to the ground voltage VSS by the reset circuit RST (FIG. 2 (h)). Note that the reset circuit RST may be formed by a high resistance disposed between the dummy bit line DBIT and the ground line VSS. In this case, the voltage decrease rate of the dummy bit line DBIT becomes slower than that in FIG. The detection circuit DETC deactivates the detection signal DETX to the high level in response to the change of the dummy bit line DBIT to the low level (FIG. 2 (i)).

  Next, when the mode signal MD changes from the low level to the high level, the state of the semiconductor memory MEM changes from the first mode MD1 to the second mode MD2 (FIG. 2 (j)). In the return period RET at the time of switching from the first mode MD1 to the second mode, the precharge circuits PRE1 and PRE2 start operating upon receiving the high-level mode signal MD.

  The bit line BIT rises from the intermediate voltage VDD / 2 to the power supply voltage VDD by the operation of the precharge circuit PRE1 (FIG. 2 (k)). The dummy bit line DBIT rises from the ground voltage VSS to the power supply voltage VDD by the operation of the precharge circuit PRE2 (FIG. 2 (l)). Here, the load LD of the dummy bit line DBIT is equal to the load of the bit line BIT, and the driving capabilities of the precharge circuits PRE1 and PRE2 are equal to each other. The drive capability is the power supply capability to the bit line BIT or the dummy bit line DBIT, and indicates the magnitude of the power supply current that can be supplied to the bit line BIT or the dummy bit line DBIT. For this reason, the voltage rising speed (waveform slope) of the bit line BIT and the dummy bit line DBIT are equal to each other.

  Therefore, when the voltage of the dummy bit line DBIT rises from the ground voltage VSS to the intermediate voltage VDD / 2, the voltage of the bit line BIT rises from the intermediate voltage VDD / 2 to the power supply voltage VDD. That is, the voltage of the bit lines BIT and BITX can be monitored using the dummy bit line DBIT whose voltage is lower than that of the bit line BIT. As a result, it is possible to detect that the bit line BIT has been precharged to the power supply voltage VDD using a simple detection circuit DETC such as a CMOS inverter.

  The detection circuit DETC activates the detection signal DETX to low level when the voltage of the dummy bit line DBIT rises to the intermediate voltage VDD / 2 (FIG. 2 (m)). At the time when the detection signal DETX is activated, the voltage of the bit line BIT has increased to the power supply voltage VDD by the operation of the precharge circuit PRE1. For this reason, the semiconductor memory MEM can start an access operation immediately after the detection signal DETX is activated. In other words, the semiconductor memory MEM can start an access operation in a minimum time after the voltage of the bit line BIT rises to the power supply voltage VDD.

  For example, when the threshold voltage of a transistor or the like varies due to variations in manufacturing conditions of the semiconductor memory MEM, the electrical characteristics of the precharge circuits PRE1 and PRE2 change with the same tendency. For this reason, the rising speed of the voltage of the bit line BIT and the dummy bit line DBIT does not deviate even when the manufacturing conditions fluctuate. Even when the wiring width and film thickness of the bit line BIT and the dummy bit line DBIT change due to the change in the manufacturing conditions, the voltage rise rate of the bit line BIT and the dummy bit line DBIT does not deviate. Furthermore, when the power supply voltage VDD varies or the operating temperature varies, the electrical characteristics of the precharge circuits PRE1 and PRE2 change with the same tendency. Therefore, the rising speed of the voltages of the bit line BIT and the dummy bit line DBIT It will not come off. As a result, even if the return period RET until the precharge of the bit line BIT is changed due to a change in manufacturing conditions or the like, the access operation can always be started in a minimum time according to this change.

  As described above, in this embodiment, the time from the return from the first mode MD1 to the second mode MD2 until the memory cell MC can be accessed can be minimized, and the access efficiency of the semiconductor memory MEM can be improved.

  FIG. 3 shows an example of a semiconductor memory MEM in another embodiment. The same elements as those described in the above-described embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted. For example, the semiconductor memory MEM is an SRAM. The semiconductor memory MEM may operate in synchronization with the clock signal or may operate asynchronously with the clock signal.

  The semiconductor memory MEM includes a plurality of memory blocks BLK (BLK1 to BLK4), a buffer circuit PBUF corresponding to each of the memory blocks BLK1 to BLK4, a dummy circuit DMY, inverters IV1, IV2, and IV3 and pMOS transistors P1 and P3. . For example, each of the memory blocks BLK1 to BLK4 has an area for storing data received at a 16-bit data terminal I / O (I / O1-I / O16). The number of memory blocks BLK and the number of data terminals I / O are not limited to the numbers shown in FIG.

  In the read operation and the write operation, one of the memory blocks BLK1 to BLK4 is selected according to a block address supplied from the outside of the semiconductor memory MEM. The read operation and the write operation are executed during the normal mode in which the sleep signal SLPX received at the sleep terminal is deactivated to a high level. The sleep signal is an example of a mode signal for setting the semiconductor memory MEM to the normal mode or the sleep mode. The memory blocks BLK1 to BLK4 are the same circuits as each other except that the block addresses are assigned differently. Therefore, hereinafter, the memory block BLK1 will be described.

  The memory block BLK1 includes a plurality of memory cells MC arranged in a matrix, a precharge circuit PRE connected to a column of memory cells MC arranged in the vertical direction in FIG. 3 (hereinafter also referred to as a memory cell column), a column switch CSW. And a sense amplifier SA. The memory cell column, the precharge circuit PRE, and the column switch CSW are connected to each other by a complementary bit line pair BIT, BITX. In this example, one of data terminals I / O1-I / O16 is assigned to every four memory cell columns. An example of the memory cell MC is shown in FIG. Bit lines BIT and BITX are examples of real bit lines.

  Four memory cell columns and four column switches CSW corresponding to each data terminal I / O1-I / O16 are selected according to a column selection signal COLX (COL1X-COL4X). The sense amplifier SA operates during a read operation, amplifies the voltage difference between the bit line pair BIT, BITX connected to the column switch CSW selected according to the column selection signal COLX, and reads data I / O1-I / O16. Is generated. Note that the sense amplifier SA may generate read data by using one voltage of the bit line pair BIT, BITX.

  Since the four buffer circuits PBUF are the same circuit, the buffer circuit PBUF corresponding to the memory block BLK1 will be described. In FIG. 3, the column selection signals COL1X-COL4X having the same sign are supplied to the four buffer circuits PBUF. Actually, the column selection signals COL1X-COL4X are used to identify the memory blocks BLK1-BLK4. Contains block address logic. Therefore, the column selection signals COL1X-COL4X supplied to the four buffer circuits PBUF are different from each other.

  The buffer circuit PBUF has four NAND gates each receiving a column selection signal COLX (COL1X-COL4X). Each NAND gate deactivates the corresponding precharge signal PREX (PRE1X-PRE4X) to a high level when receiving the low level sleep signal SLPX or the low level column selection signal COLX. By deactivation of the precharge signal PREX, the precharge operation of the corresponding bit line pair BIT, BITX is stopped. In the read operation or the write operation, one of the column selection signals COL1X is activated, the corresponding precharge signal PREX is deactivated, and read data or write data is transmitted to the bit line pair BIT and BITX that are in a floating state. The Note that the number of memory cell columns and the number of column selection signals COLX are not limited to the numbers shown in FIG. The buffer circuits PBUF may be formed in the memory blocks BLK1 to BLK4, respectively.

  The dummy circuit DMY has a plurality of dummy memory cells DMC connected to the dummy bit line DBIT. The length of the dummy bit line DBIT is the same as the length of the bit line BIT, and the structure (wiring width, film thickness, material, wiring layer, etc.) of the dummy bit line DBIT is the same as the structure of the bit line BIT. For example, the structure (transistor size, threshold voltage, film thickness, material, wiring layer, etc.) of the dummy memory cell DMC is the same as that of the memory cell MC, and the electrical characteristics of the dummy memory cell DMC are as follows. It is equal to the electrical characteristics of MC. The number of dummy memory cells DMC is the same as the number of memory cells MC arranged in one memory cell column. Thereby, the load of the dummy bit line DBIT can be made the same as the load of the bit line BIT. The dummy bit line DBIT has one end connected to the output of the inverter IV2 and the other end connected to the input of the inverter IV3.

  For example, the dummy circuit DMY is formed in the memory cell array together with the memory blocks BLK1 to BLK4. In this example, the dummy memory cell DMC is formed using a dummy memory cell column arranged outside the memory cell column located at the right end of the memory block BLK4. Similarly, the dummy bit line DBIT is a dummy bit line connected to the dummy memory cell column. The dummy memory cell columns are formed around the memory cell array in order to make the wiring of the memory cells MC and the shape of the diffusion layer uniform. By forming the dummy memory cell DMC using the dummy memory cell column, it is possible to prevent the area of the semiconductor memory MEM from increasing.

  Examples of the memory cell MC and the dummy memory cell DMC are shown in FIG. Instead of the dummy memory cell DMC, a transistor having the same size as the transfer transistor in the memory cell MC may be formed and connected to the dummy bit line DBIT.

  Inverter IV1 inverts the logic of sleep signal SLPX and outputs it to the gate of pMOS transistor P1 and the input of inverter IV2. The pMOS transistor P1 turns on during the normal mode (sleep signal SLPX = high level) to connect the power supply line VDD to the power supply line VDD2, and turns off during the sleep mode (sleep signal SLPX = low level) to turn off the power supply line VDD2 and the power supply. Disconnect line VDD. The sleep mode is an example of a first mode in which access to the memory cell MC is prohibited. The normal mode is an example of a second mode in which access to the memory cell MC is permitted and a read operation and a write operation are performed. In the sleep mode, the precharge operation of the bit lines BIT and BITX is prohibited, and the bit lines BIT and BITX are in a floating state. Thereby, in the sleep mode, the power consumption of the semiconductor memory MEM can be reduced as compared with the standby state in which the read operation and the write operation are not performed in the state where the bit lines BIT and BITX are precharged.

  The inverter IV2 has a pMOS transistor P2 and an nMOS transistor N2. The inverter IV2 turns on the nMOS transistor N2 during the normal mode, and connects the dummy bit line DBIT to the ground line VSS. The inverter IV2 turns on the pMOS transistor P2 and connects the dummy bit line DBIT to the power supply line VDD during the sleep mode. The nMOS transistor N2 of the inverter IV2 is an example of a reset circuit that sets the dummy bit line DBIT to the ground voltage VSS during the sleep mode. The reset circuit may be formed by a high resistance arranged between the dummy bit line DBIT and the ground line VSS instead of the nMOS transistor N2.

  Inverter IV3 receives the voltage on the other end side of dummy bit line DBIT, and outputs a sleep cancel signal SLPOUTX. The sleep release signal SLPOUTX is set to a low level when the voltage of the dummy bit line DBIT is high, and is set to a high level when the voltage of the dummy bit line DBIT is low.

  The pMOS transistor P3 is turned on when the sleep cancel signal SLPOUTX is activated to the low level, and connects the power supply line VDD to the power supply line VDD2. The pMOS transistor P3 is turned off when the sleep cancel signal SLPOUTX is inactivated to a high level, and disconnects the power supply line VDD and the power supply line VDD2.

  In this example, the driving capability of the pMOS transistor P2 is lower than the driving capability of the pMOS transistor P1. The driving capability of the pMOS transistors P1 and P2 is such that the charging speed of the dummy bit line DBIT charged by the pMOS transistor P2 is equal to the charging speed of the bit lines BIT and BITX of the memory blocks BLK1 to BLK4 charged by the pMOS transistor P1. Designed to be

  The driving capability of the pMOS transistor P1 is lower than the driving capability of the pMOS transistor P3. When returning from the sleep mode to the normal mode, the bit lines BIT and BITX in the floating state are precharged using the pMOS transistor P1 having a relatively low driving capability. For this reason, even when all the memory blocks BLK1 to BLK4 are precharged at the same time, it is possible to prevent the power supply current from increasing rapidly and to prevent the generation of power supply noise.

  The driving capability of the pMOS transistors P1 and P2 is increased by increasing the ratio W / L of the gate width W to the channel length L, and is decreased by decreasing the ratio W / L. The pMOS transistor P3 having a high driving capability is used for the precharge operation of the bit line pair BIT and BITX after the access operation executed during the normal mode. The pMOS transistor P3 having high driving capability may be formed by connecting a plurality of transistors in parallel. At this time, the pMOS transistor P3 may be arranged for each of the memory blocks BLK1 to BLK4, or the pMOS transistor P3 may be arranged for each predetermined number of memory cell examples. Similarly, the pMOS transistor P2 may be formed by connecting a plurality of transistors in parallel.

  FIG. 4 shows an example of a main part of the semiconductor memory MEM shown in FIG. 4 shows a precharge circuit PRE, a memory cell MC, and a bit line pair BIT, BITX arranged at the right end of the memory block BLK4 of FIG. The precharge circuit PRE includes pMOS transistors P4 and P5 that connect the power supply line VDD2 to the bit lines BIT and BITX, respectively, and a pMOS transistor P6 that connects the bit line pair BIT and BITX to each other.

  The pMOS transistors P4, P5, and P6 are turned on when the gate receives the low-level precharge signal PRE4X, and supplies the power supply voltage VDD2 to the bit line pair BIT and BITX. The pMOS transistors P4, P5, and P6 are turned off when the gate receives the high-level precharge signal PRE4X. That is, the precharge circuit PRE is turned off during the sleep mode (SLPX = low level) and when the memory cell column is selected during the normal mode (COL4X = low level), and the memory cell column is selected during the normal mode. Turns on when not present (COL4X = high level).

  The memory cell MC is a general SRAM memory cell, and includes load transistors L1 and L2, drive transistors D1 and D2, and transfer transistors T1 and T2. The load transistors L1 and L2 and the drive transistors D1 and D2 form a latch. A pair of input / output nodes of the latch are connected to the bit lines BIT and BITX via the transfer transistors T1 and T2, respectively.

  In this example, each memory cell column has 512 memory cells MC connected to 512 word lines WL (WL1 to WL512). Note that the number of word lines WL is not limited to 512. When the semiconductor memory MEM is formed as a macro, the number of word lines WL varies depending on user specifications using the semiconductor memory MEM. As the number of word lines WL increases, the number of memory cells MC connected to the bit lines BIT and BITX increases, the bit lines BIT and BITX become longer, and the load (load capacitance and wiring resistance) of each bit line BIT and BITX. Becomes bigger.

  In the dummy memory cell DMC, except that the gates of the transfer transistors T1 and T2 are connected to the ground line VSS instead of the word line WL, and the transfer transistors T1 and T2 are connected to the dummy bit lines DBIT and DBITX. The same as the memory cell MC. In other words, the dummy memory cell DMC is formed using the same layout data as the memory cell MC except for the wiring pattern. Since the dummy memory cell DMC is laid out adjacent to the memory cell MC, the electrical characteristics of the dummy memory cell DMC are the same as the electrical characteristics of the memory cell MC. The number of dummy memory cells DMC is 512, which is the same as the number of memory cells MC. As a result, the load on the dummy bit line DBIT becomes the same as the load on each bit line BIT, BITX.

  In FIG. 4, a pMOS transistor P1 is an example of a first transistor. The pMOS transistor P3 is an example of a second transistor. Each of the pMOS transistors P4 and P5 is an example of a third transistor. The pMOS transistors P1, P4 and the pMOS transistors P1, P5 are an example of a first precharge circuit. The pMOS transistor P2 is an example of a second precharge circuit. The pMOS transistors P3 and P4 or the pMOS transistors P3 and P5 are an example of a third precharge circuit. That is, the pMOS transistors P4 and P5 are elements common to the first precharge circuit and the third precharge circuit.

  FIG. 5 shows an example of electrical characteristics of the inverter IV3 shown in FIG. For example, the inverter IV3 is a CMOS inverter having a pMOS transistor and an nMOS transistor. The inverter IV3 changes the output voltage VOUT from the high level to the low level when the input voltage VIN exceeds the intermediate voltage VDD / 2 between the power supply voltage VDD and the ground voltage VSS. The inverter IV3 changes the output voltage VOUT from the low level to the high level when the input voltage VIN becomes lower than the intermediate voltage VDD / 2. When a detection circuit is formed by connecting a plurality of inverters including the inverter IV3 in series, the inverter IV3 is arranged in the first stage and connected to the other end side of the dummy bit line DBIT.

  FIG. 6 shows an example of the entire block of the semiconductor memory MEM shown in FIG. The semiconductor memory MEM has memory blocks BLK1-BLK4, a dummy circuit DMY, a word decoder WDEC, a column decoder CDEC, and control circuits CNT1-CNT4. The memory blocks BLK1 to BLK4 have a memory cell array MCA, a precharge unit PREU, a column switch unit CSWU, and a sense amplifier unit SAU. Memory cell array MCA includes memory cells MC arranged in a matrix. The precharge unit PREU includes the precharge circuit PRE and the buffer circuit PBUF shown in FIG. The column switch unit CSWU includes the column switch CSW shown in FIG. The sense amplifier unit SAU includes the sense amplifier SA shown in FIG.

  In the read operation and the write operation, the word decoder WDEC selects one of the word lines WL shown in FIG. 4 according to the address signal received at the address terminal, and sets the selected word line WL to the high level. In the read operation and the write operation, the column decoder CDEC activates one of the column selection signals COLX shown in FIG. 3 according to the address signal received at the address terminal in order to select the memory cell MC to be accessed.

  For example, the control circuit CNT1 has a buffer that receives the sleep signal SLPX. For example, the control circuit CNT2 has a command decoder that decodes the command signal CMD received at the command terminal, and generates a timing signal for executing a read operation or a write operation. For example, the control circuit CNT3 includes inverters IV1 and IV2 and pMOS transistors P1 and P3 shown in FIG. For example, the control circuit CNT4 includes the inverter IV3 shown in FIG. 3 and a data input / output circuit that outputs or inputs a data signal to the data terminal I / O. The data terminals may be formed separately for output and input.

  FIG. 7 shows an example of the operation of the semiconductor memory MEM shown in FIG. Detailed descriptions of the same operations as those in FIG. 2 are omitted. FIG. 7 shows an operation when the number of word lines WL is large (for example, 512). The normal mode is indicated by a symbol NRM, and the sleep mode is indicated by a symbol SLP.

  Since the pMOS transistor P2 shown in FIG. 3 is turned on during the normal mode NRM, the dummy bit line DBIT is set to the high level (FIG. 7A). When the sleep signal SLPX changes from the high level to the low level, the semiconductor memory MEM shifts from the normal mode NRM to the sleep mode SLP (FIG. 7B). As a result, the pMOS transistors P1 and P2 shown in FIG. 3 are turned off and the nMOS transistor N2 is turned on.

  As the nMOS transistor N2 is turned on, the dummy bit line DBIT is reset from the high level to the low level (FIG. 7C). The voltage drop rate of the dummy bit line DBIT depends on the driving capability of the nMOS transistor N2. Inverter IV3 receives the low level of dummy bit line DBIT and changes sleep cancel signal SLPOUTX from the low level to the high level (FIG. 7 (d)).

  The pMOS transistor P3 shown in FIG. 3 receives the high level sleep cancel signal SLPOUTX and is turned off. By turning off the pMOS transistors P1, P2, and P3, the bit line pair BIT and BITX are in a floating state, and gradually fall to the intermediate voltage VDD / 2 (FIG. 7E). The reason why the voltage drops to the intermediate voltage VDD / 2 is the same as that described in FIG. During the sleep mode SLP, the power supply line VDD2 is also in a floating state. However, since the pMOS transistors P1 and P3 that are turned off function as a high resistance whose resistance value is very high, the power supply line VDD2 has a smaller voltage drop amount than the bit line pair BIT and BITX (FIG. 7 ( f)).

  Thereafter, in order to return to the normal mode NRM, the sleep signal SLPX is changed to a high level, and the state of the semiconductor memory MEM transits to the return period RET (FIG. 7 (g)). The pMOS transistors P1 and P2 are turned on almost simultaneously by the high level sleep signal SLPX, and the precharge operation of the bit lines BIT and BITX and the dummy bit line DBIT is started. The bit line pair BIT, BITX gradually rises from the intermediate voltage VDD / 2 to the power supply voltage VDD, and the dummy bit line DBIT gradually rises from the ground voltage VSS to the power supply voltage VDD (FIG. 7 (h, i)). ).

  As in FIG. 2, the voltage rising speeds (waveform slopes) of the bit lines BIT and BITX and the dummy bit line DBIT are equal to each other. Therefore, when the voltage of the dummy bit line DBIT rises from the ground voltage VSS to the intermediate voltage VDD / 2, the voltage of the bit line BIT rises from the intermediate voltage VDD / 2 to the power supply voltage VDD. That is, the voltage of the bit lines BIT and BITX can be monitored using the dummy bit line DBIT having a voltage different from that of the bit lines BIT and BITX. As a result, it is possible to detect that the bit lines BIT and BITX are precharged up to the power supply voltage VDD using the simple inverter IV3.

  Note that when the sleep signal SLPX changes to a high level, the pMOS transistors P4, P5, and P6 of the precharge circuit PRE shown in FIG. 4 are turned on. However, since the pMOS transistor P3 is off during the return period RET, the precharge operation of the bit lines BIT and BITX is executed only through the pMOS transistor P1. By turning off the pMOS transistor P3 having a high driving capability during the return period RET, the bit lines BIT and BITX can be prevented from being precharged abruptly, and the generation of power supply noise can be prevented. Furthermore, by connecting the pMOS transistors P1 and P3 in parallel between the power supply line VDD and the precharge circuit PRE, the semiconductor memory MEM can be designed using the existing precharge circuit PRE.

  In FIG. 7, the three waveforms respectively shown for the dummy bit line DBIT, the bit lines BIT, BITX, and the sleep release signal SLPOUTX indicate at least one of a change in manufacturing conditions of the semiconductor memory MEM, a change in power supply voltage VDD, and a change in operating temperature. This shows the change in timing. The earliest waveform shows the timing when the threshold voltage of the transistor is relatively low, when the power supply voltage VDD is relatively high, when the operating temperature is relatively low, or when these multiple conditions overlap. ing. Conversely, the slowest waveform is when the threshold voltage of the transistor is relatively high, when the power supply voltage VDD is relatively low, when the operating temperature is relatively high, or when these multiple conditions overlap. Timing is shown. The middle waveform shows the standard timing.

  The inverter IV3 shown in FIG. 3 has the electrical characteristics shown in FIG. 5, and activates the sleep release signal SLPOUTX to a low level when the voltage of the dummy bit line DBIT rises to the intermediate voltage VDD / 2. (FIG. 7 (j)). The activation of the sleep release signal SLPOUTX determines that the voltages of the bit lines BIT and BITX have increased to the power supply voltage VDD, the return period RET ends, and the access operation can be performed. In FIG. 7, the worst condition in which the activation timing of the sleep release signal SLPOUTX is the latest is the end timing of the return period RET. The end timing of the return period RET under the worst condition is obtained by circuit simulation or evaluation of electrical characteristics of the semiconductor memory MEM. For example, the worst return period RET is used as a setup time (timing specification of the semiconductor memory MEM) until the access operation of the semiconductor memory MEM can be executed after the sleep mode SLP is released.

  The pMOS transistor P3 is turned on in response to the activation of the sleep cancel signal SLPOUTX. The pMOS transistor P3 having a high driving capability is used for the precharge operation of the bit lines BIT and BITX after the read operation or the write operation. By turning on the pMOS transistor P3 at the end of the return period RET, the ability to precharge the bit lines BIT and BITX can be changed between the return period RET and the subsequent access operation. That is, in the return period RET in which all the bit lines BIT and BITX are precharged simultaneously, the precharge operation can be executed using only the pMOS transistor P1 having a low driving capability. On the other hand, in the normal mode NRM in which only the accessed bit lines BIT and BITX are precharged, the precharge operation can be executed using the pMOS transistor P3 and the pMOS transistor P3 having high driving capability. As a result, it is possible to quickly execute the precharge operation during the access operation while suppressing generation of power supply noise during the return period RET.

  As in FIG. 2, when the sleep release signal SLPOUTX is activated, the voltages of the bit lines BIT and BITX are increased to the power supply voltage VDD by the operation of the pMOS transistor P1. For this reason, the semiconductor memory MEM can start an access operation immediately after the sleep release signal SLPOUTX is activated. Therefore, the setup time corresponding to the return period RET can be minimized, and the access efficiency of the semiconductor memory MEM can be improved.

  Note that the sleep release signal SLPOUTX may be output to a controller (such as the CPU in FIG. 15) that accesses the semiconductor memory MEM in order to notify that the access operation can be executed.

  FIG. 8 shows another example of the operation of the semiconductor memory MEM shown in FIG. Detailed descriptions of the same operations as those in FIGS. 2 and 7 are omitted. FIG. 8 shows an operation when the number of word lines WL is small (for example, 128). When the number of word lines WL is small, the number of memory cells MC connected to the bit lines BIT and BITX is reduced, and the bit lines BIT and BITX are shortened. For this reason, the load (load capacitance or wiring resistance) of each bit line BIT, BITX is relatively small. Similarly, the load on the dummy bit line DBIT is also relatively reduced. Therefore, in the return period RET, the rising speed of the voltages of the bit lines BIT, BITX and the dummy bit line DBIT is increased, and the return period RET is shortened (FIG. 8 (a, b)). The waveforms excluding the return period RET are the same as those in FIG.

  In this embodiment, the setup time (timing specification) from when the sleep mode SLP is released until the access operation of the semiconductor memory MEM becomes executable is determined according to the return period RET depending on the number of word lines WL. Is possible. In particular, when the semiconductor memory MEM is formed as a macro, for example, every time the number of word lines WL is increased by 64, the setup time can be increased in order. At this time, the setup time is set based on the return period RET when the number of word lines WL is the maximum (64, 128, 192, etc.). As a result, the semiconductor memory MEM can be efficiently accessed with a minimum setup time in accordance with the number of word lines WL.

  FIG. 9 shows another example of the operation of the semiconductor memory MEM shown in FIG. In this example, the period of the sleep mode SLP is shorter than that in FIG. 7, and when the state of the semiconductor memory MEM transitions from the sleep mode SLP to the normal mode NRM, the voltages of the bit lines BIT and BITX are set to the intermediate voltage VDD / Higher than 2. The other operations are the same as those in FIG. 7 except that the time until the voltage of the bit lines BIT and BITX changes to the power supply voltage VDD is early in the return period RET.

  When the period of the sleep mode SLP is short and the voltages of the bit lines BIT and BITX are higher than the intermediate voltage VDD / 2, the voltages of the bit lines BIT and BITX rise to the power supply voltage VDD during the return period RET. For this reason, the waveforms of the bit lines BIT and BITX during the return period RET are different from the waveforms of the dummy bit lines DBIT during the return period RET. However, since the voltages of the bit lines BIT and BITX are set to the power supply voltage VDD at the end of the return period RET, the access operation in the normal mode NRM is executed without any problem.

  FIG. 10 shows another example of the semiconductor memory MEM. FIG. 10 is a comparative example with the semiconductor memory MEM shown in FIG. The semiconductor memory MEM has a memory block BLK (BLK1-BLK4), a buffer circuit PBUF corresponding to each of the memory blocks BLK1-BLK4, and three delay circuits DLY. The memory blocks BLK1-BLK4 are the same as the memory blocks BLK1-BLK4 in FIG. 3 except that the precharge circuit PRE shown in FIG. 4 is connected to the power supply line VDD instead of the power supply line VDD2. The buffer circuit PBUF is the same as that in FIG.

  For example, each delay circuit DLY delays the rising edge received at the input terminal and outputs it to the output terminal, and outputs the falling edge received at the input terminal to the output terminal without delaying. The delay times of the rising edges of the delay circuits DLY are equal to each other. The delay time of the rising edge of each delay circuit DLY is set in accordance with the time until the bit lines BIT and BITX of each memory block BLK change from the intermediate voltage VDD / 2 to the power supply voltage VDD in the return period RET. . In each delay circuit DLY, two inverters are connected in series, but an even number of inverters may be connected in series.

  The buffer circuit PBUF corresponding to the memory block BLK2 receives the sleep signal SLP1X obtained by delaying the sleep signal SLPX by the delay circuit DLY1. The buffer circuit PBUF corresponding to the memory block BLK3 receives the sleep signal SLP2X obtained by delaying the sleep signal SLP1X by the delay circuit DLY2. The buffer circuit PBUF corresponding to the memory block BLK4 receives the sleep signal SLP3X obtained by delaying the sleep signal SLP2X by the delay circuit DLY3. Accordingly, the semiconductor memory MEM performs the precharge operation of the bit lines BIT and BITX for each of the memory blocks BLK1 to BLK4 in the return period RET after the sleep signal SLPX is deactivated to the high level.

  FIG. 11 shows an example of the operation of the semiconductor memory MEM shown in FIG. FIG. 11 shows an operation when the number of word lines WL is large (for example, 512). In FIG. 11, the delay time of the rising edge of the delay circuit DLY is indicated by the symbol DLY. In this example, the rising edge of the sleep signal SLPX is delayed by the delay time of the delay circuit DLY, and the sleep signals SLP1X, SLP2X, and SLP3X sequentially rise. For this reason, in the return period RET, the precharge operation of the bit lines BIT and BITX of the memory blocks BLK1 to BLK4 is sequentially performed.

  The three waveforms shown for the bit lines BIT, BITX and the sleep signals SLPX, SLP1X, SLP2X, SLP3X are the same as in FIG. The change of the timing by at least one is shown. The change in timing includes a change in the delay time of the delay circuit DLY.

  Since the precharge operation is executed in a distributed manner for each of the memory blocks BLK1 to BLK4 using the delay circuit DLY, the power supply current necessary for the precharge operation is distributed. For this reason, the precharge can be executed using only the precharge circuit PRE shown in FIG. 4 without using the pMOS transistor P1 having a low driving capability shown in FIG. 3 in the return period RET.

  On the other hand, the recovery period RET takes into account the fluctuation of the rise time to the power supply voltage VDD of the bit lines BIT and BITX of the memory blocks BLK1 to BLK4 and the fluctuation of the delay time of the delay circuit DLY, It is necessary to set the time after adding the delay time. For this reason, the return period RET is longer than that in FIG. 7, and the effect of improving the access efficiency of the semiconductor memory MEM is low.

  FIG. 12 shows another example of the operation of the semiconductor memory MEM shown in FIG. Detailed descriptions of the same operations as those in FIG. 11 are omitted. FIG. 12 shows an operation when the number of word lines WL is small (for example, 128). Since the number of word lines WL is small, the bit lines BIT and BITX are shortened, and the load on each bit line BIT and BITX is relatively reduced. Therefore, in the recovery period RET, the time for precharging the bit lines BIT and BITX from the intermediate voltage VDD / 2 to the power supply voltage VDD is shorter than that in FIG.

  However, the delay time of rising of the delay circuit DLY does not depend on the number of word lines WL and is fixed. Therefore, the period from the completion of the precharge operation of the bit lines BIT and BITX of the memory block BLK1 to the start of the precharge operation of the bit lines BIT and BITX of the memory block BLK2 includes a wasteful time. Similarly, the period from the completion of the precharge operation of the bit lines BIT and BITX of the memory block BLK2 to the start of the precharge operation of the bit lines BIT and BITX of the memory block BLK3 includes useless time. The period from the completion of the precharge operation of the bit lines BIT and BITX of the memory block BLK3 to the start of the precharge operation of the bit lines BIT and BITX of the memory block BLK4 includes useless time. As a result, when the number of word lines WL is small, the return period RET is reduced only by a decrease in the precharge time of the bit lines BIT and BITX of the memory block BLK4.

  As described above, also in this embodiment, the same effect as that of the above-described embodiment can be obtained. Furthermore, even when the number of word lines WL is different, the return period RET can be set to the minimum according to the load of the bit lines BIT and BITX, and the semiconductor memory MEM can be efficiently accessed with the minimum setup time.

  Further, by providing a pMOS transistor P3 having a high driving capability for precharging the bit lines BIT and BITX during the access operation separately from the pMOS transistor P1, the bit lines BIT and BITX are set at an optimum speed during the return period RET. Can be precharged. As a result, while suppressing generation of power supply noise during the return period RET, the precharge operation during the access operation can be quickly performed, and access efficiency can be improved.

  FIG. 13 shows an example of a semiconductor memory MEM in another embodiment. Detailed description of the same elements as those in FIG. 3 is omitted. The memory blocks BLK1-BLK4 and the dummy circuit DMY are the same as those in FIG. In this embodiment, the buffer circuit PBUF corresponding to each of the memory blocks BLK1 to BLK4 operates in response to the sleep cancel signal SLPOUTX instead of the sleep signal SLPX. Similar to FIG. 3, the column selection signals COL1X-COL4X supplied to the buffer circuit PBUF include the logic of the block address, and are different for each memory block BLK1-BLK4.

  The sleep signal SLPX is directly supplied to each of the memory blocks BLK1 to BLK4. The pMOS transistor P1 shown in FIG. 3 is formed inside the precharge circuit PRE with a low driving capability. The pMOS transistor P3 shown in FIG. 3 is deleted, and the precharge circuit PRE functions instead of the pMOS transistor P3. Other configurations in the state of the semiconductor memory MEM are the same as those in FIG. 3 except that the inverters IV4, IV5, and IV6 are connected in series to the output of the inverter IV3.

  FIG. 14 shows an example of a main part of the semiconductor memory MEM shown in FIG. Detailed description of the same elements as those in FIG. 4 is omitted. FIG. 14 shows a precharge circuit PRE, a memory cell MC, and a bit line pair BIT, BITX arranged at the right end of the memory block BLK4 of FIG.

  The precharge circuit PRE has a plurality of pMOS transistors P1 for connecting the bit lines BIT and BITX to the power supply line VDD. That is, the pMOS transistor P1 is provided for each of the bit lines BIT and BITX. The structure (transistor size, threshold voltage, film thickness, material, wiring layer, etc.) of each pMOS transistor P1 is the same as that of the pMOS transistor P2. The electrical characteristics of each pMOS transistor P1 are the same as those of the pMOS transistor P2. Equal to electrical characteristics. That is, the driving capability of the pMOS transistor P2 is equal to the driving capability of each pMOS transistor P1.

  The pMOS transistors P4, P5, and P6 of the precharge circuit PRE operate by receiving a precharge signal (in this example, PRE4X) from the corresponding buffer circuit PBUF at the gate. Each of the pMOS transistors P4 and P5 is an example of a second transistor. The pMOS transistor P1 is an example of a first precharge circuit and a third precharge circuit. The pMOS transistor P2 is an example of a second precharge circuit.

  The buffer circuit PBUF receives a signal obtained by inverting the sleep cancel signal SLPOUTX via the inverters IV4, IV5, and IV6 at the NAND gate. The buffer circuit PBUF sets the corresponding precharge signal PREX (in this example, PRE4X) to high when the sleep release signal SLPOUTX is at high level or when the column selection signal COLX (in this example, COL4X) is received at low level. Deactivate to level. By deactivation of the precharge signal PREX, the precharge of the corresponding bit line pair BIT, BITX is stopped.

  The buffer circuit PBUF activates the corresponding precharge signal PREX to a low level when the sleep release signal SLPOUTX is at a low level and the column selection signal COLX is at a high level. The precharge operation of the corresponding bit line pair BIT, BITX is executed by the activation of the precharge signal PREX.

  For example, the drive capability of each pMOS transistor P4, P5 is higher than the drive capability of each pMOS transistor P1. The memory cell MC, dummy memory cell DMC, bit lines BIT, BITX, and dummy bit line DBIT are the same as those in FIG.

  The operation of this embodiment is the same as in FIGS. In this embodiment, the precharge operation of the bit lines BIT and BITX in the return period RET is performed using the corresponding pMOS transistor P1. The load on each bit line BIT, BITX and the load on the dummy bit line DBIT are equal to each other, and the driving capabilities of the pMOS transistors P1, P2 are equal to each other. For this reason, the rising speed of the voltage of each bit line BIT, BITX in the return period RET is equal to the rising speed of the voltage of the dummy bit line DBIT.

  The precharge operation of the bit lines BIT and BITX after the sleep release signal SLPOUTX in the return period RET is activated to a low level and returns to the normal mode NRM uses not only the pMOS transistor P1 but also the pMOS transistor P4 (or P5). Executed.

  As described above, also in this embodiment, the same effect as that of the above-described embodiment can be obtained. Furthermore, by providing the pMOS transistor P1 that is operated during the return period RET for each of the bit lines BIT and BITX, the pMOS transistors P1 and P2 can be designed to have the same drive capability. As a result, the rising speeds of the bit lines BIT, BITX and the dummy bit line DBIT during the return period RET can be easily and reliably set to the same speed without performing circuit simulation or the like.

  Since the pMOS transistors P4 and P5 used for precharging at the time of the access operation are directly connected to the power supply line VDD, the precharge operation of the bit lines BIT and BITX after the access operation can be quickly performed, and the access efficiency can be improved. . By controlling the operation of the buffer circuit PBUF using the logic of the sleep release signal SLPOUTX, the pMOS transistors P4 and P5 of the precharge circuit PRE can be turned off during the return period RET. Therefore, it is possible to prevent the bit lines BIT and BITX from being precharged by the pMOS transistors P4 and P5 having high driving capability during the return period RET, and it is possible to prevent generation of power supply noise.

  FIG. 15 shows an example of a system SYS on which the above-described semiconductor memory MEM is mounted. The system SYS (user system) forms at least a part of a microcomputer system such as a portable device, for example. The system SYS has a system-on-chip SoC in which a plurality of macros are integrated on a silicon substrate. Alternatively, the system SYS has a multi-chip package MCP in which a plurality of chips are stacked on a package substrate. Alternatively, the system SYS has a system-in-package SiP in which a plurality of chips are mounted on a package substrate such as a lead frame. Furthermore, the system SYS may be formed in the form of chip-on-chip CoC or package-on-package PoP.

  For example, the system SYS includes a CPU (Central Processing Unit), a ROM (Read Only Memory), a peripheral circuit I / O, and a semiconductor memory MEM. The CPU, ROM, peripheral circuit I / O, and semiconductor memory MEM are connected to each other by a system bus SBUS.

  The CPU accesses the ROM, the peripheral circuit I / O, and the semiconductor memory MEM and controls the operation of the entire system. The CPU outputs a command signal CMD, an address signal AD, and a write data signal I / O to the semiconductor memory MEM in order to execute a write operation. The CPU outputs a command signal CMD and an address signal AD to the semiconductor memory MEM to execute a read operation, and receives a read data signal I / O from the semiconductor memory MEM. The CPU outputs a sleep signal SLPX for setting the state of the semiconductor memory MEM to the normal mode NRM or the sleep mode SLP to the semiconductor memory MEM. The minimum configuration of the system SYS is a CPU and a semiconductor memory MEM.

The invention described in the above embodiments is organized and disclosed as an appendix.
(Appendix 1)
Real memory cells,
It is connected to the real memory cell, and is set to an intermediate voltage between the power supply voltage supplied to the first power supply line and the ground voltage by entering a floating state during the first mode in which access to the real memory cell is prohibited. Real bit line,
The connection between the first power supply line and the real bit line is released during the first mode, and the first power supply line is connected to the real bit line during the second mode in which access to the real memory cell is permitted. A first precharge circuit that
A dummy bit line having the same load as that of the real bit line;
A second precharge circuit that disconnects the first power supply line and the dummy bit line during the first mode and connects the first power supply line to the dummy bit line during the second mode;
A reset circuit for setting the dummy bit line to the ground voltage during the first mode;
At the time of switching from the first mode to the second mode, when the voltage of the dummy bit line rising from the ground voltage by the operation of the second precharge circuit exceeds the intermediate voltage, the second mode A semiconductor memory comprising: a detection circuit that activates a detection signal indicating return to the mode.
(Appendix 2)
The first precharge circuit is provided in common for a predetermined number of the real bit lines,
The driving capability of the second precharge circuit is lower than the driving capability of the first precharge circuit, and the charging speed of the dummy bit line charged by the second precharge circuit is charged by the first precharge circuit. The semiconductor memory according to claim 1, wherein the driving capacity is set to be equal to a charging speed of each of the predetermined number of the real bit lines.
(Appendix 3)
The first power supply line and the real bit line are disconnected during the first mode, and the first response is made in response to activation of the detection signal when switching from the first mode to the second mode. The semiconductor memory according to appendix 1 or appendix 2, wherein a power supply line is connected to the real bit line, and a third precharge circuit having a drive capability higher than that of the first precharge circuit is provided.
(Appendix 4)
A second transistor disposed between the first power supply line and the second power supply line and turned off during the first mode and turned on in response to activation of the detection signal; A first transistor disposed between two power lines and turned off during the first mode and turned on during the second mode;
A third transistor disposed between the second power supply line and the real bit line and turned off during the first mode and turned on when the real memory cell is not accessed during the first mode;
With
The first precharge circuit includes the first transistor and the third transistor,
The semiconductor memory according to appendix 3, wherein the third precharge circuit includes the second transistor and the third transistor.
(Appendix 5)
A plurality of memory blocks each including the real memory cell and the real bit line;
The semiconductor memory according to appendix 4, wherein the first transistor and the second transistor are provided in common in the memory block.
(Appendix 6)
The first precharge circuit is provided for each real bit line,
The semiconductor memory according to appendix 1, wherein the drive capability of the second precharge circuit is equal to the drive capability of the first precharge circuit.
(Appendix 7)
The first power supply line and the real bit line are disconnected during the first mode, and the first response is made in response to activation of the detection signal when switching from the first mode to the first mode. The semiconductor memory according to appendix 6, wherein a power supply line is connected to the real bit line, and a third precharge circuit having a drive capability higher than that of the first precharge circuit is provided.
(Appendix 8)
A first transistor disposed between the first power supply line and each of the real bit lines and turned off during the first mode and turned on during the first mode;
A second transistor disposed between the first power supply line and each real bit line, and turned off during the first mode and turned on in response to activation of the detection signal;
The first precharge circuit includes the first transistor,
The semiconductor memory according to appendix 7, wherein the third precharge circuit includes the second transistor.
(Appendix 9)
A dummy memory cell connected to the dummy bit line;
The dummy memory cell includes a transistor formed in the real memory cell and having the same structure as a transistor connected to the real bit line,
9. The semiconductor memory according to claim 1, wherein the number of the dummy memory cells is equal to the number of the real memory cells connected to the real bit line.
(Appendix 10)
The semiconductor memory according to appendix 9, wherein the dummy memory cell has the same structure as the real memory cell.
(Appendix 11)
The semiconductor memory according to any one of appendix 1 to appendix 10, and
A controller for accessing the semiconductor memory,
The controller outputs a mode signal for setting the semiconductor memory to the first mode or the first mode to the semiconductor memory;
The semiconductor memory includes a mode terminal for receiving the mode signal.

  From the above detailed description, features and advantages of the embodiments will become apparent. This is intended to cover the features and advantages of the embodiments described above without departing from the spirit and scope of the claims. Further, any person having ordinary knowledge in the technical field should be able to easily come up with any improvements and changes, and there is no intention to limit the scope of the embodiments having the invention to those described above. It is also possible to rely on suitable improvements and equivalents within the scope disclosed in.

  BIT, BITX bit line; BLK1-BLK4 memory block; CDEC column decoder; CNT1-CNT4 control circuit; COL1X-COL4X column selection signal; CSW column switch; CSWU column switch unit; DBIT dummy bit line DETC ... detection circuit; DETX ... detection signal; DMC ... dummy memory cell; DMY ... dummy circuit; I / O ... data terminal; LD ... load; MC ... memory cell; MD ... mode signal; Normal mode; PBUF ... buffer circuit; PRE, PRE1, PRE2 ... precharge circuit; PRE1X-PRE4X ... precharge signal; PREU ... precharge part; RET ... return period; SA ... sense amplifier; SAU ... sense amplifier part; Sleep mode; SLPO TX ‥ wake signal; SLPX ‥ sleep signal; VDD, VDD2 ‥ power line; WDEC ‥ word decoder

Claims (8)

Real memory cells,
It is connected to the real memory cell, and is set to an intermediate voltage between the power supply voltage supplied to the first power supply line and the ground voltage by entering a floating state during the first mode in which access to the real memory cell is prohibited. Real bit line,
The connection between the first power supply line and the real bit line is released during the first mode, and the first power supply line is connected to the real bit line during the second mode in which access to the real memory cell is permitted. A first precharge circuit that
A dummy bit line having the same load as that of the real bit line;
A second precharge circuit that disconnects the first power supply line and the dummy bit line during the first mode and connects the first power supply line to the dummy bit line during the second mode;
A reset circuit for setting the dummy bit line to the ground voltage during the first mode;
At the time of switching from the first mode to the second mode, when the voltage of the dummy bit line rising from the ground voltage by the operation of the second precharge circuit exceeds the intermediate voltage, the second mode A semiconductor memory comprising: a detection circuit that activates a detection signal indicating return to the mode. The first precharge circuit is provided in common for a predetermined number of the real bit lines,
The driving capability of the second precharge circuit is lower than the driving capability of the first precharge circuit, and the charging speed of the dummy bit line charged by the second precharge circuit is charged by the first precharge circuit. 2. The semiconductor memory according to claim 1, wherein the semiconductor memory is set to have a driving capability equal to a charging speed of each of the predetermined number of the real bit lines. The first power supply line and the real bit line are disconnected during the first mode, and the first response is made in response to activation of the detection signal when switching from the first mode to the second mode. 3. The semiconductor according to claim 1, further comprising a third precharge circuit that connects a power supply line to the real bit line and has a drive capability higher than that of the first precharge circuit. 4. memory. A first transistor disposed between the first power line and the second power line and turned off during the first mode and turned on during the second mode;
A second transistor disposed between the first power supply line and the second power supply line and turned off during the first mode and turned on in response to activation of the detection signal;
A third transistor disposed between the second power supply line and the real bit line and turned off during the first mode and turned on when the real memory cell is not accessed in the second mode ;
With
The first precharge circuit includes the first transistor and the third transistor,
The semiconductor memory according to claim 3, wherein the third precharge circuit includes the second transistor and the third transistor. The first precharge circuit is provided for each real bit line,
2. The semiconductor memory according to claim 1, wherein the drive capability of the second precharge circuit is equal to the drive capability of the first precharge circuit. The first power supply line and the real bit line are disconnected during the first mode, and the first response is made in response to activation of the detection signal when switching from the first mode to the second mode . The semiconductor memory according to claim 5, further comprising a third precharge circuit that connects a power supply line to the real bit line and has a drive capability higher than that of the first precharge circuit. A first transistor disposed between the first power supply line and each of the real bit lines and turned off during the first mode and turned on during the second mode ;
A second transistor disposed between the first power supply line and each real bit line, and turned off during the first mode and turned on in response to activation of the detection signal;
The first precharge circuit includes the first transistor,
The semiconductor memory according to claim 6, wherein the third precharge circuit includes the second transistor. A semiconductor memory according to any one of claims 1 to 7,
A controller for accessing the semiconductor memory,
The controller outputs a mode signal for setting the semiconductor memory to the first mode or the second mode to the semiconductor memory;
The semiconductor memory includes a mode terminal for receiving the mode signal.

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