JP5772040B2 - Data transfer system, data transfer scheduling program - Google Patents

Description

  The present invention relates to a data transfer system and a data transfer scheduling program executed in this system.

  In a data transfer system having a bus having a bus arbiter, a plurality of bus masters connected to the bus, and a CPU (Central Processing Unit), a task for realizing a predetermined function is executed by the CPU. A task is an execution unit of program processing, and is also called a process or a thread. The task causes the bus master corresponding to the data transfer request to execute the data transfer request in the task. When a task makes a data transfer request to the bus master, it calls and executes an API (Application Program Interface) for data transfer. At this time, the task sets a data transfer source address, a transfer destination address, and the like as arguments to the data transfer request API.

  This task can execute a data transfer request to each bus master sequentially or simultaneously. Each bus master that has received this data transfer request issues a bus use request to the arbiter of the bus to which it is connected. When the bus arbiter of this bus receives bus use requests simultaneously from a plurality of bus masters, the bus arbiter arbitrates the bus use requests.

  As an arbitration method, for example, every time a predetermined cycle time elapses, a right to use the bus is given to each bus master according to a priority (also referred to as priority) determined for each bus master. The first bus master that has received the bus use right from the bus arbiter executes data transfer using the bus for a predetermined cycle time. When this cycle time elapses, the bus arbiter passes this usage right to the second bus master having a low priority. The first bus master that has lost this right to use suspends data transfer. When the first bus master receives the right to use the bus again from the bus arbiter, the data transfer is resumed. The first and second bus masters repeat this process until the data transfer is completed.

  For example, five bus masters BM1 to BM5 are connected to the bus, and priority 1 to 5 (the higher the priority number, the higher the priority) is set by the bus arbiter as the priority for the bus masters BM1 to BM5. To do.

  When the bus masters BM1 to BM5 request the bus to use the bus at the same time, the bus arbiter gives the bus master BM5 ... BM1, BM5 ... Repeat the process of sequentially passing to the bus masters BM5 to BM1 like BM1, ... That is, the bus arbiter assigns the bus use right in a time division manner. The bus master that has received the right to use the bus from the bus arbiter executes data transfer during the cycle time.

Japanese Patent Laid-Open No. 10-40211 JP 2007-109086 A

  As described above, when the bus arbiter arbitrates bus use requests, a bus master among a plurality of bus masters can continue to use (occupy) the bus only for the predetermined cycle time. Therefore, it may be difficult to complete within a predetermined time a data transfer that must be completed within a predetermined time, that is, a data transfer with strict time requirements.

  For example, in a data transfer system having a multi-stage bus in which a bus B3 is connected to the bus B1 and the bus B2, and a bus B4 is connected to the bus B3, a first DMAC (Direct Memory Access) having a plurality of channels is connected to the bus B1. Controller), the second DMAC is also connected to the bus B2, and the multiple channels of the first DMAC and the multiple channels of the second DMAC access the memory connected to the bus B4 and access the data simultaneously. Assume that transfer is performed. In this case, the bus B1 or the bus B2 functions as a bus master for the bus B3.

  At this time, the arbiter of bus B1 arbitrates the bus use request from the first DMAC, the arbiter of bus B2 arbitrates the bus use request from the second DMAC, and the arbiter of bus B3 Arbitrates bus use requests from B1 and B2. In this way, the bus arbiter arbitrates requests to use the bus.

  For this reason, for example, when the first DMAC performs data transfer, the bus usage right for buses B1, B3, and B4 must be acquired at the same time. It becomes lower than the bus configuration.

  Therefore, when the first DMAC has to perform data transfer with strict time requirements, it is more difficult to execute data transfer efficiently and reliably execute data transfer requests that satisfy the time requirements. become.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a data transfer system and a data transfer scheduling program that efficiently execute data transfer.

A first aspect of the data transfer system includes a bus, a CPU connected to the bus, a plurality of bus masters connected to the bus and executing data transfer via the bus, and a bus use request from the bus master. A bus arbiter that grants a bus use right to any one of the bus masters, a bus master driver means that controls the plurality of bus masters, a data transfer request generated by a task executed by the CPU, and the received data Selecting a data transfer request having the highest priority from among the transfer requests, and scheduling means for instructing the bus master driver means to execute the selected data transfer request, wherein the bus master driver means In response, the selected data transfer request is sent to the bus master corresponding to the selected data transfer request. Is executed, said one of the plurality of bus masters, a data transfer request to the task is generated, executed without passing through the scheduling means, the scheduling means, bus bus master performs data transfer request accepting Based on the data transfer amount of the data transfer request, the available time is calculated to be longer than the bus usable time of the bus master that does not execute the data transfer request, and the bus arbiter gives priority to the bus master with the longer bus usable time. Gives bus use rights .

  According to the first aspect, in a data transfer system having a bus and a plurality of bus masters, it is possible to efficiently execute data transfer and reliably execute data transfer with strict time requirements.

FIG. 3 is a functional block diagram illustrating a first embodiment. FIG. 2 is a functional block diagram of hardware according to the first embodiment. FIG. 3 is a functional block diagram of software according to the first embodiment. It is a figure which shows the content of the data transfer request. FIG. 6 is a first flowchart for explaining the start of execution of a data transfer request. FIG. 10 is a second flowchart for explaining the start of execution of a data transfer request. FIG. 10 is a third flowchart for explaining the start of execution of a data transfer request. FIG. 6 is a first flowchart illustrating a process executed when data transfer is completed. FIG. 10 is a second flowchart for explaining processing executed when data transfer is completed. FIG. 6 is a first flowchart illustrating suspension of a data transfer request. FIG. 10 is a second flowchart for explaining a suspension of a data transfer request. FIG. 10 is a third flowchart for explaining a temporary suspension of a data transfer request. FIG. 5 is a first flowchart for explaining resumption of a temporarily stopped data transfer request. FIG. 10 is a second flowchart for explaining the resumption of a temporarily stopped data transfer request. FIG. 10 is a third flowchart for explaining resumption of a temporarily stopped data transfer request. FIG. 6 is a first flowchart for explaining forced termination of a data transfer request. FIG. 10 is a second flowchart illustrating forced termination of a data transfer request. FIG. 10 is a third flowchart illustrating forced termination of a data transfer request. FIG. 6 is a functional block diagram of hardware according to a second embodiment. FIG. 6 is a functional block diagram of software according to a second embodiment. FIG. 10 is a functional block diagram of hardware according to a third embodiment. FIG. 10 is a functional block diagram of software of a third embodiment. It is a functional block diagram of a bus arbiter control unit and a bus arbiter driver group. It is a functional block diagram of a bus arbiter. FIG. 10 is a functional block diagram of software according to a fourth embodiment. FIG. 6 is a first flowchart for explaining the start of execution of a PIO data transfer request. FIG. 10 is a second flowchart for explaining the start of execution of a PIO data transfer request. FIG. 10 is a third flowchart for explaining the start of execution of a PIO data transfer request. FIG. 6 is a first flowchart for explaining processing executed when PIO data transfer is completed. FIG. 10 is a second flowchart illustrating a process executed when PIO data transfer is completed.

(First embodiment)
FIG. 1 is a functional block diagram for explaining the first embodiment. The data transfer system 1 includes hardware 10 having hardware components and software 20 executed by the CPU 12 of the hardware 10.

  The hardware 10 comprises an internal bus master (multi-channel DMAC) 11 that executes DMA transfer processing, which is an internal bus master, a CPU 12, an IRC 13 that functions as an interrupt controller (IRC: Interrupt Request Controller), and RAM and ROM, for example. And a bus 16 for connecting these hardware components to each other. The bus 16 includes a bus arbiter 16a that arbitrates a bus use request for each bus master according to the priority set in the DMAC 11 or the external bus master 15. The DMAC 11 has a multi-channel DMAC and functions as a plurality of bus masters. In response to the bus use requests from the plurality of bus masters, the bus arbiter 16a assigns bus use rights in a time division manner, for example, according to the priority set for the plurality of bus masters.

  The software 20 accepts the task 21 executed by the CPU 12 and the data transfer request generated by the task 21, selects the data transfer request with the highest priority among the accepted data transfer requests, and selects the selected data transfer request. Scheduling means 22 for instructing the bus master driver means to execute, so-called operating system OS (Operating System) 23, and bus master driver means 24 for controlling the bus master (for example, DMAC 11). In response to an instruction from the scheduling means 22, the bus master driver means 24 causes the bus master corresponding to the data transfer request selected by the scheduling means 22 to execute this data transfer request. In response to the instruction, the bus master driver means 24 causes the bus master corresponding to the selected data transfer request to execute the selected data transfer request.

  Further, when the scheduling unit 22 receives a data transfer request newly generated by the task 21 while the selected data transfer request is being executed by the bus master, the priority of the received data transfer request is executed. If the priority is higher than the priority of the data transfer request, the bus master driver means 24 is instructed to temporarily stop the data transfer request being executed, and the bus master driver means 24 is instructed to execute the newly generated data transfer request. To do. In response to the instruction, the bus master driver means 24 causes the bus master to temporarily stop the data transfer request being executed, and causes the bus master corresponding to the newly generated data transfer request to execute the data transfer request.

  When the scheduling unit 22 receives a completion notification indicating that execution of the newly generated data transfer request is completed from the OS 23, the scheduling unit 22 responds to the completion notification to resume the suspended data transfer request. Command means 24.

  Details of the data transfer system 1 that executes scheduling of such data transfer requests will be described below.

  FIG. 2 is a functional block diagram of the hardware 10. The DMAC 11 includes a plurality of channels DMACch0_110 to DMACch7_117 that execute DMA transfer, a DMAC bus 113 to which the DMACch0_110 to DMACch7_117 are connected, and a DMAC bus arbiter 114 that arbitrates bus use requests from the DMACch0_110 to DMACch7_117. The number of channels is an example.

   The CPU 12 is a CPU that executes the software 20.

  The bus 1A_161A is a bus connected to the DMAC 11, the bus 2A_162A, and the bus 2B_162B, and includes a bus 1A arbiter 161a. The bus 2A_162A is a bus connected to the bus 1A_161A, the bus 1B_161B, and the external bus I / O 163, and includes a bus 2A arbiter 162a. The external bus I / O 163 is a bus connected to the bus 2A_162A and the external bus 166, and includes an external bus arbiter 163a.

  The bus 1B_161B is a bus connected to the CPU 12, the bus 2A_162A, the bus 2B_162B, and the bus 2C_162C, and includes a bus 1B arbiter 161b. The bus 2B_162B is a bus connected to the bus 1A_161A, the bus 1B_161B, and the memory IF 164, and includes a bus 2B arbiter 162b. The memory IF 164 is a memory IF (InterFace) connected to the bus 2B_162B and the memory bus 165. The memory bus 165 is connected to the memory IF 164 and the memory 14. The bus 2C_162C is a bus connected to the bus 1B_161B and the IRC13.

  The external bus 166 is connected to the external bus I / O 163, the external bus master 151, and the external slave device 152. The external bus master 151 and the external slave device 152 are devices newly added by the user as will be described later. As described above, the hardware 10 has a bus structure in which a plurality of buses are connected in multiple stages. These buses and bus arbiters correspond to the bus 16 and bus arbiter 16a in FIG.

  When the IRC 13 receives the data transfer completion notification from the DMAC 11, the IRC 13 issues a transfer completion interrupt to the CPU 12 to notify the completion of the data transfer.

  FIG. 3 is a detailed functional block diagram of the software 20. The request generation accepting means 221 of the scheduling means 22 accepts the data transfer request, data transfer pause request, data transfer resume request, and data transfer forced termination request generated by the task 21. The request completion notification receiving unit 222 receives a transfer completion notification from the bus master driver unit 24. The request management unit 223 manages the data transfer request received by the request generation receiving unit 221. The scheduler with priority 224 schedules a data transfer request having the priority of the data transfer request based on this priority.

  The bus / transfer control means 225 instructs the bus master driver control means 226 to execute execution, temporary suspension, resumption, and forced termination of the data transfer request. The bus master driver control means 226 controls the bus master driver means 24 in response to a command from the bus / transfer control means 225. The bus master driver means 24 is a bus master, that is, a driver that controls the DMAC 11 in the example of FIG. The bus master driver unit 24 further includes a completion interrupt reception unit 241 that receives a completion interrupt notification from the OS 23.

  The OS 23 controls the task 21 and the scheduling means 22. The memory 14 has a request storage unit 141 for storing a data transfer request received by the request generation receiving means 221 together with a data transfer request identifier and a status flag, which will be described later, and a FIFO function. The data transfer request is queued according to priority. And a priority-specific request queue 142 that is managed in the network.

  The software 20 is composed of a program stored in a program storage memory (not shown). Among these programs, a program corresponding to the scheduling means 22 is a data transfer scheduling program. The CPU 12 reads this program from this memory and executes it as necessary. Note that this program may be stored in the memory 14.

  FIG. 4 shows the contents of the data transfer request. The data transfer request includes the data transfer information shown in FIG. The type of data transfer request is referred to in order to identify the bus master that executes the data transfer request. The internal DMAC transfer indicates that the DMAC 11 executes the data transfer, and the external bus master 151 executes the data transfer. Indicates the type of data transfer request, such as external DMAC transfer indicating CPU and PIO (Programmed I / O) transfer of the CPU indicating that the CPU 12 is to execute data transfer. With reference to the type of data transfer request, the scheduling means 22 causes the bus master corresponding to the data transfer request with the highest priority to execute this data transfer request. In the first embodiment, internal DMAC transfer will be described. External DMAC transfer will be described in the second embodiment, and CPU PIO transfer will be described in the fourth embodiment.

  The priority of the data transfer request indicates the execution priority indicating which data transfer request is to be executed preferentially when there are multiple data transfer requests. For example, priority 1 to 5 is recorded and the numerical value is large. The higher the priority. The data transfer source indicates a data transfer source address, the data transfer destination indicates a data transfer destination address, and the data transfer size (data transfer amount) indicates the size of all data to be transferred. The data size of the transfer unit indicates the data size that is transferred by one access. The transfer method indicates a transfer method of incrementing, decrementing, or fixing the data transfer destination and transfer source address.

  Next, data transfer in the present embodiment will be described in detail with reference to FIGS.

  5A to 5C are flowcharts for explaining the start of execution of a data transfer request.

  Step S1: The task 21 calls the data transfer request API for instructing the scheduling means 22 to execute a data transfer request. At this time, the data transfer request described in FIG. 4 is generated by the task 21 and set as an argument in the data transfer request API. As a result, a data transfer request is input to the scheduling means 22. “Internal DMAC transfer” is recorded as the data transfer request type of the data transfer request set as an argument.

  Step S2: The request generation accepting means 221 of the scheduling means 22 accepts this data transfer request and assigns an identifier for identifying the data transfer request to this data transfer request. This identifier is used by the scheduling means 22 to manage the data transfer request. This identifier is input to the task 21 as a return value of the data transfer request API called by the task 21.

  Step S3: The request generation acceptance unit 221 instructs the request management unit 223 to store the accepted data transfer request in the request storage unit 141.

  Step S4: In response to this command, the request management means 223 stores the data transfer request and its identifier input from the request generation acceptance means 221 in the request storage unit 141. Here, the request management means 223 stores the data transfer request including the identifier assigned by the request generation accepting means 221 and the status flag. In the status flag, the status of the data transfer request is recorded. Examples of the status include waiting for execution, executing transfer, pausing due to an interrupt, and pausing due to a task. Here, the request management means 223 records the waiting for execution in the status flag.

  Step S5: The request management means 223 instructs the scheduler 224 with priority to specify the priority and register the identifier of the data transfer request in the last part of the request queue 142 by priority. At the same time, the request management unit 223 outputs the identifier of the data transfer request and this priority to the scheduler 224 with priority.

  Step S6: The scheduler with priority 224 registers the input data transfer request identifier in the last part of the list of the request queue by priority 142. At the same time, the scheduler with priority 224 also registers this priority corresponding to the identifier of the registered data transfer request. If an identifier is registered in the priority-specific request queue 142 before this registration, the data transfer request corresponding to the identifier of the data transfer request with the highest priority is the data transfer request being executed. If there are multiple identifiers of the data transfer request with the highest priority, it corresponds to the identifier of the data transfer request registered first in the request queue by priority 142 (closest to the head of the request queue by priority 142). Assume that the data transfer request to be executed is a data transfer request being executed.

  Step S7: The scheduler with priority 224 selects (searches) the identifier of the data transfer request with the highest priority among the data transfer requests registered in the priority-specific request queue 142. When there are a plurality of identifiers of data transfer requests with the highest priority, the identifier of the data transfer request registered first in the request queue by priority 142 is selected. The same applies hereinafter.

  Step S8: The priority-attached scheduler 224 newly registers the data transfer request identifier in the priority-specific request queue 142, so that the identifier of the data transfer request with the highest priority is the data transfer request being executed. Check if the identifier has changed. Here, the scheduler with priority 224 confirms whether or not the identifier of the data transfer request with the highest priority selected in step S7 is a newly registered identifier.

  For example, if a data transfer request (identifier) with priority 5 is registered in step S6 while a data transfer request with priority 3 is being executed, the data transfer request with the highest priority is the data being executed. Judge that it is different from the identifier of the transfer request. On the other hand, if a data transfer request with priority 3 is registered in step S6 while a data transfer request with priority 5 is being executed, the data transfer request with the highest priority is the data transfer request being executed. Judge that it is not different from the identifier.

  Step S9: If the data transfer request with the highest priority is different from the identifier of the data transfer request being executed (step S9 / YES), the process proceeds to step S10. Even when a data transfer request is newly registered in the priority request queue 142 in step S6 when the priority request queue 142 is empty, the process proceeds to step S10. If not changed (step S9 / NO), the process is terminated. At this time, the data transfer request registered in step S6 is executed after step S27 in FIG. 6B described later.

  Step S10: The scheduler with priority 224 outputs the identifier of the data transfer request with the highest priority to the bus / transfer control means 225.

  Step S11: The bus / transfer control means 225 instructs the bus master driver control means 226 to execute the data transfer request based on the data transfer request with the highest priority. At this time, the bus / transfer control means 225 outputs the identifier of the data transfer request with the highest priority to the bus master driver control means 226.

  Step S12: The bus master driver control means 226 instructs the bus master driver means 24 to temporarily stop the data transfer request being executed and execute the data transfer request with the highest priority. As described above, when the priority request queue 142 is empty, if a new data transfer request is registered in the priority request queue 142 in step S6, the pause instruction is not executed. .

  Here, the bus master driver control means 226 outputs the identifier of the input data transfer request to the request management means 223. The request management unit 223 reads a data transfer request corresponding to the input identifier from the request storage unit 141 and outputs it to the bus master driver control unit 226. Further, when the request management means 223 outputs the data transfer request to the bus master driver control means 226, the request management means 223 changes the status flag of the data transfer request being executed (recording that the transfer is being executed) to be suspended during the interruption, The transfer execution status is recorded in the status flag of the data transfer request corresponding to the input identifier.

  That is, the bus master driver control unit 226 reads out a data transfer request corresponding to the input identifier from the request storage unit 141 via the request management unit 223. The bus master driver control means 226 outputs the read data transfer request to the bus master driver means 24.

  In response to the temporary stop command from the bus master driver control unit 226, the bus master driver unit 24 instructs the DMAC 11 via the OS 23 to temporarily stop the data transfer request being executed by the DMAC 11. In response to the pause command from the bus master driver means 24, the DMAC 11 temporarily stops the data transfer being executed.

  In response to the data transfer execution command from the bus master driver control unit 226, the bus master driver unit 24 outputs the input data transfer request to the DMAC 11 via the OS 23. The DMAC 11 performs data transfer based on the input data transfer request.

  The process described in step S2 is an example of a process of receiving a data transfer request generated by the task 21 executed by the CPU 12.

  The process described in step S7 is an example of a process in which the scheduling unit 22 selects a data transfer request with the highest priority among the received data transfer requests.

  In the processing described in step S10 and subsequent steps, the scheduling unit 22 instructs the bus master driver unit 24 to execute the selected data transfer request, and the bus master driver unit 24 responds to the selected data transfer request. This is an example of a process for causing the bus master (DMAC 11) to execute the selected data transfer request.

  In the processing described in steps S7 to S10, when the scheduling unit 22 receives a data transfer request newly generated by the task 21 while the selected data transfer request is being executed by the bus master (step S2 If the priority of the accepted data transfer request is higher than the priority of the data transfer request being executed (step S9 / YES), the data transfer request being executed is suspended and A step of instructing the bus master driver means 24 to execute the generated data transfer request (see step S12), and the scheduling means 22 causes the bus master driver means 24 to temporarily stop the data transfer request being executed to the bus master. Example of the process of causing the bus master corresponding to the newly generated data transfer request to execute the data transfer request A.

  In this way, the data transfer request generated by the task is collectively received by the scheduling means 22 and scheduled. Therefore, the bus arbiter has only to give a bus use right to this bus master in response to a bus use request from one bus master. As a result, the bus master can use the bus exclusively by acquiring the right to use the data transfer path. Therefore, even data transfer with strict time requirements can be completed within a predetermined time.

  For example, when the data transfer information of the data transfer request to be executed records the internal DMAC transfer as the type of data transfer request, the address of the memory 14 as the data transfer source, and the address of the external slave device 152 as the data transfer destination 5A to 5C are executed, and the DMAC 11 performs data transfer based on the input data transfer request. At this time, for example, DMACch0_110 accesses the memory 14 via the DMAC bus 113, the bus 1A_161A, the bus 2B_162B, the memory IF164, and the memory bus 165, reads the data, the memory bus 165, the memory IF164, the bus 2B_162B, the bus 1A_161A, A process of writing the read data to the external slave device 152 via the bus 2A_162A, the external bus I / O 163, and the external bus 166 is executed. This read / write processing is executed until data of the data transfer size recorded in the data transfer information is written to the external slave device 152.

  At this time, according to the present embodiment, the DMACch0_110 can acquire the right to use the bus serving as the data transfer path all at once and can use this bus exclusively.

  6A and 6B are flowcharts for explaining processing executed when data transfer is completed.

  Step S21: The bus master driver means 24 accepts the data transfer completion notification from the OS 23 and activates the request completion notice acceptance means 222. Specifically, when the DMAC 11 completes the data transfer being executed, the DMAC 11 notifies the IRC 13 that the data transfer has been completed. When receiving a transfer completion notification from the DMAC 11, the IRC 13 issues a transfer completion interrupt to the CPU 12 to notify the completion of the data transfer. Upon receiving the transfer completion interrupt notification, the CPU 12 outputs a transfer completion notification to the completion interrupt reception unit 241 of the bus master driver unit 24 via the interrupt handler 231 of the OS 23. The completion interrupt reception unit 241 outputs the received transfer completion notification to the request completion notification reception unit 222.

  Step S22: The request completion notification receiving means 222 receives a transfer completion notification.

  Step S23: The request completion notification accepting unit 222 instructs the request management unit 223 to delete the data transfer request corresponding to the transfer completion notification from the request storage unit 141.

  Step S24: In response to this command, the request management means 223 deletes the data transfer request corresponding to the transfer completion notification from the request storage unit 141. That is, the data transfer request whose status flag is set to transfer in progress is deleted.

  Step S25: The request completion notification accepting means 222 instructs the scheduler 224 with priority to delete the identifier of the data transfer request corresponding to the transfer completion notification from the priority-specific request queue 142.

  Step S26: The scheduler with priority 224 deletes the identifier of the data transfer request corresponding to the transfer completion notification from the request queue by priority 142. Here, for example, the identifier of the data transfer request with the highest priority may be deleted from the priority-specific request queue 142. If there are a plurality of identifiers of the data transfer request with the highest priority, the identifier of the data transfer request registered first in the priority-specific request queue 142 may be deleted.

  Step S27: After this deletion, the scheduler with priority 224 selects the identifier of the data transfer request with the highest priority among the identifiers of the data transfer request registered in the request queue by priority 142. When there are a plurality of identifiers of data transfer requests with the highest priority, the identifier of the data transfer request registered first in the request queue by priority 142 is selected. If there is no data transfer request in the priority request queue 142, the process is terminated.

  Step S28: The scheduler with priority 224 outputs the identifier of the data transfer request with the highest priority to the bus / transfer control means 225.

  Step S29: The bus / transfer control means 225 instructs the bus master driver control means 226 to execute the data transfer request based on the data transfer request with the highest priority. At this time, the identifier of the data transfer request with the highest priority is output to the bus master driver control means 226.

  Step S30: The bus master driver control means 226 instructs the bus master driver means 24 to execute the data transfer request with the highest priority. Specifically, as described in step S12, the bus master driver control unit 226 reads a data transfer request corresponding to the input identifier from the request storage unit 141 via the request management unit 223. The bus master driver control means 226 outputs the read data transfer request to the bus master driver means 24. The request management unit 223 records the transfer in progress in the status flag of the data transfer request corresponding to this identifier.

  In response to the data transfer execution command from the bus master driver control unit 226, the bus master driver unit 24 outputs the input data transfer request to the DMAC 11 via the OS 23. The DMAC 11 performs data transfer based on the input data transfer request. The bus master driver means 24 resumes the suspended data transfer when the status flag of the input data transfer request indicates that the pause due to the interrupt or the pause due to the task described later is recorded. Instruct DMAC11 as follows:

  In the present embodiment, the task 21 can execute not only the data transfer request but also the temporary suspension and restart of the data transfer request and the forced termination of the data transfer request.

  FIG. 7A to FIG. 7C are flowcharts for explaining suspension of a data transfer request.

  Step S41: The task 21 calls a pause request API for issuing a data transfer request pause instruction to the scheduling means 22. At this time, the identifier of the data transfer request to be paused described in step S2 of FIG. 5A is set as an argument to the pause request API. As a result, a temporary stop request including the identifier is input to the scheduling unit 22.

  Step S42: The request generation accepting means 221 accepts this temporary stop request. That is, the request generation accepting means 221 accepts a data transfer request temporary stop command from the task 21.

  Step S43: The request generation acceptance means 221 instructs the request management means 223 to search the request storage unit 141 for a data transfer request corresponding to the accepted suspension request.

  Step S44: In response to this command, the request management means 223 searches the request storage unit 141 for a data transfer request corresponding to the temporary stop request, and records that the task is temporarily stopped in the status flag of the searched data transfer request. To do. This search is executed using the identifier of the data transfer request corresponding to the suspension request as a key.

  Step S45: The request generation accepting unit 221 instructs the scheduler 224 with priority to delete the identifier of the data transfer request corresponding to the accepted suspension request from the request queue 142 by priority.

  Step S46: The scheduler with priority 224 searches the priority-specific request queue 142 for the identifier of the data transfer request corresponding to the suspension request, and deletes the identifier of the searched data transfer request. That is, the priority-attached scheduler 224 suspends scheduling of the data transfer request in response to the pause command.

  Step S47: After deletion, the scheduler 224 with priority selects the identifier of the data transfer request with the highest priority among the identifiers of the data transfer request registered in the request queue by priority 142.

  Step S48: The priority-attached scheduler 224 determines whether the identifier of the data transfer request with the highest priority has been changed from the identifier of the data transfer request being executed by this deletion, that is, the identifier of the data transfer request being executed. Check if it has been deleted (whether the data transfer request being executed is suspended).

  Step S49: If the identifier is different from the identifier of the data transfer request being executed (step S49 / YES), the processing of steps S50 and S51 is executed. If it has not changed (step S49 / NO), that is, if the data transfer request waiting for execution is suspended, the processing is terminated.

  Since the processing of steps S50 to S52 is the same as the processing of steps S10 to S12, the description thereof is omitted.

  8A to 8C are flowcharts for explaining resumption of a data transfer request that has been temporarily stopped. This process describes the process for resuming the data transfer request suspended by the task, as described with reference to FIGS. 7A to 7C.

  Step S61: The task 21 calls the resume request API for instructing the scheduling means 22 to resume the data transfer request that has been suspended. At this time, the identifier of the data transfer request to be restarted described in step S2 of FIG. 5A is set as an argument in the restart request API. As a result, a restart request including the identifier is input to the scheduling means 22.

  Step S62: The request generation accepting means 221 accepts this restart request. That is, the request generation accepting unit 221 accepts a data transfer request resumption command that has been temporarily stopped from the task 21.

  Step S63: The request generation acceptance unit 221 instructs the request management unit 223 to search the request storage unit 141 for a data transfer request corresponding to the accepted resumption request.

  Step S64: In response to this command, the request management means 223 searches the request storage unit 141 for a data transfer request corresponding to this restart request. This search is executed using the identifier of the data transfer request corresponding to the restart request as a key.

  Step S65: The request generation accepting means 221 instructs the scheduler 224 with priority to register the identifier of the data transfer request corresponding to the accepted restart request at the head of the request queue 142 by priority.

  Step S66: In response to this command, the scheduler 224 with priority registers the identifier of the data transfer request corresponding to the restart request at the head of the request queue 142 by priority. In other words, the scheduler with priority 224 responds to the resume command and resumes the scheduling of the data transfer request that has been suspended. Here, the scheduler 224 with priority obtains the identifier and priority of the data transfer request corresponding to the restart request searched by the request management unit 223 in step S64 from the request management unit 223, and executes this registration.

  The description of the processing in steps S67 and S68 is the same as the processing in steps S7 and S8, and thus the description thereof is omitted.

  Step S69: When the identifier of the data transfer request with the highest priority is different from the identifier of the data transfer request being executed (step S69 / YES), that is, when the priority of the data transfer request to be resumed is the highest , Step S70 follows. If not changed (step S69 / NO), the process is terminated.

  Since the processes in steps S70 and S71 are the same as those in steps S10 and S11, the description thereof is omitted.

  Step S72: The bus master driver control means 226 instructs the bus master driver means 24 to temporarily stop the data transfer request being executed and execute the data transfer request with the highest priority (data transfer request to be resumed). Specifically, the bus master driver control unit 226 sends a data transfer request corresponding to the identifier input from the bus / transfer control unit 225 in step S71 (see step S11) via the request management unit 223 to the request storage unit 141. Read from. Note that details are omitted because they have been described in step S12. The bus master driver control means 226 outputs the read data transfer request to the bus master driver means 24. Since the status flag of the read data transfer request indicates that the task is temporarily stopped, the bus master driver means 24 instructs the DMAC 11 to execute the data transfer request that has been temporarily stopped by the request from the task. Can be ordered.

  When the identifier is input (see step S12), the request management means 223 sets the status flag of the data transfer request being executed (set to transfer in progress) to be suspended during interruption. The status flag of the data transfer request corresponding to the identified identifier is set during transfer execution.

  In response to the pause command from the bus master driver control means 226, the bus master driver means 24 pauses the data transfer request being executed by the DMAC 11. In response to the data transfer execution command from the bus master driver control means 226, the bus master driver means 24 outputs the input data transfer request to the DMAC 11. The DMAC 11 performs data transfer based on the input data transfer request.

9A to 9C are flowcharts for explaining the forced termination of the data transfer request.
Step S81: The task 21 calls the forced termination request API for instructing the scheduling means 22 to forcibly terminate the data transfer request. At this time, the identifier of the data transfer request to be forcibly terminated described in step S2 of FIG. 5A is set as an argument to the forcible termination API. As a result, a forced termination request including the identifier is input to the scheduling means 22.

  Step S82: The request generation acceptance means 221 accepts this forced termination request. That is, the request generation accepting means 221 accepts a data transfer request forced termination command from the task 21.

  Step S83: The request generation accepting unit 221 searches the request storage unit 141 for a data transfer request corresponding to the accepted forced termination request and instructs the request managing unit 223 to delete it.

  Step S84: In response to this command, the request management unit 223 searches the request storage unit 141 for a data transfer request corresponding to the forced termination request, and deletes the searched data transfer request. This search is executed using the identifier of the data transfer request corresponding to the forced termination request as a key.

  Step S85: The request generation accepting unit 221 instructs the scheduler 224 with priority to delete the identifier of the data transfer request corresponding to the accepted forced termination request from the request queue 142 by priority.

  Step S86: The priority-added scheduler 224 searches the priority-specific request queue 142 for the identifier of the data transfer request corresponding to the forced termination request, and deletes the searched data transfer request identifier. In other words, the scheduler with priority 224 responds to the forcible termination command and ends the scheduling of the data transfer request.

  Step S87: After this deletion, the scheduler with priority 224 selects the identifier of the data transfer request with the highest priority among the identifiers of the data transfer request registered in the request queue by priority 142.

  Step S88: The prioritized scheduler 224 determines whether the identifier of the data transfer request with the highest priority has been changed from the identifier of the data transfer request being executed by this deletion, that is, the identifier of the data transfer request being executed. Check whether it has been deleted (whether the data transfer request being executed is forcibly terminated).

  Step S89: If the identifier is different from the identifier of the data transfer request being executed (step S89 / YES), the processing of steps S90 and S91 is executed. If it has not changed (step S89 / NO), that is, if the data transfer request waiting for execution is forcibly terminated, the processing is terminated.

  Step S90: The scheduler with priority 224 outputs the identifier of the data transfer request with the highest priority to the bus / transfer control means 225.

  Step S91: The bus / transfer control means 225 instructs the bus master driver control means 226 to execute the data transfer request based on the data transfer request with the highest priority. At this time, the identifier of the data transfer request with the highest priority is output to the bus master driver control means 226.

  Step S92: The bus master driver control means 226 instructs the bus master driver means 24 to forcibly terminate the data transfer request being executed and to execute the data transfer request with the highest priority.

  Here, the bus master driver control unit 226 reads a data transfer request corresponding to the input identifier from the request storage unit 141 via the request management unit 223. The bus master driver control means 226 outputs the read data transfer request to the bus master driver means 24. As described in step S12, when the request management unit 223 outputs the data transfer request to the bus master driver control unit 226, the request management unit 223 records that transfer is being performed in the status flag of the data transfer request corresponding to the input identifier.

  In response to the forced termination command from the bus master driver control unit 226, the bus master driver unit 24 commands the DMAC 11 via the OS 23 to forcibly terminate the data transfer request being executed by the DMAC 11. In response to the forced termination command from the bus master driver means 24, the DMAC 11 forcibly terminates the data transfer being executed.

  In response to the data transfer execution command from the bus master driver control unit 226, the bus master driver unit 24 outputs the input data transfer request to the DMAC 11 via the OS 23. The DMAC 11 performs data transfer based on the input data transfer request.

  According to the first embodiment, even if the bus master that executes data transfer has a multi-stage bus structure, the bus master that acquires the right to use the data transfer path is obtained all at once, and this bus is monopolized. Therefore, data transfer can be performed efficiently. As a result, even data transfer with strict time requirements can be completed within a predetermined time.

  The bus arbiter cannot arbitrate the bus use request based on the priority of the data transfer request itself. However, according to the first embodiment, since the scheduling means schedules the data transfer request based on the priority, efficient data transfer can be executed.

  In addition, since one bus master requests the bus use right from the bus arbiter, this bus master can immediately obtain the bus use right. As a result, there is no waiting time until the bus master acquires the right to use the bus, and the operation of the bus master does not stop.

(Second embodiment)
Incidentally, the user may add a new bus master to the hardware 10. This bus master is also called a user-defined bus master. In such a case, when the newly added bus master executes data transfer without entering the control of the scheduling means 22, this bus master and the bus master that executes the data transfer scheduled by the scheduling means 22 are simultaneously connected to the bus. May request use. As a result, the efficiency of data transfer scheduled by the scheduling means 22 is reduced. Therefore, the data transfer executed by the newly added bus master needs to be scheduled by the scheduling means 22.

  FIG. 10 is a functional block diagram of hardware for explaining the second embodiment. The external bus master 151 is a bus master (user-defined bus master) newly added by the user. The external bus master 151 is a bus master that performs data transfer via the external bus I / O 163 that functions as an interface bus for the bus master and connects to the external bus I / O 163 via the external bus 166. The external bus master 151 may be directly connected to the external bus I / O 163. In other words, the external bus master 151 executes data transfer via the bus and is directly connected to this bus or indirectly connected via another bus or the like.

  FIG. 11 is a functional block diagram of software for explaining the second embodiment. The scheduling unit 22 causes the external bus master 151 to execute a scheduled data transfer request. The external bus master driver control means 31 controls the external bus master driver means 32 based on a command from the bus / transfer control means 225. The external bus master driver means 32 is a driver that controls the external bus master 151. The completion interrupt acceptance means 33 accepts a completion interrupt notification from the OS 23 and outputs it to the request completion notification acceptance means 222.

  The scheduling means 22 selects the data transfer request with the highest priority among the received data transfer requests (see steps S7 to S9 in FIG. 5B). When the selected data transfer request causes the external bus master 151 to execute the data transfer request, the external bus master driver unit 32 is instructed to execute the data transfer request. In response to this command, the external bus master driver means 32 causes the external bus master 151 to execute the selected data transfer request.

  The task 21 calls the data transfer request API as described in step S1 of FIG. 5A. At this time, the data transfer request described in FIG. 4 is generated by the task 21 and set as an argument in the data transfer request API. As a result, a data transfer request is input to the scheduling means 22. “External DMAC transfer” is recorded as the data transfer request type of this data transfer request. Hereinafter, this data transfer request is referred to as an external bus master data transfer request.

  The processing described with reference to FIGS. 5A and 5B is executed by the scheduling unit 22 by calling the data transfer request API. At this time, the request generation accepting means 221 confirms that “external DMAC transfer” (see FIG. 4) is recorded in the type of data transfer request, and the request for external bus master data transfer request is sent to the external bus master data transfer request. Assign an identifier.

  Then, as described in step S10 of FIG. 5B, the identifier of the data transfer request with the highest priority, here the identifier of the external bus master data transfer request is input to the bus / transfer control means 225 from the scheduler with priority 224. The The bus / transfer control means 225 outputs the identifier to the external bus master driver control means 31 because the input identifier is the identifier of the external bus master data transfer request.

  As described in step S12, the external bus master driver control means 31 reads the external bus master data transfer request corresponding to this identifier from the request storage section 141 via the request management means 223 via the request management means 223. . The external bus master driver control means 31 outputs the read data transfer request to the external bus master driver means 32. The external bus master driver means 32 instructs the external bus master 151 to execute the data transfer request via the OS 23 based on the read data transfer request. The external bus master 151 executes a data transfer request in response to this command.

  When the DMAC 11 or the external bus master 151 is executing a data transfer request, the bus / transfer control means 225 temporarily executes the data transfer request being executed when the identifier of the external bus master data transfer request is input. It instructs the DMAC 11 or the external bus master 151 via the bus master driver control means 226 or the external bus master driver control means 31 to stop.

  When the external bus master 151 completes the data transfer request, the request completion notification accepting means 222 sends the data transfer completion notice to the completion interrupt accepting means 33 of the external bus master driver means 32 as described in step S21 of FIG. 6A. Accept from. Specifically, when the external bus master 151 completes the data transfer, the external bus master 151 notifies the IRC 13 that the data transfer is complete. When the IRC 13 receives a transfer completion notification from the external bus master 151, the IRC 13 issues a transfer completion interrupt to the CPU 12 to notify the completion of the data transfer. Upon receiving the transfer completion interrupt notification, the CPU 12 outputs a transfer completion notification to the completion interrupt acceptance means 33 of the external bus master driver means 32 via the interrupt handler 231 of the OS 23. The completion interrupt reception unit 33 outputs the received transfer completion notification to the request completion notification reception unit 222.

  Thereafter, the data transfer completion process described with reference to FIGS. 6A and 6B is executed.

  Thus, even if the user newly adds a bus master to the hardware 10, the scheduling means 22 can schedule the data transfer executed by the bus master.

(Third embodiment)
The task 21 may make a data transfer request directly to the bus master instead of the scheduling means 22. A bus master that directly receives the data transfer request without passing through the scheduling means 22 (hereinafter referred to as an unscheduled bus master) executes the data transfer request.

  When such a non-scheduled bus master executes a data transfer request while a bus master scheduled by the scheduling means 22 (hereinafter referred to as a scheduled bus master) is executing a data transfer request, a plurality of bus arbiters are simultaneously provided. The use request from the bus master must be arbitrated. As a result, the scheduled bus master cannot efficiently execute the data transfer request.

  In such a case, it is preferable that the bus arbiter dynamically changes the priority of the bus use request from the scheduled bus master, that is, gives the bus use right preferentially to the scheduled bus master.

  A bus arbiter that performs arbitration of such bus use requests will be described below with reference to FIGS.

  FIG. 12 is a functional block diagram illustrating a bus having a bus arbiter that preferentially gives a bus use right to a scheduled bus master.

  FIG. 13 is a functional block diagram for explaining the bus arbiter control means 41 for controlling the bus arbiter shown in FIG. 12 and the arbiter driver group 42 having a bus arbiter driver.

  FIG. 14 is a functional block diagram of the bus arbiter control means 41 and the arbiter driver group 42.

  FIG. 15 is a functional block diagram of any of the bus arbiters shown in FIG. 12 and the bus arbiter driver means of this bus arbiter. The bus arbiter 160 corresponds to one of the bus arbiters (DMAC bus arbiter 114 ′, bus 1A arbiter 161a ′, bus 2A arbiter 162a ′, bus 1B arbiter 161b ′, bus 2B arbiter 162b ′, external bus arbiter 163a ′) shown in FIG. . The bus arbiter driver means 420 is a driver means for controlling the bus arbiter 160, and each arbiter driver means (DMAC arbiter driver means 421, bus 1A arbiter driver means 422, bus 2A arbiter driver in FIG. 14). Means 423, bus 1B arbiter driver means 424, bus 2B arbiter driver means 425, external bus arbiter driver means 426).

  First, a process for calculating the number of usable cycles indicating the number of cycles in which the bus master can use the bus in a predetermined period, which is information referred to when the bus arbiter preferentially gives the bus use right to the scheduled bus master, will be described.

  14 includes arbiter driver means (DMAC arbiter driver means 421, bus 1A arbiter driver means 422, bus 2A arbiter driver means 423, bus 1B arbiter driver means 424, bus 2B arbiter driver. The corresponding bus arbiter (DMAC bus arbiter 114 ', bus 1A arbiter 161a', bus 2A arbiter 162a ', bus 1B arbiter 161b', bus 2B arbiter 162b ', external bus arbiter 163a' via means 425, external bus arbiter driver means 426) ) Read the bus master statistical information. This statistical information indicates a bus used time in which a bus master of a certain bus has used this bus during a predetermined period. For example, in the case of the external bus I / O 163 in FIG. 12, the bus 2A_162A and the external bus master 151, which are the bus masters of the external bus I / O 163, are the number of use cycles using the external bus I / O 163 in a predetermined period. Since only the external bus master 151 is connected to the external bus 166, the external bus master 151 becomes the bus master of the external bus I / O 163. Here, the bus used times of the bus 2A_162A and the external bus master 151 are T1 and T2, respectively.

  The usage rate calculation means 412 calculates the bus usage rate (hereinafter abbreviated as usage rate) of each bus master of the bus by (Equation 1).

Usage ratio of bus master of a certain bus = Usage ratio used in the past by this bus master x (α) + Usage ratio used in the future by this bus master x (1-α) (Equation 1)
Hereinafter, the usage ratio used in the past by the bus master is referred to as the past usage ratio, and the usage ratio used in the future by the bus master is referred to as the expected bus usage ratio of the bus master. Α is a weighting coefficient and is a numerical value of 0 or more and 1 or less such as 0, 0.25, 0.5, 0.75, 1.00. When this value is smaller than 0.5, the bus master's expected bus usage rate is more reflected in the calculation of the bus master usage rate. Α can be arbitrarily changed.

  The past use ratio is obtained by dividing the bus used time of each bus master of a bus by the total bus used time of all bus masters of this bus. In the above example, the usage ratios of the bus 2A_162A and the external bus master 151 are T1 / (T1 + T2) and T2 / (T1 + T2), respectively.

  The expected bus usage ratio is calculated by dividing the data transfer amount that each bus master of a certain bus will execute in the future (corresponding to the data transfer size in Fig. 4) by the total data transfer amount that all bus masters of this bus will execute in the future. can get. The amount of data transfer to be executed in the future is obtained as follows.

  First, the bus arbiter control unit 41 accesses the request storage unit 141 via the bus / transfer control unit 225 and the request management unit 223 at a predetermined timing, and transfers the data waiting for execution stored in the request storage unit 141. Search for requests. Then, all the buses of the data transfer path configured when executing the searched data transfer request and the bus master of this bus are specified. A bus path configured when executing this data transfer request is referred to as a data transfer path.

  In order to specify the bus that constitutes the data transfer path, connection information between the buses and connection information of the bus master connected to the bus are necessary. These connection information is managed by the bus / transfer control means 225, for example. , Shall be recorded.

  For example, it is assumed that the first data transfer request waiting for execution is stored in the request storage unit 141. In the first data transfer request, it is assumed that, for example, DMACCh0_110 of the DMAC 11 functioning as a bus master executes data transfer of the data transfer amount D1 from a device (not shown) connected to the bus 1A_162A to the external slave device 152, for example. As shown in FIG. 4, the data transfer amount D1 is recorded in the data transfer size of the first data transfer request.

  The bus arbiter control means 41 specifies all the buses constituting the first data transfer path of the first data transfer request and the bus master of this bus. The buses constituting the first data transfer path are a DMAC bus 113, a bus 1A_161A, a bus 2A_162A, an external bus I / O163, and an external bus 166. Then, the bus master of each bus is specified. In the above example, the bus master of the DMAC bus 113 is identified as DMACch0_110, the bus master of the bus 1A_161A is identified as the DMAC bus 113, the bus master of the bus 2A_162A is identified as the bus 1A_161A, and the bus master of the external bus I / O163 is identified as the bus 2A_162A. Next, let D1 be the data transfer amount of the specified bus master.

  Then, the data transfer amount of a bus master other than the specified bus master is set to a data transfer amount D2 smaller than the data transfer amount D1. The data transfer amount D2 is 0, for example.

  Then, for each identified bus, the sum of the data transfer amounts of each bus master for each bus is calculated. In the case of the external bus I / O 163, since the bus masters are the bus 2A_162A and the external bus master 151, the total data transfer amount of the external bus I / O 163 is (D1 + D2). Then, the data transfer amount D1 of the bus 2A_162A, which is the bus master, is divided by the total sum (D1 + D2) of the calculated data transfer amount. This division value is the expected bus usage rate for bus 2A_162A.

  Similarly, the data transfer amount D2 of the external bus master 151, which is a bus master, is divided by the calculated sum of data transfer amounts (D1 + D2). This division value is the expected bus use ratio of the external bus master 151. This bus use expectation calculation process is executed for each bus master of all buses.

  By substituting the past usage rate and the expected bus usage rate calculated as described above into (Equation 1), the usage rates of the bus master 2A_162A and the external bus master 151 of the external bus I / O 163 can be calculated. .

  The usage ratio of the bus 2A_162A is ((T1 / (T1 + T2)) × α) + ((D1 / (D1 + D2)) × (1-α)). Hereinafter, the calculated usage ratio of the bus 2A_162A is R1.

  The usage ratio of the external bus master 151 is ((T2 / (T1 + T2)) × α) + ((D2 / (D1 + D2)) × (1−α)). Hereinafter, the calculated usage ratio of the external bus master 151 is R2.

  The usage rate calculation unit 412 executes the bus master usage rate calculation process described above for each bus master of all the buses, and outputs the calculation result to the usable cycle number calculation unit 413. In addition, although the case where one data transfer request is stored in the request storage unit 141 is illustrated, the same applies to two or more data transfer requests.

  Next, the usable cycle number calculating unit 413 calculates the usable cycle number of each bus master of all the buses based on the calculation result input from the use ratio calculating unit 412. The number of usable cycles is calculated based on (Equation 2).

Number of usable cycles for a certain bus master = number of cycles for the scheduling period x usage ratio of this bus master ... (Formula 2)
The number of cycles in the scheduling period is the number of cycles corresponding to the predetermined period, and can be arbitrarily changed. The bus master usage rate is the value calculated by (Equation 1).

  The number of usable cycles of the bus 2A_162A that is the bus master of the external bus I / O 163 is the number of scheduling period cycles × the usage ratio R1 of the bus 2A_162A.

  The number of usable cycles of the external bus master 151 which is the bus master of the external bus I / O 163 is the number of scheduling period cycles × the usage ratio R2 of the external bus master 151.

  In other words, the usable cycle number calculation means 413 calculates the number of usable cycles (bus usable time) of a bus master that executes a data transfer request waiting for execution (data transfer request being accepted), that is, a scheduled bus master. Based on the data transfer amount of the transfer request, it is calculated to be longer than the number of usable cycles of the bus master that does not execute the data transfer request waiting for execution, that is, the bus master that is not scheduled. This is because the expected bus usage rate of the scheduled bus master is larger than the expected bus usage rate of the non-scheduled bus master. In this case, it is preferable to set the weighting coefficient α in (Equation 1) to 0.

  The usable cycle number calculating means 413 can also calculate the number of usable cycles of the scheduled bus master based on the data transfer amount of the bus master and the bus used time. In this case, the weighting coefficient α in (Equation 1) is 0 <α <1. Based on this used time, the number of usable cycles can be calculated in consideration of the past bus use status of the bus master. In this case, the number of usable cycles of the unscheduled bus master is calculated based on the bus used time. Therefore, even a bus master that is not scheduled can execute a data transfer request.

  The usable cycle number calculation means 413 executes the bus master usable cycle number calculation process described above for each bus master of all the buses, and outputs the calculation result to the allocation information setting means 415. The processing executed by the allocation information setting unit 415 will be described later.

  Next, processing for calculating the priority of the bus master will be described. As described above, the priority of the bus master is higher as the numerical value is higher. First, as described above, the bus arbiter control unit 41 first accesses the request storage unit 141 via the bus / transfer control unit 225 and the request management unit 223, and waits for execution stored in the request storage unit 141. Search for the data transfer request and specify the priority of the searched data transfer request.

  Then, the priority of the bus master of the bus constituting the data transfer path of the data transfer request with the highest priority is calculated as the highest priority, for example, priority 5, and other bus masters have a priority lower than the highest priority. For example, priority 4 is calculated.

  For example, when the priority of the first data transfer request is the highest, the priority of the DMACch0_110, the DMAC bus 113, the bus 1A_161A, and the bus 2A_162A that are the bus masters of the data transfer path of the first data transfer request The degree is calculated as priority 5. In the case of the external bus I / O 163, the priority level 5 is calculated for the bus 2A_162A, and the priority level 4 is calculated for the external bus master 151.

  In addition, the priority of the bus master may be calculated based not only on the priority of the data transfer request but also on the data transfer amount of the data transfer request. For example, if there are multiple data transfer requests with the highest priority, the priority of the bus master of the bus that constitutes the data transfer path of the data transfer request with the largest data transfer amount among the data transfer requests with the highest priority. Make it the highest priority. Then, the priority of the bus master of the bus constituting the data transfer path of the data transfer request having the next largest data transfer amount is set to a priority lower than the highest priority. Then, the priority of other bus masters is set lower than this low priority.

  In addition, the priority of the bus master of the bus constituting the data transfer path of the data transfer request with the highest priority is set as the highest priority. Then, the priority of the bus master of the bus constituting the data transfer path of the data transfer request that has just ended is set to a priority lower than the highest priority. Then, the priority of other bus masters is set lower than this low priority.

  In the above example, the priority calculation means 414 calculates the priority of the bus master at five levels. However, in the bus arbiter, only three levels of priority may be set as the bus master due to specifications. In such a case, the priority calculation means 414 compresses the calculated priority value range so as to correspond to the specifications of the bus arbiter. For example, when the priority calculation unit 414 calculates the priority 5, the value range is compressed to the priority 3 in order to correspond to the specification of the bus arbiter. If the bus arbiter specification is in 10 stages, the calculated priority range is expanded to correspond to the bus arbiter specification.

  For example, when the priority calculation unit 414 searches for a plurality of data transfer requests having the same priority, the same priority may be calculated for different bus masters of a certain bus. In some cases, the bus arbiter of this bus has a specification that cannot set the same priority as the bus master. In such a case, the priority calculation means 414 sequentially changes the priority of each bus master and changes the priority so as not to have the same priority.

  The priority calculation unit 414 executes the bus master priority calculation process described above for each bus master of all the buses, and outputs the calculation result to the allocation information setting unit 415.

  The allocation information setting unit 415 includes the number of usable cycles of each bus master corresponding to each bus input from the usable cycle number calculating unit 413 and the priority of each bus master corresponding to each bus input from the priority calculating unit 414. The degree is set in the allocation register 1604 (see FIG. 15) of the bus arbiter 160 via the bus arbiter driver corresponding to each bus.

  In the above example, the allocation information setting unit 415 in FIG. 14 includes the number of usable cycles from the usable cycle number calculating unit 413 and the number of usable cycles of the bus 2A_162A that is the bus master of the external bus I / O 163 and the number of usable cycles of the external bus master 151. Entered. Further, the priority of the external bus master 151 and the priority of the external bus master 151 are input to the allocation information setting unit 415 from the priority calculation unit 414.

Then, the allocation information setting unit 415 uses the register setting unit (see FIG. 14) of the external bus arbiter driver unit 426 that controls the external bus arbiter 163a ′ of the external bus I / O 163, so that the allocation register 1604 ( (See Fig. 15). Assignment register 1604 stores the priority and the number of usable cycles of the bus 2A_162A which is set the bus master information 1601 ₁ available cycle number 1601b bus master memory 1601 is allocated corresponding to the bus 2A_162A, the priority 1601a To do. Similarly, assignment register 1604, set the external bus master 151 of available cycle number and priority and the external bus master 151 to the bus master information 1601 ₂ available cycle number 1601b bus master memory 1601 is allocated corresponding priority Store in degrees 1601a.

  The allocation information setting means 415 executes this setting process for all bus arbiters. Details of the bus master memory 1601 and the like will be described with reference to FIG.

  Next, processing for dynamically changing the priority order of bus masters with reference to the set number of usable cycles and priority will be described with reference to FIGS.

  The bus arbiter 160 in FIG. 15 arbitrates the bus use request from the bus master according to the priority set for each bus master. At this time, as described later, the used cycle number counter 1602 of the bus arbiter 160 counts the bus used time (number of used cycles) of the bus master.

  Here, in a predetermined period (scheduling period cycle number), the number of used cycles of the first bus master exceeds the number of usable cycles stored corresponding to the first bus master, and further, the first bus master If there is a bus use request from the second bus master and these bus use requests conflict, the number of usable cycles will be exceeded without passing the right to use the bus to the first bus master that has exceeded the available number of cycles. A process of giving the bus use right preferentially to the second bus master that has not been executed is executed.

  Here, it is assumed that the first bus master is a non-scheduled bus master and the second bus master is a scheduled bus master. Normally, the number of usable cycles of the first bus master is smaller than the number of usable cycles of the second bus master. As described above, the estimated bus use ratio of the first bus master is 0. Therefore, as apparent from (Equation 1), the weighting coefficient α in (Equation 1) is reduced (for example, 0). , The usage ratio of the first bus master is reduced. As a result, as apparent from (Equation 2), the number of usable cycles of the first bus master is reduced.

  That is, in the predetermined period, the second bus master has a longer bus usable time than the first bus master, so that the bus use right is given preferentially and the bus can be used preferentially. As a result, the second bus master can efficiently execute the data transfer request.

The bus master memory 1601 of the bus arbiter 160 is a memory that stores bus master information of the bus master. The bus master memory 1601 has bus master information 1601 ₁ ... 1601 _n which is an area for storing bus master information for each bus master, and includes priority 1601a, usable cycle number 1601b, usable cycle number excess flag 1601c which are bus master information. , The number of used cycles 1601d is stored. If the bus arbiter 160 is an external bus arbiter 163a ', the bus master information 1601 _1, a master information storage area provided in correspondence to the bus 2A_162A a bus master, the bus master information 1601 _2, corresponding to the external bus master 151 is a bus master The bus master information storage area is provided.

  The use cycle counter 1602 is a counter that counts the number of cycles in which the bus master that has acquired the bus use right from the bus arbiter 160 executes data transfer using the bus, and the count result is provided corresponding to this bus master. Stored in the used cycle number 1601d of the bus master memory 1601.

The statistical information register 1603 is a register that reads and stores the number of used cycles for each bus master from the number of used cycles 1601d of the bus master information 1601 _{1 to} 1601 _{n in} the bus master memory 1601 provided for each bus master. . The number of used cycles for each bus master stored in the statistical information register 1603 is read by the statistical information reading means 411 of the bus arbiter control means 41 via the statistical information register reading means 4202 of the bus arbiter driver means 420.

The allocation register 1604 corresponds to the priority and the number of usable cycles for each bus master set from the allocation information setting means 415 of the bus arbiter control means 41 via the register setting means 4201 of the bus arbiter driver means 420 for each bus master. Stored in the priority 1601a and usable cycle number 1601b of the bus master information 16011 _{1 to} 1601 _n of the provided bus master memory 1601. A specific example has been described above and will not be described.

  The scheduling cycle number counter 1605 is a counter provided for detecting whether or not a predetermined period corresponding to the above-described scheduling period cycle number has elapsed, and the scheduling cycle number recorded in the scheduling period cycle number 1606a of the scheduling memory 1606. When the number of cycle cycles elapses, the counter is reset to 0 and the cycle count starts. The count result is stored in the scheduling cycle number 1606b of the scheduling memory 1606.

  Here, when the predetermined period elapses, the bus arbiter 160 turns off all the usable cycle number excess flags 1601c stored corresponding to each bus master (reset). At this time, the value set in the allocation register 1604 is already stored in the bus master memory 1601 corresponding to each bus master.

  When the first bus master requests the bus usage right to the bus arbiter 160, the bus arbiter 160 accepts this request, passes the usage right to the first bus master, and executes data transfer. During execution of this data transfer request, the used cycle number counter 1602 counts the number of used cycles of the first bus master and stores it in the number of used cycles 1601d for the first bus master. When the second bus master requests the right to use the bus to the bus arbiter 160 during execution of this data transfer, the bus arbiter 160 accepts this request and stores it corresponding to the first and second bus masters. Arbitrate bus use request according to priority 1601a. Similarly, the used cycle number counter 1602 counts the number of used cycles of the second bus master and stores it in the number of used cycles 1601d for the second bus master.

  When the used cycle number of the first bus master exceeds the usable cycle number 1601b of the first bus master, the bus arbiter 160 sets the usable cycle number excess flag 1601c to ON.

  Then, if there is a bus use request again from the first bus master in which the usable cycle count excess flag is set on and the second bus master in which the flag is set off in a predetermined period, the bus arbiter 160 Executes control to pass the bus usage right to the second bus master without passing the bus usage right to the first bus master. As a result, the second bus master that has acquired the bus use right can use the bus preferentially.

  Thereafter, when the predetermined period elapses, the bus arbiter 160 turns off all the usable cycle number excess flags 1601c recorded for each bus master.

  Here, as described above, it is assumed that the first bus master is a non-scheduled bus master and the second bus master is a scheduled bus master. When there is a bus use request from the first bus master and the second bus master, the usable cycle count excess flag of the first bus master is earlier than the usable cycle count excess flag of the second bus master is set to ON. Set to on. This is because, as described above, the number of usable cycles (usable time) of the first bus master is smaller than the number of usable cycles of the second bus master. If the usable cycle count excess flag of the first bus master is set to ON first, the second bus master can use the bus preferentially and perform data transfer efficiently.

  As described above, according to the third embodiment, the data transfer by the scheduled second bus master is not hindered by the data transfer executed by the first non-scheduled bus master. The second bus master can execute data transfer efficiently.

(Fourth embodiment)
The CPU 12 has a function of executing PIO transfer. The PIO transfer function allows the CPU 12 to execute data transfer independently. A task executed in the CPU 12 may execute data transfer using the PIO transfer function.

  In such a case, if the CPU 12 executes PIO transfer without being scheduled by the scheduling means 22, the efficiency of the data transfer request executed by the scheduled bus master decreases. Therefore, it is necessary to schedule the PIO transfer executed by the CPU 12 by the scheduling means 22.

  FIG. 16 is a functional block diagram of software according to the fourth embodiment.

  The task 51 is a task including a processing unit (program) that causes the CPU 12 to execute the PIO transfer, and is executed by the CPU 12 as described above.

  The PIO transfer start request API calling means 511 calls an API for executing a PIO transfer start request to the scheduling means 22. By this API call, a data transfer request for PIO transfer is generated by the task 51 and input to the scheduling means 22. The data transfer request type of this data transfer request records the PIO transfer of the CPU (see FIG. 4). Hereinafter, this data transfer request is referred to as a PIO data transfer request.

  The PIO transfer instruction means 512 instructs the CPU 12 to execute a PIO data transfer request and causes the CPU 12 to execute a PIO transfer corresponding to the PIO data transfer request. When the PIO data transfer is completed, the PIO transfer completion notification API calling unit 513 calls the PIO transfer completion notification API that notifies the scheduling unit 22 of the completion. The task 51 executes the PIO transfer start request API calling means 511, the PIO transfer instruction means 512, and the PIO transfer completion notification API calling means 513 in this order. Therefore, the PIO transfer corresponding to the PIO data transfer request is executed by the CPU 12 by the execution of the PIO transfer start request API calling means 511.

  Therefore, when the request generation accepting means 221 accepts the PIO data transfer request, the scheduling means 22 does not cause the CPU 12 to start executing the PIO transfer corresponding to this PIO data transfer request. When the priority of the PIO data transfer request becomes the highest among the received data transfer requests, the CPU 12 is caused to start executing this PIO transfer. In this way, the scheduling means 22 can schedule PIO transfer by the CPU 12.

  Note that task 51 executes some processing before executing PIO transfer start request API calling means 511, and task 51 executes the following processing after executing PIO transfer completion notification API calling means 513. There is.

  The CPU core control means 52 controls the core of the CPU 12 via the OS 23 in response to an instruction from the request generation accepting means 221 or the bus / transfer control means 225. The task suspension instruction means 521 executes an instruction to suspend execution of the task 51 to the CPU 12 via the OS 23. With this temporary stop instruction, the CPU 12 temporarily stops the execution of the task 51. As a result, the PIO transfer execution instruction by the PIO transfer instruction means 512 is not issued to the CPU 12, and the CPU 12 does not start executing the PIO transfer. The task resuming instruction means 522 executes a command for resuming the execution of the task temporarily suspended in the CPU 12 via the OS 23. With this resume instruction, the CPU 12 resumes the execution of the task that has been paused. As a result, a PIO transfer execution instruction is performed by the PIO transfer instruction means 512, and the CPU 12 starts executing the PIO transfer.

  17A to 17C are flowcharts for explaining the start of execution of a PIO data transfer request.

  Step S101: The PIO transfer start request API calling means 511 calls the PIO transfer start request API. At this time, the PIO data transfer request generated by the task 51 is set as an argument in the PIO transfer start request API. In the type of data transfer request of this PIO data transfer request, “PIO transfer by CPU” (see FIG. 4) is recorded.

  Step S102: The request generation accepting means 221 of the scheduling means 22 accepts the PIO data transfer request, confirms that “PIO transfer by CPU” is recorded in the type of data transfer request, and identifies the identifier for the PIO data transfer request. Is assigned to this PIO data transfer request. This identifier is used by the scheduling means 22 to manage the PIO data transfer request. This identifier is input to the task 51 as a return value of the data transfer request API called by the task 51.

  Step S103: The request generation accepting means 221 instructs the CPU core control means 52 to suspend the task 51 being executed by the CPU 12 based on the confirmation in step S102.

  Step S104: The task suspension instruction means 521 of the CPU core control means 52 instructs the CPU 12 to instruct suspension of the task being executed via the OS 23. The CPU 12 temporarily stops the task being executed. As a result, no PIO transfer is performed.

  Step S105: The request generation acceptance unit 221 instructs the request management unit 223 to store the accepted PIO data transfer request in the request storage unit 141. At the same time, the request generation accepting means 221 outputs this data transfer request and identifier to the scheduler 224 with priority.

  Since the processing of steps S106 to S112 is the same as the processing of steps S4 to S10, description thereof is omitted.

  Step S113: The bus / transfer control means 225 instructs the CPU core control means 52 to execute the PIO data transfer request based on the highest priority data transfer request, that is, the PIO data transfer request. As described in step S11, in step S112, the identifier of the data transfer request with the highest priority, that is, the identifier for the PIO data transfer request is input to the bus / transfer control means 225 from the scheduler 224 with priority. Based on this PIO data transfer request identifier, the bus / transfer control means 225 determines that the data transfer request to be executed is PIO data transfer, and executes the above-mentioned instruction to the CPU core control means 52. At this time, if a data transfer request being executed by the DMAC 11 is being executed, the bus master driver control means 226 is instructed to temporarily stop the data transfer request. This data transfer temporary stop instruction has been described in step S12 in FIG.

  Step S114: The task resumption instruction means 522 of the CPU core control means 52 responds to the execution instruction of the PIO data transfer request from the bus / transfer control means 225, and resumes the task temporarily suspended via the OS 23 to the CPU 12. Command.

  Step S115: In response to the task restart command, the CPU 12 restarts the task 51, and the restarted task 51 executes the PIO transfer command means 512. That is, the CPU 12 executes PIO transfer based on the PIO data transfer request generated in step S101.

  18A and 18B are flowcharts for explaining processing when a PIO data transfer request is completed.

  Step S121: When the CPU 12 completes the PIO data transfer request described in step S115 of FIG. 17C, the task 51 executes the PIO transfer completion notification API calling means 513 to indicate that the PIO data transfer request has been completed. Is notified to the request completion notification accepting means 222 of the scheduling means 22 together with the identifier for the PIO data transfer request inputted in.

  The processing of steps S122 to S127 is the same as the processing of steps S22 to S27 described with reference to FIGS. 6A and 6B, and thus description thereof is omitted.

  Step S128: The scheduler with priority 224 outputs the identifier of the data transfer request with the highest priority to the bus / transfer control means 225.

  Step S129: The bus / transfer control means 225 instructs the CPU core control means 52 or the bus master driver control means 226 to execute the data transfer request based on the data transfer request with the highest priority. Here, if the identifier input from the priority-added scheduler 224 is an identifier for a PIO data transfer request, the above command is sent to the CPU core control means 52. If the input identifier is other than that, the command is sent to the bus master driver control means 226. When the CPU core control means 52 receives the command, the process proceeds to step S130. When the bus master driver control means 226 receives the command, the process proceeds to step S131.

  The processing in step S130 is the same as the processing in step S114 in FIG. Note that the processing in step S130 is executed when the scheduling means 22 has received a PIO data transfer request from a task other than the task 51, for example. Further, the processing in step S131 is the same as the processing in step S30 in step S6B, and thus description thereof is omitted.

  According to the fourth embodiment, the scheduling means 22 can schedule the PIO data transfer executed by the CPU. As a result, the efficiency of the data transfer request executed by the scheduled bus master does not decrease.

  In each of the described embodiments, the CPU 12 may execute a plurality of tasks. A plurality of bus master devices such as DMAC may be provided. In this case, bus master driver means for controlling the bus master device is also provided.

  Moreover, you may combine each embodiment demonstrated. For example, the second embodiment and the third embodiment may be combined. Further, the second embodiment and the fourth embodiment may be combined.

  The above embodiment is summarized as follows.

(Appendix 1)
With bus,
A CPU connected to the bus;
A plurality of bus masters connected to the bus and executing data transfer via the bus;
A bus arbiter that arbitrates a bus use request from the bus master and gives a bus use right to any of the bus masters;
Bus master driver means for controlling the plurality of bus masters;
A data transfer request generated by a task executed by the CPU is received, a data transfer request with the highest priority is selected from the received data transfer requests, and execution of the selected data transfer request is performed by the bus master. Scheduling means for instructing the driver means;
The bus master driver means, in response to the command, causes the bus master corresponding to the selected data transfer request to execute the selected data transfer request.

(Appendix 2)
In Appendix 1,
When the scheduling unit receives a data transfer request newly generated by the task while the selected data transfer request is being executed by the bus master, the priority of the received data transfer request is If the priority is higher than the priority of the data transfer request being made, the bus master driver means is instructed to temporarily stop the data transfer request being executed, and the bus master driver is requested to execute the newly generated data transfer request. Command the driver means,
The bus master driver means suspends the data transfer request being executed and suspends the data transfer request being executed in response to the execution command of the newly generated data transfer request. A data transfer system that causes a bus master to execute and causes the bus master corresponding to the newly generated data transfer request to execute the data transfer request.

(Appendix 3)
In Appendix 2,
When the scheduling means receives a completion notification indicating that the execution of the newly generated data transfer request is completed, the bus master driver resumes the suspended data transfer request in response to the completion notification. Command the means,
The bus master driver means causes the bus master to resume the temporarily stopped data transfer request.

(Appendix 4)
In any one of supplementary notes 1 to 3,
When the scheduling unit receives the data transfer request suspension command from the task, the scheduling unit suspends scheduling of the data transfer request in response to the suspension command, and the suspended data transfer from the task. A data transfer system that, upon receiving a request resumption instruction, responds to the resumption instruction and resumes scheduling of the suspended data transfer request.

(Appendix 5)
In any one of appendices 1 to 4,
When the scheduling means receives a forced termination command for the data transfer request from the task, the scheduling means ends the scheduling of the data transfer request in response to the forced termination command.

(Appendix 6)
In any one of appendices 1 to 5,
The bus arbiter is a data transfer system that assigns bus usage rights to the buses in a time-sharing manner according to the priority set for the plurality of bus masters in response to bus use requests from the plurality of bus masters.

(Appendix 7)
In any one of supplementary notes 1 to 6,
The bus is a data transfer system having a bus structure in which a plurality of buses are connected in multiple stages.

(Appendix 8)
In any one of appendices 1 to 7,
Furthermore, an external bus master that performs data transfer via the bus and is directly connected to the bus or connected via another bus,
External bus master driver means for controlling the external bus master;
The scheduling means instructs the external bus master driver means to execute the data transfer request when the selected data transfer request causes the external bus master to execute the data transfer request;
The external bus master driver means causes the external bus master to execute the selected data transfer request in response to the command.

(Appendix 9)
In any one of appendices 1 to 7,
Any of the plurality of bus masters executes the data transfer request generated by the task without passing through the scheduling means,
The scheduling means calculates the bus usable time of the bus master executing the accepted data transfer request based on the data transfer amount of the data transfer request longer than the bus usable time of the bus master not executing the data transfer request. ,
The bus arbiter is a data transfer system that preferentially gives a bus use right to a bus master having a longer bus usable time.

(Appendix 10)
In Appendix 9,
The bus arbiter counts the bus used time of the plurality of bus masters,
The data transfer system, wherein the scheduling means calculates a bus usable time of the bus master based on a bus used time of the bus master.

(Appendix 11)
In any one of appendices 1 to 7,
The CPU executes PIO (Programmed I / O) transfer,
The task generates a PIO data transfer request that causes the CPU to execute a PIO transfer, causes the CPU to execute a PIO transfer corresponding to the PIO data transfer request,
When the scheduling means accepts the PIO data transfer request, the scheduling means does not cause the CPU to start executing the PIO transfer, and the priority of the PIO data transfer request becomes the highest among the accepted data transfer requests. A data transfer system for causing the CPU to start executing the PIO transfer.

(Appendix 12)
In a data transfer system comprising a bus, a CPU connected to the bus, a plurality of bus masters connected to the bus and executing data transfer via the bus, and bus master driver means for controlling the plurality of bus masters A data transfer scheduling program executed by the CPU,
Receiving a data transfer request generated by a task executed by the CPU;
The data transfer request having the highest priority is selected from the received data transfer requests, the bus master driver means is instructed to execute the selected data transfer request, and the bus master driver means selects the selected data transfer request. A data transfer scheduling program for causing the CPU to execute a step of causing the bus master corresponding to the data transfer request to execute the selected data transfer request.

(Appendix 13)
In Appendix 12,
Further, when a data transfer request newly generated by the task is received while the selected data transfer request is being executed by the bus master, the priority of the received data transfer request is being executed. When the priority of the data transfer request is higher, the data transfer request being executed is temporarily stopped, and the bus master driver means is instructed to execute the newly generated data transfer request. Means for causing the bus master to temporarily stop the data transfer request being executed, and causing the CPU to execute a step of causing the bus master corresponding to the newly generated data transfer request to execute the data transfer request. Transfer scheduling program.

1 ... Data transfer system, 10 ... Hardware, 11 ... DMAC, 12 ... CPU, 13 ... IRC, 14 ... Memory, 15 ... External bus master, 16 ... Bus, 16a ... Bus arbiter, 20 ... Software, 21 ... Task, 22 ... Scheduling means, 221 ... request generation acceptance means, 222 ... request completion notice acceptance means, 223 ... request management means, 224 ... scheduler, 225 ... transfer control means, 226 ... bus master driver control means, 23 ... OS, 24 ... bus master driver means , 141 ... request storage unit, 142 ... request queue according to priority, 31 ... external bus master driver control means, 32 ... external bus master driver means, 41 ... bus arbiter control means, 411 ... statistical information reading means, 412 ... usage rate calculation means, 413 ... Usable cycle number calculating means, 414 ... Priority calculating means, 415 ... Assignment information setting means, 42 ... Arbiter driver group, 420 ... Bus arbiter driver means, 4201 ... Register setting means, 4202 ... Statistical information register reading means, 51 ... Task, 511 ... PIO transfer start request API calling means, 512 ... PIO transfer instruction means, 513 ... PIO transfer completion notification API calling means, 52 ... CPU core control means, 521 ... Task temporary stop command means, 522 ... Task restart command means.

Claims (7)

With bus,
A CPU connected to the bus;
A plurality of bus masters connected to the bus and executing data transfer via the bus;
A bus arbiter that arbitrates a bus use request from the bus master and gives a bus use right to any of the bus masters;
Bus master driver means for controlling the plurality of bus masters;
A data transfer request generated by a task executed by the CPU is received, a data transfer request with the highest priority is selected from the received data transfer requests, and execution of the selected data transfer request is performed by the bus master. Scheduling means for instructing the driver means;
The bus master driver means, in response to the command, causes the bus master corresponding to the selected data transfer request to execute the selected data transfer request,
Any of the plurality of bus masters executes the data transfer request generated by the task without passing through the scheduling means,
The scheduling means calculates the bus usable time of the bus master executing the accepted data transfer request based on the data transfer amount of the data transfer request longer than the bus usable time of the bus master not executing the data transfer request. ,
The bus arbiter is a data transfer system that preferentially gives a bus use right to a bus master having a longer bus usable time. In claim 1 ,
When the scheduling unit receives a data transfer request newly generated by the task while the selected data transfer request is being executed by the bus master, the priority of the received data transfer request is If the priority is higher than the priority of the data transfer request being made, the bus master driver means is instructed to temporarily stop the data transfer request being executed, and the bus master driver is requested to execute the newly generated data transfer request. Command the driver means,
The bus master driver means suspends the data transfer request being executed and suspends the data transfer request being executed in response to the execution command of the newly generated data transfer request. A data transfer system that causes a bus master to execute and causes the bus master corresponding to the newly generated data transfer request to execute the data transfer request. In claim 1 ,
When the scheduling means receives a completion notification indicating that execution of the newly generated data transfer request is completed, the scheduling means resumes the suspended data transfer request in response to the completion notification. Command the driver means,
The bus master driver means causes the bus master to resume the temporarily stopped data transfer request. In claim 1 ,
The bus arbiter is a data transfer system that assigns bus usage rights to the buses in a time-sharing manner according to the priority set for the plurality of bus masters in response to bus use requests from the plurality of bus masters. In claim 1 ,
The bus is a data transfer system having a bus structure in which a plurality of buses are connected in multiple stages. In claim 1 ,
The bus arbiter counts the bus used time of the plurality of bus masters,
The data transfer system, wherein the scheduling means calculates a bus usable time of the bus master based on a bus used time of the bus master. A bus, a CPU connected to the bus, a plurality of bus masters that are connected to the bus and execute data transfer via the bus, and a bus use request from the bus master is arbitrated to any bus master. A bus arbiter that gives a right to use and bus master driver means for controlling the plurality of bus masters, and any of the plurality of bus masters executes a data transfer request generated by the task without passing through the scheduling means; A data transfer scheduling program executed by the CPU in a data transfer system,
Receiving a data transfer request generated by a task executed by the CPU;
The data transfer request having the highest priority is selected from the received data transfer requests, the bus master driver means is instructed to execute the selected data transfer request, and the bus master driver means selects the selected data transfer request. Causing the bus master corresponding to the data transfer request to execute the selected data transfer request;
Based on the data transfer amount of the data transfer request, the scheduling means calculates the bus usable time of the bus master that executes the accepted data transfer request longer than the bus usable time of the bus master that does not execute the data transfer request. Process,
Causing the bus master to preferentially give a bus use right to the bus master having a longer bus usable time by the bus arbiter;
A data transfer scheduling program to be executed by the CPU.

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