JP5692279B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof.

  Nitride substrates such as a gallium nitride (GaN) substrate having an energy band gap of 3.4 eV and high thermal conductivity are attracting attention as materials for semiconductor devices such as short-wavelength optical devices and power electronic devices. Such a nitride substrate is expensive. Japanese Patent Laid-Open No. 2006-210660 (Patent Document 1) discloses a method for manufacturing a semiconductor substrate for forming a nitride semiconductor thin film having a low dislocation density on a silicon (Si) substrate or a substrate made of an arbitrary material. Is disclosed.

  It is described that the manufacturing method of the semiconductor substrate of the said patent document 1 is equipped with the following processes. First, ions are implanted near the surface of the first nitride semiconductor substrate. Thereafter, the surface side of the first nitride semiconductor substrate is overlaid on the second substrate. Thereafter, the two stacked substrates are heat-treated. Next, most of the first nitride semiconductor substrate is peeled off from the second substrate with the ion-implanted layer as a boundary.

JP 2006-210660 A

  However, when the present inventor forms an epitaxial layer on the first nitride substrate of the semiconductor substrate manufactured by the method for manufacturing a semiconductor substrate disclosed in Patent Document 1, cracks are likely to occur in the epitaxial layer, or It has been found that there is a problem that the epitaxial layer is easily peeled off from the semiconductor substrate.

  Accordingly, an object of the present invention is to provide a semiconductor substrate and a method of manufacturing a semiconductor substrate that can suppress the occurrence of cracks when an epitaxial layer is formed on a nitride layer, and can suppress the peeling of the epitaxial layer from the semiconductor substrate. It is to provide a semiconductor device having improved quality and a method for manufacturing the semiconductor device by using the semiconductor device.

  The present inventors diligently studied the problem that the crack is likely to occur when the epitaxial layer is formed on the main surface of the nitride layer and the cause of the problem that the epitaxial layer is easily peeled off from the semiconductor substrate. As a result, the following factors were found. When an epitaxial layer is formed on the main surface of the first nitride substrate (nitride layer), the epitaxial layer is determined from the difference in thermal expansion coefficient between the nitride layer and the epitaxial layer and the second substrate (different substrate). Is stressed. When tensile stress is applied, a crack is generated in the epitaxial layer, and when compressive stress is applied, the epitaxial layer is peeled off from the semiconductor substrate. Therefore, the inventor of the present invention has completed the present invention by paying attention to removing such factors.

  That is, the semiconductor device of the present invention includes a heterogeneous substrate and a nitride layer formed on the heterogeneous substrate, and the nitride layer is formed on the main surface of the semiconductor substrate having a stress relaxation region and the nitride layer of the semiconductor substrate. An epitaxial layer formed and a Schottky electrode formed on the epitaxial layer are provided.

  The method for manufacturing a semiconductor device of the present invention includes the following steps. A nitride substrate having a main surface and a back surface opposite to the main surface is prepared, ions are implanted into the back surface of the nitride substrate, and the back surface of the nitride substrate and the dissimilar substrate are bonded together to form a bonded substrate A nitride layer is formed by forming and peeling a part of the nitride substrate from the bonded substrate, and the nitride layer has a stress relaxation region to manufacture a semiconductor substrate. An epitaxial layer is formed on the nitride layer of the semiconductor substrate. A Schottky electrode is formed on the epitaxial layer.

  The above-mentioned “stress relaxation region” means the difference between the thermal expansion coefficient of the nitride layer and the thermal expansion coefficient of the heterogeneous substrate, or the thermal expansion coefficient of the nitride layer and the laminated epitaxial layer formed thereon and the heterogeneous substrate. It means a region provided to relieve stress due to the difference from the coefficient of thermal expansion.

  According to the semiconductor substrate and the manufacturing method thereof used in the semiconductor device and the manufacturing method thereof of the present invention, the nitride layer has a stress relaxation region. The stress relaxation region can suppress the application of tensile stress and compressive stress to the nitride layer or the laminate of the nitride layer and the epitaxial layer. The generation of cracks can be suppressed if the application of tensile stress to the nitride layer or the laminate of the nitride layer and the epitaxial layer can be alleviated. If the compressive stress applied to the nitride layer or the stack of the nitride layer and the epitaxial layer can be alleviated, the region where the epitaxial layer is peeled off from the semiconductor substrate can be reduced. Therefore, it is possible to suppress the occurrence of cracks when an epitaxial layer is formed on the nitride layer, and to suppress the epitaxial layer from peeling from the semiconductor substrate.

Te manufacturing method smell of the semiconductor device and the semiconductor device, the stress relaxation region is inversion layer.

  When a groove is formed in the nitride layer, even if a crack is generated, the crack is interrupted by the groove, so that it is possible to prevent the crack from penetrating the epitaxial layer. When a polycrystalline region is formed in the nitride layer, the extending direction can be increased unlike a single crystal in which the extending direction is one direction. For this reason, the applied stress can be dissipated. When an inversion layer or a dissimilar material film is formed on the nitride layer, stress from one side can be retained at the interface. Therefore, since the stress applied to the epitaxial layer can be reduced in these stress relaxation regions, it is possible to suppress the occurrence of cracks when the epitaxial layer is formed on the nitride layer, and the epitaxial layer is a semiconductor substrate. It can suppress peeling from.

  Preferably, in the semiconductor device and the method for manufacturing the semiconductor device, the stress relaxation region has a dot shape, a stripe shape, or a lattice shape on the main surface of the nitride layer.

  Thereby, since the stress relaxation region is formed in a dispersed manner on the main surface of the nitride layer, the applied stress can be dissipated. For this reason, since stress can be reduced, it can suppress that a crack generate | occur | produces when forming an epitaxial layer on a nitride layer, and can suppress that an epitaxial layer peels from a semiconductor substrate.

  Preferably, in the semiconductor device manufacturing method, in the step of preparing the nitride substrate, a nitride substrate having a stress relaxation region on the back surface is prepared.

  Thereby, the semiconductor substrate provided with the nitride layer which has a stress relaxation area | region can be manufactured easily.

  According to the semiconductor device and the semiconductor device manufacturing method of the present invention, a semiconductor substrate capable of suppressing the occurrence of cracks when the epitaxial layer is formed on the nitride layer and suppressing the peeling of the epitaxial layer from the semiconductor substrate. It has. For this reason, the quality of a semiconductor device can be improved by forming an epitaxial layer on this semiconductor substrate.

  As described above, according to the semiconductor substrate and the semiconductor substrate manufacturing method used in the semiconductor device and the manufacturing method of the present invention, it is possible to suppress the occurrence of cracks when an epitaxial layer is formed on the nitride layer. And it can suppress that an epitaxial layer peels from a semiconductor substrate. Moreover, according to the semiconductor device and the manufacturing method of the semiconductor device of the present invention, a semiconductor device with improved quality can be obtained.

BRIEF DESCRIPTION OF THE DRAWINGS The semiconductor substrate in Embodiment 1 of this invention is shown schematically, (A) is sectional drawing, (B)-(D) is a top view. It is a flowchart which shows the manufacturing method of the semiconductor substrate in Embodiment 1 of this invention. It is sectional drawing which shows schematically the nitride board | substrate in Embodiment 1 of this invention. It is sectional drawing which shows schematically the state which ion-implanted in the nitride board | substrate in Embodiment 1 of this invention. It is sectional drawing which shows schematically the dissimilar board | substrate in Embodiment 1 of this invention. It is sectional drawing which shows roughly the state which bonded the nitride board | substrate and dissimilar board | substrate in Embodiment 1 of this invention. It is sectional drawing which shows roughly the state which peels a part of nitride board | substrate from the bonding board | substrate in Embodiment 1 of this invention. It is sectional drawing which shows schematically the semiconductor substrate in Embodiment 2 of this invention. It is sectional drawing which shows roughly the nitride board | substrate in Embodiment 2 of this invention. It is sectional drawing which shows schematically the state which ion-implanted in the nitride board | substrate in Embodiment 2 of this invention. It is sectional drawing which shows roughly the state which bonded the nitride board | substrate and dissimilar board | substrate in Embodiment 2 of this invention. It is sectional drawing which shows roughly the state which peels a part of nitride board | substrate from the bonding board | substrate in Embodiment 2 of this invention. It is sectional drawing which shows schematically the semiconductor substrate in Embodiment 3 of this invention. It is sectional drawing which shows schematically the manufacturing process for forming the nitride board | substrate in Embodiment 3 of this invention. It is sectional drawing which shows schematically the manufacturing process for forming the nitride board | substrate in Embodiment 3 of this invention. It is sectional drawing which shows schematically the nitride board | substrate in Embodiment 3 of this invention. It is sectional drawing which shows schematically the state which ion-implanted in the nitride board | substrate in Embodiment 3 of this invention. It is sectional drawing which shows roughly the state which bonded the nitride board | substrate and dissimilar board | substrate in Embodiment 3 of this invention. It is sectional drawing which shows schematically the state which peels a part of nitride board | substrate from the bonding board | substrate in Embodiment 3 of this invention. It is sectional drawing which shows schematically the nitride board | substrate in Embodiment 4 of this invention. It is sectional drawing which shows roughly the semiconductor device in Embodiment 5 of this invention. It is a flowchart which shows the manufacturing method of the semiconductor device in Embodiment 5 of this invention. 6 is a cross-sectional view schematically showing a semiconductor substrate of Comparative Example 1. FIG. 10 is a cross-sectional view schematically showing a semiconductor substrate of Comparative Example 2. FIG.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following drawings, the same or corresponding parts are denoted by the same reference numerals, and description thereof will not be repeated. In the present specification, individual surfaces are indicated by (), and aggregate surfaces are indicated by {}. As for the negative index, “−” (bar) is added on the number in crystallography, but in this specification, a negative sign is attached before the number.

(Embodiment 1)
With reference to FIGS. 1A to 1D, a semiconductor substrate 10a according to an embodiment of the present invention will be described. As shown in FIG. 1A, a semiconductor substrate 10a in the present embodiment includes a heterogeneous substrate 11 and a nitride layer 12 formed on the heterogeneous substrate 11.

The heterogeneous substrate 11 includes, for example, a substrate 13 and a layer 14 formed on the substrate 13. The substrate 13 is, for example, a silicon (Si) substrate. The layer 14 is, for example, a silicon dioxide (SiO ₂ ) layer. The heterogeneous substrate 11 has a main surface 11a and a back surface 11b opposite to the main surface 11a.

  The heterogeneous substrate 11 is not particularly limited as long as it is a different material from the nitride layer 12. Further, the heterogeneous substrate 11 may be one layer or two or more layers. The substrate 13 in the case of one layer or two or more layers is not particularly limited, and metal, Si, silicon carbide (SiC), or the like can be used. Further, in the dissimilar substrate 11, the positions of the substrate 13 and the layer 14 are opposite, that is, the substrate 13 may be formed on the layer 14.

The nitride layer 12 is not particularly limited as long as it is a nitride, and is, for example, Al _x In _y Ga _(1-xy) N (0 ≦ x ≦ 1, x + y ≦ 1), and includes gallium nitride (GaN) and aluminum nitride. (AlN) or the like is preferable.

  The nitride layer 12 has a main surface 12a, a back surface 12b opposite to the main surface 12a, and a groove 19a as a stress relaxation region. The back surface 12 b is in contact with the dissimilar substrate 11.

  The groove 19 a is formed by the difference between the thermal expansion coefficient of the nitride layer 12 and the thermal expansion coefficient of the heterogeneous substrate 11, or the thermal expansion coefficient of the nitride layer 12 and the epitaxial layer formed thereon and the heat of the heterogeneous substrate 11. This is a region formed to relieve stress due to the difference from the expansion coefficient.

  The groove 19a may have a stripe shape shown in FIG. 1B or a dot shape shown in FIG. 1C on the main surface 12a of the nitride layer 12, as shown in FIG. It may be a lattice shape as shown. Further, the region appearing as the nitride layer 12 in FIGS. 1B to 1D (region other than the groove 19a) and the stress relaxation region (groove 19a) may be reversed.

  The groove 19a may be formed so as to penetrate to the main surface 11a of the dissimilar substrate 11 as shown in FIG. 1A, or may be formed so as not to penetrate to the main surface 11a of the dissimilar substrate 11. (Not shown).

  The main surface 12a is a (0001) plane, that is, a plane from which Ga atoms are exposed (Ga atomic plane), and the back plane 12b is a (000-1) plane, that is, a plane from which N atoms are exposed (N atomic plane). It is preferable that When an epitaxial layer is formed on the Ga atom plane, an epitaxial layer with improved characteristics can be formed. Therefore, the main surface 12a of the nitride layer 12 is preferably a Ga atom plane.

  The main surface 12a of the nitride layer 12 is not limited to the (0001) plane, and may be a plane having an off angle from the (0001) plane, such as a {1-100} plane, a {11-20} plane Or the like.

  The thickness of the nitride layer 12 is preferably smaller than the thickness of the heterogeneous substrate 11. In this case, the cost of the semiconductor substrate 10 can be reduced by reducing the thickness of the expensive nitride layer 12. The thickness of nitride layer 12 is not less than 100 nm and not more than 900 nm, for example.

  Then, the manufacturing method of the semiconductor substrate 10 in this Embodiment is demonstrated. As shown in FIGS. 2 and 3, first, a nitride substrate 15 having a main surface 15a and a back surface 15b opposite to the main surface 15a is prepared (step S1). The main surface 15a is preferably a (0001) plane, that is, a Ga atom plane, and the back surface 15b is preferably a (000-1) plane, that is, an N atom plane.

The nitride substrate 15 to be prepared is, for example, an Al _x In _y Ga _(1-xy) N (0 ≦ x ≦ 1, x + y ≦ 1) substrate, and is preferably a GaN substrate, an AlN substrate, or the like.

  In the present embodiment, in step S1 to be prepared, a groove 19a as a stress relaxation region is formed on the back surface 15b. The method for forming the groove 19a is not particularly limited, and for example, mechanical processing such as dicing, etching such as dry etching, wet etching, or the like can be employed. The groove 19a may penetrate to the main surface 15a of the nitride substrate 15, but preferably does not penetrate to the main surface 15a.

  Next, as shown in FIGS. 2 and 4, ions are implanted into the back surface 15b of the nitride substrate 15 (step S2). In this step S2, ion implantation is performed from the back surface 15b of the nitride substrate 15. Thereby, a region containing a large amount of impurities can be formed in the vicinity of the back surface 15 b of the nitride substrate 15. The region containing a large amount of impurities is a fragile region.

In this step S2, it is preferable to implant a dose of 1 × 10 ¹⁷ cm ⁻² or more and 1 × 10 ¹⁸ cm ⁻² or less, and a dose of 1 × 10 ¹⁷ cm ⁻² or more and 8 × 10 ¹⁷ cm ⁻² or less. More preferably, it is injected. Since the region implanted with ions of 1 × 10 ¹⁷ cm ⁻² or more is fragile, the nitride substrate can be easily peeled off. On the other hand, in the case of 1 × 10 ¹⁸ cm ⁻² or less, an increase in resistance of the nitride layer 12 (see FIG. 7) to be formed can be suppressed. Further, separation of the nitride substrate 15 at the time of ion implantation can be suppressed. In the case of 8 × 10 ¹⁷ cm ⁻² or less, the low-resistance nitride layer 12 can be formed.

  The dose amount shows the maximum value in the nitride substrate 15. For example, the dose amount is maximum at a depth H15 from the back surface 15b of the nitride substrate 15 (a dotted line region in FIG. 4).

  The ions to be implanted are not particularly limited, and for example, hydrogen ions, helium ions, nitrogen ions and the like can be used.

Next, as shown in FIGS. 2 and 5, the heterogeneous substrate 11 is prepared (step S3). The heterogeneous substrate 11 is not particularly limited, and may be a single layer or a plurality of layers. In the present embodiment, a heterogeneous substrate 11 including a substrate 13 and a layer 14 formed on the substrate 13 is prepared. For example, the heterogeneous substrate 11 in which the substrate 13 is a Si substrate and the layer 14 is a SiO ₂ layer is prepared. The substrate 13 can be a metal substrate, a SiC substrate, or the like. As the metal substrate, it is preferable to use Mo (molybdenum), W (tungsten), or the like. In the case of a single layer, it is preferable to use the same material as the substrate 13. Further, a heterogeneous substrate 11 including the layer 14 and the substrate 13 formed on the layer 14 may be prepared.

  Next, as shown in FIGS. 2 and 6, a bonded substrate 16a is formed by bonding the back surface 15b of the nitride substrate 15 and the heterogeneous substrate 11 (step S4). In the present embodiment, bonding is performed so that the back surface 15b of the nitride substrate 15 and the layer 14 (main surface 11a) of the dissimilar substrate 11 are in contact with each other.

  The method of bonding is not particularly limited, and for example, a method of bonding by applying pressure in the atmosphere can be employed. Moreover, you may heat at the time of bonding, and heating temperature is 25 degreeC-1000 degreeC, for example. Thereby, as shown in FIG. 6, a bonded substrate 16 a including the heterogeneous substrate 11 and the nitride substrate 15 formed on the heterogeneous substrate 11 can be formed.

  Next, as shown in FIGS. 2 and 7, a part of the nitride substrate 15 is peeled from the bonded substrate 16a (step S5).

  As a peeling method, for example, the bonded substrate 16a is heat-treated, so that the nitride substrate 15 can be divided with the fragile region (region located at the depth H15 from the back surface 15b in FIG. 6) as a boundary. The heat treatment temperature is, for example, 100 ° C to 700 ° C. Note that a peeling method is not particularly limited. For example, a method of applying stress or a method of irradiating light may be used.

  As a result, a multilayer substrate including the heterogeneous substrate 11 and the nitride layer 17 formed on the heterogeneous substrate 11 can be formed. The nitride layer 17 has a main surface 17a and a back surface 17b opposite to the main surface 17a, and the back surface 17b of the nitride layer 17 coincides with the back surface 15b of the nitride substrate 15. As a result, a part of the expensive nitride substrate 15 (nitride layer 18) can be peeled off and reused, and only the remaining part (nitride layer 17) can be used, so that the manufacturing cost can be reduced.

  By performing the above steps S1 to S5, the semiconductor substrate 10a shown in FIG. 1 can be manufactured. When this semiconductor substrate 10a is used for a semiconductor device, it can be used as a horizontal semiconductor device, for example. Alternatively, when the semiconductor substrate 10 includes the insulating layer 14, a step of removing the layer 14 may be further performed.

  In the present embodiment, the nitride substrate 15 in which the groove 19a is formed in step S1 is prepared. However, the step of forming the groove 19a may be performed after any of steps S1 to S5.

  As described above, according to the semiconductor substrate 10a and the manufacturing method thereof in the present embodiment, the nitride layer 12 having the groove 19a as the stress relaxation region is provided. Since the nitride layer 12 is thin, when the epitaxial layer is formed on the main surface 12 a of the nitride layer 12, the epitaxial layer is greatly affected by the heterogeneous substrate 11. In the present embodiment, the groove 19 a can suppress the lamination of the nitride layer 12 and the epitaxial layer or the application of tensile stress and compressive stress to the nitride layer 12. That is, the groove 19a can relieve the nitride layer 12 and the epitaxial layer, or the strain generated in the nitride layer 12. If the application of tensile stress to the nitride layer 12 or the laminate of the nitride layer 12 and the epitaxial layer can be alleviated, the occurrence of cracks in the epitaxial layer can be suppressed. Further, even if a crack starts to occur, the crack is interrupted by the groove 19a, so that it is possible to prevent the crack from penetrating the nitride layer 12 or the epitaxial layer. Further, if the nitride layer 12 and the epitaxial layer are stacked or the compressive stress is applied to the nitride layer 12 by the groove 19a, the region where the epitaxial layer is peeled off from the semiconductor substrate 10a can be reduced. Accordingly, it is possible to suppress the occurrence of cracks when an epitaxial layer is formed on the main surface 12a of the nitride layer 12, and the epitaxial layer is peeled off from the heterogeneous substrate 11 or the nitride layer 12, and the nitride layer 12 is heterogeneous. The peeling from the substrate 11 can be suppressed.

  Even when heating is performed in step S4 for forming the bonded substrate 16a or step S5 for peeling off a part of the nitride substrate 15, it is not usually performed at a high temperature. However, when an epitaxial layer is formed on the semiconductor substrate 10a, it is usually performed in a high temperature atmosphere. For this reason, when the epitaxial layer is formed, a large stress is applied due to the difference in thermal expansion coefficient between the heterogeneous substrate 11 and the epitaxial layer. Therefore, according to the present embodiment, peeling and cracking can be suppressed particularly when the epitaxial layer is formed.

(Embodiment 2)
Referring to FIG. 8, the semiconductor substrate 10b of the second embodiment of the present invention basically has the same configuration as the semiconductor substrate 10a shown in FIG. 1, but the stress relaxation region is a dissimilar material film 19b. There are some differences. The dissimilar material film 19b is not particularly limited as long as it is a material different from that of the nitride layer 12, and for example, a SiO ₂ (silicon dioxide) film, a SiN (silicon nitride) film, or the like can be used.

  The manufacturing method of the semiconductor substrate 10b in the present embodiment is basically the same as the manufacturing method of the semiconductor substrate 10a in the first embodiment, but differs in that a stress relaxation region made of a different material film 19b is formed.

  Specifically, first, as in the first embodiment, as shown in FIG. 3, a groove 19 a is formed on the back surface 15 b of the nitride substrate 15. Thereafter, as shown in FIG. 9, a dissimilar material film 19b is formed inside the groove 19a. The method for forming the dissimilar material film 19b is not particularly limited, and can be formed by a CVD (Chemical Vapor Deposition) method or the like. Thereby, the nitride substrate 15 having the stress buffer region can be prepared (step S1).

  Next, as shown in FIGS. 2 and 10, ions are implanted into the back surface 15b of the nitride substrate 15 (step S2). Next, as shown in FIGS. 2 and 5, the heterogeneous substrate 11 is prepared (step S3). Next, as shown in FIGS. 2 and 11, a bonded substrate 16b is formed by bonding the back surface 15b of the nitride substrate 15 and the heterogeneous substrate 11 (step S4). Next, as shown in FIGS. 2 and 12, a part of the nitride substrate 15 is peeled off from the bonded substrate 16b (step S5). Steps S2 to S5 are the same as in the first embodiment, and therefore description thereof will not be repeated.

  By performing the above steps S1 to S5, the semiconductor substrate 10b shown in FIG. 8 can be manufactured. In the semiconductor substrate 10b, since the dissimilar material film 19b is formed on the nitride layer 12, the tensile stress from one side can be kept in the nitride layer 12 at the interface with the dissimilar material film 19b. For this reason, the stress applied by the dissimilar material film 19b can be reduced. Therefore, it is possible to suppress the occurrence of cracks when an epitaxial layer is formed on the nitride layer 12, and the epitaxial layer is peeled off from the nitride layer 12 or the heterogeneous substrate 11, or the nitride layer 12 is separated from the heterogeneous substrate 11. It can suppress peeling.

The dissimilar material film 19b is preferably made of a material having low reactivity with the raw material for forming the epitaxial layer. Examples of such a material include the above-described SiO ₂ film and SiN film. In this case, an epitaxial layer with improved quality can be formed. In the case of the groove 19a of the first embodiment, the heterogeneous substrate 11 is exposed. Therefore, according to the heterogeneous material film 19b of the present embodiment, the reaction between the heterogeneous substrate 11 and the raw material can be suppressed. .

(Embodiment 3)
Referring to FIG. 13, the semiconductor substrate 10c of the third embodiment of the present invention basically has the same configuration as the semiconductor substrate 10a shown in FIG. 1, but the stress relaxation region is a polycrystal 19c. It is different in point.

  The polycrystal 19c is observed in the nitride layer 12 because of poorer crystallinity than regions other than the polycrystal 19c, for example, a high dislocation density. In the nitride layer 12, the polycrystal 19c and the other region may be made of the same material or different materials.

  The method for manufacturing the semiconductor substrate 10c in the present embodiment is basically the same as the method for manufacturing the semiconductor substrate 10a in the first embodiment, but differs in that a stress relaxation region made of the polycrystal 19c is formed.

  Specifically, first, as shown in FIG. 14, with the mask pattern 32 formed on the base substrate 31, crystals forming the nitride substrate 15 are formed as shown in FIG. Thereafter, the base substrate 31 is removed as shown in FIG. Thereby, the nitride substrate 15 having the polycrystal 19c as the stress relaxation region can be prepared (step S1).

  The method for forming the polycrystal 19c is not particularly limited. For example, as in the first embodiment, as shown in FIG. 3, after forming groove 19a on back surface 15b of nitride substrate 15, polycrystal 19c may be formed inside groove 19a.

  Next, as shown in FIGS. 2 and 17, ions are implanted into the back surface 15b of the nitride substrate 15 (step S2). Next, as shown in FIGS. 2 and 5, the heterogeneous substrate 11 is prepared (step S3). Next, as shown in FIGS. 2 and 18, a bonded substrate 16c is formed by bonding the back surface 15b of the nitride substrate 15 and the heterogeneous substrate 11 (step S4). Next, as shown in FIGS. 2 and 19, a part of the nitride substrate 15 is peeled off from the bonded substrate 16c (step S5). Steps S2 to S5 are the same as in the first embodiment, and therefore description thereof will not be repeated.

  By performing the above steps S1 to S5, the semiconductor substrate 10c shown in FIG. 13 can be manufactured. In the semiconductor substrate 10c, since the polycrystal 19c is formed in the nitride layer 12, the extending direction can be increased unlike a single crystal in which the extending direction is one direction. For this reason, the stress applied to an epitaxial layer can be dissipated. Therefore, it is possible to suppress the occurrence of cracks when an epitaxial layer is formed on the nitride layer 12, and the epitaxial layer is peeled off from the nitride layer 12 or the heterogeneous substrate 11, or the nitride layer 12 is separated from the heterogeneous substrate 11. It can suppress peeling.

(Embodiment 4)
Referring to FIG. 20, the semiconductor substrate 10d of the fourth embodiment of the present invention basically has the same configuration as the semiconductor substrate 10a shown in FIG. 1, but the stress relaxation region is the inversion layer 19d. It is different in point.

  The inversion layer 19d has, for example, a main surface 19d1 and a back surface 19d2 opposite to the main surface 19d1. In the nitride layer 12, the polarity of the main surface 19d1 of the inversion layer 19d and the main surface 12a of the other region are different, and the polarity of the back surface 19d2 of the inversion layer 19d and the back surface 12b of the other region is different. Is different. For example, the main surface 12a in the region other than the inversion layer 19d and the back surface 19d2 of the inversion layer 19d are the (0001) plane, that is, the surface from which Ga atoms are exposed (Ga atom surface), and the back surface in the region other than the inversion layer 19d. The main surface 19d1 of 12b and the inversion layer 19d is a (000-1) plane, that is, a plane from which N atoms are exposed (N atomic plane).

  The manufacturing method of the semiconductor substrate 10d in the present embodiment is basically the same as the manufacturing method of the semiconductor substrate 10a in the first embodiment, but differs in that a stress relaxation region including the inversion layer 19d is formed.

  Specifically, first, as in the third embodiment, a nitride substrate 15 is formed as shown in FIG. 15 with a mask pattern 32 formed on the base substrate 31 as shown in FIG. . At this time, a nitride layer (nitride substrate 15) is grown on the region in contact with the base substrate 31 that is not covered with the mask so that the (0001) plane is the main surface, and on the region in contact with the mask layer. The nitride layer (inversion layer 19d) grows so that the (000-1) plane becomes the main surface. Thereafter, the base substrate 31 is removed as necessary. Further, the main surface (growth surface) is polished as necessary. Thereby, the nitride substrate 15 having the inversion layer 19d as the stress relaxation region can be prepared (step S1).

  Since subsequent steps S2 to S5 are the same as those in the third embodiment, the description thereof will not be repeated.

  In the present embodiment, in the inversion layer 19d, the main surface 19d1 and the back surface 19d2 have opposite polarities, but there is no particular limitation as long as the plane orientations are different.

  By performing the above steps S1 to S5, the semiconductor substrate 10d shown in FIG. 20 can be manufactured. In the semiconductor substrate 10d, since the inversion layer 19d is formed on the nitride layer 12, the tensile stress from one side can be kept in the nitride layer 12 at the interface with the inversion layer 19d. Therefore, the stress applied to the epitaxial layer can be reduced by the inversion layer 19d. Therefore, it is possible to suppress the occurrence of cracks when an epitaxial layer is formed on the nitride layer 12, and the epitaxial layer is peeled off from the nitride layer 12 or the heterogeneous substrate 11, or the nitride layer 12 is separated from the heterogeneous substrate 11. It can suppress peeling.

  In addition, although the said Embodiment 1-4 was mentioned as an example and demonstrated as a semiconductor substrate provided with the nitride layer 12 which has a stress relaxation area | region, the stress relaxation area | region of this invention is not limited to Embodiment 1-4. . Moreover, you may combine the stress relaxation area | region in any one of Embodiment 1-4.

(Embodiment 5)
With reference to FIG. 21, a Schottky Barrier Diode (SBD) 20 as a semiconductor device in an embodiment of the present invention will be described. As shown in FIG. 21, the SBD 20 includes a semiconductor substrate 10, an epitaxial layer 21 formed on the semiconductor substrate 10, an electrode 22 formed on the back surface of the semiconductor substrate 10, and a shot formed on the epitaxial layer 21. And a key electrode 23.

  The semiconductor substrate 10 is basically the same as the semiconductor substrate 10a of the first embodiment, but uses a heterogeneous substrate 11 made of a conductive material. The semiconductor substrate 10 to be used is not particularly limited, and for example, the semiconductor substrates 10b to 10d of the second to fourth embodiments may be used. In the present embodiment, for example, a conductive substrate is used as the heterogeneous substrate 11. As the heterogeneous substrate 11, a Mo substrate, a W substrate, or the like is preferably used. The heterogeneous substrate 11 may be a single layer or a plurality of layers.

Epitaxial layer 21 is formed on main surface 12 a of nitride layer 12 constituting semiconductor substrate 10. Epitaxial layer 21 is, for example, a drift layer. Epitaxial layer 21 is preferably a nitride semiconductor layer, for example, an Al _x In _y Ga _(1-xy) N (0 ≦ x ≦ 1, x + y ≦ 1) layer, and preferably a GaN layer or the like. . Epitaxial layer 21 preferably has the same composition as nitride layer 12 constituting semiconductor substrate 10.

  The electrode 22 is formed under the heterogeneous substrate 11 constituting the semiconductor substrate 10. The electrode 22 is, for example, an ohmic electrode. The Schottky electrode 23 is formed on the epitaxial layer 21.

  Next, a method for manufacturing the Schottky barrier diode 20 in the present embodiment will be described.

  First, as shown in FIG. 22, the semiconductor substrate 10 is manufactured according to the manufacturing method of the semiconductor substrate 10a of the first embodiment except that the conductive heterogeneous substrate 11 is prepared (steps S1 to S5).

  Next, as shown in FIG. 22, the epitaxial layer 21 is formed on the semiconductor substrate 10 (step S7). In the present embodiment, epitaxial layer 21 is formed on main surface 12 a of nitride layer 12 constituting semiconductor substrate 10.

In this step S7, the epitaxial layer 21 made of, for example, Al _x In _y Ga _(1-xy) N (0 ≦ x ≦ 1, x + y ≦ 1) is formed. The epitaxial layer 21 may be a single layer or a plurality of layers.

  In addition, it is preferable to form an epitaxial layer 21 having the same composition as that of the nitride layer 12 constituting the semiconductor substrate 10. In this case, since problems such as lattice mismatch can be alleviated, the epitaxial layer 21 with improved characteristics can be formed.

  The method for forming the epitaxial layer 21 is not particularly limited, and HVPE (Hydride Vapor Phase Epitaxy) method, MBE (Molecular Beam Epitaxy) method, OMVPE (OrganoMetallic Vapor Phase Epitaxy: organometallic vapor phase). Growth) method, vapor phase growth method such as sublimation method, liquid phase growth method such as flux method, high nitrogen pressure solution method, and the like can be employed. Thereby, an epitaxial wafer including the semiconductor substrate 10 and the epitaxial layer 21 formed on the semiconductor substrate 10 can be manufactured.

  Next, the electrode 22 is formed on the surface of the semiconductor substrate 10 opposite to the surface on which the epitaxial layer 21 is formed, that is, on the heterogeneous substrate 11 side. For example, an ohmic electrode is formed as the electrode 22. Next, the Schottky electrode 23 is formed on the epitaxial layer 21 (step S8). The formation method of the Schottky electrode 23 and the electrode 22 is not specifically limited, For example, it forms by a vapor deposition method etc.

  Through the above steps S1 to S5, S7, and S8, the Schottky barrier diode 20 shown in FIG. 21 can be manufactured.

  As described above, according to the SBD 20 as the semiconductor device and the manufacturing method of the SBD 20 in the present embodiment, the semiconductor substrate including the nitride layer 12 having the stress relaxation region is used. For this reason, when the epitaxial layer 21 is formed on the main surface 12 a of the nitride layer 12 of the semiconductor substrate 10, it is possible to suppress the generation of cracks and to suppress the epitaxial layer 21 from peeling from the nitride layer 12. Therefore, since the crystallinity of the epitaxial layer 21 can be improved, the SBD 20 with improved quality can be realized.

  In the present embodiment, the SBD is described as an example of the semiconductor device. However, the semiconductor device of the present invention is not limited to the SBD, and an LED (Light Emitting Diode), an LD (Laser Diode: laser diode). ), MOSFET (Metal Oxide Semiconductor Field Effect Transistor), JFET (Junction Field-Effect Transistor), pn diode, IGBT (Insulated Gate Bipolar Transistor) be able to.

In this example, the effect of providing a nitride layer having a stress relaxation region was examined.
( Reference Examples 1 to 10, 14, and 15 of the present invention)
Reference Examples 1 to 10, 14, and 15 of the present invention were basically manufactured according to the method for manufacturing the semiconductor substrate 10a of the first embodiment.

Specifically, first, a nitride substrate 15 was prepared as follows (step S1). A main surface 15a and a back surface 15b were mirror-finished by polishing, and a GaN substrate having a diameter of 2 inches (5.08 cm) and a thickness of 500 μm doped with oxygen was prepared. The specific resistance of this GaN substrate was 1 Ω · cm or less, and the carrier concentration was 1 × 10 ¹⁷ cm ⁻³ or more. Moreover, the main surface 15a was a Ga atom surface, and the back surface 15b was an N atom surface. Thereafter, in Reference Examples 1 to 10 of the present invention, a groove 19a having a width (W19a in FIG. 3) and an interval (P19a in FIG. 3) described in Table 1 below is formed on the back surface 15b by dicing (see FIG. 3). Cutting was performed so that H19a) was 100 μm. Further, in Reference Examples 14 and 15 of the present invention, the groove 19a having the width (W19a in FIG. 3) and the interval (P19a in FIG. 3) shown in Table 1 below is formed on the back surface 15b by RIE or wet etching ( Processing was performed such that H19a) in FIG. 3 was 5 μm. Thereby, the nitride board | substrate 15 of this invention reference examples 1-10, 14, 15 was prepared.

Next, as step S2 for ion implantation, hydrogen ions were implanted into the back surface 15b (N atomic surface) of the prepared GaN substrate. Hydrogen ions were implanted at an acceleration voltage of 90 keV, and the dose was 7 × 10 ¹⁷ cm ⁻² . Note that the dose was set to the maximum concentration in the region where hydrogen ions were implanted. In Reference Examples 1 to 10, 14, and 15 of the present invention, the dose amount of implanted hydrogen ions was maximum in the region where the depth H15 from the N atomic plane (see FIG. 4) was about 600 nm.

Thereafter, the back surface 15b (N atomic plane) of the GaN substrate implanted with hydrogen ions was cleaned. Next, the back surface 15b was made a clean surface by plasma obtained by discharging in an argon (Ar) gas with a dry etching apparatus. The plasma generation conditions for cleaning the back surface 15b of the GaN substrate were an RF power of 100 W, an Ar gas flow rate of 50 sccm (volume (cm ³ / min) of gas flowing in one minute in a standard state), and a pressure of 6.7 Pa.

Next, in step S3 of preparing the dissimilar substrate 11, the heterogeneous substrate 11 where the Si substrate to form a SiO ₂ layer having a thickness of 100nm on the surface by thermal oxidation, i.e. SiO ₂ layer as shown in FIG. 5 (layer 14) A Si substrate (substrate 13) on which was formed was prepared. The main surface 11a of the heterogeneous substrate 11 was made a clean surface by plasma obtained by discharging in Ar gas with a dry etching apparatus. The plasma generation conditions for cleaning the main surface 11a of the heterogeneous substrate 11 were the same as those for the back surface 15b of the GaN substrate.

Next, as a step S4 for forming the bonded substrate 16a by bonding the back surface 15b of the nitride substrate 15 and the heterogeneous substrate 11, the clean surfaces, that is, the back surface 15b (N atomic surface) of the GaN substrate, The main surface 11a of the Si substrate (the heterogeneous substrate 11) on which the SiO ₂ layer was formed was bonded in the air. Thereby, the bonded substrate 16a shown in FIG. 6 was obtained.

Next, as step S5 for peeling off a part of the nitride substrate 15, the bonded substrate 16a was heat-treated at 300 ° C. for 2 hours in an N ₂ gas atmosphere. As a result, the bonding strength was increased, and the GaN substrate as the nitride substrate 15 was separated from the back surface 15b by a region having a depth H15 of about 600 nm. That is, in the ion implantation step S2, a part of the GaN substrate is separated in the region where the dose amount is maximum in the GaN substrate. As a result, as shown in FIG. 7, a bonded substrate (laminated substrate) having a GaN layer having a thickness of about 600 nm was obtained as the nitride layer 17.

By carrying out the above steps S1 to S5, the semiconductor substrate 10a of Reference Examples 1 to 10, 14, and 15 of the present invention shown in FIG. 1 was manufactured.

( Reference Example 11 of the present invention)
In Reference Example 11 of the present invention, the semiconductor substrate 10c was manufactured according to the third embodiment. The manufacturing method of the semiconductor substrate 10c in Reference Example 11 of the present invention was basically the same as that of Reference Example 1 of the present invention, but was different in Step S1 in which the nitride substrate 15 was prepared.

Specifically, a GaN crystal was grown with the mask pattern 32 formed on the base substrate 31 shown in FIG. Thus, a nitride substrate 15 of Reference Example 11 of the present invention having polycrystalline GaN as a polycrystal 19c having a width of 50 μm and single crystal GaN as a single crystal having a width of 500 μm was prepared in a stripe shape. The single crystal region had the same characteristics as the GaN substrate of Reference Example 1 of the present invention.

(Invention Example 12)
In the present invention embodiment 12, according to the fourth embodiment, it was manufactured semiconductor substrate 10d. The method of manufacturing a semiconductor substrate 10d in the present invention Example 12 was basically the same as the present invention in Reference Example 1, was different in step S1 of preparing a nitride substrate 15.

Specifically, as in Reference Example 11 of the present invention, a GaN crystal was grown with the mask pattern 32 formed on the base substrate 31. Thus, a GaN main surface 12a of the inversion layer 19d having a width 50μm in stripes is Ga plane, the nitride substrate 15 of the present invention Example 12 and a GaN is main surface N face width of 500μm Got ready. The region other than the inversion layer 19d had the same characteristics as the GaN substrate of Reference Example 1 of the present invention.

( Reference Example 13 of the present invention)
In Reference Example 13 of the present invention, the semiconductor substrate 10b was manufactured according to the second embodiment. The manufacturing method of the semiconductor substrate 10b in Reference Example 13 of the present invention was basically the same as that of Reference Example 1 of the present invention. However, after forming a groove in the GaN substrate in Step S1 for preparing the nitride substrate 15, SiO ₂ was formed. It was different in that a film was formed.

( Reference Example 16 of the present invention)
The semiconductor substrate of Reference Example 16 of the present invention was basically manufactured in the same manner as Reference Example 1 of the present invention. However, after step S5 for peeling a part of the nitride substrate from the bonded substrate 16a, a groove 19a was formed. It was different in point.

( Reference Example 17 of the present invention)
The semiconductor substrate of Reference Example 17 of the present invention was basically manufactured in the same manner as Reference Example 1 of the present invention, but differed in that a sapphire substrate was used as the heterogeneous substrate 11.

(Comparative Example 1)
As shown in FIG. 23, the semiconductor substrate 40 of Comparative Example 1 was basically manufactured in the same manner as Reference Example 1 of the present invention, but differed in that the groove 19a as a stress buffering region was not formed. That is, the semiconductor substrate 40 of Comparative Example 1 includes the nitride layer 12 that does not have the groove 19a.

(Comparative Example 2)
As shown in FIG. 24, a semiconductor substrate 50 of Comparative Example 2 is basically prepared in the same manner as the present invention in Reference Example 1, point was Tsu Naka a groove 19a as a stress relief region, and a heterologous substrate The difference was that the sapphire substrate 53 was used. That is, as shown in FIG. 24, the semiconductor substrate 50 of Comparative Example 2 was basically provided with the same configuration as that of the semiconductor substrate of Reference Example 17 of the present invention, but the nitride layer 12 having no groove 19a. It was different in that it had.

(Evaluation method)
A thickness of 3 μm is formed on the main surface of the nitride layer (GaN layer) constituting the semiconductor substrates of Reference Examples 1 to 11 , 13 to 17 of the present invention, Example 12 of the present invention and Comparative Examples 1 and 2 by OMVPE method. An n-type GaN epitaxial layer having the following structure was formed to manufacture an epitaxial wafer.

  About each epitaxial wafer, the peeling ratio and the crack generation rate were measured. The results are shown in Table 1 below.

  As the peeling ratio, the area ratio of the region where the nitride layer 12 or the epitaxial layer was not peeled from the heterogeneous substrate 11 was measured.

In addition, 100 semiconductor substrates of Reference Examples 1 to 11 , 13 to 17 of the present invention, Example 12 of the present invention and Comparative Examples 1 and 2 were manufactured, and an epitaxial layer was similarly formed to manufacture 100 epitaxial wafers. . The crack occurrence rate was determined by measuring the ratio of the number of epitaxial wafers with cracks to the total number of epitaxial wafers during or after epitaxial growth. Here, the epitaxial wafer having a crack is an epitaxial wafer having a surface linear crack having a length of 2.0 mm or more, and an epitaxial having three or more surface linear cracks having a length of 0.5 mm or more and 2.0 mm or less. A wafer or an epitaxial wafer having 21 or more surface linear cracks of 0.1 mm or more and 0.5 mm or less occurred.

(Evaluation results)
When an Si substrate is used as the heterogeneous substrate 11, when an epitaxial layer is formed, tensile stress is applied to the laminate of the nitride layer 12 and the epitaxial layer due to the difference in thermal expansion coefficient. However, as shown in Table 1, the present invention reference examples 1 to 11, 13 to 16 and the present invention example 12 using the Si substrate as the heterogeneous substrate 11 are compared with the comparative example 1 using the same heterogeneous substrate 11. Thus, the crack generation rate could be reduced. From this, it was found that when tensile stress is applied, the rate of occurrence of cracks can be reduced by forming a stress relaxation region in the nitride layer 12.

  Further, it has been found that forming the groove 19a, the dissimilar material film 19b, the polycrystal 19c, and the inversion layer 19d as the stress relaxation region is effective in reducing the crack generation rate.

  Further, it has been found that the stress relaxation region having a dot shape, stripe shape, or lattice shape on the main surface 12a of the nitride layer 12 is effective in reducing the crack generation rate.

  Moreover, it was found that the method for forming the stress relaxation region is not particularly limited, and the order of the steps for forming the stress relaxation region is not particularly limited.

When a sapphire substrate is used as the heterogeneous substrate 11, when an epitaxial layer is formed, a compressive stress is applied to the laminate of the nitride layer 12 and the epitaxial layer from the difference in thermal expansion coefficient. However, as shown in Table 1, it can be seen that Reference Example 17 of the present invention using a sapphire substrate as the heterogeneous substrate 11 improves the ratio of not peeling compared to Comparative Example 2 using the same heterogeneous substrate 11. It was.

  As described above, according to this example, by providing the nitride layer having the stress relaxation region, it is possible to suppress the occurrence of cracks when the epitaxial layer is formed on the main surface of the nitride layer, and the epitaxial layer. It can be confirmed that can be prevented from peeling from the semiconductor substrate.

In the present embodiment, the GaN layer is described as an example of the nitride layer. However, when the inventor uses a nitride substrate, the present invention reference examples 1 to 11, 13 to 17 and the present invention example 12 are used. It has been found that a semiconductor substrate having the same non-peeling ratio and crack generation rate can be manufactured.

  Although the embodiments and examples of the present invention have been described above, it is also planned from the beginning to appropriately combine the features of the embodiments and examples. The embodiments and examples disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is shown not by the above-described embodiment but by the scope of claims, and is intended to include all modifications within the meaning and scope equivalent to the scope of claims.

  10, 10a, 10b, 10c, 10d, 40, 50 Semiconductor substrate, 11 Different substrate, 11a, 12a, 15a, 17a, 19d1 Main surface, 12, 17, 18 Nitride layer, 11b, 12b, 15b, 17b, 19d2 Back surface, 13 substrate, 14 layers, 15 nitride substrate, 16a, 16b, 16c bonded substrate, 19a groove, 19b dissimilar material film, 19c polycrystal, 19d inversion layer, 20 Schottky barrier diode (SBD), 21 epitaxial layer , 22 electrodes, 23 Schottky electrodes, 31 base substrate, 32 mask pattern, 53 sapphire substrate.

Claims (5)

A semiconductor substrate comprising: a heterogeneous substrate; and a nitride layer formed on the heterogeneous substrate, wherein the nitride layer has a stress relaxation region;
An epitaxial layer formed on the main surface of the nitride layer of the semiconductor substrate;
And a Schottky electrode formed on the epitaxial layer,
The semiconductor device , wherein the stress relaxation region is an inversion layer . The semiconductor device according to claim 1, wherein the stress relaxation region has a dot shape, a stripe shape, or a lattice shape on the main surface of the nitride layer. Preparing a nitride substrate having a main surface and a back surface opposite to the main surface;
Implanting ions into the back surface of the nitride substrate;
Forming a bonded substrate by bonding the back surface of the nitride substrate and a heterogeneous substrate;
Forming a nitride layer by peeling a part of the nitride substrate from the bonded substrate,
The nitride layer has a stress relaxation region, and a step of manufacturing a semiconductor substrate by a method of manufacturing a semiconductor substrate;
Forming an epitaxial layer on the nitride layer of the semiconductor substrate;
And a step of forming a Schottky electrode on said epitaxial layer,
The method of manufacturing a semiconductor device , wherein the stress relaxation region is an inversion layer . 4. The method of manufacturing a semiconductor device according to claim 3 , wherein the stress relaxation region has a dot shape, a stripe shape, or a lattice shape on the main surface of the nitride layer. 5. 5. The method of manufacturing a semiconductor device according to claim 3 , wherein in the step of preparing the nitride substrate, the nitride substrate having the stress relaxation region on the back surface is prepared.

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