JP5593565B2 - Game machine - Google Patents

Description

  The present invention relates to a gaming machine including a plurality of group unit control means for controlling a production device divided into groups and a group overall control means for controlling a plurality of group unit control means, in particular, from the group overall control means to the group unit control means. It relates to the data transmission method.

By improving the signal transmission method between the main control unit and the peripheral control unit, especially from the main control unit to the peripheral control unit, the complexity of the signal line system is eliminated and the electrical configuration is simplified. There are known gaming machines that can be used. In this gaming machine, transmission of a command signal from the main control unit to the peripheral control unit is performed in a state where the peripheral control unit that is an operation command target can be specified. This makes it possible to share a signal transmission path to a plurality of peripheral control units. As a result, the number of signal lines can be greatly reduced as compared to a mode in which a command signal transmission path is formed for each peripheral control unit, and the command signal output port on the main control unit side can be integrated. Therefore, the complexity of the signal line system can be eliminated and the electrical configuration can be simplified (for example, Patent Document 1).

JP 2001-038021 A

However, in the conventional gaming machine, wiring could not be reduced .

In the present invention, an object to provide a gaming machine which can reduce the wiring.

The present invention corresponds to a game control means for comprehensively controlling a game, a plurality of effect devices for effecting a game, an image output device for outputting an image related to a game effect, and a command from the game control means. Group control means for controlling the effect devices belonging to the divided group, the effect control means for controlling the plurality of effect devices, and dividing the plurality of effect devices into a plurality of groups. provided for each, the presentation control means, before Symbol constitute a group unit control means as a group supervisory controlling means for centrally controlling the timing signal line for transmitting a timing signal from said group integrated control unit to the group-unit control unit and wherein said group supervisory controlling means by a data line for transmitting data to the group-unit control unit from the group supervisory controlling means And loop-unit control unit is connected, the said group supervisory controlling means to enable the data transfer to and from each group unit control means, said group integrated control unit, the update period of image to be output to the image output device Data is sequentially transmitted to the connected group unit control means by repeatedly changing the signal level of the timing signal line while setting the signal level of the data line to the signal level corresponding to the transmission data in synchronization with By controlling the signal levels of the data line and the timing signal line in a manner different from that at the time of data transmission in the middle of data transmission by the transmission means or at the last timing of data transmission. Update command signal output means for outputting the update command signal to the group unit control means. -Loop unit control means includes a common address as a common between each group unit control means, and the individual address differs in each group unit control means to each other, with but pre-assigned, as said common address, at least the initialization A first common address used in the process and a second common address used in the control other than the initialization are allocated, and the contents of the address included in the data transmitted from the group overall control unit are determined. When it is determined that the address is an individual address addressed to itself or the second common address, the transmitted data is taken as control information, and the rendering device is controlled based on the control information, If it is determined that the address is the first common address, the transmitted data is taken as initialization instruction information, Initialize itself based on the initialization instruction information, capture means for capturing the data transmitted by the transmission means, and update the output mode of the rendering device in correspondence with the data captured by the capture means Output mode update means, and the output mode update means updates the output mode of the rendering device at the timing of receiving the update command signal.

According to the present invention , wiring can be further simplified.

It is explanatory drawing of the game machine of the 1st Embodiment of this invention. It is a front view of the game board of a 1st embodiment of the present invention. It is a disassembled perspective view of the center case of the 1st Embodiment of this invention. It is a figure which shows the state before the movable production apparatus of the 1st Embodiment of this invention operate | moves. It is a figure which shows the state which contact | abutted in the contact part as a result of the movable production | presentation apparatus of the 1st Embodiment of this invention operating | moving and operating the 1st presentation unit and the 2nd presentation unit. It is a disassembled perspective view of the 1st production member of the 1st Embodiment of this invention. It is a disassembled perspective view of the 2nd production member of the 1st Embodiment of this invention. It is a figure explaining wiring of the game machine of a 1st embodiment of the present invention. It is a block diagram which shows the structure of the game machine of the 1st Embodiment of this invention. It is a block diagram which shows the structure of the presentation control apparatus of the 1st Embodiment of this invention. It is a block diagram which shows the structure of the 1st master IC with which the presentation control apparatus of the 1st Embodiment of this invention was equipped, and the presentation apparatus with which the game board was equipped. It is a block diagram which shows the structure of the 2nd master IC with which the presentation control apparatus of the 1st Embodiment of this invention was equipped, and the presentation apparatus with which the front frame was equipped. It is a figure which shows the structure of the game board of the 1st Embodiment of this invention. It is a figure which shows the structure of the front frame of the 1st Embodiment of this invention. It is a figure explaining the connection state of the production | generation control apparatus of the 1st Embodiment of this invention, the relay board | substrate contained in a game board, and a decoration control apparatus. It is a figure explaining the connection state of the presentation control apparatus of the 1st Embodiment of this invention, the simple relay board | substrate contained in a front frame, and a decoration control apparatus. It is a block diagram of the decoration control apparatus of the 1st Embodiment of this invention. It is a block diagram showing a configuration of a first embodiment of the I ² CI / O expander of the present invention. It is a circuit diagram around the I ² CI / O expander of the decoration control device that controls the decoration device of the first embodiment of the present invention. It is a circuit diagram around the I ² CI / O expander of the decoration control device of the first exemplary embodiment of the present invention, and shows a case where a motor and a solenoid are controlled. It is a circuit diagram of the connection line regarding the input / output of the decoration control device (including the relay board and the simple relay board) of the first embodiment of the present invention. It is explanatory drawing of the slave address contained in the data output to the decoration control apparatus from the presentation control apparatus of the 1st Embodiment of this invention. It is an explanatory view of I ² CI / O expander address table according to the first embodiment of the present invention. It is a diagram for explaining a first embodiment of the I ² CI / O Aix work register assigned to the output setting register provided in expander of the present invention. It is explanatory drawing of the start condition and stop condition which the master IC of the 1st Embodiment of this invention outputs data via the connection line SDA and the connection line SCL. It is a timing chart which the decoration control apparatus into which the data output from the master IC of the 1st Embodiment of this invention was input outputs a response signal. It is a timing chart of the signal level of the connection line SDA and the connection line SCL when the master IC according to the first embodiment of the present invention outputs effect control data. When the master IC according to the first embodiment of the present invention specifies the individual address of the slave and sets the effect control data in the decoration control device, transmission / reception is performed between the master IC and the I ² CI / O expander. It is a figure explaining the format of data to be performed. When the master IC according to the first embodiment of the present invention specifies the individual address of the slave and sets the effect control data in the decoration control device, transmission / reception is performed between the master IC and the I ² CI / O expander. It is the figure which applied the specific numerical value to the production control data to be performed. It is a figure explaining the order which transmits the production | presentation control data of the master IC of the 1st Embodiment of this invention. When the first embodiment of the master IC of the present invention initializes the I ² CI / O expander, describing the format of the initialization instruction data transmitted to the I ² CI / O expander from the master IC FIG. It is a figure explaining the abnormality determination table of the 1st master IC of the 1st Embodiment of this invention. It is a figure explaining the abnormality determination table of the 2nd master IC of the 1st Embodiment of this invention. Information transmitted / received between the CPU and the master IC (first master IC or second master IC) when each decoration control device (slave) according to the first embodiment of the present invention is initialized (reset) will be described. FIG. Information transmitted and received between the CPU and the master IC (the first master IC or the second master IC) when transmitting the effect control data to each decoration control device (slave) according to the first embodiment of the present invention. It is a figure explaining. It is a figure explaining the step which transmits production | presentation control data to the master IC (1st master IC or 2nd master IC) from the production | presentation control apparatus of the 1st Embodiment of this invention. It is a flowchart which shows the procedure of the process by the presentation control apparatus of the 1st Embodiment of this invention. It is a flowchart which shows the procedure of the 1st master IC side slave initialization start process and 2nd master IC side slave initialization start process of the 1st Embodiment of this invention. It is a flowchart which shows the procedure of the slave output start process of the 1st Embodiment of this invention. It is a flowchart which shows the procedure of the slave output data edit process of the 1st Embodiment of this invention. It is a flowchart which shows the procedure of the process at the time of transmission interruption interruption | occurrence | production by the 1st master IC and 2nd master IC of the 1st Embodiment of this invention. It is a flowchart which shows the procedure of the process at the time of the time-out interruption generation | occurrence | production by the 1st master IC and the 2nd master IC of the 1st Embodiment of this invention. It is a flowchart which shows the procedure of the transmission resumption process of the initialization instruction | indication data of the 1st Embodiment of this invention. It is a flowchart which shows the procedure of the transmission resumption process of the production control data of the 1st Embodiment of this invention. It is a flowchart which shows the procedure of the data transmission process by the master IC of the 1st Embodiment of this invention. It is a flowchart which shows the procedure of the address recognition process of the 1st Embodiment of this invention. It is a flowchart which shows the procedure of the byte unit data transmission process of the 1st Embodiment of this invention. It is a timing chart which shows the state in which the process by each master IC is performed in parallel by the instruction | indication from CPU at the time of VDP interruption of the presentation control apparatus of the 1st Embodiment of this invention. It is a figure which shows the example of a connection of the decoration control apparatus and decoration apparatus in the 1st Embodiment of this invention, and is a figure which shows the structure which controls LED for 8 sets by two decoration control apparatuses. It is a figure which shows the timing which the decoration control apparatus in the 1st Embodiment of this invention receives data, and controls a production | presentation apparatus, and is a figure explaining the case where the data received at the time of outputting a stop condition are reflected. is there. Executed when the master IC (universality master IC) of the second embodiment of the present invention detects a start condition on the connection lines SCL and SDA while waiting for a command from the CPU. It is a flowchart which shows the procedure of a process. It is a flowchart which shows the procedure of the address recognition process of the 2nd Embodiment of this invention. In a network in which a plurality of versatility master ICs used in the second embodiment of the present invention are connected, a plurality of versatility master ICs simultaneously output data designating a destination address on a data line. It is a figure which shows a mode that the collision generate | occur | produced above. Since the versatility master IC used in the second embodiment of the present invention is outputting data designating a destination address on the data line in a single master system environment, noise is generated and the master It is a figure which shows the state which has functioned as a slave. It is a figure explaining the abnormality determination table corresponding to the game effect group of the 3rd Embodiment of this invention. It is a figure explaining the abnormality determination table corresponding to the reliability alerting | reporting group of the 3rd Embodiment of this invention. It is a flowchart which shows the procedure of the slave output start process of the 3rd Embodiment of this invention. It is a flowchart which shows the procedure of the transmission resumption process of the presentation control data with respect to the decoration control apparatus which controls the decoration apparatus which performs the reliability notification of the 3rd Embodiment of this invention. It is a figure which shows the example of a connection of the decoration control apparatus and decoration apparatus in the 4th Embodiment of this invention, and is a figure which shows the structure which controls LED for 5 sets by one decoration control apparatus. It is a figure which shows the timing which the decoration control apparatus in the 4th Embodiment of this invention receives data, and controls an effect apparatus, and is a figure explaining the case where the data received at the time of outputting ACK are reflected. .

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
FIG. 1 is an explanatory diagram of the gaming machine 1 according to the first embodiment of this invention.

  A front frame (game frame) 3 of the gaming machine 1 is assembled to the main body frame (outer frame) 2 via a hinge 4 so as to be openable and closable on the front surface of the gaming machine 1. A game board 10 (see FIG. 2) is accommodated on the front side of the front frame 3. Further, a glass frame 18 having a cover glass (transparent member) covering the front surface of the game board 10 is attached to the front frame 3.

  Around the cover glass of the glass frame 18, decoration members 9 a and 9 b that emit decoration light are provided. The decoration members 9a and 9b are provided with a decoration device composed of a lamp, an LED, or the like. By causing the decoration device to emit light in a predetermined light emission mode, the decoration members 9a and 9b emit light in a predetermined light emission mode.

  Speakers 30 that emit sound (for example, sound effects) are provided on the left and right sides of the glass frame 18. An illumination unit 11 is provided above the glass frame 18.

  In the illumination unit 11, a first movable illumination 13 and a second movable illumination 14 are arranged on the left and right. The first movable illumination 13 and the second movable illumination 14 include an illumination drive first motor (MOT) 13a and an illumination drive second motor (MOT) 14a in addition to an illumination member such as an LED. It is controlled so as to operate according to the contents of the production.

  An abnormality notification LED 29 for notifying that an abnormality has occurred in the gaming machine 1 is provided at the lower right of the lighting unit 11.

  The open / close panel 20 below the front frame 3 is provided with an upper plate for supplying a game ball to a ball hitting device (not shown), and the fixed panel 22 is provided with a lower plate 23 and an operation unit 24 of the ball hitting device. The lower tray 23 is provided with a lower tray ball removing mechanism 16 for discharging the game balls stored in the lower tray 23. A key 25 for locking the glass frame 18 is provided on the lower right side of the front frame 3.

  Further, when the player turns the operation unit 24, the hitting ball launching device launches a game ball supplied from the upper plate 21.

  In addition, the upper edge portion of the upper plate 21 is provided with an effect button 17 for receiving an operation input from the player. When the player operates the effect button 17, the effect content of the special figure variation display game on the display device 53 (see FIG. 2) provided on the game board 10 is selected, and the special figure variation display game on the display device 53 is selected. In addition, it is possible to perform an effect in which the player's operation is intervened.

  The special figure variation display game is started when the launched game ball wins a start opening 36 (see FIG. 2) provided in the game board 10. In the special figure fluctuation display game, a plurality of pieces of identification information are variably displayed on the display device 53. Then, when the identification information that has been variably displayed is stopped and the result mode of the stopped identification information is a specific result mode, the state of the gaming machine 1 is advantageous to the player (a state where a privilege is granted) Transition to a special gaming state.

  In the upper right portion of the upper plate 21, a ball lending button 26 that is operated when a player borrows a game ball and a discharge button 27 that is operated to discharge a prepaid card from a card unit (not shown) are provided. . Further, a balance display unit 28 for displaying the balance of the prepaid card is provided between the ball lending button 26 and the discharge button 27.

  FIG. 2 is a front view of the game board 10 according to the first embodiment of this invention.

  The gaming machine 1 shown in FIG. 1 fires a game ball in an internal game area 10a (bounces it) to play a game, and a game area 10a is provided on the back side of the cover glass of the glass frame 18. The game board 10 which comprises is installed.

  The game board 10 includes a flat game board main body 10b (made of wood or synthetic resin) serving as a mounting base for various members, and has a game area 10a surrounded by a guide rail 32 on the front surface of the game board main body 10b. ing. A front component 33 is attached to the front surface of the game board main body 10 b and outside the guide rail 32. Then, a game ball (hit ball; game medium) is launched from the launching device into the game area 10a surrounded by the guide rail 32 to play a game.

  A center case 51 that forms a window 52 serving as a display area for a special figure variation display game is attached to the approximate center of the game area 10a. Behind the window 52 formed in the center case 51, a display device 53 is arranged as an effect display device capable of executing an effect of a special figure variable display game that displays a plurality of identification information in a variable manner. The display device 53 includes, for example, a liquid crystal display, and is arranged so that a display portion 53 a whose display contents can be changed is visible from the front side of the game board 10 through the window portion 52 of the center case 51. Note that the display device 53 is not limited to a device including a liquid crystal display, and may include a display such as an EL or a CRT.

  In addition, a reliability notification device 15 that notifies the possibility of jackpot (reliability) is provided on the upper portion of the center case 51. The reliability notification device 15 includes LEDs of a plurality of colors (for example, LEDs of three colors of red, blue, and green) and is controlled to emit light in a color and manner according to the reliability.

  Further, a ball introduction path (warp flow path) 50 through which a game ball can flow down is provided on the left portion of the center case 51, and is opened with the entrance 50a open toward the game area 10a. The ball introduction path 50 communicates with the inside of the center case 51, and the game ball that has flowed from the inlet 50a passes through the back side of the center case 51 and is discharged onto the unit-side stage portion 49b. Further, the game ball that rolls on the unit-side stage portion 49b can flow down onto the base-side stage portion 49a disposed below the unit-side stage portion 49b.

  A plurality of ornaments 47 are arranged on the peripheral edge of the center case 51. A decorative lamp 48 is disposed at the lower left portion of the center case 51, and a plurality of decorative pieces 46 are disposed in an upper and lower movable state at the upper portion of the center case 51. The decoration tool 47, the decoration lamp 48, and the decoration piece 46 perform an effect operation according to a command from an effect control device 550 described later. The configuration of the center case 51 will be described in more detail with reference to FIG.

  Further, in the game area 10a, below the center case 51, a start opening 36 for starting a special figure changing display game that can receive (win) a game ball is arranged. Further, on the side of the center case 51 (on the left side), a general map start gate 34 for starting the general map change display game is arranged.

  Further, in the game area 10a, side lamps 45 that perform various decorative displays by light emission are arranged on the lower left and lower right of the center case 51. The side lamp 45 is provided with a general winning opening 44.

  Further, a big winning opening 42 is arranged below the start opening 36, and an out opening for collecting the game balls that have flowed down without winning at the lower edge of the gaming area 10a below the big winning opening 42. 43 is established. The special winning opening 42 includes an attacker-type opening / closing door 42a that can be opened by rotating in a direction in which the upper end side is tilted to the near side. The state of the open / close door 42a is changed from a closed state (a disadvantageous state for the player) to an open state (a state advantageous for the player) according to the result of the special figure variation display game.

  In addition, in the game area 10a excluding attachment portions such as the center case 51, the start port 36, the side lamp 45, etc., there are a windmill (not shown) as a hitting direction changing member, and many No. nails (not shown) are provided. A vertically arcuate game ball passage 57 is formed between the center case 51 and the front structural member 33 located on the opposite side of the normal start gate 34 with the center case 51 interposed therebetween.

  Further, the game board 10 is provided with a special figure / special figure display 35 for executing a special figure change display game and a normal figure change display game. The general-purpose / special-figure display 35 displays the number of unprocessed times (special figure start memory number) of the special-figure display game and the unprocessed number of general-purpose variable display games (number of general figure start memory). The general-purpose / special-purpose display 35 is provided as a segment LED together with a game state display LED (not shown) representing a game state.

  A gate SW 34a (see FIG. 9) for detecting a game ball that has passed through the general chart start gate 34 is provided in the general chart start gate 34. Then, when the game ball that has been driven into the game area 10a passes through the normal figure start gate 34, the normal figure change display game is started.

  In addition, when the game ball passes through the general chart start gate 34 in a state where the normal map variable display game cannot be started, if the general chart start memory number is less than the upper limit number, the general chart start memory number is incremented by one, One random number indicating whether or not the normal figure change display game is won is stored as a normal figure start memory.

  The state in which the general map change display game cannot be started is, for example, a state in which the general map change display game has already been performed and the normal map change display game has not been completed, Is the state that has been converted to the open state.

  It should be noted that the universal map change display game may display the universal map change display game in a part of the display area of the display device 53. In this case, for example, numbers, symbols, character designs, etc. are used as identification symbols. This identification symbol is displayed by variably displaying for a predetermined time and then stopped and displayed.

  When the stop display of the normal map change display game becomes a special result mode, the opening / closing member 36a of the start port 36 is opened for a predetermined time (for example, 0.5 seconds) as a win for the normal map change display game. Is done. Thereby, it becomes easy to win a game ball in the start opening 36, and the special figure variation display game can be started easily. The opening / closing member 36a of the start port 36 normally maintains a closed state (a disadvantageous state for the player) with an interval of about the diameter of the game ball. When the stop display mode is entered (when the normal-game fluctuation display game is won), the game ball is opened in the reverse “C” shape by the solenoid (Fuden SOL 36b, see FIG. 9), and the game ball is placed at the start port 36. It is changed to a state that is easy to flow in (a state that is advantageous to the player).

  Further, the gaming machine 1 according to the first embodiment of the present invention shortens the variation display time of the special figure variation display game on the display device 53 as a gaming state based on the result aspect of the special figure variation display game. An operation state (second operation state) can be generated. The short-time operation state (second operation state) is a state in which the opening / closing member 36a of the start port 36 is likely to be open compared to the normal operation state (first operation state).

  In the short-time operation state, the execution time of the normal variation display game is controlled to be shorter than the execution time in the normal operation state (for example, 10 seconds is 1 second), and the number of opening of the start port 36 per unit time is It is controlled to increase substantially. Further, in the short-time operation state, when the start port 36 is opened due to the winning of the normal fluctuation display game, the opening time is controlled to be longer than the opening time of the normal operation state (for example, 0 3 seconds is 1.8 seconds). Further, in the short-time operation state, the start port 36 is opened a plurality of times (for example, two times) instead of once for the one-time winning result of the normal map display game. Further, in the short-time operation state, control is performed so that the probability of winning the normal-variation display game is higher than that in the normal operation state. That is, the number of times of opening of the start port 36 is increased as compared with the normal operation state, and it becomes easy to win a game ball in the start port 36, and the special figure variation display game can be started easily.

  In addition, a start port SW 36 d (see FIG. 9) for detecting a game ball that has passed through the start port 36 is provided inside the start port 36. When a game ball is detected by the start port SW36d, a start right for starting a special figure variation display game as an auxiliary game is generated. At this time, the right to start the special figure variation display game is stored as a special figure start memory within a predetermined upper limit number (for example, 4).

  When the special figure fluctuation display game cannot be started immediately, for example, when the special figure fluctuation display game has already been performed and the special figure fluctuation display game has not been completed, or when the special game state has been entered, the start port 36 When the game ball wins, if the special figure start memory number is less than the upper limit number (for example, less than 4), the special figure start memory number is incremented by 1 and extracted at the timing when the game ball wins the start opening 36. One random number is stored as a special figure start memory. When the special figure fluctuation display game is ready to start, the special figure fluctuation display game is started based on the special figure start memory.

  The special figure variation display game as an auxiliary game is executed by the general figure / special figure display device 35 provided on the game board 10, and after a plurality of identification information is variably displayed, a predetermined result mode is stopped and displayed. Done. Further, a plurality of types of identification information (for example, numbers, symbols, character designs, etc.) are displayed in a variable manner on the display device 53 in correspondence with the special figure fluctuation display game. And as a result of the special figure variation display game, when the display mode of the general figure / special map display 35 becomes a special result mode, it becomes a big win and becomes a special game state (so-called big hit state). Correspondingly, the display mode of the display device 53 is also a special result mode (for example, any one of the numbers in the flat order such as “7, 7, 7”). In addition, you may comprise so that a special figure fluctuation display game may be performed only with the display apparatus 53 instead of the general figure and special figure display 35. FIG.

  Further, the gaming machine 1 according to the first embodiment of the present invention can generate a probability variation state (second probability state) as a gaming state based on the result form of the special figure variation display game. This probability variation state (second probability state) is a state in which the probability of a hit result in the special figure variation display game is higher than the normal probability state (first probability state). Note that the probability variation state and the above-described short-time operation state can be generated independently, and both can be generated at the same time, or only one of them can be generated.

  FIG. 3 is an exploded perspective view of the center case 51 according to the first embodiment of the present invention.

  The center case 51 includes a frame decoration portion 65 disposed as a front surface configuration portion on the front side of the game board main body 10b (game board 10), and a frame base portion 60 disposed as a back surface configuration portion on the back surface side of the game board main body 10b. And are polymerized before and after. The frame decoration portion 65 includes an annular decoration base 66 that is fixed to the surface of the game board main body 10b. On the back side of the decoration base 66, there is provided a decoration panel unit 67 that is substantially the same size as the decoration base 66 and formed in a circular shape, and the frame decoration portion 65 superimposes the decoration base 66 and the decoration panel unit 67 back and forth. Configured.

  Under the decoration base 66, a base side stage portion 49a capable of rolling a game ball in the front-rear direction and the left-right direction is disposed on the upper surface, and a decoration lamp is provided between the base side stage portion 49a and the game ball passage 57. 48 is arranged (see FIG. 2). A ball introduction path (warp flow path) 50 through which a game ball can flow down is provided on the opposite side of the decoration lamp 48 across the base side stage portion 49a, and the entrance 50a of the ball introduction path 50 is connected to the decoration base 66. The outlet 50b of the ball introduction path 50 is communicated with the back side of the decorative panel unit 67 described later.

  The decorative panel unit 67 includes a cover panel portion 69 formed of a substantially circular transparent resin plate, and a plurality of decorative tools 47 are arranged on the peripheral edge of the front side of the cover panel portion 69. When the decorative panel unit 67 and the frame decorative portion 65 are overlapped, the decorative tool 47 is set so as to be arranged along the inner peripheral edge of the decorative base 66 (see FIG. 2). In addition, a reliability notification device 15 is disposed on the upper portion of the cover panel unit 69.

  In addition, a unit-side stage portion 49b capable of rolling a game ball in the front-rear direction and the left-right direction is disposed on the upper surface at the lower portion on the back side of the cover panel portion 69. The unit side stage portion 49b is disposed above the base side stage portion 49a of the decorative base 66.

  Further, a sphere inlet 68 is opened at a location where the cover panel 69 overlaps with the outlet 50 b of the sphere introduction path 50, and the sphere introduction path 50 and the unit side stage portion 49 b communicate with each other via the sphere inlet 68. doing. Therefore, when a game ball flowing down the game area 10a flows into the ball introduction path 50, the ball introduction path 50 is configured so that the game ball can be introduced onto the unit side stage portion 49b.

  The frame base 60 includes a frame-like base case 61 that is fixed to the back side of the game board 10 in a state where the front side is open, and is opened inside the base case 61 (in other words, inside the center case 51). The part 62a forms a concave chamber 62 provided on the front side.

  In addition, a rectangular window 52 is opened in the front-rear direction behind the concave chamber 62 in the base case 61, and a display device 53 is attached from the rear of the base case 61 to display the display portion of the display device 53. 53 a faces the front of the center case 51 through the window 52 and the recessed chamber 62.

  Further, a plurality of decorative pieces 46 that can be moved up and down by an accessory driving solenoid (not shown) are disposed on the front side of the upper edge of the window 52, and display portions are provided on the left and right edges of the window 52. A movable effect device 58 that moves forward 53a and performs an effect operation is provided.

  Then, when the frame decoration portion 65 is overlapped in front of the frame base portion 60, the opening 62a and the window portion 52 of the concave chamber 62 are covered with the cover panel portion 69 from the front, and the display portion 53a of the display device 53 is covered with the frame decoration portion. It is configured to face the front of the center case 51 from the inside of 65 (where the cover panel portion 69 is exposed).

  4 and 5 are diagrams illustrating the configuration of the movable effect device 58 according to the first embodiment of this invention.

  The movable effect device 58 is configured by providing the first effect unit 63 and the second effect unit 64 at positions separated from each other, and the first effect unit 63 and the second effect unit 64 are operated in conjunction with each other. .

  FIG. 4 is a diagram illustrating a state before the movable effect device 58 is operated, and FIG. 5 is a result of the movable effect device 58 being operated and the first effect unit 63 and the second effect unit 64 being operated. It is a figure which shows the state contact | abutted in a part (1st contact part 121 and 2nd contact part 122).

  The first effect unit 63 is disposed on the left side of the center case 51, that is, on the left side of the peripheral edge of the window portion 52 of the base case 61. Further, the second effect unit 64 is disposed on the right side of the center case 51. When viewed from the front of the center case 51, the concave chamber 62 and the window 52 are arranged so as to face between the first effect unit 63 and the second effect unit 64.

  The first effect unit 63 includes a first effect member 70 that can move forward of the display unit 53a, and an accessory driving first motor (MOT) that serves as a first effect drive source that generates the driving force of the first effect member 70. ) 71 and a first effect transmission mechanism (a first main arm member 73 and a first sub arm member 74) that transmits the driving force (rotational power) generated from the accessory driving first MOT 71 to the first effect member 70. .

  Further, an output shaft (first output shaft) 71a of the accessory driving first MOT 71 extends in the front-rear direction of the center case 51, and a first drive gear 76 is rotatably mounted on the first output shaft 71a. Yes.

  The first main arm member 73 is formed with a first main arm gear 77 that meshes with the first drive gear 76, and is pivotally mounted above the first drive gear 76. The first sub arm member 74 is formed with a first sub arm gear 78 that meshes with the first drive gear 76, and is pivotally attached to the lower side of the first drive gear 76. The first main arm member 73 and the first sub arm member 74 are axially attached to the first effect member 70 at positions where the end portions opposite to the end portions axially attached to the base case 61 are different from each other. 70 is supported.

  When the first effect unit 63 drives the accessory driving first MOT 71 and rotates the first driving gear 76 in the clockwise direction when viewed from the front of the center case 51, the driving force (rotation power) of the accessory driving first MOT 71 is generated. The first main arm member 73 is transmitted to the first main arm member 73 via the first drive gear 76 and the first main arm gear 77, and the first main arm member 73 is rotated counterclockwise when viewed from the front of the center case 51 by this driving force. To do. The driving force of the accessory driving first MOT 71 is transmitted to the first sub arm member 74 via the first driving gear 76 and the first sub arm gear 78, and the first sub arm member 74 is transmitted to the first main arm 74 by this driving force. It rotates in the same counterclockwise direction as the arm member 73. As a result, the first effect member 70 rises while being supported by the first main arm member 73 and the first sub arm member 74.

  Then, when the first main arm member 73 and the first sub arm member 74 are extended upward by the driving force of the accessory driving first MOT 71 and set in the vertical posture, as shown in FIG. The first effect stop state is set to be deviated from the front of the display portion 53a, and the first effect member 70 is located on the side of the window portion 52 and is hidden behind the frame decoration portion 65 and behind the game board main body 10b. (See FIG. 2).

  On the other hand, when the first driving gear MOT 71 is driven from the first effect stop state and the first driving gear 76 is rotated counterclockwise when viewed from the front of the center case 51, the driving force (rotational power) of the first driving gear MOT 71 is rotated. ) Is transmitted to the first main arm member 73 via the first drive gear 76 and the first main arm gear 77, and the first main arm member 73 rotates clockwise as viewed from the front of the center case 51 by this drive force. Move.

  The driving force of the accessory driving first MOT 71 is transmitted to the first sub arm member 74 via the first driving gear 76 and the first sub arm gear 78, and the first sub arm member 74 is transmitted to the first main arm 74 by this driving force. It rotates in the same clockwise direction as the arm member 73. As a result, the first effect member 70 is lowered while being supported by the first main arm member 73 and the first sub arm member 74.

  Then, when the first main arm member 73 and the first sub arm member 74 are extended to the front of the display unit 53a and set in the horizontal posture by the driving force of the accessory driving first MOT 71, as shown in FIG. The first effect execution state is reached in which the member 70 is positioned in front of the display unit 53a, and the first effect member 70 is in front of the central portion of the display unit 53a in the space between the display unit 53a and the cover panel unit 69. To position.

  The second effect unit 64 includes a second effect member 80 that can move to the front of the display unit 53a, and an accessory driving second motor (MOT) as a second effect drive source that generates the drive force of the second effect member 80. ) 81 and a second effect transmission mechanism (second main arm member 83 and second sub arm member 84) that transmits the driving force (rotation power) generated from the accessory driving second MOT 81 to the second effect member 80. .

  Further, the accessory driving second MOT 81 has an output shaft (second output shaft) 81a extending in the front-rear direction of the center case 51, and a second drive gear 86 is pivotally attached to the second output shaft 81a so as to be able to rotate together. Yes.

  The second main arm member 83 is formed with a second main arm gear 87 that meshes with the second drive gear 86, and is pivotally attached to a position closer to the first effect unit 63 than the second drive gear 86. The second sub arm member 84 is formed with a second sub arm gear 88 that meshes with the second drive gear 86, and is pivotally attached to the lower side of the second drive gear 86. The second main arm member 83 and the second sub arm member 84 are pivotally attached to the second effect member 80 at positions where the end portions opposite to the end portions that are axially attached to the base case 61 are different from each other. 80 is supported.

  When the second effect unit 64 drives the accessory driving second MOT 81 and rotates the second driving gear 86 in the clockwise direction when viewed from the front of the center case 51, the driving force (rotation power) of the accessory driving second MOT 81 is generated. This is transmitted to the second main arm member 83 via the second drive gear 86 and the second main arm gear 87, and the second main arm member 83 rotates counterclockwise when viewed from the front of the center case 51 by this driving force. To do. Further, the driving force of the accessory driving second MOT 81 is transmitted to the second sub arm member 84 via the second driving gear 86 and the second sub arm gear 88, and the second sub arm member 84 is transmitted to the second main arm member 84 by this driving force. It rotates in the same counterclockwise direction as the arm member 83. As a result, the second effect member 80 is lowered while being supported by the second main arm member 83 and the second sub arm member 84.

  Then, the second main arm member 83 and the second sub arm member 84 are rotated by the driving force of the accessory driving second MOT 81 to cause the second effect member 80 to reach the bottom dead center, and then the second main arm member 83 and When the second sub-arm member 84 is rotated to extend obliquely downward and set in a vertical posture and the second effect member 80 is slightly raised from the bottom dead center, as shown in FIG. The second effect stop state is reached in which the member 80 is positioned away from the front of the display unit 53a, and the second effect member 80 is hidden behind the frame decoration part 65 and behind the game board main body 10b (see FIG. 2).

  On the other hand, when the accessory driving second MOT 81 is driven from the second effect stop state and the second driving gear 86 is rotated counterclockwise as viewed from the front of the center case 51, the driving force (rotational power) of the accessory driving second MOT 81 is rotated. ) Is transmitted to the second main arm member 83 via the second drive gear 86 and the second main arm gear 87, and the second main arm member 83 rotates clockwise as viewed from the front of the center case 51 by this driving force. Move.

  Further, the driving force of the accessory driving second MOT 81 is transmitted to the second sub arm member 84 via the second driving gear 86 and the second sub arm gear 88, and the second sub arm member 84 is transmitted to the second main arm member 84 by this driving force. It rotates in the same clockwise direction as the arm member 83. As a result, the second effect member 80 rises while being supported by the second main arm member 83 and the second sub arm member 84.

  Then, when the second main arm member 83 and the second sub arm member 84 are extended to the front of the display unit 53a and set in the horizontal posture by the driving force of the accessory driving second MOT 81, as shown in FIG. The second effect execution state in which the member 80 is positioned in front of the display unit 53a is entered, and the second effect member 80 is in front of the central portion of the display unit 53a in the space between the display unit 53a and the cover panel unit 69. To position.

  FIG. 6 is an exploded perspective view of the first effect member 70 according to the first embodiment of the present invention.

  The first effect member 70 is a substantially semicircular member when viewed from the front of the center case 51, and is set in a posture in which an arc surface is disposed on the first effect unit 63 side.

  The first effect member 70 is provided with a first effect base 100 serving as a base. The first effect base 100 is formed of a transparent resin. Formed on the upper part of the first effect base 100 is a first main arm shaft attachment portion 101 for axially attaching the first main arm member 73 from the front of the first effect base 100, and on the lower part of the first effect base 100, A first sub-arm shaft attachment portion 102 for attaching the first sub-arm member 74 from the rear of the first effect base 100 is formed.

  A first light diffusion sheet 103 that can transmit light while diffusing light is superposed on the front surface of the first effect base 100. Furthermore, the transparent first protective panel 104 is polymerized on the front surface of the first light diffusing sheet 103 to prevent the first light diffusing sheet 103 from falling off the first effect member 70.

  Further, the rear portion of the first production base 100 is recessed forward to form a first substrate storage space portion 105, and a light emitting device such as an LED (decoration device 620, see FIG. 17) is formed in the first substrate storage space portion 105. The mounted first light emitting substrate 106 is accommodated. Further, in this state, the first substrate housing space portion 105 is closed with the first base lid portion 107 to prevent the first light emitting substrate 106 from falling off the first effect member 70.

  Then, when light is generated from the light emitting device of the first light emitting substrate 106, the light passes through the first effect base 100, the first light diffusion sheet 103, and the first protective panel 104 and is irradiated to the front of the center case 51. It is configured as follows.

  Further, a first effect magnet holder 124 whose rear part is opened is formed on the first substrate housing space 105 side of the first contact part 121 so as to be recessed. The first effect magnet holder 124 has a first magnet 125 made of a button-shaped permanent magnet in a posture in which the magnetic pole faces the second effect member 80 side, and the first magnet 125 is connected to the first contact portion 121 (first effect). The magnet holder 124) is stored so as not to fall off.

The first light emitting substrate 106 is equipped with an I ² CI / O expander 615 (see FIG. 17) for controlling the light emission of the decoration device 620, and a control signal (electric signal) output from the effect control device 550, etc. A data line and a clock line (signal line) for transmission are connected. Further, a power line for supplying power necessary for causing the decoration device 620 to emit light is connected. These connection lines are connected together as a cable 108.

  FIG. 7 is an exploded perspective view of the second effect member 80 according to the first embodiment of the present invention.

  The second effect member 80 has a substantially parallelogram shape with a cutout portion at the top when viewed from the front of the center case 51. In the second effect stop state, the upper and lower side surfaces of the second effect member 80 are inclined downward from the second effect unit 64 side toward the first effect unit 63 side (see FIG. 4), and in the second effect execution state, The left and right side surfaces of the second effect member 80 are set in a posture to incline downward from the second effect unit 64 side toward the first effect unit 63 side (see FIG. 5).

  The second effect member 80 includes a second effect base 110 that serves as a base. The second effect base 110 is formed of a transparent resin. In the upper part of the second effect base 110, a second main arm axis attaching part 111 for axially attaching the second main arm member 83 from the front of the second effect base 110 is formed, and in the lower part of the second effect base 110, A second sub-arm shaft attachment portion 112 for attaching the second sub-arm member 84 from the rear of the second effect base 110 is formed.

  Further, a second light diffusing sheet 113 that can transmit light while diffusing light is superposed on the front surface of the second effect base 110. By superposing the transparent second protective panel 114 on the front surface of the second light diffusing sheet 113, the second light diffusing sheet 113 is prevented from falling off the second effect member 80.

  In addition, the rear portion of the second effect base 110 is recessed forward to form a second substrate storage space 115, and a light emitting device (decoration device 620) such as an LED is mounted in the second substrate storage space 115. The second light emitting substrate 116 is accommodated, and in this state, the second substrate accommodating space 115 is closed by the second base lid portion 117 to prevent the second light emitting substrate 116 from dropping from the second effect member 80. .

  Then, when light is generated from the light emitting device of the second light emitting substrate 116, the light passes through the second effect base 110, the second light diffusion sheet 113, and the second protection panel 114 and is irradiated to the front of the center case 51. It is configured as follows.

  Further, a second effect magnet holder 128 having an open rear portion is formed on the second substrate housing space 115 side of the second contact portion 122 so as to be recessed. In the second effect magnet holder 128, a second magnet 129 made of a button-shaped permanent magnet is stored at a position symmetrical to the first magnet 125 across the first contact portion 121 and the second contact portion 122. Has been.

Similarly to the first light emitting substrate 106, the second light emitting substrate 116 is equipped with an I ² CI / O expander 615 (see FIG. 17) for controlling the light emission of the decoration device 620, and outputs from the effect control device 550. A data line and a clock line (signal line) for transmitting the transmitted control signal and the like are connected. Further, a power line for supplying power necessary for causing the decoration device 620 to emit light is connected. These connection lines are connected together as a cable 118.

  The movable effect device 58 includes the first contact member 121 on the first effect member 70 and the second contact member 122 on the second effect member 80. When the first effect unit 63 is converted to the first effect execution state and the second effect unit 64 is converted to the second effect execution state, the first contact portion 121 and the second contact portion 122 contact each other. The first effect member 70 and the second effect member 80 form one decorative body. At this time, the first magnet 125 and the second magnet 129 are arranged so as to generate an attractive force between the first magnet 125 and the second magnet 129. Further, the decorative body thus formed is configured to be positioned in front of the central portion of the display portion 53a.

  FIG. 8 is a diagram illustrating wiring of the gaming machine 1 according to the first embodiment of this invention.

  FIG. 8 shows a state before the center case 51 is attached to the game board main body 10 b and the display device 53 is attached to the center case 51. An effect control device 550 is attached to the back surface of the display device 53. The effect control device 550 is provided with a connection terminal 90, and transmits a control signal and supplies power to the effect device to be controlled via the connection terminal 90. Specifically, it is connected via a cable 91 to a relay board 600 described later.

  In addition, a game control device 500 and a control unit 700 including various control boards are arranged at the lower back of the game board main body 10b. The control board mounted on the control unit 700 includes a relay board 600 that relays the control signal transmitted from the effect control apparatus 550 to the decoration control apparatus 610 (see FIG. 11). Although the details will be described later, the decoration control device 610 controls an effect device such as a light emitting device (for example, LED) or a movable object (for example, a motor) for effecting a game. The relay board 600 can be connected to a light emitting device or a movable object, similarly to the decoration control device 610.

  The relay board 600 is provided with an upstream connector 601 connected to the effect control device 550 via the cable 91. One connector 91a of the cable 91 is connected to the connection terminal 90 of the effect control device 550 as described above. The other connector 91 b of the cable 91 is connected to the upstream connector 601 of the relay board 600. Furthermore, connectors 602a to 602e for connecting to a decoration control device 610 that controls each effect device provided in the gaming machine 1 are provided.

  Further, the relay board 600 is provided with a vacant terminal monitor 603 indicating the connection state of the connected cables. Details of the empty terminal monitor 603 will be described with reference to FIG.

  Although illustration is omitted, units constituting the game control device 500 are provided so as to cover the connector mounting surface of the relay board 600. Therefore, the game control apparatus 500 has an arrangement configuration that is attached after attaching necessary cables to the connectors of the relay board 600.

  Connected to the front frame 3 is a cable 3b for transmitting signals for controlling the speaker 30 and the decorative members 9a, 9b and the like disposed on the front frame 3. The connector of the cable 3b is connected to the connection terminal 92 of the effect control device 550.

  An opening 45b for attaching the side lamp 45 is formed in the game board main body 10b. A cable 45a for transmitting power and signals is connected to the side lamp 45, and is introduced from the opening 45b to the back side of the game board 10. The cable 45a introduced to the back side of the game board 10 is connected to the relay board 600, for example, connected to the connector 602d.

  Further, as shown in FIG. 2, a starting port 36 and a special winning port 42 are arranged at the lower part of the game board 10. On the back side of the game board 10 on which the start port 36 is arranged, there is arranged a general electric solenoid (SOL) 36b for opening and closing an open / close member 36a that is opened when a win-win game is won. In addition, a special winning opening SOL 42 b for opening and closing the special winning opening 42 when the special figure variation display game is won is also arranged on the back side of the game board 10. A cable (not shown) for receiving an input of a control signal is connected to the general electric power SOL 36 b and the special winning opening SOL 42 b, and these cables are connected to the game control device 500. The cable 42C is connected to the relay board 600 as a cable for transmitting power and a signal for lighting the effect LED provided in the special winning opening 42, and is connected to the connector 602f, for example.

  As described above, the center case 51 is attached to the center of the game board 10. Inside the center case 51, a movable effect device 58 constituted by the first effect member 70 and the second effect member 80 is provided. In FIG. 8, the first effect member 70 and the second effect member 80 are in contact with each other at the contact surfaces (121, 122).

  Further, as described above, the first effect unit 63 and the second effect unit 64 of the movable effect device 58 include the motor (the accessory driving first motor) for operating the first effect member 70 and the second effect member 80. 71, an accessory driving second motor 81) is provided. A cable 652 for supplying signals for controlling these motors and power for driving the motors is connected to the movable effect device 58. In addition, the movable rendering device 58 is provided with a motor position detection sensor (not shown) for detecting the operation state of these motors, and a cable 651 for receiving a sensing result is connected. The cable 652 and the cable 651 extend from the opening 51 b of the center case 51 to the back side of the game board 10 and are connected to the relay board 600. For example, the cable 652 is connected to the connector 602C, and the cable 651 is connected to the connector 602e.

  Furthermore, a cable 653 is connected to transmit the control signal output from the effect control device 550 to a decoration control device 610 (see FIG. 11) for controlling the effect device such as an LED disposed inside the center case 51. The The cable 653 is connected to the relay board 600 on the back side of the game board 10 through an opening 51a provided in the center case 51, and is connected to, for example, a connector 602a.

  FIG. 9 is a block diagram showing a configuration of the gaming machine 1 according to the first embodiment of this invention.

  The gaming machine 1 includes a game control device 500 that controls the game in an integrated manner, an effect control device 550 that controls the display device 53 and the speaker 30 to perform various effects, and a payout motor (not shown) for paying out game balls. A payout control device 580 for controlling is provided.

  First, the configuration of the game control device 500 will be described. The production control device 550 will be described with reference to FIG.

  The game control device 500 includes a game microcomputer 501, an input I / F (Interface) 505, an output I / F (Interface) 506, and an external communication terminal 507.

  The gaming microcomputer 501 includes a CPU 502, a ROM (Read Only Memory) 503, and a RAM (Random Access Memory) 504.

  The CPU 502 is a main control device that controls the game in an integrated manner, and controls the game. The ROM 503 stores invariant information (programs, data, etc.) for game control. The RAM 504 is used as a work area during game control.

  The external communication terminal 507 connects the game control device 500 to an external device such as an inspection device that inspects the setting information of the game control device 500.

  The CPU 502 receives various input devices (start opening SW36d, general winning openings SW44a to 44n, gate SW34a, count SW42d, glass frame opening SW18a, front frame opening SW3a, ball break SW54, vibration sensor 55, and the like via the input I / F 505. In response to the detection signal from the magnetic sensor 56), various processes such as a big hit lottery are performed.

  The start port SW36d is a switch that detects that a game ball has won the start port 36. The general winning ports SW 44 a to 44 n are switches that detect that a game ball has won the general winning port 44.

  The gate SW 34a is a switch that detects that a game ball has passed through the usual start gate 34. The count SW 42d is a switch that detects that a game ball has won a prize winning opening 42.

  The glass frame opening SW 18a is a switch that detects that the glass frame 18 has been opened. The front frame opening SW 3a is a switch for detecting that the front frame 3 is opened.

  The ball cut SW 54 is a switch that detects that the number of game balls stored in the gaming machine 1 and used for payout has become a predetermined number or less.

  The vibration sensor 55 is a sensor that detects vibration applied to the gaming machine 1 and detects an illegal act such as vibrating the gaming machine 1. The magnetic sensor 56 is provided in the vicinity of the second start winning opening, the general winning opening 44, the large winning opening 42, and the normal start gate 34 of the start opening 36, and is a sensor for detecting magnetic force. The magnetic sensor 56 detects a fraud that brings a magnet close to each winning hole and guides the game ball launched to the gaming area 10a to each winning hole.

  In addition, the CPU 502 transmits a command signal to the ordinary / special-purpose display 35, the ordinary electric power SOL 36b, the special winning opening SOL 42b, the payout control device 580, and the effect control device 550 via the output I / F 506, thereby playing Overall control.

  As described above, the special figure change display game and the universal figure change display game are executed on the special figure / special figure display unit 35. Furthermore, the number of unprocessed times (special figure start memory number) of the special figure change display game and the number of unprocessed times (standard figure start memory number) of the normal figure change display game are displayed. A general chart start memory including a random number indicating whether or not the special figure fluctuation display game is won and a special figure start memory including a random number indicating whether or not the special figure fluctuation display game is a win are stored.

  The general electric power SOL 36b opens the opening / closing member 36a when the stop display of the general-purpose variable display game becomes a special result mode, thereby making it easy for the game ball to win the start opening 36.

  The special winning opening SOL42b opens the open / close door 42a of the special winning opening 42 when the result of the special figure change display game becomes a special result mode and becomes a special gaming state (a big hit state), and a game ball Is converted to a state where it is easy to win.

  The game control device 500 outputs game machine data from the external information terminal 508 to a game hall management device (not shown) via an information collection terminal device (not shown). The gaming hall management device is a computer that collects and manages gaming data of the gaming machines 1 installed in the gaming hall.

  The payout control device 580 receives, from the game control device 500, a payout command for the number of game balls corresponding to the winning port when the game ball wins the general winning port 44 or the big winning port 42. Further, even when the ball lending button 26 is operated, a payout command for paying out a predetermined number of game balls is received from the game control device 500. The payout control device 580 controls a payout motor (not shown) based on the received payout command, and pays out the number of game balls specified in the payout command.

  The game control device 500 uses a change start command, a customer waiting demo command, a fanfare command, a probability information command, an error designation command, and the like as game data indicating the game situation via the output I / F 506, and the effect control device 550. Send to.

  FIG. 10 is a block diagram illustrating a configuration of the effect control device 550 according to the first embodiment of this invention.

  The effect control device 550 determines the contents of the effect based on the game data input from the game control device 500, controls the display device 53, and controls various effect devices provided in the game board 10 and the front frame 3. To do. The rendering device includes a light emitting device such as an LED and a movable object such as a motor or a solenoid.

  The production control device 550 includes a CPU 551, a control ROM 552, a RAM 553, an image ROM 554, a sound ROM 555, a VDP 556, a sound LSI 557, an input I / F 558b, an output I / F 558a, a power-on detection circuit 559, a first master IC 570a, a second master IC 570b, A NOR gate circuit 561 and a monitoring timer circuit 562 are provided. Further, the effect control device 550 includes a connection terminal 90 connected to the game board 10 and a connection terminal 92 connected to the front frame 3. The functions common to the first master IC 570a and the second master IC 570b will be described simply as “master IC”.

  The CPU 551 receives the command signal transmitted from the game control device 500 as an interrupt signal (INT) as a communication interrupt, and controls various effects based on the input command signal. The CPU 551 receives an interrupt signal (INT) as a master interrupt from the first master IC 570a and the second master IC 570b, and also receives an interrupt signal (INT) as an image update interrupt from the VDP 556. Is done.

  Further, the CPU 551 receives an interrupt signal (INT) as a timeout interrupt also from the monitoring timer circuit 562. The timeout monitoring circuit 562 includes a plurality of types of monitoring timers, and outputs an interrupt signal to the CPU 551 when the monitoring timer value set by the CPU 551 times out. When the CPU 551 receives an input of an interrupt signal, the CPU 551 interrupts the process being executed and executes a process corresponding to the input interrupt signal.

  The control ROM 552 stores invariant information (program, data, etc.) for effect control. The RAM 553 is used as a work area during production control.

  The image ROM 554 is connected to the VDP 556 and stores image data displayed on the display device 53. The VDP 556 is a processor that controls image output to the display device 53.

  In addition, the VDP 556 includes a synchronization signal generating unit that generates a synchronization signal that is synchronized with a cycle (33 ms cycle) for updating an image displayed on the display device 53. Every time the synchronization signal is generated, the synchronization signal generation means inputs the generated synchronization signal to the CPU 551 as an interrupt signal.

  The sound ROM 555 is connected to the sound LSI 557 and stores sound data output from the speaker 30 provided in the front frame 3. The sound LSI 557 is a circuit that controls the sound output from the speaker 30.

  The input I / F 558b is an interface that receives information input from the outside via the filters 565a and 565b. Specifically, input of a signal indicating that the effect button 17 provided on the front frame 3 has been operated is received, position information of each motor detected by a motor position detection sensor provided on the game board 10, etc. Or accept input.

  The power-on detection circuit 559 generates a reset signal that initializes the registers of the first master IC 570a and the second master IC 570b to a default state (all 0) when the effect control device 550 is powered on, and generates a NOR gate. Output to the circuit 561.

  Further, the CPU 551 outputs a reset signal to the output I / F 558a via the bus 563 when a predetermined condition is satisfied. The output I / F 558a outputs the input reset signal to the NOR gate circuit 561, and further outputs the reset signal from the NOR gate circuit 561 to the first master IC 570a and the second master IC 570b. The predetermined condition is, for example, a case where an error flag is “ON” in all the decoration control devices 610 (see FIGS. 32 and 33).

  Further, the output I / F 558a outputs a control signal to an effect device (an effect device driven by a movable object such as a motor or a solenoid) provided in the game board 10 or the front frame 3 via the driver 564a and the driver 564b. .

  Note that the reset signal input from the power-on detection circuit 559 to the NOR gate circuit 561 and the reset signal input from the CPU 551 to the NOR gate circuit 561 via the output I / F 558a are in a LOW level state in any case. It functions as a signal to command reset at Therefore, if a reset signal is output to the NOR gate circuit 561 from at least one of the power-on detection circuit 559 and the CPU 551, the reset signal is input to the first master IC 570a and the second master IC 570b via the NOR gate circuit 561. .

  FIG. 11 is a block diagram showing the configuration of the first master IC 570a provided in the effect control device 550 and the effect device provided in the game board 10 according to the first embodiment of the present invention.

  The game board 10 includes a relay board 600 connected to the first master IC 570a, a decoration device board 625 connected to the relay board 600, and an auxiliary game device unit 12.

  The relay board 600 transmits (relays) the electrical signal transmitted from the first master IC 570 a to the decoration control device 610 provided in the game board 10. In addition, the relay board 600 has a function of controlling the effect device, similarly to the decoration control device 610, and controls the decoration device board 625 directly connected to the relay board 600.

The decoration device 620 is a light emitting device that is controlled by an I ² CI / O expander 615 (see FIG. 17) provided in the decoration control device 610 and flashes light when an electric current is applied. It is. The decoration device substrate 625 is a substrate provided on the side lamp 45 (see FIG. 8), and a light emitting device (LED) of the side lamp 45 is mounted thereon. The light emitting device of the side lamp 45 is directly controlled by an I ² CI / O expander 615 provided on the relay board 600.

  The auxiliary gaming device unit 12 includes a decoration device 620 that is a light emitting device such as an LED, a first accessory driving first motor (MOT) 71 that is a movable object, and a second accessory driving second MOT 81. The decoration device 620 in the auxiliary gaming device unit 12 is controlled by the decoration control device 610 included in the auxiliary gaming device unit 12. In the first embodiment of the present invention, the accessory driving first MOT 71 and the accessory driving second MOT 81 are configured to be controlled by the relay board 600, but the auxiliary gaming device unit is similar to the decoration device 620. 12 may be configured to be controlled by a decoration control device 610 included in the control unit 610.

The first accessory driving MOT 71 and the second accessory driving MOT 81 are driving devices that perform an effect operation by rotating when current flows. Since the accessory driving first MOT 71 and the accessory driving second MOT 81 are directly controlled by the driver 564 of the effect control device 550 via the relay board 600, the process of interposing the I ² CI / O expander 615 is not performed. .

  In the first embodiment of the present invention, the accessory driving first MOT 71 and the accessory driving second MOT 81 are included in the movable effect device 58. Specifically, the accessory driving first MOT 71 is the first effect unit 63, The object driving second MOT 81 is included in the second effect unit 64.

  The effect control device 550 controls the first and second effect units driving MOT 71 and second MOT 81 to cause the first effect unit 63 and the second effect unit 64 to perform an effect operation.

The first master IC 570a designates an address individually assigned to the decoration control device 610 that controls the decoration device 620 to be controlled, and outputs the control contents of the decoration device 620 to the decoration control device 610 of the designated individual address. To do. The individual address of the decoration control device 610 is precisely the individual address of the I ² CI / O expander 615 (see FIG. 17) included in the decoration control device 610.

  The first master IC 570a is connected to a relay board (decoration control device) via seven types of connection lines: a connection line SDA, a connection line SCL, a connection line GND, a connection line Vcc, a connection line Vled, a connection line Vms, and a connection line Vse. ) 600. These connection lines are configured by a cable 91 (see FIG. 8) that connects the first master IC 570a and the relay substrate 600.

  Connection line SDA is a connection line for communicating data between effect control device 550 and decoration control device 610, and functions as a data line in the first embodiment of the present invention. The connection line SCL is a connection line for inputting / outputting a clock signal used for data communication on the connection line SDA, and functions as a timing signal line in the first embodiment of the present invention. The connection line GND is a ground of the power supplied by the connection line Vcc, the connection line Vled, the connection line Vms, and the connection line Vse.

  The connection line Vcc is a connection line for supplying logic power to the relay board 600 and the decoration control device 610. The connection line Vled is a connection line for supplying power for causing the LED (decoration device 620) to emit light. The connection line Vms is a connection line for supplying power to the motors and solenoids (specifically, the accessory driving first MOT 71 and the accessory driving second MOT 81) included in the auxiliary gaming device unit 12. The connection line Vse is a connection line for supplying power to various sensors (a state detection sensor that detects the state of the motor included in the rendering device, and specifically corresponds to the motor position detection sensor 560a). is there.

  Between the relay board 600 and the auxiliary gaming device unit 12, seven types of connection lines that connect the effect control device 550 and the relay board 600 are connected. In the first embodiment of the present invention, the motor position detection sensor 560a, the accessory driving first MOT 71, and the accessory driving second MOT 81 are directly controlled by the relay board 600. Therefore, among the seven types of connection lines described above, Five types of connection lines other than the connection line Vms and the connection line Vse are connected to the decoration control device 610 disposed in the uppermost stream of the auxiliary gaming device unit 12. Specifically, a connection line Vcc, a connection line Vled, a connection line SDA, a connection line SCL, and a connection line GND are connected between the relay board 600 and the decoration control device 610.

  When the wiring (cable) shown in FIG. 8 is associated with each connection line, various connection lines (connection line Vcc, connection line Vled, connection line SDA, connection line SCL) delivered from the effect control device 550 to the relay board 600 are provided. , Connection line Vms, connection line Vse, and connection line GND) are included in the cable 91.

  These various connection lines are further branched from the relay board 600 and delivered to another board. The connection line Vcc, the connection line Vled, the connection line SDA, and the connection line SCL branched from the relay board 600 are connected to the cable 653. The connection line Vms is included in the cable 652, and the connection line Vse is included in the cable 651. Further, the connection line GND branched from the relay board 600 is included in all the cables 651 to 653.

  The first master IC 570a and the decoration control device 610 perform two-line bidirectional communication using the connection line SDA and the connection SCL. The first master IC 570a functions as a (first) signal level control means for controlling each signal level of the connection line SDA and the connection line SCL connected to the decoration control device 610 based on a command from the CPU 551. To do.

  When transmitting data to the relay board 600 and the decoration control device 610, the first master IC 570a first changes the signal level of the connection line SDA from HIGH to LOW while maintaining the signal level of the connection line SCL at HIGH. As a result, a start condition for starting data output to the decoration control device 610 is satisfied (a start condition is issued (output) to the decoration control device 610).

  Thereafter, the first master IC 570a changes the signal level of the connection line SCL to LOW, and sets the signal level of the connection line SDA to the level of the first bit of the transmission data while the signal level of the connection line SCL is LOW. Then, after a predetermined time, the signal level of the connection line SCL is changed from LOW to HIGH. When the signal level of the connection line SCL changes to HIGH, the decoration control device 610 acquires the signal level of the connection line SDA and recognizes it as the first bit of the transmission data. Next, the first master IC 570a returns the signal level of the connection line SCL from HIGH to LOW.

  When this procedure is executed once, 1-bit data is transmitted from the first master IC 570a to the decoration control device 610. Finally, this procedure is repeated 8 times, so that all 8 bits of the transmission data are transferred to the first master. The data is transmitted from the IC 570a to the decoration control device 610 (1 byte of data is transmitted).

  Then, when the data transmission of the last 8 bits is completed, the first master IC 570a releases the connection line SDA and returns a response from the decoration control device 610 when the signal level of the connection line SCL is returned from HIGH to LOW. A reception standby state in which a signal is received is set.

  In the reception standby state, the decoration control device 610 returns a 1-bit response signal (ACK or NACK described later) to the first master IC 570a via the connection line SDA. Next, when the first master IC 570a changes the signal level of the connection line SCL from LOW to HIGH to capture the level of the response signal, and changes the signal level of the connection line SCL from HIGH to LOW after a predetermined time, the decoration control device 610 releases the connection line SDA.

  The first master IC 570a alternately repeats the data transmission for 1 byte and the reception of the response signal for 1 bit, and continues until all the data to be output to the decoration control device 610 is output. When the output of data to be output is completed, the first master IC 570a changes the signal level of the connection line SDA from LOW to HIGH while maintaining the signal level of the connection line SCL at HIGH, thereby controlling the decoration. A stop condition for ending data output to the device 610 is established (a stop condition is issued to the decoration control device 610).

  The input buffer 571 is a storage device that temporarily stores data input from the decoration control device 610 via the connection line SDA.

  Specifically, when the first master IC 570a is set to the input mode, the data transmitted from the decoration control device 610 to the first master IC 570a is temporarily removed to the input buffer 571 after the noise is removed by the filter 575a. Is remembered.

  The output buffer 572 temporarily stores data output to the decoration control device 610 via the connection line SDA.

  The reset register (REG) 573 is connected to the bus 563, receives a command from the CPU 551 of the effect control device 550, and outputs a reset signal to the controller 574. The controller 574 comprehensively controls the first master IC 570a and executes various processes.

  The filter 575a removes noise from data input from the connection line SDA. When the driver 576a outputs data from the connection line SDA, the driver 576a applies a voltage at which the transistor 578a can operate to the transistor 578a.

  A predetermined voltage is applied to the connection line SDA by a pull-up resistor R (see FIG. 21), and the connection line SDA is connected to the filter 575a and the transistor 578a.

  As the transistor 578a, a field effect transistor (FET) is used in order to suppress power consumption. The gate of the transistor 578a is connected to the driver 576a, the drain is connected to the connection line SDA to which a predetermined voltage is applied by the pull-up resistor R, and the source is grounded.

  If the voltage applied to the gate of the transistor 578a is smaller than a predetermined value for operating the transistor 578a, no current flows between the drain and the source, so that the voltage applied to the connection line SDA does not drop, and as a result The connection line SDA becomes HIGH level. On the other hand, if the voltage applied to the gate of the transistor 578a is equal to or higher than a predetermined value for operating the transistor 578a, a current flows from the drain to which the voltage of the predetermined value is applied to the grounded source. As a result, the connection line SDA becomes LOW level.

Note that the transistor 578a has a specification that does not break even when a current of about 10 milliamperes flows from the drain to the source. For this reason, it is possible to flow a current of about 10 milliamperes, which is much larger than the current value used when using a normal I ² C bus, to the connection line SDA, and the effect control device 550 and the decoration control device 610 The data transmission between them is configured to withstand failures due to noise.

  When the driver 576a outputs data from the connection line SDA, the driver 576a applies a voltage having a value at which the transistor 578a can operate to the gate of the transistor 578a so that a current flows between the drain and the source of the transistor 578a. Then, the driver 576a outputs data from the connection line SDA by setting the voltage of the connection line SDA to the HIGH level or the LOW level.

  Further, the filter 575b removes noise from data input from the connection line SCL. When the driver 576b outputs data from the connection line SCL, the driver 576b applies a voltage at which the transistor 578b can operate to the transistor 578b.

  A predetermined voltage is applied to the connection line SCL by the pull-up resistor R (see FIG. 21), and the connection line SCL is connected to the filter 575b and the transistor 578b.

  A field effect transistor (FET) is used as the transistor 578b in order to reduce power consumption. The gate of the transistor 578b is connected to the driver 576b, the drain is connected to the connection line SCL to which a predetermined voltage is applied by the pull-up resistor R, and the source is grounded.

  If the voltage applied to the gate of the transistor 578b is smaller than a predetermined value for operating the transistor 578b, no current flows between the drain and the source, so that the voltage applied to the connection line SCL does not drop, and as a result The connection line SCL becomes HIGH level. On the other hand, if the voltage applied to the gate of the transistor 578b is equal to or higher than a predetermined value for operating the transistor 578b, a current flows from the drain to which the predetermined voltage is applied to the grounded source, whereby the connection line SCL As a result, the connection line SCL becomes the LOW level.

Note that the transistor 578b has a specification that does not break even when a current of about 10 milliamperes flows from the drain to the source. Therefore, a current of about 10 milliamperes, which is much larger than the current value used when using the normal I ² C bus, can be passed through the connection line SCL, and between the effect control device 550 and the decoration control device 610. The data transmission is configured to withstand failures due to noise.

  When the driver 576b outputs a clock signal from the connection line SCL, the driver 576b applies a voltage having a value at which the transistor 578b can operate to the gate of the transistor 578b so that a current flows between the drain and the source of the transistor 578b. Then, the driver 576b outputs a clock signal from the connection line SCL by repeatedly changing the voltage of the connection line SCL between a HIGH level and a LOW level.

  The power-on reset circuit 577 defaults storage areas such as the input buffer 571 and the output buffer 572 when the first master IC 570a is powered on and the voltage in the power-on reset circuit 577 reaches a predetermined value. A reset signal for setting the state is output to the controller 574. The power-on reset circuit 577 may be provided outside the first master IC 570a and shared with the second master IC 570b described later.

  The command register (REG) 581 is a register for receiving a command from the CPU 551 of the effect control device 550. In the first embodiment of the present invention, each bit of STA, STO, SI, and MODE is pre-assigned to the command register 581, and “0” or “1” is individually assigned to each bit by the CPU 551. Can be set.

  The STA is a bit for the first master IC 570a to instruct the decoration control device 610 to be controlled to output a start condition (start condition). When “1” is set in the STA, the first master IC 570a issues (outputs) a start condition to the decoration control device 610 to be controlled to establish the start condition.

  The STO is a bit for the first master IC 570a to instruct the decoration control device 610 to be controlled to output a stop condition (stop condition). When “1” is set in the STO, the first master IC 570a issues (outputs) a stop condition to the decoration control device 610 to be controlled to establish the stop condition.

  SI is a bit that is set when an interrupt is generated in the effect control device 550 from the first master IC 570a. When an interrupt is generated from the first master IC 570 a to the CPU 551, “1” is set to SI by the controller 574 and an interrupt signal (INT) is input to the CPU 551. Thereafter, while the SI is set to “1”, the first master IC 570a suspends processing. However, when the CPU 551 sets SI to “0”, the first master IC 570a interrupts. Suspend and resume processing.

  MODE is a bit for designating a mode for transmitting data, and “buffer mode” is designated when “1” is set, and “byte mode” is designated when “0” is set. . The buffer mode is a mode for transmitting a plurality of continuous bytes of data at a time and transmitting a maximum of 68 bytes of data. The byte mode is a mode in which only one byte of data can be transmitted in one transmission, and is used for data transmission / reception in units of bytes.

  The status register (REG) 582 stores information indicating the status of the first master IC 570a. “0” is always set in the lower 2 bits, and the status code is set in the upper 5 bits.

  The own address setting register (REG) 583 is a register that is set when the first master IC 570a functions as a slave (decoration control device). A commercially available master IC usually has a function as a master and a function as a slave, and is used according to the application. In the own address setting REG 583, an address for specifying itself when the first master IC 570a functions as a slave is set.

  FIG. 12 is a block diagram showing the configuration of the second master IC 570b provided in the effect control device 550 and the effect device provided in the front frame 3 according to the first embodiment of the present invention.

  The front frame 3 includes a simple relay board 1600 connected to the second master IC 570b, a decoration control device 610 connected to the simple relay board 1600, a speaker 30, a motor position detection sensor 560b, an illumination drive first MOT 13a, and an illumination drive first. 2MOT 14a and the like are included.

The simple relay board 1600 transmits (relays) the electrical signal transmitted from the second master IC 570 b to the decoration control device 610 provided in the front frame 3. Unlike the relay board 600, the simple relay board 1600 does not include the I ² CI / O expander 615. Therefore, the electronic component provided in the simple relay board 1600 includes arithmetic processing for controlling the effect device. Does not have a function to execute. Therefore, since the illumination driving first MOT 13a and the illumination driving second MOT 14a that are directly connected to the simple relay board 1600 cannot be controlled by their own judgment, the simple relay board 1600 receives the electric signal received from the second master IC 570b. Thus, it plays a role of relaying to the illumination driving first MOT 13a and the illumination driving second MOT 14a.

  The illumination drive first MOT 13a and the illumination drive second MOT 14a drive the light emitting member provided inside based on the signal transmitted from the effect control device 550, and execute various effects.

  In addition, the effect control device 550 receives a signal indicating that the effect button 17 has been operated from the effect button 17 via the simple relay board 1600. Further, the position information of the illumination drive first MOT 13 a and the illumination drive second MOT 14 a detected by the motor position detection sensor 560 b is input via the simple relay board 1600.

  Further, the simple relay board 1600 receives a signal from the sound LSI 557 of the effect control device 550 and outputs it from the speaker 30.

  Since the configuration of the second master IC 570b is the same as that of the first master IC 570a, the same reference numeral is assigned to each configuration of the second master IC 570b, and description thereof is omitted. Similarly to the first master IC 570a, the second master IC 570b controls the signal levels of the connection line SDA and the connection line SCL connected to the decoration control device 610 based on a command from the CPU 551 ( It functions as a second) signal level control means.

  The connection method between the effect control device 550 and the relay board 600 and the connection method between the relay board 600 and the decoration control device 610 other than the relay board 600 will be described in detail later with reference to FIGS. The configuration of the relay board 600 and the decoration control device 610 will be described in detail later with reference to FIGS.

  The decoration control device 610 is mainly attached to the game board 10 and the front frame 3. The decoration device (LED) 620 controlled by the decoration control device 610 attached to the front frame 3 irradiates the decoration members 9a and 9b, the illumination unit 11, and the abnormality notification LED 29. On the other hand, the decoration control device 610 attached to the game board 10 is included in the auxiliary game device unit 12 configured by integrating the center case 51, the display device 53, and the effect control device 550.

  In FIG. 13, a configuration and connection form of the decoration control device 610 included in the relay board 600 and the auxiliary game device unit 12 provided in the game board 10 will be described. In FIG. 14, configurations and connection forms of the simple relay board 1600 and the decoration control device 610 provided in the front frame 3 will be described.

  FIG. 13 is a diagram illustrating a configuration of the game board 10 according to the first embodiment of this invention.

  As described above, the center case 51 constituting the auxiliary gaming device unit 12 is configured by combining the frame decoration portion 65 and the frame base portion 60.

  The frame decoration unit 65 is provided with a plurality of effect devices for performing auxiliary games such as a variable display game, and a decoration control device 610 for controlling the effect devices. These decoration control devices 610 are connected to each other by a predetermined signal cable, and the effect device controlled by the decoration control device 610 is also connected by a cable, whereby the frame decoration portion 65 is integrally configured.

  The frame base 60 is also provided with a plurality of effect devices for performing an auxiliary game such as a variable display game, and a plurality of decoration control devices 610 for controlling the effect devices. By connecting these decoration control devices 610 to each other by a predetermined signal cable, and also connecting the effect device controlled by the decoration control device 610 with a cable, the frame base 60 is integrally configured.

  Therefore, the frame decoration part 65 and the frame base 60 constitute an integrated production unit in the present embodiment. On the other hand, since the side lamps 45 and the like are single production devices that are not included in the integrated production unit, they constitute a separate production device.

  Note that not all of the effect devices included in the auxiliary gaming device unit 12 need be controlled by the decoration control device 610 inside the auxiliary gaming device unit 12. For example, in the first embodiment of the present invention, the movable object arranged in the center case 51 is directly controlled by the effect control device 550 via the relay board 600.

The decoration controller 610, as described above, is mounted I ² CI / O expander 615 for controlling the decoration device 620, the I ² CI / O expander 615, individual I ² CI / O An individual address for identifying the expander 615 is assigned. In the first embodiment of the present invention, as described above, the individual address of the I ² CI / O expander 615 is used as the individual address of the decoration control device 610.

The effect control device 550 can execute the effect operation by individually controlling the decoration device 620 by designating the individual address of the I ² CI / O expander 615 and transmitting the control signal. In principle, different individual addresses (indicated by “ad =” in the figure) are assigned to the respective decoration control devices 610.

  Further, the decoration control device 610 is classified into three types according to a connection form: a branch type (branch substrate), a connection type (connection substrate), and a termination type (termination substrate). The decoration device 620 can be connected to any one of the branch type, the connection type, and the terminal type decoration control device 610, and the connected decoration device 620 can be controlled.

  In the branch type decoration control device 610, a plurality of decoration control devices 610 are directly connected to the downstream side, and the received control signals are transmitted to the plurality of decoration control devices 610. The connected decoration control device 610 is connected to one decoration control device 610 on the downstream side, and transmits the received control signal to the connected decoration control device 610. The terminal-type decoration control device 610 does not connect the decoration control device 610 on the downstream side, and only controls the decoration device 620. Details of the branch type, connected type, and terminal type decoration control device 610 will be described later with reference to FIG.

  The upstream side refers to the side that transmits the electrical signal in the configuration in which the electrical signal is transmitted from the effect control device 550 to the terminal decoration control device 610 through the decoration control device 610 on the way. On the other hand, the downstream side is the side that receives this electrical signal.

  In short, when the signal cable from the production control device 550 to the decoration control device 610 at the end is traced in order, the decoration control device 610 connected to the side closer to the production control device 550 becomes the upstream side, and more terminal. The decoration control device 610 connected to the side closer to the decoration control device 610 is the downstream side. For example, the decoration control devices 610A and 610C are arranged on the upstream side of the decoration control device 610H, and the decoration control devices 610I and 610J are arranged on the downstream side of the decoration control device 610H.

  Here, in the first embodiment of the present invention, as described above, the decoration control device 610 is arranged on the movable parts of the first effect member 70 and the second effect member 80 that constitute the movable effect device 58. . In other words, in FIG. 6, the decoration control device 610 (first light emitting substrate 106) is disposed on the movable part (first effect base 100) of the first effect member 70, and in FIG. 7, the movable part of the second effect member 80. The decoration control device 610 (second light emitting substrate 116) is disposed on the (second effect base 110).

  At this time, if each decoration control device 610 is wired in a daisy chain as in a conventional shift register, only one of the decoration control devices 610 at the end of the daisy chain can be connected only by an input cable. That's it. However, it is necessary to connect an input cable and an output cable to the other decoration control device 610 configured to be connected in the middle of the daisy chain. When a plurality of cables are connected to the movable part, the decoration control device 610 (the first light emitting board 106 and the second light emitting board 116) itself moves together with the movable part, and the cable also moves. It can be difficult. Furthermore, the movement of the cable may cause a disconnection of the connection line constituting the cable, which may affect the production.

  In the first embodiment of the present invention, the decoration control device 610 disposed in the first effect member 70 and the second effect member 80 is a terminal type, and a branch type decoration control device is provided upstream of these decoration control devices 610. 610 is arranged. Therefore, the terminal-type decoration control device 610 (the first light-emitting board 106 and the second light-emitting board 116) sends a signal to the other decoration control devices 610 provided outside the first effect member 70 and the second effect member 80. The transmitting cable is not connected. If the decoration control device 610 is arranged in this way, only the input cable needs to be connected to the decoration control device 610 arranged in the movable part. Therefore, the wiring can be easily routed and the possibility of disconnection can be reduced as compared with the case of wiring by daisy chain.

  When the destination address of the received control signal is not addressed to itself, the decoration control device 610 transmits the received control signal if the decoration control device 610 is further connected to the downstream side. If there is no transmission destination, the received control signal is discarded.

The decoration control device 610 can control the LEDs corresponding to the 16 ports. The decoration control device 610 includes an LED mounted on the decoration control device 610 and an external decoration device substrate 625 connected to the decoration control device 610. If the total number of mounted LEDs is 16 or less, both LEDs can be controlled. In other words, in the integrated decoration control device 610 (corresponding to the main active substrate on which both the I ² CI / O expander 615 and the decoration device 620 are arranged), the decoration device substrate 625 (the I ² CI / O expander 615 is arranged). In addition, it is possible to control both the decoration device 620 provided inside and the decoration device 620 connected to the outside by further connecting a driven substrate on which the decoration device 620 is disposed.

  By doing so, it is possible to control the decoration devices 620 arranged at a distance by one decoration control device 610, and the number of decoration control devices 610 can be minimized.

The relay board 600 is connected to the first master IC 570a mounted on the effect control device 550 on the upstream side, and receives a control signal transmitted from the first master IC 570a. Further, on the downstream side, it is connected to a decoration control device 610A included in the auxiliary gaming device unit 12 (more precisely, a decoration control device 610A included in the frame base 60 which is an integrated production unit). Further, the relay board 600 is connected to a decoration device board 625 (a board provided on the side lamp 45 (see FIG. 8)) which is a separation type effect device provided in the game board 10, and is provided in the relay board 600. The decoration device 620 mounted on the decoration device substrate 625 is controlled by the I ² CI / O expander 615.

  The auxiliary gaming device unit 12 includes decoration control devices 610A to 610J. The decoration control device 610A is a branch type decoration control device, and transmits the control signal received from the first master IC 570a to the decoration control device 610B and the decoration control device 610C. In addition, a decoration device substrate 625B is connected to the decoration control device 610B, and an effect device (decoration device 620) such as an LED disposed on the decoration device substrate 625B is controlled by the decoration control device 610B.

  The decoration control device 610C is a branch type decoration control device 610, and transmits the received control signal to the decoration control device 610D and the decoration control device 610H on the downstream side. The decoration control device 610D is connected to a branch type decoration control device 610E, and further controls the decoration device 620D included in the decoration device substrate 625D.

  The decoration control device 610E is connected to a decoration control device 610F that controls the first effect member 70 and a decoration control device 610G that controls the second effect member 80. The first effect member 70 and the second effect member 80 perform an effect operation in conjunction with each other. The decoration control device 610F is disposed on the first light emitting substrate 106 included in the first effect member 70 (FIG. 6), and the decoration control device 610G is disposed on the second light emitting substrate 116 included in the second effect member 80. (FIG. 7).

  The first light emitting substrate 106 itself may function as the decoration control device 610F, and the second light emitting substrate 116 itself may function as the decoration control device 610G.

  In the first embodiment of the present invention, the decoration control device 610F controls the LEDs included in the first effect member 70, and the decoration control device 610G controls the LEDs included in the second effect member 80. Note that the accessory driving first MOT 71 and the accessory driving second MOT 81 for outputting the driving force for moving the first effect member 70 and the second effect member 80 to the front of the display unit 53a are controlled by the relay board 600. Is done.

  The effect control device 550 controls the first effect unit 63 (the first effect member 70) and the second effect unit 64 (the second effect member 80) when the predetermined condition is satisfied, such as when the variable display game is executed. Perform the action. Specifically, in order to control the accessory driving first MOT 71 included in the first effect unit 63 and the accessory driving second MOT 81 included in the second effect unit 64, the individual address (“0000”) of the relay board 600 is set. Designate and send control signals to operate these motors. Furthermore, a control signal for controlling a light emitting device such as an LED included in the first effect member 70 is transmitted by designating the individual address (“0110”) of the decoration control device 610F for controlling the first effect member 70. Similarly, a control signal for controlling a light emitting device such as an LED included in the second effect member 80 is transmitted by designating the individual address (“0111”) of the decoration control device 610G for controlling the second effect member 80. After that, issue a stop condition.

  The decoration control device 610H is a connection type decoration control device 610, and is further connected to a connection type decoration control device 610I and a terminal type decoration control device 610J. The terminal-type decoration control device 610J controls the decoration device 620J included in the decoration device substrate 625J.

  In the first embodiment of the present invention, the decoration control device 610H and the decoration control device 610I control an effect device (LED) included in the reliability notification device 15. When the predetermined condition is satisfied, a control signal for indicating a predetermined mode is transmitted from the first master IC 570a of the production control device 550, and the production is performed in the designated mode.

  FIG. 14 is a diagram illustrating a configuration of the front frame 3 according to the first embodiment of this invention.

  The gaming machine 1 according to the first embodiment of the present invention has a plurality of specifications, and there are a normal version gaming machine 1 and an inexpensive version gaming machine 1. The normal version gaming machine 1 includes a front frame 3 (hereinafter, referred to as a normal version front frame 3) having a standard decorative member. The low-priced gaming machine 1 includes a front frame 3 (hereinafter referred to as a low-priced front frame 3 ') that includes a decorative member configured at a lower cost than a standard decorative member. The upper side of FIG. 14 shows the configuration of the normal version front frame 3, and the lower side shows the configuration of the inexpensive version front frame 3 ′. In the gaming machine 1, only the front frame 3 of one of the specifications is shown. Is attached and connected to the production control device 550, so that either the normal version front frame 3 or the inexpensive version front frame 3 ′ is connected to the second master IC 570b.

  The normal plate front frame 3 and the inexpensive plate front frame 3 ′ are different in the number of decoration devices 620 included in the decoration members 9 a and 9 b, and also in the number of decoration control devices 610 that control the decoration device 620. Specifically, the decoration members 9a and 9b of the normal plate front frame 3 are controlled by seven decoration control devices 610, and the decoration members 9a 'and 9b' of the inexpensive plate front frame 3 'are controlled by five decoration control devices 610. Is done. Since the decorative members 9a and 9b irradiate with more LEDs than the decorative members 9a ′ and 9b ′, the normal plate front frame 3 becomes brighter than the inexpensive plate front frame 3 ′, which increases the variation of executable effects. It is also possible. Therefore, the control of the decoration device 620 when the normal plate front frame 3 is attached is different from the control of the decoration device 620 when the inexpensive plate front frame 3 ′ is attached.

  For this reason, when the same address is assigned to the individual address of the decoration control device 610 attached to the normal plate front frame 3 and the individual address of the decoration control device 610 attached to the inexpensive plate front frame 3 ′, the effect control device 550 Since the production control data to be transmitted to the decoration control device 610 needs to be different between the case of the normal version front frame 3 and the case of the inexpensive version front frame 3 ′, it is usually determined according to the front frame 3 attached to the gaming machine 1. The production control device 550 for the plate and the production control device 550 for the low cost version must be prepared. Therefore, when the manufacturer ships the gaming machine 1, the production control device 550 for the normal version and the production control device 550 for the low-priced version must be prepared, resulting in an increase in manufacturing cost.

  Therefore, in the first embodiment of the present invention, different addresses are assigned to the individual addresses of the decoration control device 610 whose control is different between the normal version front frame 3 and the low price version front frame 3 ′. The effect control data to be transmitted to the decoration control device 610 is configured so as to be common to the case of the normal version front frame 3 and the case of the low cost version front frame 3 ′, so that one effect control device 550 is used for the normal version. And control for the low cost version can be executed. By doing so, it is not necessary to prepare the production control device 550 for the normal version and the production control device 550 for the low-priced version, and the manufacturing cost can be suppressed. In the first embodiment of the present invention, the game board 10 has the same configuration regardless of whether it is a normal version or a low-priced version.

  Hereinafter, the configurations of the normal plate front frame 3 and the inexpensive plate front frame 3 'will be described in detail.

  The normal plate front frame 3 includes a simple relay board 1600 connected to the second master IC 570b. A branch type decoration control device 610K and illumination drive motors (13a, 14a) are connected to the simple relay board 1600.

  The decoration control device 610K is arranged in the lighting unit 11 and controls the decoration device 620 provided on the decoration device substrate 625K. Specifically, the LED included in the illumination unit 11 and the abnormality notification LED 29 are controlled.

  The decoration control device 610K is a branch type decoration control device, and transmits the received control signal to the decoration control device 610L and the decoration control device 610P. The decoration control devices 610 </ b> L to 610 </ b> N control the decoration member 9 a on the left side portion of the normal plate front frame 3. Further, the decoration control devices 610P to 610R control the decoration member 9b on the right side portion of the normal plate front frame 3.

  The decoration member 9a on the left side portion of the normal plate front frame 3 includes connection type decoration control devices 610L and 610M and a terminal type decoration control device 610N. The decoration control device 610L receives the control signal transmitted from the second master IC 570b of the effect control device 550 from the decoration control device 610K and transmits it to the decoration control devices 610M and 610N.

  As described above, the decoration member 9b on the right side portion of the normal plate front frame 3 includes the connection type decoration control devices 610P and 610Q and the terminal type decoration control device 610R. The decoration control device 610P receives the control signal transmitted from the second master IC 570b of the effect control device 550 from the decoration control device 610K and transmits the control signal to the decoration control devices 610Q and 610R.

  Also, different individual addresses are assigned to the decoration control devices 610L to 610R included in the decoration member 9a and the decoration member 9b, and different rendering operations are performed based on the control signals transmitted from the second master IC 570b. Can be executed. Specifically, “0000” is used for the individual address of the decoration control device 610K included in the lighting unit 11, and “0001” “0010” is used for the individual addresses of the decoration control devices 610L, 610M, and 610N included in the decoration member 9a. “001”, “0100”, “0101”, and “0110” are assigned to the individual addresses of the decoration control devices 610P, 610Q, and 610R included in the decoration member 9b.

  On the other hand, the low-priced front frame 3 ′ is similar to the normal plate front frame 3 in that the simple relay board 1600 connected to the second master IC 570 b and a board having substantially the same function (hereinafter referred to as the low-priced simple relay board 1600). 'And). However, in the low-priced front frame 3 ', only the branch type decoration control device 610S is connected to the simple relay board 1600', and the cost is reduced without the illumination drive motors (13a, 14a).

  The decoration control device 610S is disposed in the lighting unit 11, and controls the decoration device 620 provided on the decoration device substrate 625S. Specifically, the LED included in the illumination unit 11, the abnormality notification LED 29, and the like are controlled and are the same as those of the normal plate front frame 3. The decoration control device 610S is the same substrate as the decoration control device 610K that controls the illumination unit 11 of the normal plate front frame 3, and is assigned the same individual address (“0000”). Therefore, the same control is executed in the decoration control device 610K of the normal plate front frame 3 and the decoration control device 610S of the inexpensive plate front frame 3 '.

  The decoration control device 610S is a branch type decoration control device, and transmits the received control signal to the decoration control device 610T and the decoration control device 610V. The decoration control devices 610T and 610U control the decoration member 9a 'on the left side portion of the normal plate front frame 3. Further, the decoration control devices 610V and 610W control the decoration member 9b 'on the right side portion of the normal plate front frame 3.

  Further, in the inexpensive plate front frame 3 ', decoration control devices 610T and 610U for controlling the left decoration member 9a' and decoration control devices 610V and 610W for controlling the right decoration member 9b 'are attached. The decoration control device 610T is the same substrate as the decoration control device 610L of the normal plate front frame 3, and is assigned the same individual address (“0001”). Similarly, the decoration control device 610V is the same substrate as the decoration control device 610P of the normal plate front frame 3, and is assigned the same individual address (“0001”). Therefore, the same control is executed in the decoration control device 610L of the normal plate front frame 3 and the decoration control device 610T of the inexpensive plate front frame 3 ′, and the decoration control device 610P of the normal plate front frame 3 and the inexpensive plate front frame 3 are controlled. In the 'decoration control device 610V, the same control is executed.

  The same individual address (“0111”) is assigned to the decoration control devices 610U and 610W. Therefore, in the low-price front frame 3 ′, the same control is executed by the decoration control devices 610 </ b> U and 610 </ b> W with the left and right decoration members, that is, the irradiation by the controlled LED is executed at the same timing. In addition, the decoration control devices 610U and 610W are assigned individual addresses that are not assigned to the decoration control device 610 of the normal front frame 3.

And even if it is a case where it is used for any of the normal version front frame 3 and the inexpensive plate front frame 3 ′, the decoration control device included in the decoration members 9a, 9b, 9a ′, 9b ′ is provided from the effect control device 550. Production control data is transmitted to all individual addresses assigned to the I ² CI / O expander 615 of 610.

  As described above, the low price front frame 3 'corresponds to the decoration control devices 610M, 610N, 610Q and 610R (first specification-dependent group unit control means) among the decoration control devices provided. Instead, decoration control devices 610U and 610W (second specification-dependent group unit control means) are attached. The normal plate front frame 3 is equipped with decoration control devices 610M, 610N, 610Q and 610R (first specification-dependent group unit control means), whereas the inexpensive plate front frame 3 ′ has fewer. A number of decoration control devices 610U and 610W (second specification-dependent group unit control means) are attached.

  The decoration control device 610K and the decoration control device 610S, the decoration control device 610L and the decoration control device 610T, and the decoration control device 610V and the decoration control device 610P are common to the normal plate front frame 3 and the inexpensive plate front frame 3 ′. It is configured as a usable substrate.

  Therefore, the production control device 550 according to the first embodiment of the present invention can share the control for the normal version and the control for the inexpensive version, and there is no need to change the control for each front frame. The manufacturing cost of the production control device 550 can be reduced.

  In the following description, unless otherwise specified, it is assumed that the normal version front frame is attached to the gaming machine 1 according to the first embodiment of the present invention.

In the low price front frame 3 ′, the I ² CI / O expander 615 with individual addresses “0010”, “0011”, “0101” and “0110” is not used. The I ² CI / O expander 615 whose individual address is “0111” is not used. Therefore, in any front frame 3, there is an unconnected I ² CI / O expander 615 in the abnormality determination table 3300 (see FIG. 33). However, as will be described later, if data is normally transmitted between at least one I ² CI / O expander 615 registered in the abnormality determination table 3300 and the second master IC 570b, Since it is determined to be operating, the process is not interrupted due to this.

  FIG. 15 is a diagram illustrating a connection state between the effect control device 550 and the relay board 600 and the decoration control device 610 included in the game board 10 according to the first embodiment of this invention.

  In FIG. 15, connection of the effect control device 550, the relay board 600, and the decoration control devices 610A, 610B, and 610C will be described. For convenience of explanation, description of the decoration control device 610 is omitted for one relay board 600 and each decoration control device (610D to 610J) connected downstream from the decoration control device 610C. The connection between the decoration control devices 610 is the same.

  The production control device 550 includes a connection line Vcc, a connection line Vled, a connection line SDA, a connection line SCL, a connection line GND, connection lines M11 to M14, connection lines M21 to M24, connection lines M31 to M34, a connection line SL1, and a connection line. The relay board 600 is connected by SL2, the connection lines SE1 to 3, the connection line Vms, and the connection line Vse.

  The connection line Vcc, the connection line Vled, the connection line SDA, the connection line SCL, the connection line GND, the connection line Vms, and the connection line Vse are as described in FIG.

  Signals for controlling the first to fourth phases of the accessory driving first MOT 71 included in the first effect unit 63 are transmitted to the connection lines M11 to M14. Signals for controlling the first to fourth phases of the accessory driving second MOT 81 included in the second effect unit 64 are transmitted to the connection lines M21 to M24. The accessory driving first MOT 71 and the accessory driving second MOT 81 use a four-phase driving stepping motor.

  The connection lines M31 to M34 are connection lines for controlling the motor. However, in the first embodiment of the present invention, since the motor corresponding to the relay board 600 is not connected, an empty terminal monitor that displays the connection state. 603 is connected. The vacant terminal monitor 603 includes four LEDs corresponding to the connection lines M31 to M34, and can check whether or not each connection line is disconnected. Therefore, when some or all of the connection lines are disconnected, a part of the vacant terminal monitor 603 is not lit, so that it can be determined that the quality of the cable is bad.

  In particular, as in the gaming machine 1 according to the first embodiment of the present invention, the cable 91 that connects the first master IC 570a and the relay board 600 has a connection line GND, a connection line Vcc, The connection line Vled, the connection line Vms, and the connection line Vse are included (see FIG. 11 or FIG. 15). These wires for supplying electric power are originally used as cables having a large (thick) cross-sectional area that can secure a sufficient amount of current in order to realize a stable operation.

  However, when a flat cable such as the cable 91 is used, the cross-sectional area of each cable needs to be the same (common) because of the connection of the connectors. Therefore, it is conceivable to supply power using a plurality of connection lines instead of a cable having a large cross-sectional area. For example, six cables are used as the connection lines GND and three cables are used as the connection lines Vms. A configuration such as use can be realized.

  At this time, even if a part of the connection line for supplying power is disconnected, if all the connection lines are not disconnected, it will operate without any problem, so that the LED is turned on, Although it is possible to drive the motor, since a sufficient amount of current cannot be secured, abnormal heat generation may occur on the cable. In such a case, by connecting a power supply line to the vacant terminal monitor 603, a cable with inferior quality such that some of the connection lines are disconnected even though it seems to be operating normally at first glance is discovered. It is possible to perform replacement or perform necessary maintenance before a failure occurs.

  In addition, the relay board 600 supplies the electric power supplied from the connection line Vms to each motor in order to drive the accessory driving motor (the accessory driving first MOT 71, the accessory driving second MOT 81). The electric power supplied to the accessory driving solenoid for moving the decoration piece 46 up and down is also supplied from the connection line Vms.

  The relay board 600 is connected to a motor position detection sensor 560a for detecting the rotational position of the accessory driving motor. Connection lines SE1 to SE3 are connection lines for receiving the detection result by the motor position detection sensor 560, and the relay board 600 indicates the rotation position of the accessory driving motor detected by the motor position detection sensor 560a. It transmits to production control device 550 via SE1-3.

  The connection line SL1 and the connection line SL2 are connection lines for controlling the accessory driving solenoid. When the accessory driving solenoid is not used, the connection line SL1 and the connection line SL2 are also connected to the vacant terminal monitor 603 for displaying the connection state, similarly to the connection lines M31 to M34 described above.

  The decoration control device 610 including the relay board 600 includes a connection line Vcc, a connection line Vled, a connection line SDA, a connection line SCL, and a connection line GND (hereinafter, a bundle of these five types of connection lines is referred to as one harness). Are connected to each other.

  In addition, a decoration control device 610B and a decoration control device 610C are connected to the decoration control device 610A via a harness, and a decoration control device 610D (not shown) is connected to the decoration control device 610C via a harness.

  Each decoration control device 610 includes a connector serving as an attachment port for connecting the harness to itself. Since this connector is common to each decoration control device 610, the connection order of each connection line is common, and erroneous wiring can be prevented.

  FIG. 16 is a diagram illustrating a connection state between the effect control device 550 according to the first embodiment of this invention, the simple relay board 1600 and the decoration control device 610 included in the normal plate front frame 3.

  In FIG. 16, connection of the effect control device 550, the simple relay board 1600, and the decoration control devices 610K, 610L, and 610P will be described. For convenience of explanation, the description of the decoration control devices 610L and the decoration control devices connected downstream of the decoration control device 610P will be omitted.

  The production control device 550 includes a connection line Vcc, a connection line Vled, a connection line SDA, a connection line SCL, a connection line GND, connection lines M11 to M14, connection lines M21 to M24, connection lines M31 to M34, a connection line SL1, and a connection line. In addition to the SL2, the connection lines SE1 to 3, the connection line Vms, and the connection line Vse, the connection line that receives the button signal from the effect button 17 and the connection line that transmits the sound signal to the speaker 30 are connected to the simple relay board 1600. The

  For the connection line Vcc, the connection line Vled, the connection line SDA, the connection line SCL, the connection line GND, the connection line Vms, and the connection line Vse, as described with reference to FIG. 15, the effect control device 550 and the game board 10 are connected. Similar to the case of connection, various signals are transmitted to and received from each decoration control device 610 arranged on the downstream side.

  Signals for controlling the illumination driving first MOT 13a of the first movable illumination 13 included in the illumination unit 11 are transmitted to the connection lines M11 to M14. Signals for controlling the illumination drive second MOT 14a of the second movable illumination 14 included in the illumination unit 11 are transmitted to the connection lines M21 to M24.

  The connection lines M31 to M34 are connection lines for controlling the motor. However, in the embodiment of the present invention, the corresponding motor is not connected to the simple relay board 1600. An empty terminal monitor 603 to be displayed is connected.

  Further, in order to drive the illumination drive motor (the illumination drive first MOT 13a and the illumination drive second MOT 14a), the electric power supplied from the connection line Vms is supplied to each motor.

  The simple relay board 1600 is connected to a motor position detection sensor 560b for detecting the rotation position of the illumination drive motor. The simple relay board 1600 transmits the rotation position of the illumination drive motor detected by the motor position detection sensor 560b to the effect control device 550 via the connection lines SE1 to SE3.

Here, a method in which the I ² CI / O expander 615 (described later in FIG. 18) provided in the decoration control device 610 controls the decoration device 620 will be described.

The effect control device 550 determines the output mode of the effect device (decoration device 620) based on the game data input from the game control device 500. Then, the production control device 550 produces production control data (production control) including the individual address of the decoration control device 610 to be controlled (the individual address of the I ² CI / O expander 615) so that the determined output mode is obtained. Information) is output to the relay board 600. At this time, the effect control data is output from the relay board 600 to all the decoration control devices 610 to be controlled through the connection line SDA.

  In the first embodiment of the present invention, the rendering device controlled by the decoration control device 610 is mainly a light emitting device such as an LED, and therefore the light emission mode of the LED corresponds to the output mode of the rendering device. In this case, lighting / flashing / extinguishing of the LED is instructed by the effect control data, and further, the flashing cycle and the lighting brightness of the LED are instructed.

Each decoration control device 610 is previously set with a unique individual address as described above. When the presentation control data is input, the address included in the input presentation control data and the set individual address It is determined whether or not. If it is determined that the address included in the input effect control data matches the set individual address, the I ² CI / O expander 615 of the decoration control device 610 captures the effect control data. Thus, the output mode of the corresponding decoration device 620 is controlled, and a response signal is output to the master IC (first master IC 570a, second master IC 570b) immediately after the 8th bit data is input.

  As described above, the master IC transmits the effect control data to all the decoration control devices 610 connected to the master IC, and requested in the decoration control device 610 corresponding to the individual address included in the effect control data. The rendering device can be controlled so as to be in the output mode.

Each decoration control device 610 is set with a reset address for initializing the I ² CI / O expander 615 of the decoration control device 610 in addition to the individual address. This reset address is an address provided in common to all the I ² CI / O expanders 615 and cannot be used as an individual address. The reset address value cannot be changed (details will be described later).

When the effect control device 550 initializes the decoration control device 610 (more precisely, the I ² CI / O expander 615 of the decoration control device 610), the effect control device 550 receives the initialization instruction data including the common address for resetting. And output to the relay board 600 or the simple relay board 1600. At this time, the initialization instruction data effect control data is output from the connection line SDA to all the decoration control devices 610 connected to the effect control device 550 via the relay substrate 600 or the simple relay substrate 1600.

Since a common address for reset is set in advance in each decoration control device 610, it is determined whether or not the address included in the input data matches the common address for reset. If it is determined that they match, the I ² CI / O expander 615 of the decoration control device 610 outputs a response signal to the master IC, takes in the input data as initialization instruction data, and outputs the I ² CI / O expander. The panda 615 itself is initialized.

When the I ² CI / O expander 615 is initialized, the rendering device controlled by the initialized I ² CI / O expander 615 is turned off.

As described above, the decoration control device 610 performs control based on a command from the effect control device 550, and therefore, the relationship between the effect control device 550 and the decoration control device 610 is the first master IC 570a of the effect control device 550 and the second master IC 570a. The master IC 570b is a master, and the I ² CI / O expander 615 of each decoration control device 610 is a slave.

  15 and 16, the control target of the decoration control device 610 other than the relay board 600 is a decoration device 620 that is a light emitting device such as an LED, but it is also possible to control a movable object such as a motor or a solenoid. It is. In this case, since the effect device serves as a drive source such as a motor or a solenoid, the operation mode of these drive sources corresponds to the output mode of the effect device. The effect control data includes an operation / stop instruction for the drive source, and it is also possible to specify the operation speed.

  Note that, even if the gaming machine 1 is provided with a low-priced front frame 3 ′ instead of the normal-price front frame 3, the connection state of various substrates included in the low-priced front frame 3 ′ is almost the same as FIG. It becomes the composition of.

  However, since the illumination drive motors (illumination drive first MOT 13a, illumination drive second MOT 14a) are not provided on the inexpensive plate front frame 3 ′, the illumination drive motor is connected to the inexpensive relay board 1600 ′. There is no connector, and the connection lines M11 to M14 and the connection lines M21 to M24 are not used. Therefore, in the low-price simple relay board 1600 ', the empty terminal monitor 603 is also connected to the connection lines M11 to M14 and the connection lines M21 to M24.

  Further, since the low-price front frame 3 'is not provided with the motor position detection sensor 560b, in the low-price simple relay board 1600', the connection lines SE1 to 3 are connected to the ground so that a signal of a certain level is obtained. However, it is configured such that it is always input to the production control device 550.

  FIG. 17 is a block diagram of the decoration control device 610 according to the first embodiment of this invention.

  As described above, the decoration control device 610 according to the first embodiment of the present invention is classified into three types: a branch type, a connection type, and a termination type, based on the connection form. FIG. 17 shows an example in which a terminal type decoration control device 610Y is connected to a branch type decoration control device 610X. Further, a decoration device substrate 625 is connected to the decoration control device 610Y.

The branch type decoration control apparatus includes an I ² CI / O expander 615, a connector (upstream connector) for receiving a signal received by the I ² CI / O expander 615, and a signal received from the upstream connector. A connector (downstream connector) for transmitting to a plurality of decoration control devices 610 is provided. For example, like the decoration control device 610X in the figure, an I ² CI / O expander 615 and an LED (decoration device 620) are provided inside, and further, one upstream connector 611 and two downstream connectors 612A and 612B are provided. .

The connection line SDA and the connection line SCL are branched into two in the decoration control device 610, and one is connected to the downstream connector 612B for output to the next decoration control device 610Y as it is. The other further branches, one connected to the I ² CI / O expander 615 and the other connected to another downstream connector 612A.

Further, a decoration device 620 to be controlled is connected to the output side of the I ² CI / O expander 615 of the decoration control device 610X. The output side of the I ² CI / O expander 615 includes ports 0 to 15 described with reference to FIG. Further, all the ports of the decoration control device 610 are connected to internal LEDs via current limiting resistors R0 to R15 described later in FIG. Note that the current control resistors R0 to R15 are also provided in the decoration control device 610.

As described above, the I ² CI / O expander 615 has an address included in the effect control data input from the effect control device 550 and an individual address set in the I ² CI / O expander 615. Only when they match, the decoration device 620 connected to the I ² CI / O expander 615 is controlled based on the decoration data included in the effect control data.

  Since only one downstream connector is provided, a decoration control device that can transmit a signal received from the upstream connector to only one decoration control device 610 is a connected decoration control device. For example, the decoration control device 610X described above includes only the downstream connector 612B and does not include the downstream connector 612A.

The terminal-type decoration control device has an I ² CI / O expander 615 and a connector (upstream connector) for receiving a signal received by the I ² CI / O expander 615. This signal is not transmitted to the other decoration control device 610. For example, the decoration control device 610Y in the figure includes an I ² CI / O expander 615 and an LED (decoration device 620), and allows a current to flow through the LED provided on the decoration device substrate 625 connected to the outside of the decoration control device 610Y. The decoration control device 610 and the decoration device substrate 625 are connected to each other through a connection line for supplying power to the LEDs of the decoration device substrate 625 and a connection wire grounded to the ground.

The decoration device substrate 625 is a substrate that does not include the I ² CI / O expander 615 but includes only a light emitting device such as an LED. In this case, the current limiting resistor connected to the LED provided on the decoration device board 625 is provided on the decoration device board 625, but is provided on the decoration control device 610 provided with the I ² CI / O expander 615. Also good.

It should be noted that the number of connection lines for passing current to these LEDs to be passed from the decoration control device 610 to the decoration device substrate 625 is determined in accordance with the number of LEDs provided on the decoration device substrate 625. . For example, when the decoration device substrate 625 includes two LEDs, two control lines for connecting the port of the I ² CI / O expander 615 and the corresponding LED, and power supplied from the Vled At least one power supply line is required.

The I ² CI / O expander 615 provided in the decoration control device 610Y is also set in the address included in the effect control data input from the effect control device 550 and the I ² CI / O expander 615. The decoration device 620 connected to the I ² CI / O expander 615 is controlled based on the decoration data included in the effect control data only when the address matches the existing address. In this case, both the decoration device 620 provided in the central decoration control device 610 and the decoration device 620 provided on the decoration device substrate 625 are controlled by the I ² CI / O expander 615.

In this way, by providing the decoration device substrate 625 and separating a part of the decoration devices (LEDs) from the decoration control device 610, even if the LEDs are arranged at remote locations, a common I ² CI / It can be controlled by the O expander 615.

  As described above, the decoration control device 610 can control a movable object such as a solenoid or a motor instead of a light emitting device such as an LED, and will be described in detail later with reference to FIG.

FIG. 18 is a block diagram illustrating a configuration of the I ² CI / O expander 615 according to the first embodiment of this invention.

The I ² CI / O expander 615 includes a transistor 630 connected to the connection line SDA, a filter 631 connected to the connection line SDA, a driver 632 connected to the connection line SDA, a filter 633 connected to the connection line SCL, Bus controller 634, output setting register 635, output controller 636, driver 637 connected to ports 0-15 on the output side of I ² CI / O expander 615, transistors 638A-638P connected to ports 0-15 , And a reset signal generation circuit 639.

  The filter 631 is connected to the connection line SDA, removes noise of data input from the connection line SDA, and outputs the data from which noise has been removed to the bus controller 634. When the driver 632 outputs a response signal from the connection line SDA, the driver 632 applies a voltage at which the transistor 630 can operate to the transistor 630.

  When the driver 632 outputs data (response signal) from the connection line SDA, the driver 632 applies a voltage at which the transistor 630 can operate to the transistor 630.

  The transistor 630 uses a field effect transistor (FET) to suppress power consumption. The gate of the transistor 630 is connected to the driver 632, and the drain is connected to a connection line SDA to which a predetermined voltage is applied by the pull-up resistor R. And the source is grounded.

  If the voltage applied to the gate of the transistor 630 is smaller than a predetermined value for operating the transistor 630, no current flows between the drain and the source. On the other hand, if the voltage applied to the gate of the transistor 630 is greater than or equal to a predetermined value that causes the transistor 630 to operate, a current flows from the drain to which the voltage of the predetermined value is applied to the grounded source. The voltage drops. Note that the transistor 630 has a specification that does not break even when a current of about 10 milliamperes flows from the drain to the source.

  When the driver 632 outputs data (response signal) from the connection line SDA, the driver 632 applies a voltage of a value that allows the transistor 630 to operate to the gate of the transistor 630 so that a current flows between the drain and the source. To do. The driver 632 outputs data from the connection line SDA by repeatedly changing the voltage of the connection line SDA from HIGH to LOW.

  The filter 633 is connected to the connection line SCL, removes noise of data input from the connection line SCL, and outputs the data from which noise has been removed to the bus controller 634.

In addition, the I ² CI / O expander 615, is set a unique address by the address setting terminals A0~A3 provided in the I ² CI / O expander 615 is input to the bus controller 634. Further, an address for resetting the I ² CI / O expander 615 is also set in advance.

The bus controller 634 determines whether or not the address of the data input from the connection line SDA matches the unique address set in the I ² CI / O expander 615. Capture as production control data.

The bus controller 634 determines whether the address of the data input from the connection line SDA matches the reset address set in the I ² CI / O expander 615. The data is fetched as initialization instruction data, and the I ² CI / O expander 615 is initialized.

  In addition, the bus controller 634 changes the signal level of the connection line SCL from LOW to HIGH, and when the signal level of the connection line SCL changes from HIGH to LOW after fetching the eighth bit data. The response signal is output from the connection line SDA to the first master IC 570a. Furthermore, when it is confirmed that the signal level of the connection line SCL changes from LOW to HIGH, and the signal level of the connection line SCL changes from HIGH to LOW again, the connection line SDA is released. In other words, the response signal is output at the timing when the signal level of the connection line SCL changes from LOW to HIGH.

In the output setting register 635, the operation mode of the I ² CI / O expander 615 and the output state of the ports 0 to 15 are set. When the bus controller 634 fetches the initialization instruction data from the connection line SDA and the I ² CI / O expander 615 is initialized, the output setting register 635 causes a current to flow to all the ports 0 to 15. The initial state is set so that there is no.

  Based on the data set in the output setting register 635, the output controller 636 causes the directing device connected to each of the ports 0 to 15 to actually output the output state of the directing device through the port driver 637. To control. This output state is updated to the contents specified in the effect control data when the bus controller 634 fetches the effect control data from the connection line SDA.

That is, based on the effect control data received from the first master IC 570a, it is set in the output setting register 635, and when the stop condition is received, the output state of each port 0-15 is updated and reflected in the effect device. Therefore, it is not necessary to receive the LAT signal as in the shift register, that is, the production control can be performed without the need for wiring for receiving the LAT signal. In particular, it is effective when the port output state needs to be updated by a plurality of I ² CI / O expanders 615 at the same time, and even if the rendering device is controlled by different I ² CI / O expanders 615, Since it can be controlled to execute the production operation at the same time, the production effect can be further enhanced.

  When a current flows through a port, the driver 637 applies a voltage at which the transistors 638A to 638P connected to the port through which the current flows can operate.

  The gates of the transistors 638A to 638P are connected to the driver 637, the drain is connected to a port terminal connected to a connection line to which a voltage for operating the effect device is applied as shown in FIGS. 19 and 20, and the source is grounded Has been.

  If the voltage applied to the gates of the transistors 638A to 638P is smaller than a predetermined value for operating the transistors 638A to 638P, no current flows between the drain and the source. On the other hand, if the voltage applied to the gates of 638A to 638P is equal to or higher than a predetermined value for operating the transistor 638, the predetermined voltage applied to the gate from the power supply Vled shown in FIG. 19 or the power supply Vmot or the power supply Vsol shown in FIG. Current flows to the source grounded through the drain of the transistor 638, so that the output state of the effect device connected to the port terminal can be controlled.

In addition, the I ² CI / O expander 615 of the decoration control device 610 can simultaneously control all effect devices (decoration devices 620 such as LEDs) connected to the port terminals of the I ² CI / O expander 615. Since it is possible, one rendering device connected to the port terminal of the I ² CI / O expander 615 can be controlled as one group.

Since the I ² CI / O expanders 615 included in each decoration control device 610 are assigned different individual addresses, the rendering device is divided into a plurality of groups. That is, the I ² CI / O expander 615 included in each decoration control device 610 is configured as a group unit control unit that can control the effect device in units of groups.

  Therefore, the effect control device 550 that controls each decoration control device 610 functions as a group control unit that controls the group unit control unit.

The reset signal generation circuit 639 is connected to a Vcc terminal connected to a connection line Vcc that supplies power to the I ² CI / O expander 615 and a RESET terminal that receives an external reset signal.

The reset signal generation circuit 639 generates a reset signal when the I ² CI / O expander 615 is turned on and the voltage rises to a predetermined value. The generated reset signal is sent to the bus controller 634, the output setting register 635, And initialization by inputting to the output controller 636.

  Note that when a LOW level reset signal is input from the outside, the reset signal generation circuit 639 outputs a reset signal, and therefore, from the CPU 551 of the effect control device 550 via the NOR gate circuit 561, from the RESET terminal. A reset signal may be input. When the RESET terminal is not used, the RESET terminal may be pulled up to HIGH as shown in FIGS.

FIG. 19 is a circuit diagram around the I ² CI / O expander 615 of the decoration control device 610 that controls the decoration device 620 according to the first embodiment of this invention.

The I ² CI / O expander 615 includes an NC terminal, a RESET terminal, an SCL terminal, an SDA terminal, a Vcc terminal, an A0 to A3 terminal, and a GND terminal as input terminals, and includes PORT0 to PORT15 as output terminals.

A power source supplied to the I ² CI / O expander 615 is connected to the RESET terminal via a pull-up resistor R. For this reason, the voltage applied to the reset terminal is always maintained HIGH.

  The SCL terminal is connected to the connection line SCL, and the SDA terminal is connected to the connection line SDA.

A power supply supplied to the I ² CI / O expander 615 is connected to the Vcc terminal. Further, a capacitor CP for removing power supply noise is connected to the Vcc terminal.

The A0 to A3 terminals are terminals for setting individual addresses in the I ² CI / O expander 615. The individual address of the I ² CI / O expander 615 is normally expressed by 4 bits. When the power of the I ² CI / O expander 615 is applied to this terminal, “1” is given to the bus controller 634. ”Is set, and when this terminal is connected to the ground,“ 0 ”is set in the bus controller 634.

Accordingly, the individual address of the I ² CI / O expander 615 shown in FIG. 19 is “0100”. The GND terminal is a terminal for grounding a voltage.

  The PORT0 terminal to the PORT15 terminal are connected to a decoration device 620 including the LEDs 0 to 15 via current limiting resistors R0 to R15. Note that one LED may be connected to one port as in PORT0, but a plurality of LEDs may be connected to one port as in PORT1-15.

When one LED is provided for every port, a maximum of 16 LEDs can be controlled by one I ² CI / O expander 615. Further, when the number of LEDs connected to each port is different, if all LEDs connected in series to one port are referred to as one type of LED, one I ² CI / O expander is used. By 615, up to 16 kinds of LEDs can be controlled.

  When a voltage is applied from the driver 637 to the gates of the transistors 638A to 638P (see FIG. 18) connected to the PORT0 terminal to the PORT15 terminal, a current flows from the drain to the source of the transistors 638A to 638P to which the voltage is applied. Thus, a current flows through the LED0 to LED15 connected to the PORT0 terminal to the PORT15 terminal, and each of the LED0 to LED15 lights up.

  On the other hand, if the driver 637 does not apply a voltage to the gates of the transistors 638A to 638P, no current flows through each LED0 to LED15, and each LED0 to LED15 is not lit.

It should be noted that a motor or solenoid can be connected to the PORT0 terminal to the PORT15 terminal of the I ² CI / O expander 615 instead of the LED, and the motor or solenoid can be configured as an effect device that is used for gaming. . Hereinafter, a case where a motor and a solenoid are controlled using the I ² CI / O expander 615 will be described with reference to FIG.

FIG. 20 is a circuit diagram around the I ² CI / O expander 615 of the decoration control device 610 according to the first embodiment of this invention, and shows a case where a motor and a solenoid are controlled.

  The motor used here is constituted by a stepping motor, and rotates by sequentially applying a predetermined voltage to signal terminals of each phase that drive the stepping motor. In the first embodiment of the present invention, the signal terminals of the respective phases of the motor are connected to the PORT0 terminal to the PORT3 terminal.

  When a voltage is applied from the driver 637 to any one of the gates of the transistors 638A to 638D connected to the PORT0 terminal to the PORT3 terminal connected to the motor, the drain to the source of the transistors 638A to 638D to which the voltage is applied Current flows to the motor, current flows to the motor connected to the PORT0 terminal to the PORT3 terminal, and the accessory driving motor is driven.

  The connection lines connecting the PORT0 to PORT3 terminals and the motor are branched, and one of the branched connection lines is connected to a power source supplied to the motor via a diode D and a Zener diode ZD.

  The PORT terminal 15 is connected to a solenoid to be used. When a voltage is applied from the driver 637 to the gate of the transistor 638P connected to the PORT15 terminal connected to the solenoid, a current can flow from the drain to the source of the transistor 638P to which the voltage is applied, A current flows through a solenoid connected to the PORT 15 terminal, and an effect device (not shown) driven by the solenoid is driven.

In FIG 20, although both the motors and solenoids to I ² CI / O expander 615 is connected, connected to one I ² CI / O expander 615, the motor and the solenoid at least one only The configuration may be also possible.

For example, as or provided or provided I ² CI / O expander 615 as a group controls only the stepping motor only, the I ² CI / O expander 615 as a group to control only the solenoid dedicated Also good. With such a configuration, it is possible to control the rendering devices belonging to the same group at the same timing, and therefore it becomes possible to group and control only the rendering devices that require high-speed processing.

  FIG. 21 is a diagram for explaining circuit configurations of the decoration control device 610, the relay board 600, and the simple relay board 1600 according to the first embodiment of the present invention, and particularly relates to input / output of signal lines and power supply lines. It is a figure for demonstrating a connection state.

  In this figure, among the decoration control device 610, the relay board 600, and the simple relay board 1600, the branch type decoration control device 610 (for example, the decoration control device 610A) will be described. Differences between the decoration control device 610, the terminal-type decoration control device 610, the relay board 600, and the simple relay board 1600 will be described.

  In the figure, description will be made with the same reference numerals as the parts provided in the above-described branch type decoration control device 610X.

The branch type decoration control device 610 includes an upstream connector 611, a downstream connector 612 (612A, 612B), and an I ² CI / O expander 615.

  The upstream connector 611 is a connector connected to the decoration control device 610 upstream from the decoration control device 610. The downstream connectors 612A and 612B are connected to the decoration control device 610 on the downstream side of the decoration control device 610.

  In order to connect the connection line SDA to the two downstream connectors 612A and 612B, the internal connection line SDA2111 extending from the upstream connector 611 branches at a branch 2101 into a first connection line SDA2121 and a second connection line SDA2131. The first connection line SDA2121 is connected to the downstream connector 612A, and the second connection line SDA2131 is connected to the downstream connector 612B.

  Similarly, the internal connection line SCL2112 extending from the upstream connector 611 branches at a branch 2102 into a first connection line SCL2122 and a second connection line SCL2132. The first connection line SCL2122 is connected to the downstream connector 612A, and the second connection line SCL2132 is connected to the downstream connector 612B.

Further, in order to connect the connection line SDA to the I ² CI / O expander 615, the second connection line SDA 2131 branches at the branch 2103, and the branched second connection line SDA 2131 is a diagram of the I ² CI / O expander 615. 19 and the SDA terminal shown in FIG. Further, in order to connect the connection line SCL to the I ² CI / O expander 615, the second connection line SCL2132 branches at the branch 2104, and the branched second connection line SCL2132 is a diagram of the I ² CI / O expander 615. 19 and the SCL terminal shown in FIG. Hereinafter, I ² CI / O expander 615, connection line SDA connected from branch 2103 to I ² CI / O expander 615, and connection line SCL connected from branch 2104 to I ² CI / O expander 615 will be described. A configuration including the I ² CI / O expander unit 2181 is included.

Note that the I ² CI / O expander 615 is supplied with a voltage Vcc that is a power supply voltage of the I ² CI / O expander 615. Although not shown in FIG. 21, from the I ² CI / O expander 615, signal lines (FIG. 19) of ports 0 to 15 for driving LEDs (decoration device 620) provided in the decoration control device 610 are provided. Reference) is output.

Further, a signal output from the I ² CI / O expander 615 of the decoration control device 610 to the upstream decoration control device 610 via the connection line SDA and an I of the decoration control device 610 from the upstream decoration control device 610. ^{2 A} Zener diode ZD2141 is connected to the internal connection line SDA2111 in order to remove noise of a signal input to the CI / O expander 615 via the connection line SDA.

  Specifically, the internal connection line SDA2111 branches at the branch 2105, the branched internal connection line SDA2111 is connected to the cathode side of the Zener diode ZD2141, and the anode side of the Zener diode ZD2141 is grounded.

  For this reason, a voltage (for example, a pulsed noise signal) higher than a predetermined voltage applied to the internal connection line SDA2111 is released by the Zener diode ZD2141.

In addition, in order to remove noise of a signal input via the connection line SCL from the upstream decoration control device 610 to the I ² CI / O expander 615 of the decoration control device 610, the internal connection line SCL2112 has a Zener. A diode ZD2142 is connected.

  Specifically, the internal connection line SCL2112 branches at a branch 2106, the branched internal connection line SCL2112 is connected to the cathode side of the Zener diode ZD2142, and the anode side of the Zener diode ZD2142 is grounded.

  For this reason, a voltage (for example, a pulse noise signal) higher than a predetermined voltage applied to the internal connection line SCL2112 is released by the Zener diode ZD2142.

Further, the I ² CI / O expander 615 of the decoration control device 610 outputs a signal output to the decoration control device 610 connected to the downstream connector 612A via the connection line SDA, and the decoration control connected to the downstream connector 612A. A zener diode ZD2143 is connected to the first connection line SDA2121 in order to remove noise of a signal input from the device 610 to the I ² CI / O expander 615 of the decoration control device 610 via the connection line SDA. .

  Specifically, the first connection line SDA2121 branches at a branch 2107, the branched first connection line SDA2121 is connected to the cathode side of the Zener diode ZD2143, and the anode side of the Zener diode ZD2143 is grounded.

  For this reason, a voltage (for example, a pulsed noise signal) higher than a predetermined voltage applied to the first connection line SDA2121 is released by the Zener diode ZD2143.

  Similarly to the Zener diode ZD2143 connected to the first connection line SDA2121, the Zener diode ZD2145 is also connected to the second connection line SDA2131.

Further, in order to remove noise of a signal input from the I ² CI / O expander 615 of the decoration control device 610 to the decoration control device 610 connected to the downstream connector 612A via the connection line SCL, the first connection line A Zener diode ZD2144 is connected to the SCL2122.

  Specifically, the first connection line SCL2122 branches at a branch 2108, the branched first connection line SCL2122 is connected to the cathode side of the Zener diode ZD2144, and the anode side of the Zener diode ZD2144 is grounded.

  For this reason, a voltage (for example, a pulsed noise signal) higher than a predetermined voltage applied to the first connection line SCL2122 is released by the Zener diode ZD2144.

  Similarly to the Zener diode ZD2144 connected to the first connection line SCL2122, the Zener diode ZD2146 is also connected to the second connection line SCL2132.

Further, from the internal connection line Vcc 2171 extending from the Vcc terminal of the upstream connector 601 connected to the connection line Vcc for supplying the power supply voltage to the I ² CI / O expander 615 of the decoration control device 610 and the GND terminal of the upstream connector 601 The extended and grounded internal connection line GND 2172 is connected via a smoothing capacitor C 2161 and a bypass capacitor CP 2162.

  The smoothing capacitor C2161 is a capacitor for smoothing the voltage waveform of the power supply, and the bypass capacitor CP2162 is a capacitor for removing noise of the power supply voltage.

For this reason, the power supply voltage supplied to the I ² CI / O expander 615 of the decoration control device 610 is smoothed by the smoothing capacitor C2161, noise is removed by the bypass capacitor CP2162, and the I ² CI / O expander is removed. The panda 615 is supplied.

  Similarly, the internal connection line Vcc2173 extending from the Vcc terminal of the downstream connectors 612A and 612B and the internal connection line GND2174 extending from the GND terminal are connected via a smoothing capacitor C2161 and a bypass capacitor CP2162. As a result, the smoothed and noise-free voltage is applied to the connection line Vcc connected to the downstream decoration control device 610.

  The branch type decoration control device 610 has been described above. Next, the connection type decoration control device 610 will be described.

  In addition to the downstream connector 612A, a Zener diode ZD2143 connected to the connection line SDA, a Zener diode ZD2144 connected to the connection line SCL, an internal connection line Vcc2173, an internal connection line GND2174, a smoothing capacitor C2161, and a bypass capacitor CP2162 are provided. The configuration is a first downstream connector portion 2182.

  In addition to the downstream connector 612B, a Zener diode ZD2145 connected to the connection line SDA, a Zener diode ZD2146 connected to the connection line SCL, an internal connection line Vcc2173, an internal connection line GND2174, a smoothing capacitor C2161, and a bypass capacitor CP2162 are provided. The configuration is a second downstream connector portion 2183.

  In the case where the decoration control device 610 is a connection type, since only one downstream connector is provided in the board, the downstream connector 612A exists but the downstream connector 612B does not exist.

  Therefore, the internal connection line SDA2111 and the internal connection line SCL2112 are configured not to branch at the branch points 2103 and 2104, and the second connection line SDA2131 and the second connection line SCL2132 do not exist. Different configuration.

  The connection type decoration control device 610 is different from the branch type decoration control device 610 in that there is no electronic component constituting the second downstream connector portion 2183. Other configurations are the same as those of the branch type decoration control device 610.

  Next, the terminal type decoration control device 610 will be described.

  In the case where the decoration control device 610 is a terminal type, the downstream connector is not provided in the board, and therefore neither of the downstream connectors 612A and 612B exists.

For this reason, the internal connection line SDA2111 and the internal connection line SCL2112 are connected to the I ² CI / O expander 615 without branching at the branch points 2101, 2102, 2103, 2104. This is a different configuration.

  The terminal-type decoration control device 610 is also different from the branch-type decoration control device 610 in that there are no electronic components constituting the first downstream connector portion 2182 and the second downstream connector portion 2183. Other configurations are the same as those of the branch type decoration control device 610.

  Next, the relay board 600 will be described.

  Since the relay board 600 is configured to include only one downstream connector in the board, similarly to the connection type decoration control device 610, the downstream connector 612A exists but the downstream connector 612B does not exist.

  Therefore, the internal connection line SDA2111 and the internal connection line SCL2112 are configured not to branch at the branch points 2103 and 2104, and the second connection line SDA2131 and the second connection line SCL2132 do not exist. It becomes composition.

  However, the relay board 600 is different from the connection type decoration control device 610 in that it includes a pull-up resistor for pulling up the voltages of the connection line SDA and the connection line SCL.

  Specifically, as shown in FIG. 21, in the relay board 600, the voltages of the upstream connection line SDA connected to the first master IC 570a and the downstream connection line SDA connected to the decoration control device 610 are set. A pull-up resistor R2151 for pulling up is connected to the first connection line SDA2121. Similarly, a pull-up resistor R2152 for pulling up the voltage of the upstream connection line SCL connected to the first master IC 570a and the downstream connection line SCL connected to the decoration control device 610 includes the first connection line. Connected to SCL2122.

  More specifically, the first connection line SDA2121 branches at the branch 2109, and the branched first connection line SDA2121 is connected to the pull-up resistor R2151. Similarly, the first connection line SCL2122 branches at the branch 2110, and the branched first connection line SCL2122 is connected to the pull-up resistor R2152. Hereinafter, the pull-up resistor R2151 for pulling up the voltage of the connection line SDA and the pull-up resistor R2152 for pulling up the voltage of the connection line SCL are collectively referred to as a pull-up resistor unit 2180.

  Next, the simple relay board 1600 will be described.

The simple relay board 1600 includes a plurality of downstream connectors (downstream connectors 612A and 612B) in the board, similarly to the branch type decoration control device 610. However, the simple relay board 1600 does not include a circuit corresponding to the I ² CI / O expander unit 2181. Instead, a circuit corresponding to the pull-up resistor unit 2180 provided in the relay board 600 is provided. This is a configuration different from the branch type decoration control device 610. Other configurations are the same as those of the branch type decoration control device 610.

  In the present embodiment, the configuration of the pull-up resistor 2180 described above is provided only on the relay board 600 and the simple relay board 1600, and is not provided in the decoration control device 610 or the effect control device 550. However, as long as the levels of the connection line SDA and the connection line SCL can be correctly generated, the decoration control device 610 and the effect control device 550 may be provided. In short, the pull-up resistors R2151 and 2152 only need to be provided at locations where the voltage Vcc can be supplied to the drain terminals of the transistors that drive the connection line SDA and the connection line SCL.

  For example, if the pull-up resistors R2151 and 2152 are provided in the first master IC 570a, it is not necessary to provide the pull-up resistor unit 2180 in the relay board 600, the simple relay board 1600, or the decoration control device 610.

  FIG. 22 is an explanatory diagram of the slave address 2200 included in the data output from the presentation control device 550 to the decoration control device 610 according to the first embodiment of this invention.

  The slave address 2200 includes a fixed address part 2201 composed of upper 3 bits and a variable address part 2202 composed of lower 5 bits.

The fixed address unit 2201 is preset with a value of “110” and cannot be changed by the I ² CI / O expander 615.

The variable address unit 2202 can be set by the I ² CI / O expander 615. The variable address unit 2202 includes a 4-bit I ² CI / O expander address 2203 corresponding to the pattern set at the terminals A0 to A3 of the I ² CI / O expander 615 to be controlled, and the data It consists of 1-bit R / W identification data 2204 indicating whether it is a read request or a write request.

  Since the effect control data output from the effect control device 550 to the decoration control device 610 is a write request, “0” is normally registered in the R / W identification data 2204.

FIG. 23 is an explanatory diagram of the I ² CI / O expander address table 2300 according to the first embodiment of this invention.

The I ² CI / O expander address table 2300 is a table managed by the first master IC 570a. The I ² CI / O expander address table 2300 shows the correspondence between the slave address 2301 and the I ² CI / O expander address 2302.

The slave address 2301 stores the slave address of the decoration control device 610 specified by the effect control device 550 as a transmission / reception target. As described above with reference to FIG. 20, the slave address is configured by combining a fixed address portion consisting of upper 3 bits, a 4-bit I ² CI / O expander address, and 1-bit R / W identification data. .

In the I ² CI / O expander address 2302, a 4-bit I ² CI / O expander address corresponding to each slave address is registered as described above with reference to FIGS.

However, among the I ² CI / O expander addresses, the address “1000” and the address “1011” (shaded entries in FIG. 23) are used to identify each I ² CI / O expander 615 from each other. It cannot be used as a unique address.

  The address “1000” is used as a default value at power-on of an address (all call address) specified when a common command is output to all the decoration control devices 610. The address “1011” is a common address used when all the decoration control devices 610 connected to the first master IC 570a are unconditionally reset by software.

As described above, since there are 14 addresses that can be set in the I ² CI / O expander 615 of the decoration control device 610, the effect control device 550 controls the 14 I ² CI / O expanders 615. be able to. Since each decoration control device 610 includes PORT0 to PORT15, it is possible to control 16 (in other words, 16 types) LEDs. Therefore, the effect control device 550 can control 224 (in other words, 224 types) LEDs.

FIG. 24 is a diagram for describing work registers assigned to the output setting register 635 included in the I ² CI / O expander 615 according to the first embodiment of this invention.

A work register (device register) and a control register (control register) are assigned to the output setting register 635 of the I ² CI / O expander 615.

Work register, I ² CI / O Aix information and for performing settings that are predefined for Panda 615, I ² CI / O Aix effect device connected to the expander 615 (decoration device 620, for example, The information for specifying the output mode of LED) is stored.

  In addition, the control register stores information defining a procedure for writing data to the work register. The work register is configured to store a plurality of pieces of information in different storage areas, and a different register number is assigned to each storage area.

The register number “00h” and the register number “01h” correspond to a mode register for performing the initial setting of the I ² CI / O expander 615. The register name “MODE1” is assigned to the storage area of the register number “00h”. The register name “MODE2” is assigned to the storage area of the register number “01h”. When values are written in the storage areas of the register numbers “00h” and “01h”, the I ² CI / O expander 615 is initialized based on the written values.

Note that bit 3 (OCH) of the “MODE2” register is a parameter that defines the timing at which the effect control data stored in the output setting register 635 of the I ² CI / O expander 615 is actually reflected in the effect device. . In the first embodiment of the present invention, as described with reference to FIG. 18, “0” is set, and the presentation control data stored in the output setting register 635 is output when the stop condition is received. The output state of the rendering device is set to be actually controlled.

Parameters to be controlled such as LEDs included in the decoration device 620 are set in the register numbers “02h” to “11h” (register names “PWM0” to “PWM15”). When a value is written in any of the storage areas of register numbers “02h” to “11h”, among the 16 LEDs constituting the light emitting device (decoration device 620) connected to the I ² CI / O expander 615 The brightness of the LED corresponding to the register number in which the value is written is adjusted based on the written value. For example, when a value is written in the storage area of the register number “02h”, the luminance of the LED 0 connected to the port 0 shown in FIG. 19 is adjusted.

Note that the I ² CI / O expander 615 can also control a movable object such as a motor or a solenoid as described above. When a solenoid is connected to the I ² CI / O expander 615, the register number corresponding to the port to which the solenoid is connected is operated by energizing the solenoid or not energized. A value indicating whether to do is written. When a motor is connected to the I ² CI / O expander 615, a value indicating the target rotational position of the motor is written in the register number corresponding to the port to which the motor is connected.

  In the register number “12h” (register name “GRPPWM”) and the register number “13h” (register name “GRPFREQ”), parameters for specifying the operation pattern of the entire control target are set. When a value is written in the storage areas of the register numbers “12h” and “13h”, the blinking pattern of the entire LED (16 LEDs) is set based on the written value. Specifically, a duty cycle that is an on / off ratio of the entire LED is set in the register number “12h”, and a blinking cycle of the entire LED is set in the register number “13h”.

  In register numbers “14h” (register name “LEDOUT0”) to “17h” (register name “LEDOUT3”), the output state of the LED controlled by each port is set. Each register can set four LED output states.

  When a value is written in the storage area of the register number “14h”, the output states of the LEDs 0 to LED3 are set based on the written value. Similarly, the output state of LED4 to LED7 is stored in the storage area of register number “15h”, the output state of LED8 to LED11 is stored in the storage area of register number “16h”, and the LED12 to LED15 are stored in the storage area of register number “17h”. Output status is set.

  Sub-addresses are set in the register numbers “18h” to “1Ah” (register names “SUBADR1” to “SUBADR3”). When values are written in the storage areas of the register numbers “18h” to “1Ah”, the first subaddress to the third subaddress are set based on the written values.

  In the register number “1Bh” (register name “ALLCALLADR”), an all call address for outputting a command to all the decoration control devices 610 is set. The all call address is used, for example, when the initialization processing is executed in all the decoration control devices 610 when the power is turned on.

  FIG. 25 is an explanatory diagram of a start condition and a stop condition in which the master IC according to the first embodiment of this invention outputs data via the connection line SDA and the connection line SCL.

  The connection line SCL has a signal level of HIGH when data is not transmitted. When outputting data to the decoration control device 610, the master IC changes the signal level of the connection line SCL from LOW to HIGH so that the decoration control device 610 acts as a strobe signal for taking in the data of the connection line SDA.

  The connection line SDA has a high signal level when data is not transmitted, and data is output from the connection line SDA in accordance with the clock signal of the connection line SCL.

  The master IC changes the signal level of the connection line SDA from HIGH to LOW while maintaining the signal level of the connection line SCL at HIGH, and outputs a signal serving as a start condition indicating that data output starts. .

The I ² CI / O expander 615 of the decoration control device 610 recognizes that output of data is started when a signal serving as a start condition is input from the connection line SDA and the connection line SCL.

  The master IC changes the signal level of the connection line SDA from LOW to HIGH while maintaining the signal level of the connection line SCL at HIGH, and outputs a signal that becomes a stop condition indicating that the output of data ends. .

The I ² CI / O expander 615 of the decoration control device 610 recognizes that the output of data is finished when a signal serving as a stop condition is input. In the first embodiment of the present invention, as described above, when the decoration control device 610 receives a signal that is a stop condition, control of the effect device (decoration device 620) controlled by the decoration control device 610 is started. .

  FIG. 26 is a timing chart at which the decoration control device 610 to which data output from the master IC according to the first embodiment of this invention is input outputs a response signal.

  The decoration control device 610 counts the number of changes in the signal level of the connection line SCL after the start condition is satisfied, and takes in data input from the connection line SDA in accordance with the clock signal of the connection line SCL.

  Then, the decoration control device 610 outputs a response signal to the master IC via the connection line SDA immediately before the start condition is satisfied and immediately before the number of changes in the signal level of the connection line SCL reaches nine. In other words, the decoration control device 610 outputs a response signal via the connection line SDA when the signal level of the connection line SCL changes from HIGH to LOW after taking the 8th bit data from the connection line SDA. To do.

  As shown in FIG. 26, a response signal (ACK response signal) indicating that data reception has been successful is indicated by a LOW level, and a response signal (NACK response signal, indicating that data reception has failed), In the figure, this corresponds to no ACK output) is indicated by a HIGH level.

  Further, when the signal level of the connection line SCL changes eight times after the start condition is satisfied, the master IC waits for a response signal from the decoration control device 610 by releasing the connection line SDA. Then, the master IC changes the signal level of the connection line SCL while releasing the connection line SDA, and takes in the response signal from the decoration control device 610.

  FIG. 27 is a timing chart of signal levels of the connection line SDA and the connection line SCL when the master IC according to the first embodiment of the present invention outputs effect control data.

  First, when starting output of data, the master IC changes the signal level of the connection line SDA from HIGH to LOW while maintaining the signal level of the connection line SCL at HIGH, thereby indicating a start condition signal. And the decoration control device 610 is notified that data output is to be started.

  Next, the master IC outputs the slave address of the decoration control device 610 to be controlled, which consists of a total of 7 bits. Further, the master IC outputs information indicating whether the request is a write request, which is a read request, at the eighth bit.

  The master IC receives a response signal from the decoration control device 610 when the signal level of the connection line SCL becomes HIGH for the ninth time. Therefore, if the response signal is an ACK response signal, the signal level of the connection line SDA is LOW. If the response signal is NACK, the signal level of the connection line SDA changes to HIGH.

  Next, after outputting the address data, the master IC outputs the data with a bit number that is a multiple of eight. Further, after the eighth bit of data is output, the ninth bit of data is output after an ACK response signal is input. Thereafter, when data of a bit corresponding to a multiple of 8 is output, after confirming that an ACK response signal is input, a (multiple of 8 + 1) th bit is output and all data is output. Repeat until.

  If the master IC outputs a bit that is a multiple of 8 after the data has been output and the ACK response signal is not input even after a predetermined time has elapsed, the master IC assumes that the data transmission has failed and starts again. Send the condition. Next, the address data is output again via the connection line SDA, and the data is output again from the first bit while confirming the ACK response signal.

  The master IC outputs the signal indicating the stop condition after outputting the data of the last bit of the data and waiting for the ACK response signal to be input.

  In FIG. 27, a total of 24 bits (slave address 8 bits, data 16 bits) of data is output after the signal indicating the start condition is output until the signal indicating the stop condition is output. Depending on the size of data to be transmitted, it may be 24 bits or more, or 24 bits or less.

FIG. 28 shows the master IC and the I ² CI / O expander when the master IC according to the first embodiment of this invention designates the slave individual address and sets the effect control data in the decoration control device 610. 6 is a diagram illustrating a format of data transmitted / received to / from 615. FIG.

The 8-bit data 2801 that is output first includes an address “A0 to A6” of the decoration control device 610 that is a target of data transmission, and a 1-bit that indicates whether the data is a read request or a write request. R / W identification data is included. Among the addresses “A0 to A6”, “A4 to A6” are fixed address portions having a value “110”, and “A0 to A3” are set to terminals A0 to A3 of the I ² CI / O expander 615. (Refer to FIG. 19). The data 2801 is data corresponding to “ADDRESS” and “R / W” in FIG.

The 8-bit data 2802 to be output next includes setting data for the control register assigned to the output setting register 635 (see FIG. 18) of the I ² CI / O expander 615. Data 2802 is data corresponding to “DATA” transmitted first in FIG.

  Here, the control register will be described. The control register consists of 8 bits, and the upper 3 bits “AI0 to AI2” are automatic write parameters for designating the writing or reading method to the work register of the output setting register 635, and the lower 5 bits “D0 to D4” are the work. This is a register address that specifies an access start position (a start position at which writing starts or a start position at which reading starts) in the register.

  The auto-write parameter is accessed by the master IC including only the access start position area specified by the register address (auto-increment is prohibited) or including the area adjacent to the access start position area specified (auto-increment). (Specifically, “000”, “100”, “101”, “110”, “111”) can be set.

  When a value of “000” is set in the automatic writing parameter, auto-increment is prohibited, and only the area at the access start position specified by the register address is accessed, and the area other than the start position is not accessed. For example, if the register address is “10100”, only the storage area with the register number “14h” is accessed, and the other storage areas are not accessed. That is, it is used when only the value of the storage area of a specific register address is changed. When the values of the storage areas of a plurality of register addresses are changed continuously, the address designation can be omitted by permitting auto-increment as described below.

  When the value of “100” is set in the auto-write parameter, auto-increment is permitted, and after accessing the area at the access start position specified by the register address, access is made sequentially while moving the area in the direction of increasing the register number. repeat. Then, after accessing the storage area where the register number is “1Bh” at the end, the storage area where the register number is “00h” is accessed and accessed again sequentially while moving the area in the direction in which the register number increases. repeat. For example, if the register address is “10100”, after accessing the storage area where the register number is “14h”, the register number is “15h” → “16h” →→→ “1Bh” → “00h” → “01h” →... (Ie, all areas) are repeatedly accessed.

  When the value of “101” is set in the automatic write parameter, the register number is set after accessing the area at the access start position specified by the register address, as in the case of setting the value of “100” in the automatic write parameter. Access is repeated in order while moving the area in the direction of increasing. However, once the storage area whose register number is “11h” is accessed, the storage area whose register number is “02h” is accessed, and thereafter, the section where the register numbers are “02h” to “11h”. The recording area (area relating to LED brightness adjustment) is repeatedly accessed. For example, if the register address is “10100”, after accessing the storage area where the register number is “14h”, the register number is “15h” → “16h” →. →→ “1Bh” → “00h” → The area which becomes “01h” →... Is accessed in order. After accessing the storage area where the register number is “11h”, the area where the register number is “02h” → “03h” → ··· “11h” → “02h” → “03h” → ··· , Repeatedly access.

  When the value “110” is set in the automatic write parameter, the register number is set after accessing the area at the access start position specified by the register address, as in the case where the value “100” is set in the automatic write parameter. Access is repeated in order while moving the area in the direction of increasing. However, once the storage area whose register number is “13h” is accessed, the storage area whose register number is “12h” is accessed, and thereafter, the section where the register numbers are “12h” to “13h”. The recording area (area related to the LED blinking cycle) is repeatedly accessed. For example, if the register address is “10100”, after accessing the storage area where the register number is “14h”, the register number is “15h” → “16h” →. →→ “1Bh” → “00h” → The area which becomes “01h” →... Is accessed in order. Then, after accessing the storage area where the register number is “13h”, the area where the register number is “12h” → “13h” → “12h” → “13h” →... Is repeatedly accessed.

  When the value “111” is set in the automatic write parameter, the register number is set after accessing the access start position area specified by the register address, as in the case where the value “100” is set in the automatic write parameter. Access is repeated in order while moving the area in the direction of increasing. However, once the storage area whose register number is “13h” is accessed, the storage area whose register number is “02h” is accessed, and thereafter, the section where the register numbers are “02h” to “13h”. The recording area (area related to LED brightness and blinking cycle) is repeatedly accessed. For example, if the register address is “10100”, after accessing the storage area where the register number is “14h”, the register number is “15h” → “16h” →. →→ “1Bh” → “00h” → The area which becomes “01h” →... Is accessed in order. After accessing the storage area where the register number is “13h”, the area where the register number is “02h” → “03h” → ··· “13h” → “02h” → “03h” → ··· , Repeatedly access.

  Here, returning to the description of FIG. 28, the work register setting data 2803 is output following the control register setting data 2802. The setting data 2803 is data corresponding to “DATA” transmitted after the second in FIG.

  When the automatic writing parameter is “000”, the setting data 2803 is 8-bit data for updating one storage area designated by the register address. When the automatic writing parameter is set to a value other than “000”, the setting data 2803 is a multiple of 8 necessary for repeatedly updating a plurality of areas starting from the storage area specified by the register address. Bit data.

FIG. 29 shows the master IC and the I ² CI / O expander when the master IC according to the first embodiment of the present invention sets the effect control data in the decoration control device 610 by specifying the slave individual address. 615 is a diagram in which specific numerical values are applied to effect control data transmitted to and received from 615. FIG. FIG. 29 shows effect control data for prohibiting auto-increment and updating only one specific storage area of the work register. Specifically, the PORT0 terminal of the I ² CI / O expander 615 A case where the light emission state of the LED connected to the PORT3 terminal is updated will be described.

First, “1101100” indicating the slave address of the I ² CI / O expander 615 of the destination decoration control device 610 is assigned to the 8-bit data 2901 output first.

The 8-bit data 2902 to be output next is set in the control register of the output setting register 635 of the I ² CI / O expander 615 assigned to set the automatic writing parameter and LED output data. Value to be included.

Here, since the light emission state of the LED connected to the PORT0 terminal to the PORT3 terminal of the I ² CI / O expander 615 is set, LEDOUT0 (address = 10100) is designated as the register address.

  Note that “000” is designated in the auto-write parameter to prohibit auto-increment.

Next, the output 8-bit data 2903 includes data for setting the light emission mode of the decoration device 620 controlled by the destination decoration control device 610. Specifically, data set in the LEDOUT0 register is assigned. As a result, the light emission state (lighting, extinguishing, blinking, etc.) of the LED connected to the PORT0 terminal to the PORT3 terminal of the I ² CI / O expander 615 is designated, and the LED emits light in the designated state.

In this way, the light emission state of the LED PORT0 terminal ~PORT3 terminal I ² CI / O expander 615 is controlled, the other PORT terminal I ² CI / O expander 615 (PORT4~PORT15) also Individual control is possible by designating the value of the control register data 2902 and setting the output data 2903. Even if a motor or a solenoid is connected to the PORT terminal, the same control is performed.

  FIG. 30 is a diagram illustrating the order in which the production control data of the master IC according to the first embodiment of this invention is transmitted. In FIG. 30, the order in which each data included in the effect control data is transmitted when auto-increment is permitted and all the storage areas of the work register are updated is defined.

  First, the master IC transmits 8-bit data (data having the same format as the data 2801 in FIG. 28) that can specify the individual address of the decoration control device 610 to be controlled.

Next, the master IC transmits data set in the control register of the output setting register 635 of the I ² CI / O expander 615 to be controlled (data having the same format as the data 2802 in FIG. 28). In FIG. 30, in order to update all the storage areas of the work register by permitting auto-increment, “100” is designated as the automatic write parameter, and the register address designating the start position of writing or reading is “00h” which is the head area of the work register is designated.

For this reason, in the I ² CI / O expander 615 of the decoration control device 610 to be controlled after receiving the control register set value, the storage area (MODE1 register) of the register number “00h” is updated first. It will be.

Next, after transmitting the control register set value, the master IC transmits a value (total of 8 bits) to be written to the MODE1 register. When the I ² CI / O expander 615 receives the write value, it updates the value of the MODE 1 register, increments the register number, and prepares to update the next “01h” storage area (MODE 2 register). .

Further, the master IC transmits values (total 8 bits) to be written to the MODE2 register, and thereafter transmits the set values in order to the remaining storage area registers whose register numbers are “02h” to “1Bh”. . Each time the I ² CI / O expander 615 receives the write value, the I ² CI / O expander 615 updates the value of the corresponding register, increments the register number, and repeats the preparation for updating the next storage area. The values of all the registers “00h” to “1Bh” assigned to are updated.

When the I ² CI / O expander 615 updates the storage area of “1Bh” which is the last of the work registers, the I ² CI / O expander 615 changes the register number to “00h” and waits for the update of the MODE1 register.

31, when the master IC of the first embodiment of the present invention initializes the I ² CI / O expander 615, the initialization instruction transmitted from the master IC to the I ² CI / O expander 615 It is a figure explaining the format of data.

  When the CPU 551 of the effect control device 550 instructs the master IC to initialize the decoration control device 610, the master IC transmits initialization instruction data to all the decoration control devices 610 connected to the master IC. .

  The 8-bit data 3101 output first includes a fixed address “110” shown in FIG. 29 and a reset address “1011” (see FIG. 23), which is a common address. The data 3101 corresponds to “ADDRESS” in FIG. 27, and “0” indicating writing is set in the bit of “R / W”.

  The first predetermined value “10100101” is set in the 8-bit data 3102 to be output next, and the second predetermined value “01011010” is set in the 8-bit data 3103 to be output next. The data 3102 corresponds to “DATA” transmitted first in FIG. 27, and the data 3103 corresponds to “DATA” transmitted second in FIG.

When all the I ² CI / O expanders 615 connected to the master IC receive initialization instruction data including a reset address, a first predetermined value, and a second predetermined value, the I ² CI / O expander 615 initializes itself.

The reason why both the first predetermined value and the second predetermined value are output after the reset address is output is that the master IC does not transmit the reset address “1011”, but the influence of noise or the like. This is because the I ² CI / O expander 615 erroneously fetches the reset address “1011” to prevent initialization from being executed at an incorrect timing.

Further, the reset address is an address common to all (in other words, a plurality) I ² CI / O expanders 615, unlike the individual address. Therefore, only transmit once initialization instruction data including the reset address, since all will be initialized by selecting I ² CI / O expander 615 (s), I ² CI / O Aix Compared with the method of individually selecting the panda 615 and instructing initialization, it is possible to instruct initialization at high speed.

  In FIG. 31, the first predetermined value and the second predetermined value are different from each other, but may be the same value. Further, either the first predetermined value or the second predetermined value may be transmitted once.

  FIG. 32 is a diagram illustrating the abnormality determination table 3200 of the first master IC 570a according to the first embodiment of this invention.

The abnormality determination table 3200 is stored in the RAM 553 of the effect control device 550. The abnormality determination table 3200 is provided for monitoring the connection state between the first master IC 570a of the effect control device 550 and the I ² CI / O expander 615 connected to the first master IC 570a. The abnormality determination table 3200 stores information corresponding to each I ² CI / O expander 615 according to the connection state.

  The abnormality determination table 3200 includes an I / O expander address 3201, a slave address 3202, an error counter 3203, a comparison value 3204, and an error flag 3205.

The I / O expander address 3201 corresponds to the address (see FIG. 19) set at the terminals A0 to A3 of the I ² CI / O expander 615 connected to the first master IC 570a.

In the slave address 3202, the slave address registered in the I ² CI / O expander address table 2300 shown in FIG. 23 is registered.

Error counter 3203 increments when sending the performance control data from the first master IC570a the I ² CI / O expander 615, can not receive an ACK from the I ² CI / O Expander 615 two consecutive Is done.

In the comparison value 3204, a value to be compared with the value of the error counter 3203 is registered in order to determine whether or not a failure has occurred in the I ² CI / O expander 615. Note that the value of the comparison value 3204 may be set according to the type of the rendering device to be controlled.

In the error flag 3205, an error flag indicating whether or not an abnormality has occurred in the connection state of the entry with the I ² CI / O expander 615 is registered.

The method for determining whether or not a failure has occurred in the I ² CI / O expander 615 will be described in detail. If the value of the error counter 3203 reaches a predetermined value set in the comparison value 3204, an error will occur. “ON” is set in the flag 3205, and it is registered that a failure has occurred in the I ² CI / O expander 615 corresponding to the entry.

  In the first embodiment of the present invention, as will be described later, the production control data output process (see FIG. 37) is executed in synchronization with a VDP interrupt (a period of about 33.3 ms). .

As described above, if the ACK from the I ² CI / O expander 615 cannot be received for the ^second transmission of the presentation control data from the first master IC 570a to the I ² CI / O expander 615, an error occurs. Counter 3003 is incremented.

Therefore, when an abnormality has occurred, the execution period of the data output process is 33.3 ms and the comparison value 3004 is “300”. Therefore, the I ² CI / O expander is 33.3 ms × 300≈10 s. It is detected that an abnormality relating to 615 has occurred.

  FIG. 33 is a diagram illustrating the abnormality determination table 3300 of the second master IC 570b according to the first embodiment of this invention.

Similar to the abnormality determination table 3200 of the first master IC 570a, the abnormality determination table 3300 of the second master IC 570b is stored in the RAM 553 of the effect control device 550. The abnormality determination table 3300 is provided to monitor the connection state between the second master IC 570b of the effect control device 550 and the I ² CI / O expander 615 connected to the second master IC 570b. The abnormality determination table 3300 stores information corresponding to each I ² CI / O expander 615 according to the connection state. The configuration of the abnormality determination table 3300 is the same as that of the abnormality determination table 3200 of the first master IC 570a.

  In the first embodiment of the present invention, since there is no decoration control device 610 connected to both the first master IC 570a and the second master IC 570b, the I / O expander address of each decoration control device 610 to be controlled. Is set for each master IC. Therefore, in FIG. 32 and FIG. 33, the same value I / O expander address is set. Since only one address can be set as the I / O expander address, it is necessary to set a common address when a plurality of master ICs control one decoration control device 610.

  The master IC according to the first embodiment of the present invention includes a plurality of registers that are used to configure device operation and transmit / receive serial data. The command register (REG) 581 shown in FIGS. 11 and 12 is one of such registers, and instructs the connected decoration control device 610 to output a start condition or a stop condition.

  The effect control device 550 transmits an effect instruction to the decoration control device (slave) 610 via the master IC, and executes various effect processes. FIG. 34 shows a procedure for initializing each slave, and FIG. 35 shows an outline of a procedure for transmitting the effect control data to each slave.

  FIG. 34 is transmitted / received between the CPU 551 and the master IC (the first master IC 570a or the second master IC 570b) when each decoration control device (slave) according to the first embodiment of the present invention is initialized (reset). It is a figure explaining information.

  When the slave initialization start process is started, the CPU 551 of the effect control device 550 sets “1” to a bit instructing execution of the start condition (STA) and the stop condition (STO) of the command REG 581 (3401).

  In accordance with the information (STO, STA) set in the command REG581, the master IC first outputs a stop condition to each decoration control device (slave) 610 to be controlled, and then outputs a start condition (3411). . By outputting a stop condition, each slave is notified that data transmission has been completed, and thereafter, by outputting a start condition, preparation for receiving an input of a command is completed in each slave.

  When outputting the start condition, the master IC inputs an interrupt signal (INT) to the CPU 551 to generate an interrupt. The CPU 551 that has generated the interrupt starts the transmission resumption process (1) of the transmission instruction data (3402). In the transmission resumption process (1) of the transmission instruction data, a reset address is set in the output buffer 572. The reset address is a fixed address determined in advance for resetting each slave. At this time, “0” is set in the STA and STO of the command REG581.

  The master IC outputs predetermined data (reset command) to the reset address set in the output buffer 572 (3412). The reset command corresponds to the first predetermined value (data 3102) and the second predetermined value (data 3103) described in FIG.

  When the master IC outputs the reset address, the master IC inputs an interrupt signal to the CPU 551 to generate an interrupt. The CPU 551 that has generated the interrupt starts the transmission resumption process (2) of the transmission instruction data (3403). In the transmission restart process (2) of the transmission instruction data, the first half value of the reset command is set in the output buffer 572. The first half value of the reset command corresponds to the first predetermined value (data 3102) described in FIG. At this time, “0” is set in the STA and STO of the command REG581. The master IC outputs the first half value of the reset command set in the output buffer 572 (3413).

  Thereafter, when the master IC outputs the first half value of the reset command, it inputs an interrupt signal to the CPU 551 to generate an interrupt. The CPU 551 that has generated the interrupt starts transmission restart processing (3) of the transmission instruction data (3404), and sets the latter half value of the reset command in the output buffer 572. At this time, “0” is set in the STA and STO of the command REG581. The master IC outputs the latter half value of the reset command set in the output buffer 572 (3414). The latter half value of the reset command corresponds to the second predetermined value (data 3103) described with reference to FIG.

  Further, when the master IC outputs the second half value of the reset command, it inputs an interrupt signal to the CPU 551 to generate an interrupt. The CPU 551 that has generated the interrupt starts transmission restart processing (4) of the transmission instruction data (3405), sets “0” to the STA of the command REG581, sets “1” to the STO, and outputs the stop condition to the master IC. Instruct.

  The master IC outputs a stop condition to each slave according to the information set in the command REG 581 (3415).

  Through the above processing, each slave is initialized. If the initialization fails (3406), the process is restarted from step 3402.

  FIG. 35 shows transmission / reception between the CPU 551 and the master IC (the first master IC 570a or the second master IC 570b) when transmitting the effect control data to each decoration control device (slave) according to the first embodiment of the present invention. It is a figure explaining the information to be performed.

  When performing the effect control, the CPU 551 of the effect control device 550 first sets “1” to a bit instructing execution of the start condition (STA) and the stop condition (STO) of the command REG581 (3501).

  The master IC outputs a stop condition to each slave based on the values (“1”) set in the STA and STO of the command REG 581, and then outputs a start condition (3511).

  When the master IC outputs a start condition to each slave, the master IC is ready to receive the presentation control data at each slave. Therefore, the master IC inputs an interrupt signal to the CPU 551 to generate an interrupt. The CPU 551 that has generated the interrupt sets presentation control data indicating the address of the slave to be controlled and the control content in the output buffer 572 (3502). At this time, “0” is set in the STA and STO of the command REG581.

  The master IC outputs the address and effect control data set in the output buffer 572 to each slave (3512). At this time, the slave corresponding to the output address executes effect processing based on the received effect control data.

  When the master IC outputs the address and the effect control data to each slave, the master IC inputs an interrupt signal to the CPU 551 to generate an interrupt. The CPU 551 that has generated the interrupt sets “1” to the STA of the command REG 581 and “0” to the STO (3503). Thereafter, the master IC outputs a so-called restart condition that outputs a start condition again (3513).

  Subsequently, the CPU 551 and the master IC perform similar processing by designating another address (3504, 3514, 3505, 3515). When the CPU 551 completes the output of the presentation control data for the last nth slave (3506), and the master IC outputs the presentation control data to the corresponding slave (3516), the output of all the data is completed, so Output the condition. Specifically, when the master IC has finished outputting the production control data to the final slave, an interrupt signal is input to cause the CPU 551 to generate an interrupt, and the CPU 551 that generated the interrupt generates “0” in the STA of the command REG581. ", STO is set to" 1 "(3507), and then the master IC outputs a stop condition (3517).

  FIG. 36 is a diagram illustrating the stage of transmitting effect control data from the effect control device 550 according to the first embodiment of this invention to the master IC (first master IC 570a or second master IC 570b).

  When the slave output data editing process described later is executed, the CPU 551 of the effect control device 550 secures an output data preparation area in the RAM 553 and stores the effect control data for each slave in the output data preparation area.

  In addition, the output data preparation area is further divided for each slave, and stores the production control data corresponding to the address and production content corresponding to each slave. Specifically, the address corresponds to the data of the transmission order 1 shown in FIG. 30, and the effect control data corresponds to the data of the transmission orders 2 to 30 shown in FIG.

  Further, the CPU 551 further secures an output data save area in the RAM 553 so that untransmitted effect control data is not overwritten, and saves the data stored in the output data preparation area by the slave output data save process to the output data save area. Let Thereafter, the saved data is set in the output buffer 572 of the master IC at a predetermined timing.

  The output data preparation area and the output data saving area are secured in the RAM 553 for each master IC, and areas corresponding to the first master IC 570a and the second master IC 570b are secured in the first embodiment of the present invention. .

  FIG. 37 is a flowchart showing a procedure of processing performed by the effect control device 550 according to the first embodiment of this invention.

  The processing shown in FIG. 37 is executed by the CPU 551 of the effect control device 550.

  When the effect control device 550 is turned on, the effect control device 550 first executes the processing of steps 3701 to 3706, and in the processing of step 3707, a synchronization signal (for example, 33.3 ms) synchronized with the image update cycle from the VDP 556. It waits until the synchronization signal (second cycle) is input to the CPU 551 as an interrupt signal. Thereafter, each time the synchronization signal synchronized with the image update cycle is input from the VDP 556 to the CPU 551 as an interrupt signal, the processing of steps 3705 to 3721 is repeatedly executed.

  First, the effect control device 550 executes initialization processing including initialization of the RAM 553 of the effect control device 550 (3701). At this time, an initialization stage number relating to the first master IC 570 described later and an initialization stage number relating to the second master IC 570b are both set to “0”.

  Then, the effect control device 550 inputs a reset pulse to the first master IC 570a and the second master IC 570b via the output I / F 558a and the NOR gate circuit 561, and initially sets the first master IC 570a and the second master IC 570b in hardware. (3702).

Subsequently, the effect control device 550 outputs initialization instruction data from the first master IC 570a in order to initialize the I ² CI / O expander 615 of all the decoration control devices 610 connected to the first master IC 570a. The first master IC 570a side slave initialization start process is executed (3703). Similarly, in order to initialize the I ² CI / O expander 615 of all the decoration control devices 610 connected to the second master IC 570b, the second master IC 570b side that outputs initialization instruction data from the second master IC 570b Slave initialization start processing is executed (3704). Details of the slave initialization start process will be described with reference to FIG.

Further, the effect control device 550 waits until both the initialization stage number related to the first master IC 570 and the initialization stage number related to the second master IC 570b become “0” (3705). The initialization stage number is a number indicating the progress of the initialization process for each of the first master IC 570a and the second master IC 570b, and is “0” immediately after the presentation control device 550 is activated immediately after the power is turned on. However, when the initialization process is started, “1” to “4” are incremented one by one step by step, and when the initialization process is completed, it is returned to “0” again. Note that in the initialization instruction data transmission restart process described with reference to FIG. 42, the processes corresponding to the set initialization stage number values are sequentially executed. When the initialization of all masters and slaves is completed, The control device 550 permits the reception of the synchronization signal (VDP interrupt) synchronized with the image update cycle from the VDP 556 and the reception of the timer interrupt (3706).

  As described with reference to FIG. 36, the effect control device 550 executes slave output data saving processing for saving the effect control data stored in the RAM 553 so as not to be overwritten (3707). As described above, the output data saved in the save area is set in the master IC at a predetermined timing.

  Then, in order to display the image on display device 53, effect control device 550 outputs data serving as a command to display an image on VDP 556 (3708). Furthermore, sound control data is output to the sound LSI 557 in order to output sound from the speaker 30 according to the gaming state. The sound LSI 557 causes the speaker 30 to output sound based on the input sound control data (3709).

  Next, the effect control device 550 executes slave output start processing for outputting the effect control data from the first master IC 570a and the second master IC 570b to the decoration control device 610 (3710). The decoration control device 610 controlled here mainly controls a light emitter such as an LED, and is a light emission control device or a light emission control slave. Details of the slave output start processing will be described later with reference to FIG.

  When the slave output start process is completed, the effect control device 550 edits the next data output to the VDP 556 (3711), and further edits the sound control data output to the sound LSI 557 (3712).

  Further, the effect control device 550 executes a slave output data editing process for editing the effect control data to be transmitted to the decoration control device 610 that controls the light emitter (3713). In the slave output data editing process, as described with reference to FIG. 36, the production control data of each slave is generated and stored in the output data preparation area secured on the RAM 553. Details of the slave output data editing process will be described with reference to FIG.

  Next, the effect control device 550 refers to the abnormality determination table 3200 shown in FIG. 32, and executes an error determination process related to the light emission control slave connected to the first master IC 570a (3714).

  In the error determination process, the effect control device 550 determines whether or not the error flags 3205 of the entries corresponding to the light emission control slaves in the abnormality determination table 3200 are all “ON”, that is, an error occurs in all the light emission control slaves. It is determined whether or not. In other words, it is determined whether or not there is at least one light emission control slave in which the error flag 3205 is “OFF”. If it is determined by this error determination process that an error has occurred in all the light emission control slaves, the conditions for resetting all the light emission control slaves connected to the first master IC 570a and the first master IC 570a are satisfied. It is assumed that.

  The effect control device 550 determines whether or not the reset condition is satisfied based on the result of the error determination process in step 3714 (3715). As described above, when the error flags 3205 of all the light emission control slaves are “ON” at the time of the error determination process in step 3714, it is determined that the reset condition is satisfied.

When it is determined that the reset condition is satisfied (the result of 3715 is “Y”), the effect control device 550 initializes the first master IC 570a (3716), and all the I connected to the first master IC 570a. ² The first master IC 570a side slave initialization start process for simultaneously outputting initialization instruction data to the CI / O expander 615 is executed (3717).

As described above, when it is determined that the reset condition is satisfied, in step 3717, all the I ² CI / O expanders 615 connected to the first master IC 570a are instructed to initialize at the same time. To do. That is, since all the I ² CI / O expanders 615 are selected and initialized at the same time, it is faster than the method of individually selecting the I ² CI / O expanders 615 and instructing the initialization. The I ² CI / O expander 615 can be quickly returned to the normal state. At this time, the CPU 551 writes the initialization instruction information to the reset REG 573 via the bus 563, thereby resetting the first master IC 570a in software.

  If it is determined that the reset condition is satisfied in the process of step 3715, an abnormality may have occurred in the first master IC 570a. Therefore, the first master IC 570a is also initialized in the process of step 3716. Yes.

  Since the first master IC 570a functions as signal level control means for controlling the signal levels of the connection lines SDA and SCL in response to a command from the CPU 551, an abnormality relating to data transmission has occurred in all the light emission control devices. In this case, an abnormality may have occurred in the first master IC 570a itself.

  Therefore, if an abnormality related to data transmission occurs in all the decoration control devices 610, the first master IC 570a is initialized by the CPU 551 (arithmetic processing means) just in case. Thus, even if an abnormality has occurred in the first master IC 570a, the first master IC 570a can be reliably controlled.

  Further, the effect control device 550 similarly executes error determination processing for the second master IC 570b (3718), and determines whether or not the reset condition is satisfied (3719). If the reset condition is satisfied, the second master IC 570b is reset (3720), and the slave initialization start processing on the second master IC 570b side for initializing the slave connected to the second master IC 570b is executed. (3721). Thereafter, it waits until a synchronization signal is input from the VDP 556 to the CPU 551.

As described above, in the process shown in FIG. 37, the first master IC 570a and the second master IC 570b of the effect control device 550 synchronize with the cycle of updating the image of the display device 53, and the I ² CI / The effect control data is transmitted to the O expander 615. Since the I ² CI / O expander 615 controls the decoration device 620 based on the received effect control data, the effect on the display device 53 and the effect on the decoration device 620 are harmonized, giving the player an uncomfortable feeling. Because there is no, it can raise interest.

In addition, whenever the decoration control device 610 receives the effect control data transmitted from the first master IC 570a and the second master IC 570b in synchronization with the cycle of updating the image on the display device 53, the I ² CI / O is received. The expander 615 updates the value of the work register (see FIG. 24). Therefore, since the value of the work register is updated to the latest state every time, even if the value of the work register is destroyed due to noise or the like, it can be restored to a normal value.

  In addition, since the error determination process is executed in steps 3714 and 3718 in synchronization with the cycle of updating the image of the display device 53, the frequency for determining the error can be set appropriately. That is, if the error determination process is executed too frequently, the processing load on the CPU 551 of the effect control device 550 increases. Conversely, if the error determination process is executed too little, the occurrence of an abnormality can be detected at an appropriate timing. Disappear. By performing the error determination in synchronization with the cycle of updating the image of the display device 53, it becomes possible to detect the error at an appropriate timing, and to appropriately cope with the occurrence of a defect in each process.

  FIG. 38 is a flowchart illustrating a procedure of slave initialization start processing on the first master IC 570a side and slave initialization start processing on the second master IC 570b side according to the first embodiment of this invention.

  The slave initialization start process on the first master IC 570a side is executed in steps 3703 and 3717 in FIG. 37, and the slave initialization start process on the second master IC 570b side is the same process executed in step 3104 or step 3121. .

  In the initialization start process on the first master IC 570a side, first, the CPU 551 of the effect control device 550 prohibits master interruption and time interruption (3801). Then, the first master IC 570a is selected as the master to be initialized (3802).

  Further, in the slave initialization start process on the second master IC 570b side, the CPU 551 of the effect control device 550 prohibits the master interrupt and the time interrupt as in the first master IC 570a side slave initialization start process (3811). Then, the second master IC 570b is selected as the master to be initialized (3812).

  In the subsequent processes, a common process is executed for the selected master for the first master IC 570a side slave initialization start process and the second master IC 570b side slave initialization start process.

  The CPU 551 of the effect control device 550 sets “1” to the initialization stage number of the selected master (3803). Further, a monitoring timer for the selected master is set (3804), and timeout monitoring is started (3805).

  In response to the selected master command REG581, the CPU 551 of the effect control device 550 sets “1” for the STA, “1” for the STO, “0” for the SI, and “0” for the MODE (3806).

  As described above, the STA is a bit for instructing the output of the start condition, and the STO is a bit for instructing the output of the stop condition. A signal corresponding to the flag for which “1” is set is output. In the process of step 3806, signals of both a start condition and a stop condition are output.

  SI is a bit for notifying the occurrence of the aforementioned master interrupt. When “1” is set, the master IC requests the CPU 551 to generate an interrupt, and this bit is set to “0”. The master IC that generated the interrupt is in a state of waiting for processing until changed to. When the CPU 551 sets “0” to this bit, the interrupt generated in the CPU 551 is canceled, and the master IC waiting for processing resumes the next processing to be performed. In the process of step 3806, since “0” is set, the generation of the interrupt is canceled, and the master IC that has been waiting for the process resumes the operation.

  MODE is a bit for designating a mode for transmitting data. When “1” is set, “buffer mode” is designated, and when “0” is set, “byte mode” is designated. Is done. In step 3806, since “0” is set, data is exchanged in the byte mode.

  Thereafter, the CPU 551 permits a master interrupt and a timeout interrupt (3807), and returns to the caller.

  FIG. 39 is a flowchart illustrating a procedure of slave output start processing according to the first embodiment of this invention.

  The slave output start process is a process executed in step 3710 shown in FIG. 37, and is a process necessary for transmitting presentation control data from each master to the light emission control slave.

  The CPU 551 first prohibits the master interrupt and the time interrupt (3901). Next, the start flag corresponding to the first master IC 570a is set to “ON” (3902). Furthermore, the monitoring timer of the first master IC 570a is set (3903), and timeout monitoring processing is started (3904). The start flag is a flag indicating whether or not the start condition is output and the transmission of the production control data is started, and is set for each master IC. The start flag is stored in the RAM 553 of the effect control device 550.

  Further, in response to the command REG 581 of the first master IC 570a, the CPU 551 sets “1” to the STA, “1” to the STO, “0” to the SI, and “1” to the MODE (3905). In the processing of step 3905, since “1” is set in MODE, data is transmitted and received in the buffer mode.

  Similarly, for the second master IC 570b, the CPU 551 sets the start flag of the second master IC 570b to ON (3906). Further, a monitoring timer is set (3907), and timeout monitoring processing is started (3908). Further, for the command REG 581 of the second master IC 570b, “1” is set in the STA, “1” in the STO, “0” in the SI, and “1” in the MODE (3909).

  The CPU 551 selects the first slave (decoration control device 610) of each master (3910), and sets the retry counter to 0 (3911). The retry counter is a counter that is incremented when transmission fails when the production control data is transmitted to each master. When the retry counter becomes larger than a predetermined value, it can be determined that some trouble has occurred.

  Thereafter, the CPU 551 permits a master interrupt and a timeout interrupt (3912), and returns to the caller.

  FIG. 40 is a flowchart illustrating a procedure of slave output data editing processing according to the first embodiment of this invention.

  In the slave output data editing process, the output data preparation area secured on the RAM 553 of the effect control device 550 is updated. As described above, effect control data for transmission to the light emission control slave for each master IC is temporarily stored in the slave output data preparation area.

  The CPU 551 first determines whether or not the process currently being executed is the confirmation mode (4001). The confirmation mode is a mode for independently confirming the operation of the decoration device 620 provided in the front frame 3 or the center case 51 when a gaming machine is manufactured. The confirmation mode may be executed, for example, by operating a dedicated switch on the effect control device 550, or may be executed when the game control device 500 and the effect control device 550 are not connected. It may be. In the case of a gaming machine installed in a gaming store, the confirmation mode is not executed in a state where the gaming machine is normally operating.

  When the confirmation mode is not being executed (the result of 4001 is “N”), the CPU 551 writes the effect control data corresponding to the game effect in the slave output data preparation area of the decoration control device 610 that performs various effects (4002). ). Here, the effect control data is written in the slave output data preparation area for the decoration control device 610 that controls the decoration device 620 other than the reliability notification device 15. Next, effect control data is written in the slave output data preparation area corresponding to the decoration control device 610 for controlling the reliability notification device 15 (4003).

  On the other hand, when the confirmation mode is being executed (the result of 4001 is “Y”), the CPU 551 determines whether it is the confirmation output switching timing (4004). During the confirmation mode, the decoration device 620 to be confirmed performs an operation that sequentially lights up every second. Therefore, here, every time the switching time (1 second) elapses, a switching timing occurs. Each time, the decoration control device 610 to be confirmed is sequentially selected and controlled by the selected decoration control device 610. The decoration device 620 to be operated is operated. Thereby, if it is LED, it can be confirmed whether each LED operate | moves normally by lighting in order.

  At this time, if the decoration control device 610 to be controlled is installed adjacent to the signal cable, it is easy for the person who inspects the decoration device 620 to check, and the confirmation (inspection) efficiency is improved. In such a confirmation mode, it is generally considered that the operation of the decoration device 620 is confirmed according to the order of the individual addresses assigned to each decoration control device 610 (slave).

  Therefore, if wiring is performed so that the distance between the decoration control device 610 and the decoration device 620 is shortened, if the individual address values of the adjacent decoration control devices 610 are assigned consecutively, the confirmation (inspection) efficiency is further increased. It is thought to improve. In addition, if a symbol or number corresponding to an individual address is written on a board corresponding to each decoration control device 610, it becomes easier to check the decoration device 620 or the decoration control device 610 in operation. ) Increase efficiency.

  In other words, the confirmation output switching timing is a predetermined interval for confirming (inspecting) the decoration control device 610 as described above. In other words, it is the timing for ending the control of the decoration device 620 by the decoration control device 610 being inspected and executing the process for starting the control of the decoration control device 610 to be inspected next.

  If it is not the confirmation output switching timing (the result of 4004 is “N”), the CPU 551 ends this processing and returns to the caller. On the other hand, when it is the confirmation output switching timing (the result of 4004 is “Y”), the operation of the corresponding decoration device 620 is finished for the output data preparation area corresponding to the decoration control device (slave) 610 being confirmed. The data is updated so as to make it happen (4005). Further, in the output data preparation area of the decoration control device (slave) 610 to be checked next, the data is updated so as to start the operation of the corresponding decoration device 620 (4006). In this way, the operation of the decoration device 620 can be confirmed for each decoration control device (slave) 610 at a predetermined interval.

  FIG. 41 is a flowchart illustrating a processing procedure when a transmission interruption interrupt occurs on the first master IC 570a side and the second master IC 570b side according to the first embodiment of this invention.

  The transmission interruption interrupt is a so-called master interruption, and processing is executed according to the state at the time of interruption.

  First, when a master interrupt from the first master IC 570a occurs, the CPU 551 ends the time-out monitoring for the first master IC 570a (4101). Further, the initialization stage number and start flag of the first master IC 570a are acquired (4102).

  Similarly, when a master interrupt from the second master IC 570b occurs, the CPU 551 ends the time-out monitoring for the second master IC 570b (4111), and acquires the initialization stage number and start flag of the second master IC 570b. (4112).

  The CPU 551 determines whether or not the initialization stage number of the master IC to be initialized is “0” (4103). The case where the initialization stage number is “0” indicates a state where the initialization process has already been completed and the production control data is being transmitted.

  If the initialization stage number of the master IC to be initialized is not “0” (result of 4103 is “N”), the CPU 551 is in the initialization process as described above, and therefore the initialization instruction data A transmission resumption process is executed (4104). Details of the transmission restart process of the initialization instruction data will be described later with reference to FIG.

  On the other hand, when the initialization stage number of the master IC to be initialized is “0” (result of 4103 is “Y”), the CPU 551 is in the middle of transmitting the effect control data, and thus the effect control. Data transmission resumption processing is executed (4105). Details of the transmission restart process of the effect control data will be described later with reference to FIG.

  FIG. 42 is a flowchart illustrating a processing procedure when a timeout interrupt is generated by the first master IC 570a and the second master IC 570b according to the first embodiment of this invention.

  This process is a process executed to initialize each master IC when a timer interrupt occurs when the first master IC 570a or the second master IC 570b does not return after a predetermined time has elapsed. .

  When a timeout interrupt occurs in the first master IC 570a, the CPU 551 performs a soft reset on the first master IC 570a (4201). Further, a slave initialization start process (FIG. 38) on the first master IC 570a side for initializing the slave connected to the first master IC 570a is executed (4202).

  When a timeout interrupt occurs in the second master IC 570b, the CPU 551 performs a soft reset on the second master IC 570b (4211). Further, slave initialization start processing (FIG. 38) on the second master IC 570b side for initializing the slave connected to the second master IC 570b is executed (4212).

  FIG. 43 is a flowchart illustrating a procedure of initialization restarting data transmission restart processing according to the first embodiment of this invention.

  First, the CPU 551 determines whether the initialization stage number matches the status code (4301), and determines whether the initialization stage number matches the status code (4302). The initialization stage number is a number indicating the progress of the initialization process as described above. The status code is a value indicating the state of the master IC, and is set in the status register (REG) 582. In the consistency determination in the process of step 4301, it is determined whether or not the state corresponding to the initialization stage number matches the status code set in the status REG582. Details of the initialization stage number and status code will be described below.

  The initialization stage number is set to any value from “1” to “4” according to the processing stage when the master IC is being initialized. When completed, it is set to “0”. However, when the initialization of the master IC is completed and the initialization stage number becomes “0”, the transmission restart process of the initialization instruction data is not called (the branch of step S4003 in the caller process of FIG. 40). Therefore, the description will be made on the assumption that the initialization stage numbers are “1” to “4”.

  When “1” is set in the initialization stage number, it means that a start condition is output from the master IC. In this case, the status code is set to “08h” or “10h” indicating that a start condition or a restart condition has been transmitted. Therefore, if the initialization stage number is set to “1” and the status code is set to “08h” or “10h”, it is determined that they are consistent.

  When “2” is set in the initialization stage number, it means that the reset address is set in the output buffer 572 of the master IC. In this case, the status code indicates that the slave address (in this case, the reset address) has been transmitted and an ACK indicating that the signal has been normally received from each slave has been returned as “18h”. "Is set. However, the status code is set to “20h” when a NACK indicating that the signal cannot be normally received from each slave is returned. Therefore, if “2” is set in the initialization stage number and “18h” is set in the status code, it is determined that the data is consistent (success in data transmission). .

  When “3” is set as the initialization stage number, it means that the first half value of the reset command is set in the output buffer 572 of the master IC. In this case, the status code is “28h” indicating that the data set in the output buffer 572 has been transmitted and an ACK indicating that the signal has been normally received from each slave has been returned. Will be set. However, the status code is set to “30h” when a NACK indicating that the signal cannot be normally received from each slave is returned. Therefore, if “3” is set in the initialization stage number and “28h” is set in the status code, it is determined that the data is consistent (success in data transmission). .

  When “4” is set in the initialization stage number, it means that the latter half value of the reset command is set in the output buffer 572 of the master IC. In this case, as in the case where the initialization stage number is “3”, “28h” or “30h” is set in the status code.

  When the initialization stage number and the status code do not match (when the result of 4202 is “N”), the CPU 551 is not in a normal state (a state in which data transmission has failed), and thus indicates a value indicating the start of initialization. “1” is set as the initialization stage number (4203). Further, a monitoring timer is set, and timeout monitoring is started (4304).

  Finally, the CPU 551 outputs “1” to the STA of the command REG581 of the master IC to be processed, “1” to the STO, “0” to the SI, and “0” to the MODE so as to output the stop condition and the start condition. The setting is made (4305), and the process returns to the calling process.

  On the other hand, when the initialization stage number and the status code match (result of 4302 is “Y”), the CPU 551 branches the process based on the initialization stage number because the initialization process is being executed ( 4306). If the initialization stage number is “1”, a reset address is set in the output buffer 572 of the processing target master IC (4307).

  Then, the CPU 551 increments the initialization stage number (4308), sets a monitoring timer, and starts time-out monitoring (4309). Finally, in order to continue the processing, “0” is set in each of the STA, STO, SI, and MODE of the command REG 581 of the master IC to be processed (4305), and the processing returns to the calling source processing.

  If the initialization stage number is “2”, the CPU 551 sets the first half of the value indicating the reset command in the output buffer 572 of the master IC to be processed (4311). If the initialization stage number is “3”, the latter half of the value indicating the reset command is set in the output buffer 572 of the processing target master IC (4312). When a value is set in the output buffer 572, the processing from steps 4308 to 4310 is executed as in the case where the initialization stage number is “1”.

  When the initialization stage number is “4”, the CPU 551 has finished processing necessary for the initialization process, and therefore turns off the error flags of all the decoration control devices 610 connected to the master IC to be processed. Then, the error counter is set to 0 and initialized (4314). Then, the initialization stage number is set to “0”. Finally, in order to complete the initialization process and to output a stop condition from the master IC to be processed to all the decoration control devices 610 connected to the master IC, the STO of the command REG 581 of the master IC to be processed is output. “1”, STA, SI, and MODE are set to “0” (4316), and the process returns to the caller process.

  FIG. 44 is a flowchart illustrating a procedure of the transmission restart process of the effect control data according to the first embodiment of this invention.

  First, the CPU 551 determines whether the start flag matches the status code (4401), and determines whether or not they match (4402). The start flag is a flag for controlling the timing of transmitting the presentation control data for each of the first master IC 570a and the second master IC 570b. Specifically, when the slave output start process (FIG. 39) of FIG. 37 is executed, the start flag is set to “ON”. Further, as described later, when the production control data is set in the output buffer 572, the start flag is set to “off”. The status code is as described in FIG.

  The correspondence between the start flag and the status code will be described below. When the start flag is “ON”, as described above, since the start condition is output, the corresponding status code is “08h” or “10h”. On the other hand, when the start flag is “off”, if the process is normally performed, “28h” indicating that data transmission has been completed normally is set in the status code.

  If the start flag matches the status code (the result of 4402 is “Y”), the CPU 551 further determines whether the start flag is “ON” (4403).

  When the start flag is “ON” (the result of 4403 is “Y”), the CPU 551 sets the data prepared on the RAM 553 in the output buffer 572 (4404). Then, the start flag is set to “off” (4405), a monitoring timer is set, and timeout monitoring is started (4406). Finally, STA, STO and SI of the command REG 581 of the master IC to be processed are set to “0”, and MODE is set to “1” in order to transmit the data set in the output buffer 572 in the buffer mode. The setting is made (4407), and the process returns to the calling process.

  On the other hand, when the start flag is “OFF” (the result of 4403 is “N”), the CPU 551 sets the error flag corresponding to the selected slave (decoration control device 610) to “OFF” (4408). Further, an error counter is initialized (4409).

  Thereafter, the CPU 551 determines whether or not the transmission resumption process has been completed for all the slaves (4410). When the processing is completed for all the slaves (the result of 4410 is “Y”), a stop condition is output, and the STO of the command REG 581 is set so that the mode for transmitting data is designated as “buffer mode”. Then, “1” is set in MODE and “0” is set in STA and SI (4411), and the process returns to the calling process.

  If the processing has not been completed for all slaves (the result of 4410 is “N”), the CPU 551 sets the retry counter to 0 (4412) and selects the next slave to be processed (4413). ). Then, output data to the selected slave is prepared (4414), a start flag is set to “ON” (4415), a monitoring timer is set, and timeout monitoring is started (4416).

  Finally, the CPU 551 outputs a start condition, and sets “1” in STA and MODE of the command REG 581 and “0” in STO and SI so as to designate the mode for transmitting data as “buffer mode” (4417). ), Return to the calling process.

  If the start flag and the status code do not match (the result of 4402 is “N”), the CPU 551 increments the value of the retry counter (4418). Then, it is determined whether or not the value of the retry counter has reached the designated value (4419). The designated value at this time is set in the abnormality determination table 3200 or the abnormality determination table 3300 shown in FIG. 32 or 33, and corresponds to the comparison value 3204 corresponding to the currently selected slave.

  When the value of the retry counter has not reached the specified value (the result of 4422 is “N”), the CPU 551 selects the slave again during the current selection (4420), and prepares data to be output to the selected slave. (4414), the processing after step 4415 is executed.

  On the other hand, when the value of the retry counter reaches the specified value (result of 4422 is “Y”), the CPU 551 sets “ON” in the error flag 3205 of the selected slave, and the processing after step 4410 Execute.

  FIG. 45 is a flowchart illustrating a procedure of data transmission processing by the master IC according to the first embodiment of this invention. This process is common to the first master IC 570a and the second master IC 570b. When the CPU 551 sets “0” to the SI bit of the command register 581 (see FIGS. 11 and 12), the interrupt process is performed. The master IC that has been waiting due to the occurrence of this starts the processing.

  First, the controller 574 of the master IC determines whether or not output of a stop condition is requested, that is, whether or not “1” is set in the STO of the command REG 581 (4501).

  When the output of the stop condition is requested (the result of 4501 is “Y”), the controller 574 confirms the transmittable state (4502).

The confirmation of the transmittable state is to confirm whether or not data can be transmitted from the master IC to the I ² CI / O expander 615 of the decoration control device 610. Specifically, the confirmation of the connection line SDA is performed. This is to check whether the signal level is set to HIGH (connection line SDA is open). When the signal level of the connection line SDA is not set to HIGH, the process waits until the signal level of the connection line SDA is set to HIGH or time out.

  When it is determined that the signal level of the connection line SDA is not HIGH, data cannot be output from the connection line SDA. Therefore, the driver 576A does not apply an operable voltage to the transistor 578A without turning on the transistor 578A (connection). With the line SDA released, the signal level of the connection SCL is changed at least nine times.

By performing such processing, the I ² CI / O expander 615 that has entered the read mode outputs data to the connection line SDA in accordance with the change in the signal level of the connection SCL. In the middle of the change being performed at least nine times, a timing for confirming the acknowledge signal from the master IC occurs. At this time, since the connection line SDA is released, it becomes HIGH level, and the I ² CI / O expander 615 that has entered the read mode determines that it has not received an acknowledge signal, so it stops data transmission and disconnects the connection line SDA. Will be released.

In this way, the connection line SDA is forcibly released from the I ² CI / O expander 615 of the decoration control device 610 in the read mode, so that the signal level of the connection line SDA is maintained at HIGH. .

  Subsequently, the controller 574 outputs a stop condition to the connected slave (4503). Further, the transmission flag of the master IC is set to “off” (4504).

  The controller 574 further determines whether or not the output of the start condition is requested, that is, whether or not “1” is set in the STA of the command REG581 (4505). When the output of the start condition is requested (the result of 4505 is “Y”), the processing after step 4508 described later is executed.

  Further, when the output of the start condition is not requested (the result of 4505 is “N”), the controller 574 sets “F8H” in the status code (4506), and ends this processing.

  When the output of the stop condition is not requested (the result of 4501 is “N”), the controller 574 further determines whether or not the output of the start condition is requested, that is, the STA of the command REG581 is “1”. Whether or not is set is determined (4507). If the output of the start condition is requested (the result of 4507 is “Y”), the transmission possible state is confirmed (4508) as in the process of step 4502.

  If transmission is possible, the controller 574 outputs a start condition to the connected slave (4509). Further, the head byte identification flag of the master IC is set to “ON” (4510).

  Subsequently, the controller 574 determines whether or not the transmission flag is OFF (4511). If the transmission flag is not off, that is, if it is on (the result of 4511 is “N”), “10h” is set in the status code (4514). In this case, a stop condition is not output, but a start condition is output again, indicating that a so-called restart condition is output. Further, “1” is set to SI of the command REG 581 so as to generate a transmission interruption interrupt (4519), and this processing is interrupted.

  On the other hand, when the transmission flag of the master IC is off (the result of 4511 is “Y”), the controller 574 sets “08H” in the status code (4512). In this case, it is indicated that the start condition is output after the stop condition is output. Further, the transmission flag is set to “on” (4513), and in order to generate a transmission interruption interrupt, “1” is set to SI of the command REG581 (4519), and this processing is interrupted.

  When the output of the start condition is not requested (the result of 4507 is “N”), the controller 574 determines whether or not the leading byte identification flag of the master IC is on (4515). When the leading byte identification flag of the master IC is “ON”, that is, immediately after the start condition is output (the result of 4515 is “Y”), the first transmitted data is an address. Address recognition processing for recognizing the address is executed (4516). The details of the address recognition process will be described later with reference to FIG. 46. When the address recognition process ends, the head byte identification flag is set to “off” (4517), and a command is issued to generate a transmission interruption interrupt. “1” is set to the SI of the REG 581 (4519), and this processing is interrupted.

  When the first byte identification flag of the master IC is not “ON”, that is, when the address recognition is completed and the data body is transmitted (the result of 4515 is “N”), the controller 574 transmits the byte unit data. Processing is executed (4518). Details of the byte unit data transmission processing will be described later with reference to FIG. Finally, in order to generate a transmission interruption interrupt, “1” is set to SI of the command REG 581 (4519), and this processing is interrupted.

  FIG. 46 is a flowchart illustrating a procedure of address recognition processing according to the first embodiment of this invention.

  First, the controller 574 confirms the transmittable state by confirming whether the signal level of the connection line SDA is set to HIGH (4601). If the signal level of the connection line SDA is not set to HIGH, it waits until it is set to HIGH.

  Next, the controller 574 outputs the first bit data while operating the connection line SCL (4602). Then, it is determined whether transmission of 8-bit data is completed (4603), and data is sequentially output bit by bit while operating the connection line SCL until transmission of 8-bit data is completed (4604). .

  When the output of data of 8 bits is completed (the result of 4603 is “Y”), the controller 574 takes in the response signal transmitted from the slave (4605). Further, it is determined whether or not the content of the fetched response signal is “ACK” (4606). If the content of the response signal is not “ACK”, that is, if it is “NACK” indicating that data could not be received (the result of 4606 is “N”), this indicates that the address could not be recognized. “20h” is set in the status REG 582 as a status code (4607).

  On the other hand, if the content of the fetched response signal is “ACK” (the result of 4606 is “Y”), the controller 574 uses “18h” indicating that the address has been recognized as the status code and the status REG582. (4608). Further, it is determined whether or not the data transmission mode is the byte mode by determining whether or not the MODE value of the command REG 581 is “0” (4609). In the byte mode (the result of 4609 is “Y”), since the transmission of data for 1 byte (8 bits) has been completed, this process is terminated and the process returns to the caller process.

  When the data transmission mode is not the byte mode (the result of 4609 is “N”), the controller 574 executes the byte unit data transmission process (4611) until all the remaining data is transmitted (4610). Details of the byte unit data transmission processing will be described later with reference to FIG.

  FIG. 47 is a flowchart illustrating a procedure of byte-unit data transmission processing according to the first embodiment of this invention.

  First, the controller 574 confirms the transmittable state by confirming whether the signal level of the connection line SDA is set to HIGH (4701). If the signal level of the connection line SDA is not set to HIGH, it waits until it is set to HIGH. Subsequently, 1 byte of data is output (4702).

  After the data output, the controller 574 takes in the response signal output from the slave (4703). Further, it is determined whether or not the content of the fetched response signal is “ACK” (4604). If the content of the response signal is not “ACK”, that is, if it is “NACK” indicating that the data could not be received (result of 4604 is “N”), this indicates that the data could not be transmitted. “30h” is set as the status code (4705).

  On the other hand, when the content of the response signal fetched is “ACK” (result of 4704 is “Y”), the controller 574 sets “28h” indicating that the data has been transmitted as the status code. (4706). Further, it is determined whether or not the data transmission mode is the byte mode by determining whether or not the MODE value of the command REG 581 is “0” (4707). In the byte mode (the result of 4707 is “Y”), since the transmission of data of 1 byte (8 bits) has been completed, this process is terminated and the process returns to the caller process.

  If the data transmission mode is not the byte mode (the result of 4707 is “N”), the controller 574 transmits data until all the remaining data is transmitted (4708). Specifically, data to be transmitted next is prepared (4709), and the processing after step 4701 is executed again (4710).

  FIG. 48 is a timing diagram showing a state in which processing by the first master IC 570a and the second master IC 570b is executed in parallel according to an instruction from the CPU 551 of the effect control device 550 at the time of VDP interruption according to the first embodiment of this invention. It is a chart.

  In the first embodiment of the present invention, when a VDP interrupt occurs at the timing of updating the image displayed on the display device 53, the CPU 551 of the effect control device 550 outputs the effect control data to each master IC. Start. When each master IC receives the effect control data from the CPU 551, the master IC performs processing such as transmitting the received effect control data to each slave independently of the other master ICs. When the output of the effect control data is completed for all the slaves, each master IC outputs a stop condition and updates the effect mode of the effect device (decoration device 620) controlled by each slave.

  In this way, the processing by the first master IC 570a and the second master IC 570b is executed in parallel, and further, the effect that is harmonized with the image display is achieved by synchronizing the update timing of the effect mode of each effect device with the VDP interrupt. Can be performed.

  More specifically, when a VDP interrupt occurs, the CPU 551 of the effect control device 550 executes a slave output start process (steps 3710 and 39 in FIG. 37) and outputs a start condition to each master IC. .

  Then, CPU 551 edits output data to each device controlled by effect control device 550. Specifically, VDP output data editing for performing an effect on the display device 53 (step 3711 in FIG. 37), speaker-related data editing for outputting sound from the speaker 30 (step 3712 in FIG. 37), and an effect device Editing of the effect control data to be output to the decoration control device 610 that controls the LED (step 3713 in FIG. 37) and data editing for controlling a driving body such as a motor are performed. If a master interrupt to the CPU 551 is generated by each master IC during the execution of these editing processes, the edited effect control data is stored in the output buffer 572 of each master IC by the effect resumption data transmission restart process (FIG. 44). Written. Then, the effect control data is output to each slave by the data transmission process by the master shown in FIG.

  Finally, when the production control data is transmitted to all of the slaves to be transmitted, a stop condition is output from the master IC to the slave by the transmission restart process of the production control data (step S4411 in FIG. 44). The effect control data received by each slave is reflected in the effect mode of each effect device.

  Thereafter, the CPU 551 waits until the next VDP interrupt occurs. When the next VDP interrupt occurs, the slave output start process (steps 3710 and 39 in FIG. 37) is executed to output a start condition to each master IC, and thereafter the same process is repeated.

  Next, a configuration example of the grouped effect device (decoration device 620) will be described.

FIG. 49 shows a decoration device 620 constituting the reliability notification device 15 according to the first embodiment of the present invention and an I ² CI / O expander 615 of the decoration control device 610 that controls the reliability notification device 15. It is a figure which shows an example of a connection, and is a figure which shows the structure which controls LED for 8 sets by the ^two I2CI / O expanders 615. FIG.

  It is assumed that the decoration device 620 is configured by an LED as an example. By controlling the three colors of red (R), green (G), and blue (B) as one set, it is possible to emit light in various colors. Make it possible. For example, when all red, green, and blue LEDs are colored, white light can be emitted.

In the first embodiment of the present invention, one I ² CI / O expander 615 can control the LEDs corresponding to the 16 ports (PORT 0 to 15), so that there are three colors. Up to 5 sets of LEDs can be connected.

However, in order to produce an effect that further enhances interest, there may be a case where an LED (production device) is connected to more than 16 ports. FIG. 49 illustrates a configuration in which five or more sets (eight sets) of LEDs are connected and controlled across two I ² CI / O expanders 615.

As described above, since the I ² CI / O expander 615 includes 16 ports (PORT 0 to 15), it is possible to connect up to 5 sets of three color LEDs. However, when the presentation is performed with eight sets of LEDs as one group, at least two I ² CI / O expanders 615 are required.

Therefore, in the configuration shown in FIG. 49, one I ² CI / O expander 615 controls the red and green LEDs in each set, and the other I ² CI / O expander 615 (615b) The blue LED is controlled. Then, these two I ² CI / O expanders 615 are controlled as the same group, and, as will be described later with reference to FIG. 50, the effect control is executed simultaneously after receiving the stop condition output from the effect control device 550. As a result, it is possible to produce an effect by the LEDs controlled by the plurality of I ² CI / O expanders 615 without a sense of incongruity.

  FIG. 50 is a diagram illustrating the timing at which the decoration control device 610 receives data and controls the effect device according to the first embodiment of the present invention, and reflects the data received at the time when the stop condition is output. It is a figure explaining about.

In this figure, first, the start condition is output from the effect control device 550, then the effect control data is sequentially output from the effect control device 550 to the plurality of I ² CI / O expanders 615, and finally, the effect is displayed. A state in which a stop condition is output from the control device 550 is shown. For convenience of explanation, it is assumed that five I ² CI / O expanders 615 of the decoration control device 610 are provided, and each of them is a first I ² CI / O expander to a fifth I ² CI / O expander.

Here, “data1” in the figure indicates the effect control data transmitted from the effect control device 550 to the first I ² CI / O expander. Hereinafter, “data2” to “data5” The effect control data transmitted from the effect control device 550 to each of the ^{second I 2} CI / O expander to the fifth I ² CI / O expander is shown.

In the figure, “Production device (1)” indicates an LED connected to the I / O port of the first I ² CI / O expander. "-" effect device (5) "is the first 2I ² CI / O expander, second 5I ² CI / O Aix LED is connected to the expander of the I / O ports, etc., respectively correspond.

Incidentally, the effect control device 550, when transmitting the performance control data to the 1I ² CI / O expander, second 5I ² CI / O expander Each of timing for switching the selection of the I ² CI / O expander Thus, a start condition (functioning as a restart condition) is output from the effect control device 550 to the I ² CI / O expander. However, the period from when the effect control device 550 first outputs the start condition to when the effect control data is transmitted to all of the first I ² CI / O expander to the fifth I ² CI / O expander (in the figure). During the period indicated by T), the stop condition is not output, and the stop condition is output after the elapse of the period T.

In the first embodiment of the present invention, the effect control data is serially transmitted from the connection line SDA, so that there is a time difference in the timing at which the effect control data arrives for each I ² CI / O expander. Each I ² CI / O expander temporarily secures the received effect control data in a buffer (not shown) built in the bus controller 634 (FIG. 18) when receiving the effect control data from the effect control device 550. It ’s just that.

Here, it is assumed that each I ² CI / O expander independently performs a process that changes the LED light emission mode simultaneously with the reception of the effect control data. Since a time difference is caused in the change in the light emission mode of the LED, there is a possibility that an uncomfortable effect may be performed.

For example, as shown in FIG. 49, when red (R), green (G), and blue (B) LEDs are connected across a plurality of I ² CI / O expanders, There is a possibility that the LED emits light in a color that misleads the player. (In a game machine with a specification that the big hit is fixed if a specific light emitter glows red, when the big hit does not occur, the red LED and the blue LED in the light emitter are turned on simultaneously so that the light emitter emits purple light. In this case, since the red LED shines before the blue LED, it is misunderstood that the player is a big hit, causing trouble between the game store and the player. .)

Therefore, in the first embodiment of the present invention, when the stop condition is received from the effect control device 550, the effect control data in the buffer is overwritten in the output setting register 635, and the storage contents of the output setting register 636 are stored. The output controller 636 reflects it in the driver 637 and changes the light emission mode of the LED connected to the I ² CI / O expander.

Therefore, as shown in FIG. 50, when the stop condition is output, the effect control data received by each I ² CI / O expander can be simultaneously reflected in the output mode of each effect device, and an effect without a sense of incongruity is performed. It becomes possible.

In the present embodiment, the timing at which the effect control data received by the I ² CI / O expander is reflected in the output mode of each effect device is the time when the stop condition exemplified as the update command signal is received. The update command signal may be used. An update command signal that can be expressed by a signal change of the connection lines SDA and SCL even if it is transmitted in the middle of the transmission of the production control data, not limited to the one transmitted at the end of the production control data as in the stop condition If so, it is applicable.

Note that in the first embodiment of the present invention, each I ² CI / O expander 615 only receives the production control data from the master IC (when ACK is returned to the master IC), and thereafter When the stop condition is received, the received effect control data is reflected in the output mode of each effect device. Therefore, even if the stop condition is received afterward in the state where the effect control data cannot be correctly received from the master IC (the state where NACK is returned to the master IC), it is not reflected in the output mode of each effect device. The light emission state of the effect device does not change.

  According to the first embodiment of the present invention, even when the effect control device 550 individually selects a plurality of decoration control devices 610 and transmits different data for each decoration control device 610, the plurality of decoration controls. Even if the device 610 is selected at the same time and it is desired to transmit the same content data to each decoration control device 610, it is possible to cope with it as necessary, so that the data transmission form using one data line is diversified. can do.

  In particular, at the time of initialization instruction data transmission, it is possible to perform high-speed processing by transmitting data to each decoration control device 610 simultaneously. In addition, since the data can be individually transmitted to each decoration control device 610 at the time of transmitting the effect control data, fine control can be performed.

Furthermore, an X-bit address (see FIG. 19) that is longer than the Y-bit individual address (the 4-bit address set by A0 to A3 in FIG. 19) set in the I ² CI / O expander 615 of the decoration control device 610. The I ² CI / O expander 615 is specified using the 8-bit slave address shown in FIG.

  Further, when data is transmitted from the effect control device 550 to the decoration control device 610, a response signal is transmitted from the decoration control device 610 to the effect control device 550, so that it is possible to confirm whether or not data transmission has been performed. Can prevent malfunction.

  In particular, according to the first embodiment of the present invention, the effect control device 550 transmits data to the decoration control device 610 via one data line (connection line SDA), and the effect control device 610 controls the effect control. Since the response signal is also transmitted to the device 550 through the same data line, the wiring between the substrates can be reduced.

  Furthermore, according to the first embodiment of the present invention, the response signal is transmitted from the decoration control device 610 to the effect control device 550 immediately after the data is transmitted from the effect control device 550 to the decoration control device 610. Data communication is possible.

  Further, even when a general-purpose master IC is used as the master IC of the effect control device 550, it is possible to prevent the master IC from erroneously shifting to a state of waiting for a command from another master IC. .

  In particular, when data is transmitted by designating an address from the effect control device 550 to the decoration control device 610, even if the level on the data line indicates an abnormality due to the occurrence of noise or the like, the general purpose of the effect control device 550 It is possible to prevent the master IC from erroneously shifting to a state of waiting for a command from another master IC.

  In addition, the production control device 550 specifies each decoration control device 610 sequentially every predetermined time, and performs the inspection easily by controlling the designated decoration control device 610 to operate the production device. Is possible.

  On the other hand, according to the first embodiment of the present invention, the timing at which the data captured by the decoration control device 610 is reflected as the output mode of the effect device is controlled by the signal level change of the SCL line and the SDA line. Thus, a signal such as a conventional LAT signal is not necessary because it is determined by an update command signal (for example, a stop condition). This eliminates the need for wiring for transmitting the LAT signal, and makes it possible to simplify the wiring.

  In addition, individual effect control data can be transmitted to the plurality of decoration control devices 610 using the same signal line, and the output mode of the effect device can be updated simultaneously.

  In particular, by setting the update command signal as a stop condition, the timing to be reflected as the output mode of the effect device can be specified at the same time as the end of data transmission, so that the data is simplified.

Further, even when the effect device includes a large number of illuminants provided with light emitting elements having different colors, control is performed using a plurality of I ² CI / O expanders 615 of the decoration control device 610. ² Signal lines can be connected without being restricted by the limit on the number of outputs per CI / O expander (up to 16 ports or the like).

At this time, even if different I ² CI / O expanders are used, it is possible to update the light emitting elements at the same time, so that it is possible to express a color without a sense of incongruity.

  Further, in the case where the effect control data is transmitted to a plurality of decoration control devices 610 that control the notification device (reliability notification device 15), an update command signal is obtained only by successful data transmission to some decoration control devices 610. Without receiving a notification that the effect control information has been normally received from all the decoration control devices 610 that control the notification device, and outputting an update command signal, the notification device is abnormal. It is possible to control so that the color is not displayed, and it is possible to prevent display that causes confusion for the player.

Even if the effect control device 550 fails to transmit the effect control data, the decoration control device 610 that controls the notification device performs an accurate display by controlling the output mode not to be updated when an error occurs. Can be done. In this case, since the decoration control device 610 that controls the notification device is controlled by the single I ² CI / O expander 615, the light emission state is reliably updated in the notification device.

On the other hand, according to the first embodiment of the present invention, the branch type decoration control device 610 is configured to branch and connect data lines to a plurality of wiring boards (decoration control device 610). Therefore, unlike the conventional shift register, there is no need to daisy chain the wiring boards with the data lines, and the wiring can be simplified. Therefore, it is possible to further branch and connect data lines at the decoration control device 610 on the downstream side, and the signal lines from the production control device 550 (group control unit) to the I ² CI / O expander 615 of the decoration control device 610. Therefore, it is possible to reduce the overall length of the network and realize a communication environment in which data transmission errors are unlikely to occur.

  In the first embodiment of the present invention, the first master IC 570a (first signal level control means) controls the effect device provided in the game board 10, and the second master IC 570b (second signal level). Control means) is configured to control the effect device provided in the front frame 3. Thus, when developing the front frame 3 and the game board 10 by making the effect device provided in the game board 10 and the effect device provided in the front frame 3 into different groups, the decoration control device. Since it is only necessary to consider the upper limit number of 610 limited to each group to be developed, it is possible to improve development efficiency, for example, by developing devices in parallel for each configuration.

Furthermore, according to the first embodiment of the present invention, the master IC is selected by the CPU 551, and the plurality of decoration control devices 610 (I ² CI / O expander 615) connected to the selected master IC are Since the initialization is performed collectively, a high-speed initialization process can be performed as compared with a method of selecting and initializing the decoration control devices 610 one by one.

  At this time, it is possible to perform control such that only the decoration control device 610 connected to the selected master IC is initialized and the decoration control device 610 connected to another master IC that is not selected is not initialized.

  Therefore, since only the decoration control device 610 belonging to the minimum necessary range can be initialized among all the decoration control devices 610 provided in the gaming machine, the decoration control device 610 is initialized and the effect device. The frequency at which the operation of 200 is interrupted can be reduced.

  Further, according to the first embodiment of the present invention, when all the master ICs are to be reset, a hard reset is performed. Therefore, each master IC is soft reset one by one. In comparison, initialization can be performed at high speed.

  On the other hand, when a part of the master ICs is to be reset, the initialization is executed by a soft reset via the data bus. Therefore, it is complicated to input signals individually to the initialization signal input terminals of all the master ICs. It is sufficient to provide one port without requiring a simple circuit. In other words, all master ICs that are always executed at the time of startup can be reset at high speed, and only a part of master ICs that are executed only in an emergency can be reset with a simplified circuit. Therefore, this is particularly effective in a configuration with a large number of master ICs.

  Further, according to the first embodiment of the present invention, since the processes by the master IC operate in parallel, high-speed processing is possible. Further, since the effect mode of the effect device is controlled to be synchronized with the screen update timing, the effect of light emission in harmony with the screen display becomes possible.

(Second Embodiment)
In the first embodiment of the present invention, the decoration control device 610 is connected to only one master IC that is controlled by itself (configured by a single master system). A network configuration (multi-master configuration) in which a plurality of master ICs are connected to the control device 610 is also conceivable.

  In such a network configuration, only one of the plurality of master ICs acquires the bus transmission right, and the master IC that has acquired the transmission right transmits data to other ICs. Accordingly, processing for transferring the transmission right to another master IC is required. In addition, since it is assumed that data is transmitted from the master IC that has acquired the transmission right to the master IC that does not acquire the transmission right, an address equivalent to the slave address (FIG. 23) is also set in the master IC itself. It is necessary to keep it.

  Therefore, when developing a highly versatile master IC that can be used in a multi-master network (hereinafter referred to as a general-purpose master IC), the general-purpose master IC itself has a function capable of setting a slave address. . When the general-purpose master IC receives data intended for data transmission to the slave address set in itself, the master IC itself is configured to function as a slave thereafter.

  Hereinafter, as a second embodiment, an embodiment for avoiding a problem that occurs when such a general-purpose master IC is used in a gaming machine will be disclosed.

  However, although the general-purpose master IC itself has a function for supporting the multi-master system, the disclosed network configuration is a single-master configuration as in the first embodiment. Therefore, in the following description of the embodiment, the same reference numerals are given to the configuration and processing common to the first embodiment, and the description is omitted.

  FIG. 51 shows a case where the start condition is detected by the connection lines SCL and SDA while the master IC (general-purpose master IC) according to the second embodiment of the present invention waits for a command from the CPU 551. It is a flowchart which shows the procedure of the process performed in FIG.

  The controller 574 first clears the comparison buffer (4801). The comparison buffer is a buffer for receiving an address transmitted from another master IC and temporarily storing the received address for comparison with the slave address of the master IC itself.

  Next, the controller 574 takes in the data of the first bit while operating the connection line SCL (4802). Further, the fetched data is fetched into the comparison buffer (4803). Then, it is determined whether or not the 8-bit data has been captured (4804), and the transmission of the 8-bit data is completed in response to the signal change of the connection line SCL output from another master IC. The data is sequentially fetched for each bit (4805).

  When the capture of the 8-bit data is completed, the controller 574 collates the value captured in the comparison buffer with its own slave address stored in the self address setting REG 583 (4806). Then, it is determined whether or not the value captured in the comparison buffer matches its own address (4807). If the address does not match (4807 result is “N”), NACK is output to the transmission source. The connection line SDA is set to H level (4808).

  On the other hand, when the value fetched in the comparison buffer matches its own address (the result of 4807 is “Y”), the controller 574 sets the connection line SDA to L level in order to output ACK to the transmission source. Set (4809). Further, based on the value of the eighth bit of the received data, it is determined whether or not it is a read request (4810). When the value of the 8th bit of the received 8-bit data is “1”, it becomes a read request, and when it is “0”, it becomes a write request.

  In the case of a read request (the result of 4810 is “Y”), the controller 574 sets the status code “B0H” in the status REG582. On the other hand, in the case of a write request (the result of 4810 is “N”), the status code “68H” is set in the status REG582. Thereafter, this process is interrupted, and an interrupt is generated in the CPU 551 of the effect control device 550.

  FIG. 52 is a flowchart illustrating a procedure of address recognition processing according to the second embodiment of this invention. In the first embodiment, when the address recognition process in step S4516 in FIG. 45 is executed, the address recognition process in FIG. 46 is called, but the general-purpose master IC in the second embodiment performs step S4516 in FIG. When executing the address recognition process of FIG. 52, the address recognition process of FIG. 52 is called instead of FIG.

  First, the controller 574 clears the comparison buffer that temporarily stores the received address (4901).

  Subsequently, in order to output an address to the decoration control device 610 (slave), the controller 574 confirms the transmission possible state by confirming whether the signal level of the connection line SDA is set to HIGH (4902). ). If the signal level of the connection line SDA is not set to HIGH, it waits until it is set to HIGH. Then, the first bit data is output while operating the connection line SCL (4903).

  Further, the controller 574 acquires the signal level from the connection line SDA (4904) and loads it into the comparison buffer (4905). Then, the fetched data and the output data are compared (4906), and it is determined whether or not they match (4907).

  If the fetched data matches the output data (the result of 4907 is “Y”), the controller 574 determines whether or not 8-bit data has been output (4908).

  If the output of 8-bit data has not been completed (the result of 4908 is “N”), the controller 574 outputs the first bit data while operating the connection line SCL (4909). Further, the processing after step 4905 is executed.

  When the output of data of 8 bits is completed (the result of 4908 is “Y”), the controller 574 takes in a response signal transmitted from the slave (4910). Further, it is determined whether or not the content of the fetched response signal is “ACK” (4911). If the content of the response signal is not “ACK”, that is, if it is “NACK” indicating that data could not be received (result of 4911 is “N”), this indicates that the address could not be recognized. “20h” is set in the status REG 582 as a status code (4912).

  On the other hand, when the content of the fetched response signal is “ACK” (the result of 4911 is “Y”), the controller 574 sets “18h” indicating that the address has been recognized as the status code and the status REG 582. (4913). Further, it is determined whether or not the data transmission mode is the byte mode by determining whether or not the MODE value of the command REG 581 is “0” (4914). In the byte mode (the result of 4914 is “Y”), since the transmission of data of 1 byte (8 bits) is completed, this process ends and the process returns to the caller process.

  When the data transmission mode is not the byte mode (the result of 4914 is “N”), the controller 574 executes the byte unit data transmission process (4916) until all the remaining data is transmitted (4915). The details of the byte-unit data transmission processing are as described in FIG. 47 in the first embodiment.

  On the other hand, if the fetched data and the output data do not match (result of 4907 is “N”), it is determined whether or not 8-bit data has been fetched (4917). If 8-bit data has not been captured (the result of 4917 is “N”), it corresponds to the signal change of the connection line SCL output from another master IC until the transmission of the 8-bit data is completed. Then, data is sequentially acquired for each bit (4918), and the captured data is captured in the comparison buffer (4919).

  When the capture of the 8-bit data is completed, the controller 574 collates the value captured in the comparison buffer with the slave address stored in the address setting REG 583 (4920). Then, it is determined whether or not the value captured in the comparison buffer matches its own slave address. If there is a match, the connection line SDA is set to L level in order to output ACK to the transmission source. If not, the connection line SDA is set to the H level in order to output NACK to the transmission source (4921).

  Further, the controller 574 determines whether or not the received data is a read request. If the request is a read request, the controller 574 sets “B0H” as the status code in the status REG 582, and if the request is a write request, sets “68H” as the status code. ”Is set. As described above, when the value of the eighth bit of the received 8-bit data is “1”, a read request is made, and when it is “0”, a write request is made. If the process fails, “38H” is set as the status code. Then, this process is terminated and the process returns to the caller.

  Thus, in the second embodiment of the present invention, the general-purpose master IC can function as a slave. Such a master IC is configured to function as a slave thereafter when the presentation control data in which an address that matches the address set in the address setting REG 583 is specified is received.

  However, when the general-purpose master IC is used in a single master network, it may be inconvenient for the general-purpose master IC itself to function as a slave. That is, if a signal requesting data transmission to the slave address of the general-purpose master IC itself is generated by the influence of noise or the like, the general-purpose master IC may be recognized as its own address.

At this time, the general-purpose master IC does not output the effect control data to the controlled slave (decoration control device 610), and transitions to a state of waiting until the effect control data is transmitted from another master IC that should not exist. Will end up. Alternatively, when an I ² CI / O expander 615 incorporating a circuit that functions as a master is used (an I ² CI / O expander having an extended function may be used), for example, the master Even if the mode is set not to use the function, the master function of the I ² CI / O expander 615 may operate at an unexpected timing due to the influence of noise or the like. Assuming such a situation, once the general-purpose master IC misrecognizes the address, the rendering device is no longer controlled by the general-purpose master IC.

  FIG. 53 shows a network in which a plurality of general-purpose master ICs used in the second embodiment of the present invention are connected (use in a multi-master environment). FIG. 10 is a diagram illustrating a state in which a collision occurs on the bus because data specifying a destination address is output upward.

  When two general-purpose master ICs (master A and master B) connected on such a network simultaneously output data on the data line (SDA line), the data line (SDA line) itself is pulled up. Therefore, if the signal level of any one of the general-purpose master ICs is LOW level, the signal level of the bus is set to LOW level. Therefore, the LOW level output has priority over the HIGH level output and is output on the bus.

  Then, the general-purpose master IC captures the signal level of the data line (SDA line) while outputting data to the data line (SDA line) (step S4909 in FIG. 52) (step S4904 in FIG. 52), and outputs itself. By checking whether the signal level is reflected on the bus (step S4906 in the figure), the collision with the data output from the other general-purpose master IC is monitored.

  At this time, if the signal level output by itself is reflected on the bus (YES in step S4907 in the figure), data is output continuously (step S4909 in the figure). If the signal level is not reflected on the bus (NO in step S4907 in the figure), the data output from itself is stopped to pass the transmission right to another general-purpose master IC, and the bus The processing shifts to processing for fetching the above data (steps S4917 to 4919 in the figure).

  In FIG. 53, when master A and master B are simultaneously outputting data specifying a destination address on the data line (SDA line), master B outputs at the timing indicated by the arrow in the figure. This shows a state where the master B has given the transmission right to the master A because the data on the bus is different from the data on the bus. At this time, the master A functions as a master, and if the address output from the master A matches the slave address set in the master B, the master B functions as a slave.

  As described above, the general-purpose master IC has an advantage of high convenience because the function is expanded so that it can be used even in the environment of a mast master. On the other hand, when the general-purpose master IC is used in a single master environment, the extended function may be harmful. An example is shown below.

  FIG. 54 shows a transmission destination on a data line (SDA line) even though the general-purpose master IC (master A) used in the second embodiment of the present invention is in a single master system environment. This indicates a state in which the above-mentioned extended function malfunctions and the master functions as a slave because noise is generated while data specifying the address is output.

  In the state shown in FIG. 54, the bit string “1011...” Is intended to be transmitted as an address. However, due to noise, the fourth bit is recognized as “0” instead of “1” in the bus data line. As a result, it has become “10101111”.

As described above, the general-purpose master IC has a function of monitoring the address value on the data line for each bit at the time of address transmission to the slave. If it is different from the transmission address, it is assumed that a signal is output from another master, and the subsequent output is stopped, and the level of the data line is held high. Even if it is held, since it is an open drain output, if there is an I ² CI / O expander 615 that changes the data line to LOW, the data line is set to the LOW level.

  At this time, the general-purpose master IC determines whether the data “10101111” generated on the bus matches the slave address set in itself, and if they match, the general-purpose master IC functions as a slave. End up.

  In other words, if the slave address of the general-purpose master IC is “10101111”, the effect control data is not transmitted to the decoration control device 610 since it functions as a slave thereafter.

Therefore, in the second embodiment of the present invention, the address set for each master IC is selected from those not used as the slave address of the I ² CI / O expander 615 (slave address 2301 in FIG. 23). Is set. With such a configuration, even if the address of the decoration control device 610 generated on the bus is read, it is erroneously determined that the slave address is set in the master IC itself, and the general-purpose master IC functions as a slave. Will not be lost.

As a precaution, the address generated when the lower (n + 1) bits of the slave address (slave address 2301 in FIG. 23) of the I ² CI / O expander 615 is replaced with a specific pattern is also used for each master. It is preferably not used as a slave address set in the IC.

  Specifically, the low-order (n + 1) bits of the slave address (slave address 2301 in FIG. 23) expressed by X (X = 8) bits are “0” at the beginning, and the subsequent n bits Those having a bit pattern such that “1” is “1” are preferably not used as slave addresses set in each master IC.

For example, as illustrated in FIG. 54, as the slave address of the I ² CI / O expander 615, if include the 8-bit pattern of "1011 ‥‥" is the lower 5 bits of the bit pattern " It is not preferable to use the value “10101111” replaced by “01111” as the slave address of the master IC.

  By setting in this way, even if the address output by the master IC itself changes to an abnormal level on the bus due to the influence of noise or the like (the bus becomes LOW level when HIGH level is output) Since it is rare that noise is generated more than once during address transmission, the frequency of coincidence with the slave address set in the master IC itself is extremely low.

  In the second embodiment of the present invention, “54h” is set as the address of the master IC. “54h” is “01010100b”, and the lower (n + 1) bits of any address listed in the slave address 2301 in FIG. 23, the first bit is “0”, and the subsequent n bits are “1”. Even if it is replaced with a bit pattern that becomes such that “01010100b” is not formed.

  According to the second embodiment of the present invention, even when a general-purpose master IC capable of functioning as a slave by an extended function is used, the effect control device 550 erroneously functions as a slave (in other words, Thus, it is possible to prevent a transition from waiting to a command from another master IC.

  Furthermore, according to the second embodiment of the present invention, when data is transmitted by designating an address from the effect control device 550 to the decoration control device 610, the level on the data line indicates an abnormality due to the occurrence of noise or the like. Even in this case, it is possible to prevent the effect control device 550 from functioning as a slave by mistake (in other words, shifting to a state of waiting for a command from another master IC).

(Third embodiment)
In the first embodiment of the present invention, all the decoration control devices 610 are controlled equally. However, in the third embodiment, in order to control an important performance device (decoration device 620) more reliably. In addition, for the decoration control device 610 that controls an important performance device, the transmission processing is repeated many times until the transmission of the performance control data is completed. Specifically, the reliability notification device 15 that can make a player have a sense of expectation and improve the interest is controlled more reliably than other effect devices.

  First, in the third embodiment of the present invention, the decoration control devices 610 are grouped, and the control timing is changed for each group. The reliability notification device 15 is controlled by the first master IC 570a. Furthermore, since the first master IC 570a also controls the decoration device 620 other than the reliability notification device 15 provided in the game board 10, a slave that controls the decoration device 620 other than the reliability notification device 15 provided in the game board 10 is used. Grouping is performed by setting the decoration control device 610 that controls the decoration device 620 included in the reliability notification device 15 as the game effect group and the reliability notification group.

  Further, if a failure occurs in the reliability notification device 15, there is a risk that the wrong reliability will be notified and the interest may be lost. Therefore, the decoration control device 610 belonging to the reliability notification group has an effect control. The transmission process is repeated many times until the data is reliably transmitted. However, when it is determined that the production control data for some of the decoration control devices 610 belonging to the reliability notification group is impossible, immediately including other decoration control devices 610 belonging to the reliability notification group. Control is performed so that the production is performed as accurately as possible by resetting.

  Hereinafter, the configuration and procedure necessary for controlling the gaming machine 1 in this way will be described. First, FIG. 55 and FIG. 56 show an example of the abnormality determination table of the first master IC 570a of the third embodiment of the present invention. Further, referring to FIG. 57 and FIG. 58, the difference from the first embodiment is shown. The procedure will be described mainly.

  The abnormality determination table of the first master IC 570a according to the third embodiment of the present invention is composed of two abnormality determination tables, an abnormality determination table 5200 corresponding to the game effect group and an abnormality determination table 5300 corresponding to the reliability notification group. Has been.

  FIG. 55 is a diagram illustrating the abnormality determination table 5200 corresponding to the game effect group according to the third embodiment of this invention.

  The abnormality determination table 5200 corresponding to the game effect group has the same format as the abnormality determination table 3200 of the first embodiment. However, this abnormality determination table 5200 excludes the decoration control device 610 (addresses “1001” and “1010”) belonging to the reliability notification group. The second master IC 570b is the same as that in the first embodiment (FIG. 33).

  FIG. 56 is a diagram illustrating the abnormality determination table 5300 corresponding to the reliability notification group according to the third embodiment of this invention.

  As described above, in the decoration control device 610 (addresses “1001” and “1010”) belonging to the reliability notification group, transmission is repeated many times until the presentation control data is reliably transmitted, but it is determined that transmission is impossible. When it is done, it is controlled to be reset immediately. Therefore, the error counter 3203, the comparison value 3204, and the error flag 3205 are not required, and only the I / O expander address 3201 and the slave address 3202 are included.

  FIG. 57 is a flowchart illustrating a procedure of slave output start processing according to the third embodiment of this invention.

  The slave output start process is a process executed in step 3710 shown in FIG. 37 in the first embodiment, and is executed instead of the slave output start process in the first embodiment shown in FIG.

  In the third embodiment of the present invention, a “time division counter” in which “0” or “1” is set as a value is introduced, and the slave to be selected is switched based on the value of the time division counter. This will be specifically described below.

  First, the CPU 551 of the effect control device 550 updates the time division counter (5401). Here, when the value of the time division counter is “0”, it is updated to “1”, and when it is “1”, it is updated to “0”. The processing from step 5401 to step 5402 after step 5401 is the same as the processing from step 3901 to 3909 in FIG.

  When the CPU 551 instructs the first master IC 570a and the second master IC 570b to output the stop condition and the start condition, the CPU 551 selects the decoration control device (slave) to be controlled by the first master IC 570a based on the value of the time division counter. Select (5411-5413).

  Specifically, the CPU 551 determines whether or not the value of the time division counter is “0” (5411). If the value of the time division counter is “0” (the result of 5411 is “Y”). ) In order to control only the decoration device 620 other than the reliability notification device 15 from all the decoration devices 620 controlled by the first master IC 570a, the first slave of the game effect group is selected (5412). ). On the other hand, when the value of the time division counter is “1” (the result of 5411 is “N”), only the decoration device 620 included in the reliability notification device 15 is controlled. The first slave is selected (5413).

  Subsequently, the CPU 551 selects the first slave of the second master IC 570b (5414). Further, the retry counter is set to 0 (5415), the master interrupt and the timeout interrupt are permitted (5416), and the process returns to the caller.

  It is to be noted that the control of the decoration device 620 provided in the front frame 3 controlled by the second master IC 570b is controlled at the same timing as the decoration device 620 provided in the game board 10, and is included in the reliability notification device 15. Only the decoration device 620 to be controlled may be configured to perform detailed control.

  FIG. 58 is a flowchart illustrating a procedure of the transmission restart process of effect control data according to the third embodiment of the present invention.

  The transmission restart process of the effect control data is a process executed in step 4133 shown in FIG. 41, but in the third embodiment, when the above-described time division counter is “0” (control of the game effect group is performed). 44), the resumption process of production control data shown in FIG. 44 is executed as in the first embodiment. When the above-described time division counter is “1” (control of the reliability notification group is performed). In the case of performing), instead of the process shown in FIG. 44, the transmission control process for effect control data shown in FIG. 58 is executed.

  In the third embodiment, the decoration control device 610 that performs reliability notification repeats the reception process many times until the presentation control data is reliably received. However, when the timeout occurs and it is determined that the reception is impossible. The production control device 550 immediately resets. A procedure for controlling in this way will be described with reference to the flowchart shown in FIG.

  First, the CPU 551 of the effect control device 550 determines whether the start flag matches the status code (5501), and determines whether or not they match (5502). When the slave output start process (FIG. 55) is executed, the start flag is set to “on”. When the production control data is set in the output buffer 572, “OFF” is set in the start flag.

  If the start flag matches the status code (the result of 5502 is “Y”), the CPU 551 further determines whether the start flag is “ON” (5503).

  If the start flag is “ON” (the result of 5503 is “Y”), the CPU 551 sets the data prepared on the RAM 553 in the output buffer 572 (5504). Then, the start flag is set to “off” (5505), a monitoring timer is set, and timeout monitoring is started (5506). Finally, STA, STO and SI of the command REG 581 of the master IC to be processed are set to “0”, and MODE is set to “1” in order to transmit the data set in the output buffer 572 in the buffer mode. The setting is made (5507), and the process returns to the calling process.

  On the other hand, when the start flag is “OFF” (the result of 5503 is “N”), the CPU 551 determines whether or not the transmission resumption processing is completed for all the slaves belonging to the reliability notification group. (5508). When the processing is completed for all the slaves (result of 5508 is “Y”), a stop condition is output, and the STO of the command REG 581 is set so that the mode for transmitting data is designated as “buffer mode”. Then, “1” is set in MODE and “0” is set in STA and SI (5509), and the process returns to the calling process.

  If the processing has not been completed for all the slaves belonging to the reliability notification group (the result of 5503 is “N”), the CPU 551 selects the next slave to be processed (5511). Then, output data to the selected slave is prepared (5512), a start flag is set to “ON” (5513), a monitoring timer is set, and timeout monitoring is started (5514).

  Finally, the CPU 551 outputs a start condition, and sets “1” to STA and MODE of the command REG 581 and “0” to STO and SI so as to designate the mode for transmitting data as “buffer mode” (5515). ), Return to the calling process.

  If the start flag and the status code do not match (the result of 5502 is “N”), the CPU 551 determines that the presentation control data is not correctly transmitted to the slave, and selects the currently selected slave again. (5510), data to be output to the selected slave is prepared (5512), and the processing after step 5513 is executed.

  In this way, when the production control data is not correctly transmitted to the slave, the first master IC 570a repeats data transmission many times until the production control data is reliably transmitted. However, if the set monitoring timer expires during repeated transmission, a timeout interrupt is generated in the CPU 551 and the first master IC 570a is initialized. At this time, all the decoration control devices 610 connected to the first master IC 570a are also initialized.

(Fourth embodiment)
In the first embodiment of the present invention, since a plurality of decoration control devices 610 belonging to the reliability notification group are provided, the reliability notification device 15 is required unless the operation timings of the decoration control devices 610 are synchronized. There is a risk that the LED used in the game may cause unexpected color development and confuse the player.

  Therefore, if the LED used in the reliability notification device 15 is controlled by the single decoration control device 610, it is not necessary to synchronize the operation timings of the plurality of decoration control devices 610, and the processing is simplified. can do. Hereinafter, the fourth embodiment of the present invention will be disclosed.

  FIG. 59 is a diagram illustrating a connection example of the decoration control device 610 and the decoration device 620 according to the fourth embodiment of the present invention, and illustrates a configuration in which five sets of LEDs are controlled by one decoration control device 610. It is. With such a configuration, since the light emission state of the five sets of LEDs connected to the decoration control device 610 is updated at the same time, the problem of unexpected color development is solved.

Note that, similarly to the first embodiment, the decoration control device 610 (I ² CI / O expander 615) shown in FIG. 59 also has only the effect control data received from the first master IC 570a. 1 ACK is returned to the master IC 570a. Thereafter, the decoration control device 610 updates the light emitting state of the connected LED at the timing when the stop condition is received from the first master IC 570a.

However, as in the first embodiment, the decoration control device 610 (I ² CI / O expander 615) shown in FIG. 59 is also unable to correctly receive the effect control data from the first master IC 570a. NACK is returned to the first master IC 570a. In this case, even if the decoration control device 610 receives a stop condition from the first master IC 570a, the lighting state of the connected LED is not updated.

The decoration control device 610 (I ² CI / O expander 615) updates the light emission state of the connected LED at the timing when the stop condition is received from the first master IC 570a. 15 is configured to be controlled by a single decoration control device 610, even if the light emission state of the connected LED is switched at a timing other than the reception timing of the stop condition from the first master IC 570a. no problem. Below, the modification of such a structure is shown.

  FIG. 60 shows a modification of the fourth embodiment of the present invention. When the decoration control device 610 receives data, when the ACK is output to the master IC, the received data is stored in the LED. It is a figure explaining the case where it reflects in a light emission state.

  As shown in FIG. 60, at the time of ACK output, each slave specifies the specific effect device by controlling the timing of transmitting the effect control data by reflecting the effect control data in the output mode of the effect device. It becomes possible to control with.

  According to the fourth embodiment of the present invention, when the master IC fails to transmit the production control information, the decoration control device 610 that controls the reliability notification device 15 does not update the output mode of the notification device. Therefore, it is possible to perform control so that an abnormal color is not displayed on the notification device, and it is possible to prevent display that causes confusion for the player.

  It should be noted that the embodiments disclosed in the present specification are naturally intended to be applicable not only to pachinko machines but also to other gaming machines such as pachislot machines.

  Also, as an embodiment, a pachinko machine that generates a special game state corresponding to the result of the variable display game is disclosed, but not limited to the variable display game, the special game corresponding to the result of other auxiliary games Of course, it may be a gaming machine that generates a state.

  For example, when a predetermined condition is satisfied, an entrance of a specific winning device is opened (the movable member of the specified winning device is actuated to open the entrance), and a game ball taken into the winning device is provided inside the winning device. A game in which lottery is selected for which winning area (there is a specific winning area or a general winning area) may be used as an auxiliary game. In this case, a special game state occurs when the game ball taken into the winning device wins a specific winning area.

  Also, as an embodiment, a pachinko machine that generates a special game state corresponding to the result of the special figure variation display game is disclosed, but in response to the result of the general figure fluctuation display game (or It is naturally intended that the present invention can be applied even to a pachinko machine that generates a special gaming state (due to the result of the display game). For example, even a pachinko machine that generates a special game state when the entrance of a specific winning device is opened according to the result of the normal game display game and a game ball taken into the winning device wins a specific winning area. The present invention is applicable.

  Further, as an embodiment, a configuration in which the game control device and the effect control device are separated is disclosed, but the game control device and the effect control device constitute a single control device. Of course, it is intended that the game control device itself may be configured as a group overall control means.

  The embodiment disclosed this time is illustrative in all points and is not restrictive. The scope of the present invention is shown not by the above description of the invention but by the scope of the claims, and is intended to include all modifications within the scope and meaning equivalent to the scope of the claims.

  As described above, the present invention can be applied to a gaming machine in which a plurality of decoration control devices are controlled by an effect control device.

1 gaming machine 2 body frame (outer frame)
3 Front frame (game frame)
9a, 9b Decoration member 10 Game board 12 Auxiliary game device unit 13 First movable illumination 13a Illumination drive first motor (MOT)
14 Second movable illumination 14a Illumination drive second motor (MOT)
15 Reliability notification device 29 Abnormality notification LED
30 Speakers 45 Side lamps 51 Center case 53 Display device 58 Movable effect device 63 First effect unit 64 Second effect unit 70 First effect member 71 The accessory drive first motor (MOT)
80 2nd production member 81 Second article drive second motor (MOT)
500 Game control device 550 Production control device 570a First master IC
570b Second master IC
581 Command register (REG)
582 Status register (REG)
583 Self-address setting register (REG)
600 Relay board 603 Empty terminal monitor 610 Decoration control device 615 I ² CI / O expander 620 Decoration device 625 Decoration device board 1600 Simple relay board 3200, 3300, 5200, 5300 Abnormality determination table

Claims (1)

Game control means for overall control of the game;
A plurality of directing devices for directing games;
An image output device for outputting an image relating to a game effect;
In response to a command from the game control means, an effect control means for controlling the plurality of effect devices,
Dividing the plurality of effect devices into a plurality of groups, and providing group unit control means for each group to control the effect devices belonging to the divided group,
It said presentation control means, constitutes a pre-SL group unit control means as a group supervisory controlling means for centrally controlling,
Timing signal line for transmitting a timing signal to the group-unit control unit from the group supervisory controlling means, and the group unit and the group supervisory controlling means by a data line for transmitting data to the group-unit control unit from the group supervisory controlling means Control means is connected to enable data transmission between the group overall control means and each group unit control means,
The group overall control means is:
The connection is made by repeatedly changing the signal level of the timing signal line while setting the signal level of the data line to the signal level corresponding to the transmission data in synchronization with the update period of the image output to the image output device. and transmitting means for sequentially transmitting data in units of groups control means are,
By controlling the signal level of the data line and the timing signal line in a different manner from the time of data transmission in the middle of data transmission by the transmission means or at the last timing of data transmission, a predetermined update command signal is Update command signal output means for outputting to the group unit control means,
With
The group unit control means includes:
A common address that is common among the group unit control means and an individual address that is different between the group unit control means are assigned in advance,
As the common address, at least a first common address used during initialization and a second common address used during control other than initialization are allocated,
Determine the content of the address included in the data transmitted from the group overall control means,
When it is determined that the address is an individual address addressed to itself or the second common address, the transmitted data is captured as control information, and the rendering device is controlled based on the control information.
When it is determined that the address is the first common address, the transmitted data is taken as initialization instruction information, and is initialized based on the initialization instruction information.
Capture means for capturing data transmitted by the transmission means;
Output mode update means for updating the output mode of the rendering device in correspondence with the data captured by the capture unit;
And the output mode update means updates the output mode of the effect device at the timing of receiving the update command signal.