JP5560932B2 - Clock distribution circuit and semiconductor circuit device including the circuit - Google Patents

Clock distribution circuit and semiconductor circuit device including the circuit Download PDF

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JP5560932B2
JP5560932B2 JP2010135770A JP2010135770A JP5560932B2 JP 5560932 B2 JP5560932 B2 JP 5560932B2 JP 2010135770 A JP2010135770 A JP 2010135770A JP 2010135770 A JP2010135770 A JP 2010135770A JP 5560932 B2 JP5560932 B2 JP 5560932B2
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clock
phase
wiring
circuit
signal
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JP2012004697A (en
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聡 松原
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富士通株式会社
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Description

  The present invention relates to a clock distribution circuit for distributing a clock signal and a semiconductor circuit device including the clock distribution circuit.

  When the reference clock is transmitted over a wide range in the semiconductor chip, the clock is generally distributed using a buffer tree.

  When distributing clocks using a buffer tree, consideration is given to matching the phases of a plurality of clocks output from a plurality of final buffers. That is, in the design of the buffer tree, the number of buffer stages or the wiring distance is adjusted. More specifically, in the design of the buffer tree, the phase delay caused by the parasitic capacitance in the buffer tree from the reference clock input terminal to the output terminal of the final buffer and the phase delay due to the buffer are made substantially the same. Processing is performed.

However, in the buffer tree over a wide range, due to manufacturing variations when manufacturing semiconductor chips or operating conditions of semiconductor circuits in the semiconductor chips, variations in parasitic capacitance in the wiring and variations in buffer characteristics, which are unexpected at the time of design, are not possible. May occur. (See Patent Document 1.)
As a result, a non-negligible phase difference may occur between a plurality of clocks output from a plurality of final buffers.

JP 2004-145443 A

  Clock distribution circuit capable of reducing manufacturing variations at the time of manufacturing a semiconductor chip or phase differences between a plurality of clocks output from a plurality of final buffers caused by operating conditions of a semiconductor circuit in the semiconductor chip The purpose is to provide.

  In order to solve the above problems, according to a first aspect of the present invention, there is provided a clock distribution circuit disposed in a circuit device, wherein the clock distribution circuit is connected to a ring-shaped clock wiring and the clock wiring, An oscillation circuit that generates a first clock signal in a clock wiring; and two or more phase adjustment circuits that are arranged at two or more locations in the circuit device and output a second clock signal, respectively, and phase adjustment Each circuit receives the first clock signal having a phase corresponding to the arrangement location, and the second clock signal output by each phase adjustment circuit is more than the phase difference between the first clock signals received by each phase adjustment circuit. There is provided a clock distribution circuit characterized in that adjustment is performed to reduce the phase difference.

  To provide a clock distribution circuit capable of reducing a phase difference between a plurality of clocks output from a plurality of final buffers due to manufacturing variations at the time of manufacturing a semiconductor chip or operating conditions of a semiconductor circuit in the semiconductor chip. Can do.

FIG. 1 shows a clock distribution circuit 10 and a semiconductor circuit device 80 according to the first embodiment. 2A and 2B are diagrams illustrating the phase adjustment circuit 30a. FIG. 3 is a diagram illustrating the clock distribution circuit 100 and the semiconductor circuit device 180 according to the second embodiment. FIG. 4 is a diagram showing the clock generation circuit 110. FIG. 5 is a diagram illustrating the arrangement of the clock wirings 211 and 212 according to the third embodiment. FIG. 6 is a diagram illustrating the arrangement of the clock wirings 311 and 312 according to the fourth embodiment. FIG. 7 is a diagram illustrating the arrangement of the clock wirings 411 and 412 according to the fifth embodiment. FIG. 8 is a diagram illustrating the arrangement of the clock wirings 511 and 512 according to the sixth embodiment.

  The present invention includes the embodiments described below that have been modified by the design that can be conceived by those skilled in the art, and those in which the components shown in the embodiments have been recombined. Further, the present invention includes those in which the constituent elements are replaced with other constituent elements having the same operational effects, and are not limited to the following embodiments.

  FIG. 1 shows a clock distribution circuit 10 and a semiconductor circuit device 80 according to the first embodiment. The semiconductor circuit device 80 includes a clock distribution circuit 10 and other internal circuits 20a, 20b, 20c, 20d, and 20e.

The semiconductor circuit device 80 is a semiconductor circuit device included in a semiconductor chip. Note that the semiconductor circuit is not limited to be included in one semiconductor chip, and may be a semiconductor circuit included across a plurality of semiconductor chips.
The internal circuits 20a, 20b, 20c, 20d, and 20e are distributed in the semiconductor chip and are block circuits that contribute to executing a predetermined function. In the first embodiment, the number of internal circuits is five blocks, but is not limited to five blocks.
The clock distribution circuit 10 is a circuit that distributes a clock signal serving as an operation reference to the internal circuits 20a, 20b, 20c, 20d, and 20e arranged in the semiconductor chip.

The clock distribution circuit 10 includes clock lines 60 and 70, an LC oscillation circuit 40, phase adjustment circuits 30a, 30b, 30c, 30d, and 30e, amplifiers 31a, 32a, 31b, 32b, 31c, 32c, 31d, 32d, 31e, and 32e. The variable capacitor 50 is included.
The clock wiring 60 is a clock wiring through which a clock signal generated by oscillation propagates, and has a loop shape. The clock wiring 70 is a clock wiring through which a complementary clock signal of the clock signal propagates, and has a loop shape.

The LC oscillation circuit 40 is an oscillation circuit including a capacitor 45, inductors 44 and 43, and inverters 42 and 41. The capacitor 45 is connected to the clock wirings 60 and 70 at both ends thereof.
The inductor 44 is an inductor included in series with the loop-shaped clock wiring 60. The inductor 43 is an inductor included in series with the loop-shaped clock wiring 70.
The inverter 41 receives a signal propagating through the clock wiring 70 and outputs the inverted signal to the clock wiring 60. The inverter 42 receives a signal propagating through the clock wiring 60 and outputs the inverted signal to the clock wiring 70. A clock signal and a complementary clock signal propagate through the inverters 41 and 42 without being attenuated through the clock lines 60 and 70. The variable capacitor 50 is connected to the clock lines 60 and 70 at both ends thereof. The variable capacitor 50 is a capacitor whose capacity changes upon receiving a signal. When the capacitance of the variable capacitor 50 changes, the capacitance between the clock wiring 60 and the clock wiring 70 changes, so that the frequency of the clock signal generated by self-oscillation by the LC oscillation circuit 40 and its complementary clock signal change.
As described above, the LC oscillation circuit 40 and the variable capacitor 50 generate clock signals having a predetermined cycle in the clock wiring 60 and the clock wiring 70.
Here, the phase of the clock signal received by the phase adjustment circuits 30a, 30b, 30c, 30d, and 30e is not affected by manufacturing variations in manufacturing a semiconductor chip or operating conditions of the semiconductor circuit. This is because the parasitic capacitance of the clock wiring is partially affected by manufacturing variations, but this does not partially change the frequency of the clock signal propagating to the entire clock wiring. Further, the frequency of the clock signal propagating to the clock wiring does not change depending on the operating conditions of the inverters 41 and 42 included in the LC oscillation circuit 40. This is because the clock wiring is ring-shaped, and the phase of the clock signal generated by self-oscillation is limited to 360 degrees when the clock wiring goes around.

The phase adjustment circuits 30a, 30b, 30c, 30d, and 30e are arranged so that clock signals 60 and 70 having a clock signal having a different phase and a complementary clock signal corresponding to each point are provided at the points where the respective phase adjustment circuits are arranged. The phase adjustment of the clock signal received by each phase adjustment circuit is performed. As a result, each of the phase adjustment circuits 30a, 30b, 30c, 30d, and 30e outputs a substantially in-phase clock signal. That is, each of the phase adjustment circuits 30a, 30b, 30c, 30d, and 30e outputs the clock signal whose phase difference is adjusted to approximately 0 degrees or its complementary clock signal to the corresponding amplifier 31a, 32a, 31b, 32b, 31c, 32c. , 31d, 32d, 31e, and 32e. Details of the phase adjustment circuit will be described with reference to FIGS. 2A and 2B.
The amplifiers 31a, 32a, 31b, 32b, 31c, 32c, 31d, 32d, 31e, and 32e are clock signals from the phase adjustment circuits 30a, 30b, 30c, 30d, and 30e or their complementary clock signals and corresponding internal circuits 20a. , 20b, 20c, 20d, and 20e.

2A and 2B are diagrams illustrating the phase adjustment circuit 30a. Each phase adjustment circuit 30a, 30b, 30c, 30d, 30e includes similar circuit elements.
The phase adjustment circuit 30a includes an amplifier that outputs the signal A and its complementary signal AX, an amplifier that outputs the signal Out and its complementary signal Outx, and an interpolator circuit.

The amplifier that outputs the signal A and its complementary signal AX is an amplifier for generating a delayed signal A and its complementary signal AX from the input signal IN and its complementary signal INX, and includes a resistor 30a1, a resistor 30a2, and an N-type transistor 30a5. 30a6 and a constant current circuit 30a7.
The resistor 30a1 is connected to the high voltage power supply Vcc and the drain of the N-type transistor 30a5. The source of the N-type transistor 30a5 is connected to the constant current circuit 30a7, receives the input signal INX at the gate, and outputs the signal A from the source.
The resistor 30a2 is connected to the high voltage power supply Vcc and the drain of the N-type transistor 30a6. The source of the N-type transistor 30a6 is connected to the constant current circuit 30a7, receives the input signal IN at the gate, and outputs the signal AX from the source.
The constant current circuit 30a7 is connected to the N-type transistors 30a5 and 30a6 at one terminal and connected to the ground power supply at the other terminal.

An amplifier connected to a terminal for outputting the signal Out and its complementary signal Outx is an amplifier for generating a signal Out and a signal Outx having a delay associated with the interpolator circuit from the input signal IN and its complementary signal INX. A resistor 30a3, a resistor 30a4, N-type transistors 30a8 and 30a9, and a constant current circuit 30a10 are included.
The resistor 30a3 is connected to the high voltage power supply Vcc and the drain of the N-type transistor 30a8. The source of the N-type transistor 30a8 is connected to the constant current circuit 30a9, receives the input signal IN at the gate, and outputs the signal Outx from the source.
The resistor 30a4 is connected to the high voltage power supply Vcc and the drain of the N-type transistor 30a9. The source of the N-type transistor 30a9 is connected to the constant current circuit 30a10, receives the input signal INX at the gate, and outputs the signal Out from the source.
The constant current circuit 30a10 is connected to the N-type transistors 30a8 and 30a9 at one terminal and connected to the ground power supply at the other terminal.

  The interpolator circuit includes N-type transistors 30a11 and 30a12 and a constant current circuit 30a13. The N-type transistor 30a11 is connected from the drain to the terminal that outputs the signal Out, receives the signal AX at the gate, and is connected to the constant current circuit 30a13 at the source. The N-type transistor 30a12 is connected from the drain to the terminal that outputs the signal Outx, receives the signal A at the gate, and is connected to the constant current circuit 30a13 at the source.

  When the driving capability of the constant current circuit 30a7 is “1”, the driving capability of the constant current circuit 30a10 is “k1”, and the driving capability of the constant current circuit 30a13 is “k2”, the relationship of k1 + k2 = 1 is established.

FIG. 2B is a diagram illustrating operation waveforms of the phase adjustment circuit 30a. In FIG. 2B, the uppermost waveform represents the input signal IN to the phase adjustment circuit 30a and its complementary signal INX. The logic of the input signal IN and its complementary signal INX changes at time T1.
In FIG. 2, the middle waveform represents the signal output from the amplifier that outputs the signal A and its complementary signal AX. The signals A and AX change in logic at time T2 with a delay of Td from the logic change of the input signals IN and INX. This is because the signal is delayed by the amplifier that outputs the signal A and its complementary signal AX.
In FIG. 2, the lower waveform shows the signal Out and the complementary signal Outx which are output signals from the interpolator. The logic of the signal Out and the complementary signal Outx changes at time T3 with a delay of (1 + k2) × Td from time T1.
This is because the signal A and the signal AX are further delayed by k2 × Td by the interpolator and the amplifier connected to the terminal that outputs the signal Out and its complementary signal Outx.

As described above, the phase adjustment circuit 30a can adjust the phase according to the current capability k2 of the constant current circuit 30a7 included in the interpolator.
Therefore, since each phase adjustment circuit 30a, 30b, 30c, 30d, 30e includes the same circuit elements as the phase adjustment circuit 30a, when the clock signal is similarly received as an input signal, it is output from each phase adjustment circuit. The phase of the clock to be adjusted can be adjusted according to the current capability of the constant current circuit of each interpolator.
Therefore, if the current capability of the constant current circuit of the interpolator is set according to the place where each phase adjustment circuit 30a, 30b, 30c, 30d, 30e is arranged, each phase adjustment circuit 30a, 30b, 30c, 30d, and 30e output substantially in-phase clock signals.
In the example of the first embodiment, the phase of the clock signal is about 0 degrees near the phase adjustment circuit 30b, and the phase of the clock signal is about 90 degrees near the phase adjustment circuit 30c. Similarly, the phase of the clock signal is about 160 degrees near the phase adjustment circuit 30d, the phase of the clock signal is about 200 degrees near the phase adjustment circuit 30e, and the phase of the clock signal is about 270 degrees near the phase adjustment circuit 30a. It is. Therefore, the phase adjustment circuit 30c performs adjustment so as to reduce the phase of 90 degrees to 0 degree, and the phase adjustment circuit 30d performs adjustment so as to reduce the phase of 160 degrees to 0 degree, thereby adjusting the phase. In the circuit 30e, an adjustment is made so that the phase of 200 degrees is reduced to 0 degree, and in the phase adjustment circuit 30a, an adjustment is made so that the phase of 270 degrees is reduced to 0 degree.

From the above, the clock distribution circuit 10
Ring-shaped clock wiring,
An oscillation circuit connected to the clock wiring and generating a first clock signal in the clock wiring by self-oscillation;
Two or more phase adjustment circuits arranged in each of the two or more locations and outputting the second clock signal in the circuit device,
Each of the phase adjustment circuits receives a first clock signal having a phase corresponding to an arrangement location, and each of the phase adjustment circuits outputs a phase difference between the first clock signals received by each of the phase adjustment circuits. Adjustment is performed to reduce the phase difference between the second clock signals.
As described above, the phase of the clock signal received by the phase adjustment circuits 30a, 30b, 30c, 30d, and 30e is not affected by manufacturing variations in manufacturing a semiconductor chip or operating conditions of the semiconductor circuit. .
As a result, the clock distribution circuit 10 according to the first embodiment is different from the internal circuits 20a, 20b, 20c, 20d, and 20e that are distributed in the semiconductor circuit 80 in that the phase adjustment circuit corresponds to each position. By adjusting the phase of the clock signal, it is possible to distribute substantially the same phase clock signal regardless of manufacturing variations and operating conditions of the semiconductor circuit.

  Here, in the first embodiment, the clock signal propagating in the ring-shaped clock wiring is generated by the self-oscillation circuit connected to the clock wiring, which exists in the circuit device. However, the clock signal propagating in the ring-shaped clock wiring may be a clock signal input from the outside of the circuit device or a clock signal synchronized with the clock signal.

  FIG. 3 is a diagram illustrating the clock distribution circuit 100 and the semiconductor circuit device 180 according to the second embodiment. The semiconductor circuit device 180 includes a clock distribution circuit 100 and other internal circuits 20a, 20b, 20c, 20d, and 20e.

The semiconductor circuit device 180 is a semiconductor circuit device included in a semiconductor chip. Note that the semiconductor circuit is not limited to be included in one semiconductor chip, and may be a semiconductor circuit included across a plurality of semiconductor chips.
The internal circuits 20a, 20b, 20c, 20d, and 20e are the same circuits as those with the same reference numerals in the first embodiment.
The clock distribution circuit 100 is a circuit that distributes a clock signal serving as an operation reference to the internal circuits 20a, 20b, 20c, 20d, and 20e arranged in the semiconductor chip.

The clock distribution circuit 100 includes clock wirings 60 and 70, a clock generation circuit 110, phase adjustment circuits 30a, 30b, 30c, 30d, and 30e, amplifiers 31a, 32a, 31b, 32b, 31c, 32c, 31d, 32d, 31e, and 32e. including. Of the circuits described above, the other circuits except the clock generation circuit 110 are the same circuits as those in the first embodiment.
The clock generation circuit 110 will be described with reference to FIG.

FIG. 4 is a diagram showing the clock generation circuit 110. The clock generation circuit 110 includes a phase frequency comparison circuit 111, a charge pump 112, a low-pass-filter 113, a frequency divider 114, and an oscillation circuit 115.
The phase frequency comparison circuit 111 is a circuit that compares the phases of a reference clock signal input from the outside of the clock distribution circuit 100 and a signal obtained by dividing the clock signal propagating through the clock wirings 60 and 70. Further, the phase frequency comparison circuit 111 sequentially outputs the comparison result as a pulse signal corresponding to the comparison result. The pulse signal according to the comparison result means that, for example, the Halth width, the pulse frequency, the pulse voltage, and the like are in accordance with the comparison result. The reference clock may be a signal generated in the semiconductor circuit device 180 or a signal given from the outside of the semiconductor circuit device 180.

The charge pump 112 is a circuit that supplies a charge corresponding to a pulse signal corresponding to the comparison result to the Low-Pass-Filter 113.
The Low-Pass-Filter 113 outputs a signal indicating a state corresponding to the supplied charge amount. Note that the signal indicating the state corresponding to the charge amount means, for example, that the voltage level of the signal is a voltage level corresponding to the charge amount.

The oscillation circuit 115 is a voltage-controlled oscillator, and the frequency of the clock signal generated changes according to the signal voltage level of the signal from the Low-Pass-Filter 113. Variable capacitors 116a and 116b, inductances 116c and 116d, and inverters 116e and 116f are included.
The variable capacitor 116 a and the variable capacitor 116 b are arranged in series between the clock wiring 60 and the clock wiring 70, the variable capacitor 116 a is connected to the clock wiring 60, and the variable capacitor 116 b is connected to the clock wiring 70. Yes. Further, a signal line from the Low-Pass-Filter 113 is connected to an intermediate node to which the variable capacitor 116a and the variable capacitor 116b are connected, and the signal line represents a state corresponding to the charge amount. A signal is output. Accordingly, the capacitance added to the clock wirings 60 and 70 by the variable capacitors 116a and 116b changes according to the voltage level of the signal representing the state corresponding to the charge amount. Note that the basic capacitance values of the variable capacitors 116 a and 116 b can be set in advance according to the frequency of the clock signal desired to be generated by the oscillation circuit 115. Here, the basic capacitance value refers to a capacitance value when the signal voltage level of a signal representing a state corresponding to the charge amount is an initial value.

The inductances 116c and 116e are inductances arranged in series with the clock wirings 60 and 70 as part of the clock wirings 60 and 70, respectively. Therefore, the frequency of the clock generated in the clock wirings 60 and 70 is determined by the capacitance added to the clock wirings 60 and 70 by the variable capacitors 116a and 116b and the inductances of the inductances 116c and 116d.
The inverter 116 e is connected to the clock wiring 60 through an input terminal, and outputs an inverted signal of the signal propagated to the clock wiring 60 to the clock wiring 70. The inverter 116 f is connected to the clock wiring 70 through an input terminal, and outputs an inverted signal of the signal propagated to the clock wiring 70 to the clock wiring 60. The clock signals generated in the clock lines 60 and 70 are maintained by the inverters 116e and 116f.
The frequency divider 114 is a circuit that divides the frequency of the clock signal propagating in the clock wirings 60 and 70. Here, the frequency divider 114 divides the clock signal so as to match the frequency of the reference clock.

In the clock generation circuit 110 described above, the divided clock signal obtained by dividing the clock signal generated by the oscillator 115 is compared with the reference clock by the phase frequency comparison circuit 111 in frequency and phase. Is done. The result is fed back to the oscillator 115 using the charge pump 112 and the Low-Pass-Filter 113. Then, the divided clock signal and the reference clock match in frequency and phase. Therefore, the clock generation circuit 110 has a function of generating a clock signal synchronized with the reference clock on the clock wirings 60 and 70.
As a result, the phase of the clock signal received by the phase adjustment circuits 30a, 30b, 30c, 30d, and 30e is not affected by manufacturing variations in manufacturing a semiconductor chip or operating conditions of the semiconductor circuit. This is because the parasitic capacitance of the clock wiring is partially affected by manufacturing variations, but this does not partially change the frequency of the clock signal propagating to the entire clock wiring. Further, the frequency of the clock signal propagating to the clock wiring does not change depending on the operating conditions of the inverters 116e and 116f included in the clock generation circuit 110. This is because the clock generation circuit 110 itself feeds back the phase of the clock signal generated by the clock generation circuit 110 so that the phase of the clock signal becomes 360 degrees when the clock wiring is rotated once.

From the above, the clock distribution circuit 100
Ring-shaped clock wiring,
An oscillation circuit connected to the clock wiring and generating a first clock signal in the clock wiring in synchronization with an externally input clock;
Two or more phase adjustment circuits arranged in each of the two or more locations and outputting the second clock signal in the circuit device,
Each of the phase adjustment circuits receives the first clock signal having a phase corresponding to the arrangement location, and each of the phase adjustment circuits outputs a phase difference between the first clock signals received by each of the phase adjustment circuits. Adjustment is performed to reduce a phase difference between the second clock signals.
Here, the clock distribution circuit 100 according to the second embodiment generates a clock signal synchronized with an external clock signal given from the outside, and distributes the clock signal to the internal circuits 20a, 20b, 20c, 20d, and 20e. Circuit.
In addition, as described above, the phase of the clock signal received by the phase adjustment circuits 30a, 30b, 30c, 30d, and 30e depends on manufacturing variations when manufacturing semiconductor chips and operating conditions of the semiconductor circuits. There is no.
Therefore, in the clock distribution circuit 100 of the second embodiment as well as the clock distribution circuit 10 of the first embodiment. With respect to the internal circuits 20a, 20b, 20c, 20d, and 20e distributed in the semiconductor circuit 80, the phase adjustment circuit adjusts the phase of the clock signal corresponding to each position. Thus, it is possible to distribute a clock signal having substantially the same phase, which is not affected by the operating conditions of the semiconductor circuit.

In the first and second embodiments, the clock wirings 60 and 70 do not cross each other. The clock wiring 60 forms an outer peripheral ring, and the clock wiring 70 forms an inner peripheral ring.
However, the clock wirings 60 and 70 are not always installed on the outer periphery or the inner periphery. That is, when setting the equal lengths of the clock lines 60 and 70, setting the clock lines to the center of the semiconductor chip, and the like, the clock lines 60 and 70 may intersect each other.

FIG. 5 is a diagram illustrating the arrangement of the clock wirings 211 and 212 according to the third embodiment. The third embodiment is a modification in which clock wirings 211 and 212 are arranged as shown in FIG. 5 instead of the clock wirings 60 and 70 in the first embodiment. Therefore, the semiconductor circuit device 200 according to the third embodiment includes a modification of the clock distribution circuit 10 in which the clock wirings 211 and 212 are replaced, and internal circuits 20a, 20b, 20c, 20d, and 20e.
The clock distribution circuit 10 according to the third embodiment has a modification example in which the clock wirings 211 and 212, the LC oscillation circuit 40, the phase adjustment circuits 30a, 30b, 30c, 30d, and 30e, the amplifiers 31a, 32a, 31b, 32b, and 31c, 32c, 31d, 32d, 31e, 32e, and variable capacitor 50 are included. Since the constituent elements other than the clock wirings 211 and 212 are the same as the constituent elements described in the first embodiment, description thereof will be omitted.

The clock wirings 211 and 212 are arranged so as to pass through the outer peripheral portion of the semiconductor chip and have a ring shape.
When a signal is output from the circuit inside the semiconductor chip to the outside of the semiconductor chip, it is usually performed via a metal pad formed on the outer periphery of the semiconductor chip. Therefore, the input / output circuit is arranged close to the metal pad in order to drive external addition such as a metal pad. Therefore, in many cases, internal circuits 20a, 20b, 20c, 20d, and 20e are arranged inside the input / output circuit.
Therefore, the outer peripheral portion generally refers to a region where input / output circuits are arranged in a semiconductor chip, for example.
By the way, in Example 3, the clock wirings 211 and 212 have the intersection 1 and the intersection 2 at the upper right and lower left corners of the semiconductor chip shown in FIG. As a result, the clock wirings 211 and 212 are switched between the outer periphery and the inner periphery at the intersection 1 and the intersection 2. Then, the wiring lengths of the clock wirings 211 and 212 are approximately equal.
Note that the intersection does not mean a point where the clock wiring 211 intersects with the clock wiring 212 but a point where the clock wirings appear to overlap each other when they intersect three-dimensionally. That is, the insulation between the clock wirings is maintained. Furthermore, when the clock wiring 211 and the clock wiring 212 are three-dimensionally crossed, it is assumed that only one clock wiring is close to the other clock wiring.

  As described above, the modification of the clock distribution circuit 10 according to the third embodiment is characterized in that the clock wiring has an intersection in the clock distribution circuit according to the first embodiment.

FIG. 6 is a diagram illustrating the arrangement of the clock wirings 311 and 312 according to the fourth embodiment. The fourth embodiment is a modification in which the clock wirings 311 and 312 are arranged as shown in FIG. 6 instead of the clock wirings 60 and 70 in the first embodiment. Therefore, the semiconductor circuit device 300 according to the fourth embodiment includes a modified example of the clock distribution circuit 10 in which the clock wirings 311 and 312 are replaced, and internal circuits 20a, 20b, 20c, 20d, and 20e.
The clock distribution circuit 10 according to the fourth embodiment has a modification example in which the clock wirings 311 and 312, the LC oscillation circuit 40, the phase adjustment circuits 30 a, 30 b, 30 c, 30 d and 30 e, amplifiers 31 a, 32 a, 31 b, 32 b, 31 c, 32c, 31d, 32d, 31e, and 32e. Since the constituent elements other than the clock wirings 311 and 312 are the same as the constituent elements described in the first embodiment, description thereof is omitted.

The clock wirings 311 and 312 are arranged so as to pass through the outer peripheral portion of the semiconductor chip and have a ring shape.
Therefore, the outer peripheral portion is, for example, a region where an input / output circuit connected to an input terminal or an output terminal in a semiconductor chip and receiving an input signal or outputting an output signal is arranged. It is similar to the outer periphery.
Incidentally, in the fourth embodiment, the clock wirings 311 and 312 have the upper right intersection 1, the lower left intersection 2 of the semiconductor chip shown in FIG. 6, and a twist portion close to the LC oscillation circuit 40. As a result, the clock wirings 311 and 312 are switched between the outer periphery and the inner periphery at the intersection and the twisted portion.
Here, the twist portion has a section in which the clock wirings 311 and 312 are close to each other, a three-dimensional intersection, and a section that is separated to a predetermined distance. Compared with the intersection of the third embodiment, in the twist portion of the fourth embodiment, consideration is given to equalizing the clock wiring and the parasitic capacitance.
Therefore, the wiring lengths of the clock wirings 311 and 312 are approximately equal. Furthermore, the parasitic capacitances of the clock wirings 60 and 70 can be brought close to each other.

As described above, the modification of the clock distribution circuit 10 according to the fourth embodiment is characterized in that the clock wiring has an intersection and a ridge portion in the clock distribution circuit according to the first embodiment.

FIG. 7 is a diagram illustrating the arrangement of the clock wirings 411 and 412 according to the fifth embodiment. The fifth embodiment is a modification in which clock wirings 411 and 412 are arranged as shown in FIG. 7 instead of the clock wirings 60 and 70 in the first embodiment. Therefore, the semiconductor circuit device 400 according to the seventh embodiment includes a modified example of the clock distribution circuit 10 in which the clock wirings 411 and 412 are replaced, and internal circuits 20a, 20b, 20c, 20d, and 20e.
The clock distribution circuit 10 according to the fifth embodiment has a modification example in which the clock wirings 411 and 412, the LC oscillation circuit 40, the phase adjustment circuits 30a, 30b, 30c, 30d, and 30e, the amplifiers 31a, 32a, 31b, 32b, and 31c, 32c, 31d, 32d, 31e, and 32e. Since the constituent elements other than the clock wirings 411 and 412 are the same as the constituent elements described in the first embodiment, description thereof is omitted.

The clock wirings 411 and 412 are arranged so as to pass through the outer peripheral portion and the central portion of the semiconductor chip and have a ring shape.
Therefore, the outer peripheral portion is, for example, generally a region where the input / output circuit is arranged in the semiconductor chip, and is the same as the outer peripheral portion in the third embodiment.
On the other hand, the central portion generally refers to a place where an internal circuit that is not connected to an input terminal or an output terminal is disposed. That is, it is a region where the internal circuits 20a, 20b, 20c, 20d, and 20e are arranged.
Therefore, the phase adjustment circuits 30a, 30b, 30c, 30d, and 30e can be disposed close to the internal circuits 20a, 20b, 20c, 20d, and 20e. As a result, the phase difference between the clock signals output from the phase adjustment circuits 30a, 30b, 30c, 30d, and 30e and receiving the clock signal can be suppressed.
By the way, in the fifth embodiment, the clock wirings 411 and 412 have the upper right intersection 1, the lower left intersection 2, the lower right intersection 3, and the lower left intersection 4 of the semiconductor chip shown in FIG. As a result, the clock wirings 411 and 412 have an even number of intersections where the outer periphery and the inner periphery are switched. Therefore, the wiring lengths of the clock wirings 411 and 412 are approximately equal.

As described above, the modification of the clock distribution circuit 10 according to the fifth embodiment is characterized in that the clock wiring has a portion that passes through the internal circuit arrangement region in the clock distribution circuit according to the first embodiment.

FIG. 8 is a diagram illustrating the arrangement of the clock wirings 511 and 512 according to the sixth embodiment. The sixth embodiment is a modification in which clock wirings 511 and 512 are arranged as shown in FIG. 8 instead of the clock wirings 60 and 70 in the first embodiment. Therefore, the semiconductor circuit device 500 according to the eighth embodiment includes a modified example of the clock distribution circuit 10 in which the clock wirings 511 and 512 are replaced, and internal circuits 20a, 20b, 20c, 20d, and 20e.
Further, the clock distribution circuit 10 according to the sixth embodiment has a modification in which the clock wirings 511 and 512, the LC oscillation circuit 40, the phase adjustment circuits 30a, 30b, 30c, 30d, and 30e, the amplifiers 31a, 32a, 31b, 32b, 31c, 32c, 31d, 32d, 31e, and 32e. Since the constituent elements other than the clock wirings 511 and 512 are the same as the constituent elements described in the first embodiment, description thereof is omitted.

The clock wirings 511 and 512 are arranged so as to pass through the outer peripheral portion and the central portion of the semiconductor chip and have a ring shape.
Therefore, the outer peripheral portion is, for example, generally a region where the input / output circuit is arranged in the semiconductor chip, and is the same as the outer peripheral portion in the third embodiment.
On the other hand, the central part is a place other than the outer peripheral part. That is, it is a region where the internal circuits 20a, 20b, 20c, 20d, and 20e are arranged.
By the way, in the sixth embodiment, the clock wirings 511 and 512 have the upper right intersection 1, the lower left intersection 2, the lower right intersection 3, the lower left intersection 4, and the lower left intersection in the semiconductor chip shown in FIG. Have
As a result, the clock lines 511 and 512 have an outer periphery and an inner periphery at the intersection. Therefore, the wiring lengths of the clock wirings 411 and 412 are approximately equal.
Further, the self-intersection is a portion where the clock wiring 511 or the clock wiring 512 intersects with its own wiring. Since there is a self-intersection in the clock wirings 511 and 512, there is an effect of increasing the degree of freedom in arrangement of the clock wirings 511 and 512.

As described above, the modified example of the clock distribution circuit 10 according to the sixth embodiment is characterized in that in the clock distribution circuit according to the first embodiment, the clock wiring has a self-intersecting portion.

  To provide a clock distribution circuit capable of reducing a phase difference between a plurality of clocks output from a plurality of final buffers due to manufacturing variations at the time of manufacturing a semiconductor chip or operating conditions of a semiconductor circuit in the semiconductor chip. Can do.

10, 100 Clock distribution circuit 20a, 20b, 20c, 20d, 20e Internal circuit 30a, 30b, 30c, 30d, 30e Phase adjustment circuit 40 LC oscillation circuit 50 Variable capacitor 80, 180, 200, 300, 400, 500 Semiconductor circuit device 110 Clock generation circuit


Claims (7)

  1. Loop- shaped clock wiring consisting of closed wiring,
    Connected to said loop-shaped clock wiring, by self-oscillation, the phase in the position of the loop of the clock wiring throat also an oscillation circuit for generating a first clock signal is within 360 degrees from the phase of the oscillation source,
    Two or more phase adjustment circuits arranged in each of the two or more locations and outputting the second clock signal in the circuit device,
    Each of the phase adjustment circuits receives the first clock signal having a phase corresponding to an arrangement location, and each of the phase adjustment circuits outputs a phase difference between the first clock signals received by each of the phase adjustment circuits. the clock distribution circuit, characterized in that it comprises an adjusting unit for reducing a phase difference between the second clock signal.
  2. Loop- shaped clock wiring consisting of closed wiring,
    A first clock signal that is connected to the loop-shaped clock wiring and synchronized with an external clock signal input from the outside, so that the phase at any position in the loop-shaped clock wiring is within 360 degrees from the phase at the oscillation source. An oscillation circuit for generating
    Two or more phase adjustment circuits arranged in each of the two or more locations and outputting the second clock signal in the circuit device,
    Each of the phase adjustment circuits receives the first clock signal having a phase corresponding to an arrangement location, and each of the phase adjustment circuits outputs a phase difference between the first clock signals received by each of the phase adjustment circuits. the clock distribution circuit, characterized in that it comprises an adjusting unit for reducing a phase difference between the second clock signal.
  3. The first clock signal is a complementary signal composed of a normal phase first clock signal and a negative phase first clock signal,
    The clock wiring includes a loop-shaped normal phase clock wiring composed of closed wiring corresponding to the normal phase first clock signal and a loop-shaped negative phase composed of closed wiring corresponding to the negative phase first clock signal. It consists of clock wiring,
    2. The clock distribution circuit according to claim 1, wherein the normal phase clock wiring and the reverse phase clock wiring are three-dimensionally crossed.
  4. The first clock signal is a complementary signal composed of a normal phase first clock signal and a negative phase first clock signal,
    The clock wiring includes a loop-shaped normal phase clock wiring composed of closed wiring corresponding to the normal phase first clock signal and a loop-shaped negative phase composed of closed wiring corresponding to the negative phase first clock signal. It consists of clock wiring,
    2. The clock distribution circuit according to claim 1, wherein the normal phase clock wiring and the reverse phase clock wiring have a section close to each other and three-dimensionally intersect.
  5. 2. The clock according to claim 1, wherein the clock wirings are three-dimensionally self-intersecting.
    Distribution circuit.
  6. A semiconductor circuit device including the clock distribution circuit according to claim 1.
  7. The semiconductor circuit device includes an input terminal for receiving a signal from the outside, or a peripheral circuit unit in which an input / output circuit connected to an output terminal for outputting a signal to the outside is disposed;
    A central portion in which an internal circuit without connection with the input terminal or the output terminal is disposed,
    The semiconductor circuit device according to claim 6, wherein a part of the clock wiring passes through the central portion.
JP2010135770A 2010-06-15 2010-06-15 Clock distribution circuit and semiconductor circuit device including the circuit Expired - Fee Related JP5560932B2 (en)

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Publication number Priority date Publication date Assignee Title
JP3073547B2 (en) * 1990-05-31 2000-08-07 株式会社東芝 The clock distribution circuit
JP2770656B2 (en) * 1992-05-11 1998-07-02 ヤマハ株式会社 Integrated circuit device
JPH0854957A (en) * 1994-08-12 1996-02-27 Hitachi Ltd Clock distribution system
JP3335839B2 (en) * 1996-03-26 2002-10-21 株式会社東芝 Electronic circuit device
JPH09330142A (en) * 1996-06-12 1997-12-22 Hitachi Ltd Clock circuit
DE60013245T2 (en) * 1999-01-22 2005-01-13 Multigig Ltd., Wilby Wellingborough Electronic circuit arrangement
JP2001044825A (en) * 1999-07-28 2001-02-16 Matsushita Electric Ind Co Ltd Semiconductor integrated circuit
JP3498069B2 (en) * 2000-04-27 2004-02-16 Necエレクトロニクス株式会社 Clock control circuit and method
JP2004087972A (en) * 2002-08-28 2004-03-18 Nec Micro Systems Ltd Semiconductor device and its clock signal wiring method
JP4743469B2 (en) * 2003-03-25 2011-08-10 株式会社日立製作所 Semiconductor integrated circuit device and clock distribution method
JP5003383B2 (en) * 2007-09-27 2012-08-15 株式会社豊田中央研究所 Oscillator and array antenna device
JP5106330B2 (en) * 2008-09-16 2012-12-26 パナソニック株式会社 Digitally controlled oscillator circuit, frequency synthesizer, and wireless communication device

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