JP5537102B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- JP5537102B2 JP5537102B2 JP2009210550A JP2009210550A JP5537102B2 JP 5537102 B2 JP5537102 B2 JP 5537102B2 JP 2009210550 A JP2009210550 A JP 2009210550A JP 2009210550 A JP2009210550 A JP 2009210550A JP 5537102 B2 JP5537102 B2 JP 5537102B2
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- 239000004065 semiconductor Substances 0.000 title claims description 34
- 238000004519 manufacturing process Methods 0.000 title claims description 31
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 87
- 229910052710 silicon Inorganic materials 0.000 claims description 85
- 239000010703 silicon Substances 0.000 claims description 85
- 239000000758 substrate Substances 0.000 claims description 81
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 30
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 30
- 239000013078 crystal Substances 0.000 claims description 26
- 238000005468 ion implantation Methods 0.000 claims description 13
- 229910021417 amorphous silicon Inorganic materials 0.000 description 50
- 230000015572 biosynthetic process Effects 0.000 description 19
- 239000007790 solid phase Substances 0.000 description 18
- 238000000034 method Methods 0.000 description 13
- 238000010438 heat treatment Methods 0.000 description 12
- 230000007547 defect Effects 0.000 description 6
- 238000009792 diffusion process Methods 0.000 description 6
- 229910052581 Si3N4 Inorganic materials 0.000 description 5
- 238000000137 annealing Methods 0.000 description 5
- 150000002500 ions Chemical class 0.000 description 5
- 238000002955 isolation Methods 0.000 description 5
- 239000013081 microcrystal Substances 0.000 description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 5
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 4
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 4
- 238000002425 crystallisation Methods 0.000 description 3
- 230000008025 crystallization Effects 0.000 description 3
- 230000001678 irradiating effect Effects 0.000 description 3
- 229910044991 metal oxide Inorganic materials 0.000 description 3
- 150000004706 metal oxides Chemical class 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- 230000001133 acceleration Effects 0.000 description 2
- -1 and for example Chemical class 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000006911 nucleation Effects 0.000 description 1
- 238000010899 nucleation Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 230000010287 polarization Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02664—Aftertreatments
- H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
- H01L29/045—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes by their particular orientation of crystalline planes
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Ceramic Engineering (AREA)
- Recrystallisation Techniques (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Thin Film Transistor (AREA)
Description
11・・・ (100)シリコン基板
12・・・ (110)シリコン基板
13・・・ アモルファスシリコン領域
2・・・ 素子分離絶縁膜
3・・・ ゲート絶縁膜
4・・・ ゲート電極
5・・・ 側壁絶縁膜
6・・・ 拡散層
7・・・ レジスト
101・・・ シリコン基板
102・・・ シリコン酸化膜
103・・・ アモルファスシリコン膜
104・・・ 単結晶シリコン膜
105・・・ ゲート絶縁膜
106・・・ ゲート電極
107・・・ 側壁絶縁膜
108・・・ 拡散層
109・・・ シリコン窒化膜
Claims (5)
- 第1の面方位を有するシリコン基板上の一部に、アモルファス層を形成する工程と、前記アモルファス層にマイクロ波を照射し、前記アモルファス層を前記シリコン基板と前記アモルファス層の界面から第1の面方位を有する結晶層とする工程と、
を有しており、
前記結晶層を形成する工程において、前記第1の面方位を有する前記シリコン基板の温度が摂氏200度以上摂氏550度以下であることを特徴とする半導体装置の製造方法。 - 前記結晶層上にトランジスタやメモリを形成する工程をさらに有していることを特徴とする請求項1に記載の半導体装置の製造方法。
- 前記アモルファス層は、前記第1の面方位を有するシリコン基板上に第2の面方位を有するシリコン基板を形成し、前記第2の面方位を有するシリコン基板にイオン注入を行うことで形成することを特徴とする請求項1に記載の半導体装置の製造方法。
- 前記アモルファス層は、前記第1の面方位を有するシリコン基板上にシリコン酸化膜を形成し、前記シリコン酸化膜の一部を除去して、前記第1の面方位を有するシリコン基板の一部を露出した後、前記露出した第1の面方位を有するシリコン基板上及び前記シリコン酸化膜上に形成することを特徴とする請求項1に記載の半導体装置の製造方法。
- 前記第1の面方位が(100)であり、前記第2の面方位が(110)であることを特徴とする請求項3に記載の半導体装置の製造方法。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2009210550A JP5537102B2 (ja) | 2009-09-11 | 2009-09-11 | 半導体装置の製造方法 |
US12/878,780 US8093141B2 (en) | 2009-09-11 | 2010-09-09 | Method of fabricating a semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2009210550A JP5537102B2 (ja) | 2009-09-11 | 2009-09-11 | 半導体装置の製造方法 |
Publications (2)
Publication Number | Publication Date |
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JP2011061072A JP2011061072A (ja) | 2011-03-24 |
JP5537102B2 true JP5537102B2 (ja) | 2014-07-02 |
Family
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JP2009210550A Expired - Fee Related JP5537102B2 (ja) | 2009-09-11 | 2009-09-11 | 半導体装置の製造方法 |
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US (1) | US8093141B2 (ja) |
JP (1) | JP5537102B2 (ja) |
Families Citing this family (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007329200A (ja) * | 2006-06-06 | 2007-12-20 | Toshiba Corp | 半導体装置の製造方法 |
US9981193B2 (en) | 2009-10-27 | 2018-05-29 | Harmonix Music Systems, Inc. | Movement based recognition and evaluation |
US9358456B1 (en) | 2010-06-11 | 2016-06-07 | Harmonix Music Systems, Inc. | Dance competition game |
JP2012182312A (ja) | 2011-03-01 | 2012-09-20 | Toshiba Corp | 半導体装置の製造方法 |
JP5615207B2 (ja) | 2011-03-03 | 2014-10-29 | 株式会社東芝 | 半導体装置の製造方法 |
JP2012234864A (ja) * | 2011-04-28 | 2012-11-29 | Toshiba Corp | 半導体装置及びその製造方法 |
JP5659098B2 (ja) | 2011-07-19 | 2015-01-28 | 株式会社東芝 | 半導体装置の製造方法 |
US20130075747A1 (en) * | 2011-09-23 | 2013-03-28 | Robert J. Purtell | Esd protection using low leakage zener diodes formed with microwave radiation |
JP2014063897A (ja) | 2012-09-21 | 2014-04-10 | Toshiba Corp | 半導体装置の製造方法、アニール装置及びアニール方法 |
JP6596285B2 (ja) | 2015-09-24 | 2019-10-23 | 東芝メモリ株式会社 | マイクロ波照射装置および基板処理方法 |
FI128442B (en) * | 2017-06-21 | 2020-05-15 | Turun Yliopisto | Silicon structure with crystalline silica |
US20230420546A1 (en) * | 2022-06-24 | 2023-12-28 | Nxp Usa, Inc. | Transistor with current terminal regions and channel region in layer over dielectric |
Family Cites Families (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2513659A1 (fr) * | 1981-09-29 | 1983-04-01 | Centre Nat Rech Scient | Procede de recuit superficiel par energie micro-onde pulsee de materiaux semi-conducteurs |
JPS5946105B2 (ja) * | 1981-10-27 | 1984-11-10 | 日本電信電話株式会社 | バイポ−ラ型トランジスタ装置及びその製法 |
JPS63261714A (ja) * | 1987-04-20 | 1988-10-28 | Sanyo Electric Co Ltd | Soi基板の製造方法 |
JP2775503B2 (ja) * | 1990-03-13 | 1998-07-16 | 三菱電機株式会社 | 接合ゲート型電界効果トランジスタの製造方法 |
JPH05234887A (ja) * | 1992-02-19 | 1993-09-10 | Sanyo Electric Co Ltd | 半導体装置の製造方法 |
JP3621154B2 (ja) * | 1995-05-19 | 2005-02-16 | 株式会社半導体エネルギー研究所 | アクティブマトリクス型表示装置の作製方法 |
JP2002289521A (ja) * | 2001-03-27 | 2002-10-04 | Sanyo Electric Co Ltd | 半導体装置の製造方法 |
US7105891B2 (en) * | 2002-07-15 | 2006-09-12 | Texas Instruments Incorporated | Gate structure and method |
US7507617B2 (en) * | 2003-12-25 | 2009-03-24 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing semiconductor device |
US7494852B2 (en) * | 2005-01-06 | 2009-02-24 | International Business Machines Corporation | Method for creating a Ge-rich semiconductor material for high-performance CMOS circuits |
JP4081580B2 (ja) * | 2005-06-22 | 2008-04-30 | 株式会社半導体エネルギー研究所 | 表示装置の作製方法 |
KR100621776B1 (ko) * | 2005-07-05 | 2006-09-08 | 삼성전자주식회사 | 선택적 에피택셜 성장법을 이용한 반도체 디바이스제조방법 |
US7396407B2 (en) * | 2006-04-18 | 2008-07-08 | International Business Machines Corporation | Trench-edge-defect-free recrystallization by edge-angle-optimized solid phase epitaxy: method and applications to hybrid orientation substrates |
JP5064841B2 (ja) * | 2007-03-06 | 2012-10-31 | ルネサスエレクトロニクス株式会社 | 半導体装置および半導体装置の製造方法 |
US7608522B2 (en) * | 2007-03-11 | 2009-10-27 | United Microelectronics Corp. | Method for fabricating a hybrid orientation substrate |
JP2009016692A (ja) | 2007-07-06 | 2009-01-22 | Toshiba Corp | 半導体記憶装置の製造方法と半導体記憶装置 |
JP2009111074A (ja) * | 2007-10-29 | 2009-05-21 | Toshiba Corp | 半導体基板 |
-
2009
- 2009-09-11 JP JP2009210550A patent/JP5537102B2/ja not_active Expired - Fee Related
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2010
- 2010-09-09 US US12/878,780 patent/US8093141B2/en active Active
Also Published As
Publication number | Publication date |
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JP2011061072A (ja) | 2011-03-24 |
US20110111580A1 (en) | 2011-05-12 |
US8093141B2 (en) | 2012-01-10 |
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