JP5510814B2 - Music generator - Google Patents

Description

  The present invention relates to a waveform memory type musical sound generation device, and more particularly to a musical sound generation device that stores waveform data in a NAND flash memory or the like, and reproduces the waveform data while reading the waveform data into a waveform memory via a buffer.

  2. Description of the Related Art Conventionally, a musical tone generating apparatus is known that stores waveform data in a hard disk (HD), reads waveform data from the HD to a buffer, reads waveform data from the buffer to a waveform memory, and plays back the waveform data ( For example, Patent Documents 1 and 2). In such a musical sound generating device, if the waveform data on the HD is read into the waveform memory via the buffer and played back after a sounding instruction is issued, the sounding start is delayed. The beginning of the waveform data is read into the waveform memory. When a sound generation instruction is issued, the reproduction of the head data on the waveform memory is started immediately, and the subsequent waveform data is read from the HD to the waveform memory via the buffer while the head data is being reproduced. put out. After the reproduction of the head portion is finished, the waveform data read out to the waveform memory is reproduced, and during the reproduction, the next subsequent waveform data is read out from the HD to the waveform memory via the buffer. Such processing is repeated to continue reproduction. Thereby, it is possible to start sound generation without delay when a sound generation instruction is given.

  In the above method, every time the waveform data (sample data) for one cluster read into the buffer is read into the waveform memory (that is, when the buffer becomes empty), a transfer request interrupt is generated for the CPU. In response to the transfer request interrupt, the CPU specifies one cluster on the HD to be read next, and instructs the transfer unit to transfer the HD from the cluster to the buffer. Therefore, CPU interrupt processing is essential.

  As a waveform memory sound source using burst transfer, there is a technique described in Patent Document 3 below. In this method, waveform samples read from the waveform memory are temporarily stored in a buffer memory, and necessary waveform samples are selectively read from the buffer memory to generate musical sounds. Reading waveform samples from the waveform memory to the buffer memory is performed by burst transfer in units of a plurality of samples. By performing burst transfer, the access time can be shortened.

  On the other hand, in recent years, the capacity and cost of NAND flash memories have increased, and attempts have been made to use NAND flash memories together with HD as a large capacity data storage means in various devices. In the NAND flash memory, it takes time to find a page (corresponding to a cluster of HD), but the data transfer rate after reading starts is high. In addition, error correction using an error correction code is essential.

Japanese Patent No. 2671747 Japanese Patent No. 4089687 Japanese Patent No. 3163984

  In the above-described tone generation apparatus using HD, there is a problem that the access speed of HD becomes a bottleneck and the number of channels that can be reproduced simultaneously is limited. In a musical sound generating device, it is desired to increase the number of simultaneous sounding channels as much as possible. Therefore, it is conceivable to use a NAND flash memory instead of using HD. Since the NAND flash memory has a data transfer speed that is significantly higher than that of HD, the size of a cluster (page) that is a unit of reading can be significantly reduced (1/10 or less). In this case, however, the frequency of transfer request interruptions to the CPU increases significantly (10 times or more). That is, when a NAND flash memory is used as a memory for storing waveform data used by a sound source, the frequency with which control by the CPU that controls the sound source is required increases, and the load on the CPU increases greatly. There is. For this reason, it is desired to reduce the CPU load by causing the tone generator hardware to execute the control performed by the CPU in accordance with the processing program in the conventional tone generator using HD and the tone generator hardware using the NAND flash memory. .

  In addition, in NAND flash memory, there is a high possibility that an error is included in data read compared to other memories. Therefore, when data is stored, an error correction code is appropriately added and stored for each page. It is essential. The HD has the same data error problem. However, in a conventional tone generator that uses HD, data correction is automatically performed as firmware processing of the processor in the HD device. For this reason, there is a time delay from when the address is supplied to the intervening processor until data is obtained. In a musical tone generation apparatus using a NAND flash memory, it is desirable not to interpose a processor between the LSI of the NAND flash memory and the LSI of the musical sound generation apparatus in order to speed up access. In that case, the NAND flash memory itself cannot perform data correction.

  Currently, there is a sound source (musical sound generation device) in which waveform data is stored in a NAND flash memory in the market. However, prior to the sound generation operation of the sound source, the CPU requires a CPU from the NAND flash memory in advance. All the waveform data to be read is read out, error-corrected, and stored in a waveform memory composed of RAM. In this case, there is a problem that the size of the waveform data is limited by the size of the waveform memory constituted by the RAM.

  An object of the present invention is to reduce a load on a CPU in a musical sound generating apparatus that stores waveform data in a NAND flash memory or the like and reproduces the waveform data from the waveform data read out to the waveform memory via a buffer. To do. Further, the present invention can realize error detection and correction for data read from a NAND flash memory or the like by using hardware in the tone generation unit without using a CPU or a processor in the flash memory. At the same time, it is an object to be able to replace a page in which an error has occurred with a new page.

  In order to achieve the above object, the invention according to claim 1 reads out the waveform data stored in the NAND flash memory or the like in units of pages without interrupting the control unit (CPU), and stores it in the buffer of the waveform memory. It is characterized by enabling sample replenishment. First, a series of sample data of a plurality of waveform data is stored in a plurality of continuous pages in a virtual address space in an external memory (NAND flash memory or the like). In addition, an address conversion table for converting a virtual page address (VP address) for specifying a page in the virtual address space into a real page address is prepared. When the control unit instructs the start of sound generation, the control register uses speed information corresponding to the pitch of the musical sound to be generated, the top waveform address that points to the top waveform area of the waveform memory of the waveform data used for sound generation, and is used for sound generation Waveform position information indicating the position of the waveform data to be recorded in the external memory, and amplitude control information defining the amplitude of the tone to be generated are set. At the start of sound generation, the sample data is read from the first waveform area in which the sample data of the first page of waveform data is stored in advance, and the page to be read next is read into the buffer before the reading of the first page is completed. For the real page address of the next page to be read, the next page address setting unit generates a virtual page address indicating the next page to be read in the virtual address space from the external memory, and refers to the address conversion table. The virtual page address is converted into a real page address, and the real page address is set in the next page address storage unit. The transfer unit can read the data of the next page to be read with the real page address of the next page address storage unit. Thereafter, the reproduction is continued while reading the sample of the next page into the buffer every time reading of one page is completed in the same manner.

  The invention according to claim 2 is characterized in that, in claim 1, the address conversion table is stored in an external memory, and is read out from the external memory and stored in the address conversion table storage unit when the apparatus is activated.

  According to a third aspect of the present invention, in the first or second aspect, the address conversion table storage unit is provided in the waveform memory.

  According to a fourth aspect of the present invention, in any one of the first to third aspects, the musical tone generating unit uses an error correction code for the page data read from the external memory by the transfer unit to detect an error in the sample data of the page. An error correction unit and an error correction unit that perform detection and determine whether or not an error exists and whether or not there is an error, determine whether or not to correct the error, and execute correction when the detected error is correctable. And an error detection unit that sends an error notification including information specifying the page on the external memory in which the error has occurred to the control unit when a correctable error is detected by the control unit. Information specifying the page on which the correctable error has occurred is recorded as a substitute waiting page, and (2) automatically when there is a page recorded as the substitute waiting page In an activated background process or a process activated by a user instruction, a substitute page is secured on the external memory, and the page data recorded as the substitute waiting page is read, and an error occurs in the read. If the error occurs, error correction is performed to obtain appropriate data, the appropriate data is stored in the substitute page, the page in which the error has occurred is replaced, and (3) the actual virtual page address of the substitute waiting page is In the conversion to the page address, the address conversion table is modified so that the real page address of the substitute page can be acquired.

  According to a fifth aspect of the present invention, in the first to fourth aspects, the external memory is a NAND flash memory configured by an independent integrated circuit.

  According to the present invention, the next page address setting unit refers to the address conversion table, converts the virtual address of the page to be read next to a real address, acquires the next page address, and the transfer unit waits for transfer. In response to an instruction from the queue, the page is read from the external memory at the next page address and transferred to the waveform memory. Accordingly, the transfer is automatically performed by hardware without interrupting the control unit (CPU), and the load on the control unit can be reduced. The address conversion table is stored in the external memory, read at the time of activation, and stored in the address conversion table storage unit, so that it can be easily taken into the musical tone generation unit.

  In addition, by providing an error correction unit and error detection unit, detection of waveform data read errors and corrections when corrections are possible are automatically performed, so music generation continues even when such errors occur. can do. Further, when a correctable error occurs, the page having the error can be recorded, and the error page can be replaced at a later appropriate timing. In this case, the correspondence between the virtual page and the real page is defined by the address conversion table, so that the error page can be easily replaced with the substitute page.

1 is an overall configuration diagram of a musical tone signal generation system according to an embodiment of the present invention. The figure which shows the memory map of NAND type flash memory Figure showing the memory map of the waveform memory Time chart for explaining the timing of waveform data transfer Detailed view of the tone generator and transfer controller The figure which shows the time change (for 1ch) of various addresses after the start of pronunciation Flow chart of main processing and note-on event processing Flowchart of processing of VP address generation unit and processing of B → M transfer unit of Mr. transfer instruction generation Flowchart of processing when there is registration of a waiting page for substitution

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 shows the overall configuration of a musical tone generation apparatus according to an embodiment of the present invention. This musical tone generating apparatus is configured by connecting a predetermined peripheral device such as a memory to a musical instrument LSI (Large Scale Integrated circuit) 100.

  The CPU 101 is a processing device that controls the operation of the entire apparatus. A memory I / F (interface) 102 is an interface for connecting a NOR flash memory 121 to the LSI 100. The NOR flash memory 121 is a rewritable nonvolatile memory that stores various data such as a program executed by the CPU 101 and tone color data. A random access memory (RAM) 103 is a volatile memory used for various work areas. The display I / F 104, the parallel I / F 105, and the serial I / F 106 are interfaces for connecting the display 122, the operator 123, and the MIDI I / O 124, respectively. The display device 122 is a display for displaying various types of information. The operation element 123 is an operation element such as various switches provided on an external panel or the like. The MIDI I / O 124 is an interface for connecting to various MIDI devices and inputting / outputting MIDI signals.

  The memory I / F 107 is an interface for accessing the NAND flash memory 125. The NAND flash memory 125 is a rewritable nonvolatile memory storing a plurality of waveform data and the like, and data is read and written in page units. The page data capacity of one page is 2112 bytes. Reading data in units of pages can be performed at high speed by burst transfer. A memory map of the NAND flash memory 125 will be described in detail with reference to FIG. The transfer buffer 109 is a buffer memory for transferring waveform data from the NAND flash memory 125 to the waveform memory 126, and is configured by a dual-port (2-port) semiconductor memory capable of simultaneous reading and writing. The capacity is 2112 bytes for one page. The transfer buffer 109 is composed of a static RAM (SRAM). The waveform memory 126 is composed of a synchronous dynamic RAM (SDRAM). The memory map of the waveform memory 126 will be described in detail with reference to FIG. The memory I / F 112 is an interface for accessing the waveform memory 126. The transfer buffer 109 and the waveform memory 126 can perform random access (reading or writing performed by individually specifying an address) at an extremely high speed as compared with the flash memory 125. Furthermore, access to consecutive addresses can be accelerated using the burst mode.

  The F → B transfer unit 108 performs a process of transferring page data from the NAND flash memory 125 to the transfer buffer 109 in units of pages. The B → M transfer unit 110 performs a process of transferring the waveform data from the transfer buffer 109 to the waveform memory 126 (dividing one page into a predetermined number of times). The error correction unit 111 performs processing such as error detection and correction on the data read from the flash memory 125. The transfer units 108 and 110 and the error correction unit 111 operate under the control of the transfer control unit 113. The timing of the transfer operation will be described in detail with reference to FIG. The transfer control unit 113 controls the transfer from the flash memory 125 to the transfer buffer 109 and the transfer from the transfer buffer 109 to the waveform memory 126. When a plurality of transfer requests are generated, control is performed so that pages are transferred one by one in the order of arrival (since only one page can be transferred at a time). Note that the data width of the currently available NAND flash memory is limited to 8 bits. Therefore, the F → B transfer unit 108 connects two data read from two consecutive addresses of the NAND flash memory 125, converts the data into 16-bit data, and writes the data into the transfer buffer 109 having a data width of 16 bits. The data width of the waveform memory 126 is 16 bits, and 16 bits of data are stored at each address. Therefore, the B → M transfer unit 110 does not have to perform the conversion as performed by the F → B transfer unit 108.

  The sound source 114 includes a plurality of sound generation channels (here, 128 channels), generates a read address for each sound generation channel, reads waveform data (waveform sample data) from the waveform memory 126, and reads the read waveform data. Envelopes are added to the sound signal to generate a tone signal for each tone generation channel. Furthermore, the sound source 114 mixes the generated music signals of a plurality of channels and gives an effect such as reverb to the mixed music signal. The musical sound signal output from the sound source 114 is converted into an analog sound signal by a DAC (digital-analog converter) 127 and emitted by the sound system 128. Reference numeral 115 denotes a bus line that interconnects the components, and is a generic term for a control bus, a data bus, and an address bus.

  A memory map of the NAND flash memory 125 will be described with reference to FIG. The NAND flash memory is less expensive than the mask ROM, and the beginning of a page (here, “cueing” refers to the period from when a read command and a read address are given to the flash memory until data reading starts. Although it takes time for the time interval or the processing performed there), the data transfer rate after the start of reading is high (burst transfer). Reading and writing of the NAND flash memory 125 are performed in units of pages.

  One page data 2112 bytes on the flash memory 125 uses 2048 bytes as a data area and 64 bytes as additional information. The additional information includes an error correction code. When writing 2048 bytes of data in the data area, an error correction code is generated from the write data by a predetermined operation and written in the additional information. When reading the page data, it is possible to check whether there is an error in the 2048-byte data read from the data area by using the error correction code in the additional information, and if there is an error (the number of error bits is a predetermined number). Correction processing can be performed (if In addition, what is necessary is just to use the production | generation arithmetic expression based on well-known methods, such as a Hamming code method and a BCH method, for the production | generation of an error correction code. In general, an error detection arithmetic expression for calculating an error state (how many bits of error can be corrected) for each generation arithmetic expression, and a bit position to be corrected when correction is possible An error correction formula for calculating is determined. For each arithmetic expression, it is determined by the β-bit error correction code how many bits of error can be corrected in the α-byte data in the data area.

  FIG. 2A shows an entire memory map of the flash memory 125. The flash memory 125 includes a plurality of real pages that can be accessed with real page addresses, and stores data in these pages. The flash memory 125 stores an address conversion table (A conversion TBL) 201 and waveform data (broadly defined) 202 in advance. Assume that the address conversion table 201 and the waveform data 202 are stored separately in pages.

  The virtual page address space is set so that the real page address and the virtual page address have a one-to-one correspondence with the real page address space of the waveform data (broadly defined) 202 in FIG. Here, both the real page address space and the virtual page address space are assumed to be accessible within a 20-bit page address.

  FIG. 2B shows the data structure of the waveform data on the virtual address space. In the waveform data 202 area, a plurality of waveform data Wave1, Wave2,... Are stored. Each waveform data is sequentially stored in a plurality of pages W2 (0) + Inf, W2 (1) + Inf,... That are consecutive at the virtual page address, for example, as indicated by Wave2 in the figure. The data area of each page continuous with the virtual page address of each waveform data Wavex (x is 1, 2,...) Or the waveform sample data (1024 words) stored in the data area is Wx (0), Wx (1 ), ... Since one-page data is obtained by adding additional information Inf (64 bytes) to the waveform sample data in such a data area, “+ Inf” is added to the symbol of each data area. As described above, the additional information Inf includes an error correction code. Since each waveform data Wavex is stored in a plurality of consecutive pages with virtual page addresses, for example, when reading Wave2, if the virtual page address P of the first page W2 (0) + Inf is given, each subsequent page W2 (1) + Inf, W2 (2) + Inf,... Can be read by virtual page addresses P + 1, P + 2,. In FIG. 2 (b), the waveform data Wave1, Wave2,... Are shown as if there is no empty page, but there may be empty pages. It is only necessary that one waveform data is continuous on the virtual page address. In FIG. 2B, WA is one of the control registers for setting the virtual page address of the second virtual page Wx (1) + Inf of the waveform data (described in detail later).

  In the above description, “each page can be read with a virtual page address” has been described, but actually, it is necessary to convert a given virtual page address into a real page address and read the page from the flash memory 125. In the LSI 100 of the present embodiment, one of the two modes 1 and 2 can be designated as a conversion method between the virtual page address and the real page address.

  Mode 1 will be described. In mode 1, as shown in FIG. 2C, the concept of a block having 16 consecutive pages as one block is introduced. The area of the waveform data 202 in FIG. 2 (a) is used by being divided into block units, and the waveform data is continuously stored in ascending order of the real page address in one block. For example, when one waveform data Wave2 is stored in the flash memory 125, the necessary number of blocks for storing the waveform data is secured in the flash memory 125, and the first page W2 (0 ) + Inf to W2 (15) + Inf are stored in order, W2 (16) + Inf to W2 (31) + Inf are stored in the next block, and so on. It is assumed that different waveform data (for example, Wave1 and Wave2) are stored in different blocks. The blocks are set so that the boundary between the blocks is boundary-adjusted in units of 16 pages.

  FIG. 2D shows a specific method of conversion from the virtual page address to the real page address in mode 1. Assume that a 20-bit virtual page address (page number) 221 is given. The upper 16 bits of the address 221 are a virtual block number for specifying a block, and the lower 4 bits are data for specifying one page among the 16 pages in the block. The upper 16-bit virtual block number is converted into the upper 16 bits of the real page address 223 using the address conversion table 222. The lower 4 bits of the virtual page address 221 are used as the lower 4 bits of the actual page address 223 as data for specifying one page out of 16 pages in the block. The flash memory 125 is accessed by the real page address 223 obtained as described above, and the page data of the virtual page address 221 is read.

  The address conversion table 222 is read from the area 201 of the flash memory 125 when the system is started up, set in the waveform memory 126, and used. In FIG. 2A, it is simply indicated as “address conversion table 201”, but in practice, a significant address conversion table can be obtained by combining data in a data area of a plurality of pages in this area 201. In the data area of a plurality of pages in the area 201, all the correspondences between virtual block numbers and real block numbers are registered when waveform data is stored in the flash memory 125 in advance. Real page addresses of a plurality of pages constituting the area 201 are determined in advance. Note that “pointer NP to the next page” in the additional information Inf in FIG. 2B is data used in the next mode 2 and is not required in mode 1.

  Mode 2 will be described. In the case of mode 2, when storing the waveform data in the flash memory 125, as shown in FIG. 2B, the 3-byte “pointer NP to the next page” is set in the additional information Inf of each page data. To do. In this “next page pointer NP”, an actual page address of the next page (a page in which the next waveform sample of the page is stored) is set in the progression order of the waveform data. FIG. 2E shows an example of the data structure of a page on a real address in Wave2 mode 2. If the real page address of W2 (0) + Inf that is the first page of the virtual page is given, the next virtual page W2 (1) + Inf can be accessed with reference to the “pointer NP to the next page” in the page data. Thereafter, the page can be traced in the same manner, and the waveform data can be read in order.

  As will be described in detail later, in both modes 1 and 2, all the first pages Wx (0) of each waveform data Wave 1, 2,... Therefore, in the case of mode 2, the page is traced with the pointer NP to the next page starting from the virtual page address WA of the second virtual page Wx (1) + Inf. The conversion from the second virtual page address WA given first to the real page address is performed using an address conversion table read on the waveform memory 126. Conversely, in the address conversion table, the second virtual page address of each waveform data Wave1, Wave2,. . The address conversion table in the case of mode 1 described with reference to FIG. 2D is a table that outputs a 16-bit real block number stored in the address when a 16-bit virtual block number is given as the address. In the case of mode 2, when a 20-bit second virtual page address of each waveform data Wave1, Wave2,... Is given, a second virtual page address that matches from the second virtual page addresses stored in the address conversion table. If a matching second virtual page address is found, a 20-bit real page address stored in association with the second virtual page address is output. In the area 201 of FIG. 2A, when the waveform data is stored in the flash memory 125 in advance, all the correspondences between the second virtual page address and the real page address are registered.

  In each of the modes 1 and 2, since one waveform is stored in a plurality of continuous pages on the virtual address, there is no need to instruct which page is to be read for each page. It is only necessary to indicate the first virtual page address of the waveform data to be read. Note that the NAND flash memory 125 reads and writes data with an 8-bit width.

  FIG. 3 shows a memory map of the waveform memory 126. The waveform memory 126 includes an address conversion table area 301, a preload area 302, a buffer area 303, and a next page address area (NPA) 304. In the address conversion table area 301, the address conversion table read from the predetermined area 201 of the flash memory 125 of FIG. The preload area 302 includes waveform data W1 (0), W2 (0), W2 (0), W1 (0), W2 (0), each of the first page corresponding to the number of waveform data Wave1, Wave2, ... stored in the NAND flash memory 125 shown in FIG. This is an area for storing W3 (0),. The waveform data of each first page is stored in the preload area 302 when the system is started up. The buffer area 303 is provided with a buffer of the number of sound generation channels × 2, that is, two buffers for each sound generation channel (the size of one buffer is 1024 words per page). Areas corresponding to pronunciation chi (i is 1, 2,..., 128) are represented by Bia and Bib. Bia and Bib are continuously arranged in the address space of the waveform memory 126.

  The words “page” and “page data” indicate a 2112-byte page including additional information Inf and data in the page on the flash memory 125 and the transfer buffer 109. Now, a 1024-word data area not including the additional information Inf and waveform sample data in the data area are shown. In short, “page” on the flash memory 125 and the transfer buffer 109 pays attention to a unit for reading and writing. When the page is read from the flash memory 125, corrected for error, and set in the waveform memory 126, one page is 1024. It is taken as waveform sample data of a word.

  The setting of the address conversion table in the address conversion table area 301 of the waveform memory 126 and the setting of the first page Wx (0) of each waveform data in the preload area 302, which are executed when the system is started up, are mainly performed by the transfer control unit 113. The initial setting process is executed. In order to easily perform the initial setting process of the preload area 302, the first pages of the waveform data Waves 1, 2,... May be stored together in a predetermined area continuous with the actual page address of the flash memory 125. Good.

  In FIG. 3A, PA is one of the control registers for setting the read address of the first page in the preload area 302 to be read first when the sound source 114 reads the waveform sample from the waveform memory 126. This figure shows a case where the reproduction of the waveform data Wave3 is designated by the second channel, and the waveform data W3 (0) of the first page on the waveform memory 126 is designated by PA. An arrow 311 indicates the traveling direction of the read address (pitch counter) when the sound source 114 reads the waveform sample of the first page. BA is one of control registers for setting a read address indicating from which buffer in the buffer area 303 the waveform sample is read after the first page of the preload area 302 has been read. Since reproduction in the second channel is designated in this figure, as the initial value at the time when the page W3 (0) has been read, the head addresses of the buffers B2a and B2b used by the second channel are set in BA. . An arrow 312 indicates the traveling direction of the read address (pitch counter). After reading the buffers B2a and B2b as indicated by the arrow 312, the operation continues to return to the head of the buffer and continues to read as indicated by the arrows 313 and 314. In order to read out such a waveform memory, the waveform sample data to be read out next is stored in the buffer B2a while the preload area W3 (0) is being read out, and the buffer B2a is further read out. The waveform sample data is stored in the buffer B2b in the meantime, the waveform sample data is then stored in the buffer B2a while the buffer B2b is being read, and the reproduction is continued using the buffers B2a and B2b alternately. . Note that the number of buffers in each channel may be three or more. The waveform memory 126 reads and writes data with a 16-bit width.

  The next page address area (NPA) 304 stores the next page address of each sounding channel. FIG. 3B shows a map of the NPA 304. NPAi indicates the next page address of the ith. The next page address NPAi is an actual page address on the flash memory 125 of the page to be read next from the flash memory 125 to the buffer area of the waveform memory 126 for the ith. The timing for setting the next page address NPAi and details of the setting data will be described in detail later.

  FIG. 4 is a time chart for explaining the timing of waveform data transfer performed by the transfer units 108 and 110 under the control of the transfer control unit 113. It is assumed that time advances in the direction of the arrow t. A plurality of vertical lines 401 indicate sampling clock generation timings, and a section between adjacent vertical lines 401 indicates one sampling period (hereinafter referred to as 1 DAC). In this embodiment, 1 DAC is 22.67 nsec. The time chart described as “NAND type flash → transfer buffer” is a time chart of processing for transferring one page of waveform samples and additional information from the NAND type flash memory 125 to the transfer buffer 109 by the F → B transfer unit 108. . In the time chart described as “transfer buffer → waveform memory”, the B → M transfer unit 110 transfers from the transfer buffer 109 to the buffer area 303 of the waveform memory 126 (the buffer corresponding to the designated channel therein) for one page. 5 is a time chart of processing for transferring waveform samples and processing for a sound source 114 to read waveform samples from the waveform memory 126.

  Reference numeral 411 denotes a period during which page cueing is performed from the start of supplying a real page address to the NAND flash memory 125 until the output of the page data indicated by the real page address is completed in the memory 125. Show. After cueing 411, as shown in 412 and 413, data for one page (2048 bytes in the data area and 64 bytes in the additional information Inf) is page read (burst transfer). In the present embodiment, as shown at 411 to 413, one page of data and additional information can be read from the NAND flash memory 125 and written to the transfer buffer 109 by 4DAC. The transfer time of 4DAC is determined based on the specifications related to page reading (burst transfer) of the NAND flash memory 125.

  Reference numeral 421 denotes a period during which the sound source 114 reads out waveform samples for 128 channels from the waveform memory 126 to generate a musical sound. Reference numeral 422 denotes a period during which one page of waveform samples in the data area on the transfer buffer 109 is transferred to the corresponding channel buffer of the waveform memory 126. This transfer is data transfer from the internal register of the LSI 100 to the DRAM, and high-speed data transfer in burst mode is performed. Reference numeral 423 denotes a period during which the waveform memory 126 is refreshed. The time length of the refresh 423 interval is determined by the specification of the waveform memory 126. A section obtained by excluding the refresh 423 from 1 DAC is divided into a waveform sample reading section 421 and a burst transfer section 422.

  The time length of the waveform sample readout section 421 in 1 DAC is determined according to the required specifications of how many channels of musical sound are generated by this apparatus and how many points are interpolated in each channel, and the sound source 114 is time-divided. The designer determines based on the specifications of how many samples can be read in one DAC at a time resolution when reading the waveform samples of ch from the waveform memory 126. The time length of the section of the burst transfer 422 in 1 DAC is based on the required specification of how many samples need to be transferred in this section and the speed specification regarding the burst transfer from the transfer buffer 109 to the waveform memory 126. The designer decides. However, since the transfer buffer 109 is a memory that can be read and written simultaneously, and its size is one page of waveform data + additional information, the waveform of one page read from the flash memory 125 to the transfer buffer 109. It is necessary to transfer the samples (2048 bytes) from the transfer buffer 109 to the waveform memory 126 with the same number of DACs as the number of DACs required for page reading from the flash memory 125 to the transfer buffer 109. Therefore, it is necessary to perform transfer of the number of samples (rounded up after the decimal point) obtained by dividing the number of samples of one page data by the number of DACs in the section of one burst transfer 422. In this embodiment, since it takes 4 DAC to read 2048 bytes = 1024 samples in the data area for one page of the flash memory 125 to the transfer buffer 109, the waveform samples for one page read to the transfer buffer 109 are waveformd. Transfer to the memory 126 is also divided into 4 DACs. Therefore, in one burst transfer section 422, 256 samples corresponding to a quarter of 2048 bytes of data for one page = 1024 samples are transferred.

  In the present embodiment, it is assumed that each channel performs two-point interpolation and a total of 128-channel musical sounds are generated, and the time length of the waveform sample reading section 421 necessary for enabling the processing is secured. It shall be. It is assumed that hardware capable of burst transfer of 256 samples (words) is used in a section 422 excluding the waveform sample reading section 421 and the refresh 423 from 1 DAC.

  Here, the error correction processing by the error correction unit 111 will be described. Data transfer from the flash memory 125 to the transfer buffer 109 in the sections 412 and 413 is performed by the F → B transfer unit 108. During the transfer, the error correction unit 111 analyzes the transfer data and performs error correction calculation. Process. Reference numeral 431 denotes a time interval in which the error correction calculation process is performed. Error correction calculation processing calculates an error correction code by performing a predetermined calculation on the data being transferred, and detects an error in the transfer data by comparing it with the error correction code recorded in the additional information Inf. Then, it is determined whether or not the detected error can be corrected, and if correction is possible, the bit position where the error is detected is specified. Since the error detection process can be performed sequentially immediately after the data transfer from the flash memory 125 in the section 412 to the transfer buffer 109 is started, the error correction calculation process 431 is started immediately after the data transfer start timing in the section 412. doing. The error correction unit 111 calculates an error correction code by executing an error detection process in the section of the error correction calculation process 431 as the data transfer 412 proceeds, and when the transfer 413 of the additional information Inf ends, the calculated error A predetermined error determination operation is performed based on the correction code and the error correction code included in the additional information Inf. Finally, the presence / absence of an error, whether error correction is possible and whether error correction is possible Determine the error correction location. On the other hand, regardless of the presence or absence of an error, the B → M transfer unit 110 writes the 1024 samples on the transfer buffer 109 into the waveform memory 126 in four sections 422. Based on the result of the error correction calculation processing 431, the error correction unit 111 corrects the error in the waveform data on the waveform memory 126 in the interval 425 when an error is detected and the error correction location is acquired. Apply. The target of error correction is 2048 bytes of data in the data area in the case of mode 1, and data obtained by combining the 2048 bytes of the data area and the pointer NP to the next page in the case of mode 2. In other words, in the case of mode 2, it is assumed that an error correction code for data including the data area and the next page pointer NP is stored in each page.

  The burst transfer from the transfer buffer to the waveform memory starts from a DAC cycle delayed by 2 DAC from the timing at which the transfer from the NAND flash to the transfer buffer is started. This is so that one page data of 2048 bytes = 1024 samples shown in the number 412 can be divided into 256 samples and transferred by the burst transfer shown in the number 422 (in short, four times). Each burst transfer 422 is delayed by 2 DAC so that 256 samples of data transferred in the burst transfer have been transferred from the NAND flash memory 125 to the transfer buffer 109 by the time the burst transfer starts. It is what. Therefore, the transfer buffer 109 does not have to be 2-port. For example, two RAMs may alternately switch between reading and writing. However, in order to perform writing and reading safely, a 2-port RAM is used. Using.

  FIG. 5 is a detailed diagram regarding the sound source unit 114 and the transfer control unit 113. In this figure, the arrows representing input / output of addresses are mainly represented by ordinary arrows, and the arrows representing input / output of data other than addresses are represented by triangles with a solid top portion.

  The sound source unit 114 includes a mode register 501. The register 501 is a register for setting mode information M for designating either mode 1 or 2 that defines a conversion method from a virtual page address to a real page address. The designer determines in advance whether the LSI 100 is operated in mode 1 or 2. In addition, an address conversion table and waveform data are stored in the flash memory 125 with a data structure corresponding to the mode. The mode information is set in the register 501 when the system is started up.

  The sound source unit 114 includes a control register (sound source register) 502. The control register 502 is a register that stores parameters and note-on NON for each channel. For example, when the CPU 101 receives a musical sound generation instruction via the MIDI I / O 124, the CPU 101 assigns a channel for generating a musical sound, sets a parameter based on the performance information in the control register 502 corresponding to the channel, and writes a note-on. . As a result, the sound source 114 starts the tone generation process for that channel. Details of each register are shown below.

(1) WA: The virtual page address of the second page Wx (1) + Inf of the waveform data Wavex to be read by the corresponding channel in the NAND flash memory 125 described with reference to FIG. 2B is set.
(2) PA: The address of the first page Wx (0) of the waveform data Wavex to be read by the channel in the preload area 302 of the waveform memory 126 described with reference to FIG. When the system is started up, the first pages W1 (0), W2 (0),... Of all waveform data Wave1, Wave2,... In the NAND flash memory 125 are stored in the preload area 302.
(3) BA: Addresses of a pair of double buffers Bna and Bnb corresponding to the ch in the buffer area 303 of the waveform memory 126 described with reference to FIG.
(4) F: Set the F number. The F number has an integer part and a decimal part, and is a parameter for shifting the pitch of the waveform data to be read. The value is determined according to the pitch (pitch) of the musical sound to be generated. That is, the value of the F number is set to “1” when it is not necessary to shift from the pitch of the waveform data, is set to a value larger than “1” when it is desired to increase the pitch, and is smaller than “1” when it is desired to decrease the pitch. Value.
(5) IL, HT, 1DR, 1DL, 2DR, 2DL, RR: registers for setting parameters for controlling the envelope of a musical sound. IL indicates an initial level, and HT indicates a hold time. These are parameters for instructing to continuously output the initial level IL as an envelope waveform in the time interval from the start of musical sound generation to the hold time HT. The waveform data prepared in the NAND flash memory 125 is waveform data that can produce a realistic musical sound by using the volume change in the original sampling waveform as it is for the rising portion. In view of this, the initial level IL is used as an envelope waveform in the time period corresponding to the hold time HT at the rising edge. 1DR is the 1st decay rate, and 1DL is the 1st decay level. This is a parameter for outputting an envelope waveform that reaches the target value 1st decay level 1DL at the rate of change of the 1st decay rate 1DR after the hold time HT. The same applies to the 2nd decay rate 2DR and the 2nd decay level 2DL, which are parameters for outputting an envelope waveform that reaches the target value 2nd decay level 2DL at the rate of change of the 2nd decay rate 2DR after the 1st decay. When note-off comes after 2nd decay, the volume level is gradually reduced at the rate of change of the release rate RR. Mute the sound when the volume level is below the specified level.
(6) NON: A register for setting note-on instructing the start of generation of musical sound.

  When the CPU 101 sets the above parameters including the note-on NON in the control register 502 corresponding to a certain channel, the sound source unit 114 starts processing for generating a musical sound in that channel. Note that the various parameters shown in the sound source unit 114 in FIG. 5 indicate the parameters of the channel being processed at that time. That is, if the ch to be processed changes, the parameter value changes accordingly.

  Hereinafter, processing for one channel in each block such as the sound source unit 114 will be described. A similar process is performed on all 128 channels in a time division manner for each DAC, and a plurality of musical sounds are generated in parallel.

  Note-on NON and F number are input to the pitch counter 504. The pitch counter 504 is reset to zero at the time of note-on, and thereafter accumulates the F number every 1 DAC. This accumulated value is output as an integer part address and a decimal part address. Data excluding the lower 10 bits of the integer part of the accumulated value (referred to as “integer part upper bits”) is input to the VP address generator 505 and the PB address generator 506. The lower 10 bits of the integer part of the accumulated value (referred to as “integer part lower 10 bits”) are input to the reading unit 507. The decimal part of the accumulated value is input to the interpolation unit 508. The pitch counter 504 outputs a transfer instruction signal to the VP address generation unit 505 and the transfer queue 521 at a predetermined timing. The time change of the integer part and the decimal part, the timing of the transfer instruction, and the like will be described in detail with reference to FIG. The pitch counter 504 continues to accumulate after note-off, but stops accumulating when the tone generation processing for that channel is stopped.

  The PB address generation unit 506 reads the address PA described in (2) and (3) of the control register (the address of the first page of the preload area 302 of the waveform memory 126 to be read immediately after the start of sound generation (FIG. 3A) ) And BA (buffer address corresponding to the channel of the waveform memory 126 (FIG. 3A)) are input, and the PB address is output to the reading unit 507. The PB address is an upper address for designating the head of the area to be read in the waveform memory 126 (in reality, since the PB address is only the upper part, 0 for 10 bits is set below the PB address. The assigned address becomes an absolute address designating the head of the area to be read in the waveform memory 126). Specifically, the PB address generator 506 outputs PA as the PB address immediately after the start of sound generation, and after reading the waveform sample data of the first page of the preload area 302 of the waveform memory 126 designated by the PA, Is output as the PB address, and after reading the waveform sample data of the buffer Bia (i is the ch number) corresponding to the channel in the buffer area 303 of the waveform memory 126 designated by the BA, BA + 1 is output as the PB address. (As described above, since BA is an upper part excluding the lower 10 bits or less, BA + 1 indicates the buffer Bib), and corresponds to the corresponding channel of the buffer area 303 of the waveform memory 126 designated by BA + 1. After reading the waveform sample data in the buffer Bib, BA is output as the PB address again. And, thereafter, it is output as PB address alternately BA and BA + 1 as read alternately buffer Bia and Bib. The lower 10 bits of the integer part output from the pitch counter 504 are added to the lower order of such a PB address to generate a read address (absolute address). The reading unit 507 reads the waveform sample data of the channel at the read address from the waveform memory 126 via the memory I / F 112. Here, it is assumed that two samples of the waveform sample at the read address and the next waveform sample are read out. The data length of the waveform memory 126 is one word, and one sample of waveform data is stored at each address.

  The interpolation unit 508 calculates one interpolation sample by performing two-point interpolation (linear interpolation) between two read samples for each DAC according to the decimal part address (output from the pitch counter 504). . For the channel for which the tone generation process has been stopped, the interpolation sample “0” is output.

  The amplitude envelope generator (EG) 503 generates an amplitude envelope (AE) waveform based on the parameters for generating the envelope waveform of the channel and outputs the amplitude envelope (AE) waveform to the volume control unit 509. For each DAC, the volume control unit 509 controls the amplitude of the interpolation sample based on the value of the AE waveform and outputs it as a musical sound sample of the channel. The accumulating unit 510 accumulates each tone sample for all channels for each DAC and outputs the tone sample as a result of mixing all channels. It should be noted that reverberation and other effects may be imparted and output by an effect imparting unit (not shown).

  The integer part upper bits output from the pitch counter 504 are input to the VP address generator 505 and the PB address generator 506. The VP address generation unit 505 receives the second virtual page address WA of the waveform data read by the channel in the NAND flash memory 125 (FIG. 2B). The VP address generation unit 505 generates a VP address based on the input data. The VP address is a virtual page address that specifies the next page to be read in the channel of the waveform data of the NAND flash memory 125. The page to be read from the flash memory 125 is on the flash memory 125 specified by the address WA while the sound source 114 is reading the waveform sample from the page specified by the address PA of the preload area 302 of the waveform memory 126 immediately after the note-on. VP address at this time is WA. As described with reference to FIG. 2, since the waveform data is stored in continuous pages in the virtual page address space, the VP address subsequently changes as WA + 1, WA + 2, WA + 3,. The change of the VP address will be described in detail with reference to FIG.

  In mode 1, the VP address generation unit 505 accesses the address conversion table 301 of the waveform memory 126 via the memory I / F 112 every time a transfer instruction is input, and corresponds to the VP address at that time. The real page address to be obtained is obtained, and the real page address is written in the NPAi of the channel on the waveform memory 126. Therefore, in mode 1, the VP address generation unit 505 functions as a “next page address setting unit”. In the case of mode 2, the VP address generation unit 505 performs the above-described mode 1 for the first VP address (when the value is WA, the first time is the first transfer instruction). Similarly, referring to the address conversion table 301, a real page address corresponding to the VP address is obtained, and the real page address is written in the NPAi of the channel on the waveform memory 126. In the case of mode 2, the setting of the NPAi of the corresponding channel when the VP address changes as WA + 1, WA + 2, WA + 3,... Is performed by the B → M transfer unit 110 and is not performed by the VP address generation unit 505. . Therefore, in the case of mode 2, the B → M transfer unit 110 functions as a “next page address setting unit” (except for the first time). The change of the address set in the NPA of the waveform memory 126 will be described in detail with reference to FIG.

  The transfer waiting queue 521 is a first-in first-out queue. When a transfer instruction is output from the pitch counter 504, the transfer queue 521 takes in the channel number output from the VP address generator 505 and registers it in the queue. The timing will be described in detail with reference to FIG. In short, the channel number registered in the transfer queue 521 is the NPAi of the channel in the waveform memory 126 until the page data read from the waveform memory 126 at that time is read for the channel of the channel number. This means that it is necessary to transfer the page data at the actual page address set to “1” from the NAND flash memory 125 to the waveform memory 126 via the transfer buffer 109. The transfer performed by the F → B transfer unit 108 and the transfer performed by the B → M transfer unit 110 described with reference to FIG. When a plurality of channel numbers are registered, the transfer queue 521 outputs the channel numbers in order from the previously registered channel number, and accordingly, the F → B transfer unit 108 and the B → M transfer unit. 110 performs transfer according to the output channel number.

  When page data is not transferred from the NAND flash memory 125 to the transfer buffer 109, the F → B transfer instruction unit 522 extracts the channel number i from the transfer waiting queue 521 and sends it to the F → B transfer unit 108. The channel number i is sent, and an instruction to transfer the page data to be read next in the NAND flash memory 125 to the transfer buffer 109 is issued. In response to this instruction, the F → B transfer unit 108 reads out the next page address NPAi of the channel number i in the waveform memory 126 via the memory I / F 112, and a read instruction designating the next page address NPAi in the flash memory 125. Is output. In response to the read command, one page data (2112 bytes) is burst transferred from the flash memory 125, so the F → B transfer unit 108 writes the transfer data into the transfer buffer 109. As a result, the one-page data transfer (numbered 411 to 413) described in the time chart of “NAND flash → transfer buffer” in FIG. 4 is performed.

  Further, when the F → B transfer instruction unit 522 issues a transfer instruction to the F → B transfer unit 108, the F → B transfer instruction unit 522 transmits the transfer instruction and the ch number to the B → M transfer instruction unit 523. Upon receiving this transfer instruction, the B → M transfer instruction unit 523 outputs the channel number and the transfer instruction to the B → M transfer unit 110, and the B → M transfer unit 110 outputs the page data (data area of the data area). 2048 bytes) is controlled to be burst transferred to the buffer corresponding to the channel of the waveform memory 126. When the B → M transfer unit 110 receives the channel number and the transfer instruction from the B → M transfer instruction unit 523, the access period of the waveform memory 126 by the sound source 114 in a period of 1 DAC cycle after 2 DAC cycles from the timing of the transfer instruction. After (421 in FIG. 4), a read command specifying the address of the page data is output to the transfer buffer 109. As a result, the first 256 words of the page data are burst-transferred from the transfer buffer 109, and the transfer data is written to the buffer area of the channel of the waveform memory 126 as shown at 422 in FIG. . Further, the subsequent 256 word × 3 block data is also written into the buffer area of the corresponding channel in the waveform memory 126 by burst transfer using the subsequent 3DAC section under the control of the B → M transfer unit 110. As described above, burst transfer (numbered 422) from the transfer buffer 109 to the buffer area of the waveform memory 126 described in the time chart of “transfer buffer → waveform memory” in FIG. 4 is performed. In the case of mode 2, the B → M transfer unit 110 performs a process of writing the “next page pointer NP” of the data in the transfer buffer to the NPAi of the chi in the waveform memory 126. This writing process to NPAi is performed at the timing of section 425 in FIG. 4 (but before error correction writing is performed).

  Note that when 256 words are transferred to the buffer area of the waveform memory 126 of the corresponding channel by burst transfer from the transfer buffer to the waveform memory, there are two buffers of the corresponding channel, Bia and Bib. It is necessary to keep. In the system of the present embodiment, at that time, the waveform sample should be read from the preload area 302 of the waveform memory 126 or one of the buffers Bia and Bib by the sound source 114 for the corresponding channel. Alternatively, if reading from the buffer Bia is performed, the buffer Bib is set as the burst transfer destination, and if reading is performed from the buffer Bib, the buffer Bia is set as the burst transfer destination.

  The error correction unit 111 analyzes the transfer data when the NAND flash → transfer buffer transfer is performed, and executes the error correction calculation process indicated by 431 in FIG. 4. When the transfer to the additional information INF transfer 413 is completed, the error correction unit 111 determines whether or not an error has occurred with respect to the transfer data, whether or not there is an error, and whether or not the error correction is possible. And confirm. If there is an error and the error can be corrected and the correction location is calculated, the error correction unit 111 issues a correction instruction for the correction location in the waveform memory 126 via the memory I / F 112 in the section 425 of FIG. Perform error correction. In the case of mode 2, since NPAi is also subject to error correction, NPAi may be corrected by this error correction.

  The error correction unit 111 outputs error correction information indicating that a correctable error has occurred to the error detection unit 524 (dotted line 541). Similarly, when there is an error and the error cannot be corrected, the error correction unit 111 outputs error correction information indicating that an uncorrectable error has occurred to the error detection unit 524 (dotted line 541). In both cases where correction is possible / impossible, the error correction information includes the actual page address on the flash memory 125 where the error has occurred.

  The error detection unit 524 inputs the error correction information from the error correction unit 111. When correctable error correction information is input, the error detection unit 524 notifies the CPU 101 of the error correction information (dotted line 542). When error correction information that cannot be corrected is input, the error detection unit 524 instructs the amplitude EG 503 to perform a force dump of the channel to rapidly attenuate the tone of the channel (dotted line 545), and also outputs the error correction information. The CPU 101 is notified (dotted line 542).

  The error detection unit 524 receives from the reading unit 507 a PB address (referred to as a “read PB address”) that is an address for specifying the buffer area on the waveform memory 126 that the sound source 114 is currently reading. (Dotted line 544). Further, the error detection unit 524 sends an address for identifying the buffer area on the waveform memory 126 that is the transfer destination of the transfer from the transfer buffer 109 from the B → M transfer unit 110 (this is referred to as the “PB address being transferred”). When the transfer is completed, a transferred signal indicating that is input (dotted line 543). If transfer and reading using the buffers Bia and Bib on the waveform memory 126 are normally performed for a certain channel, assuming that the read PB address is now Bia, the PB address being transferred next becomes Bib. The transfer starts, the transfer ends, and a transfer completed signal is input. Next, the read PB address becomes Bib and reading from the Bib starts. Next, the transfer PB address becomes Bia and the transfer starts. Then, the transfer is completed and a transferred signal is input. Next, the read PB address becomes Bia, reading from Bia starts, and so on. If the transfer cannot be made in time for some reason, the read PB address becomes Bib before the transfer complete signal is generated from the transfer PB address is Bib, or the transfer PB address is transferred from the Bia state. The read PB address becomes Bia before the signal is generated. The error detection unit 524 checks such a transfer error. When a transfer error occurs, the error detection unit 524 instructs the amplitude EG 503 to forcibly dump (force dump) the channel, as indicated by a dotted line 545. Quickly attenuates the tone of the channel. In addition, the error detection unit 524 notifies the CPU 101 that the transfer error has occurred along with the channel number (dotted line 542).

  FIG. 6 shows temporal changes (for 1 ch) of various addresses after the start of sound generation. In the figure, “integer part lower 10 bits & fraction part” indicates the time change of the integer part lower 10 bits and the fraction part of the accumulation result obtained by accumulating the F number of the channel by the pitch counter 504 in FIG. The value increases as the F number accumulates, and when the lower 10 bits of the integer part exceed 1023, a carry occurs and returns to 0 (strictly, the fractional part value remains, so it is 1 or less. Increase again). As a result, a sawtooth change as shown in the figure is shown. “Integer part upper bits” indicates the time change of the integer part upper bits of the pitch counter 504 (the higher part excluding the lower 10 bits and the decimal part of the integer part from the accumulated result). Immediately after the start of sounding, it is 0, and thereafter, every time a carry of “the lower part of the integer part 10 bits & the decimal part” occurs, it increases by one.

  “Transfer instruction” indicates a transfer instruction signal output from the pitch counter 504 of FIG. 5 to the transfer queue 521. At the start of sound generation, it is output as numbered 601 and thereafter is output as numbered 602 and 603 every time a carry of the “integer part lower 10 bits & decimal part” occurs for that channel. “PB address” indicates a time change of the PB address of the channel output from the PB address generation unit 506 in FIG. Immediately after the start of sound generation, PA (address indicating the first page of the preload area 302 of the waveform memory 126 (FIG. 3 (a))) is output as the PB address, and thereafter every time "integer part upper bits" is counted up. BA and BA + 1 (BA is the address of the buffer Bia corresponding to the channel, and BA + 1 is the address of the buffer Bib corresponding to the channel) are alternately output as the PB address.

  “VP address” indicates the time change of the VP address of the channel, which is internally generated by the VP address generation unit 505 in FIG. Immediately after the start of sound generation, the next page to be read into the waveform memory 126 is the page pointed to by the second page address WA of the waveform data (FIG. 2B), so WA is output as the VP address. Thereafter, each time “integer part upper bits” is counted up, it is incremented by one. Each time a transfer instruction for the channel is received, the VP address generation unit 505 adds the value of the “integer part upper bits” of the channel to the WA of the channel to generate a VP address of the channel. Since the waveform data is sequentially stored in successive pages with virtual page addresses, the VP address may be generated by incrementing from WA each time a transfer instruction is received. In the example of FIG. 2B, WA indicates the second page W2 (1) + Inf, WA + 1 indicates the third page W2 (2) + Inf, and so on.

  “P1 address (mode 1)” indicates a real page address corresponding to the VP address of the channel, which is a virtual page address generated by the VP address generation unit 505 in each time interval in the case of mode 1. In the case of mode 1, the basic process is to obtain the real page address corresponding to the virtual page address with reference to the address conversion table 301. While the sound source 114 is reading the waveform sample of the first page Wx (0) of the ch with PB address = PA, the VP address that is the virtual page address of the page to be read next from the flash memory 125 is given by WA. Therefore, the VP address generation unit 505 obtains the real page address T (WA) corresponding to WA with reference to the address conversion table 301 and writes the real page address in the NPAi of the corresponding channel in the waveform memory 126. T (*) indicates a real page address corresponding to the virtual page address * obtained from the address conversion table 301. Similarly, every time there is a transfer instruction, the VP address generation unit 505 obtains real page addresses corresponding to the VP addresses WA + 1, WA + 2,... And sets them in the NPAi of the waveform memory 126.

  “P2 address (mode 2)” indicates a real page address corresponding to the VP address of the channel that the VP address generation unit 505 generates in each time interval in the case of mode 2. In the case of mode 2, the basic process is to acquire the actual page address to be read next by following the “pointer NP to the next page” in the page additional information Inf read from the flash memory 125. While the sound source 114 is reading the waveform sample of the first page Wx (0) of the ch with PB address = PA, the VP address that is the virtual page address of the page to be read next from the flash memory 125 is given by WA. Therefore, the VP address generation unit 505 obtains the real page address T (WA) corresponding to WA with reference to the address conversion table 301 and writes the real page address in the NPAi of the corresponding channel in the waveform memory 126. The page data of the actual page address NPAi is read from the flash memory 125 and stored in the buffer of the waveform memory 126 at a transfer execution timing 611 described later. At this time, the B → M transfer unit 110 is read to the transfer buffer 109. “Pointer NP to next page” in the additional information Inf of the page data is set to the NPAi of the channel in the waveform memory 126. The “next page pointer NP” set in this NPAi becomes the actual page address corresponding to the next VP address = WA + 1. When VP address = WA + 1 is updated in the next transfer instruction 602, the NPAi of the channel has already been set. In the same manner, in the transfer executed at each transfer execution timing 612, 613,..., The “next page pointer NP” is set in the NPAi of the waveform memory 126, thereby substantially corresponding to each VP address. The real page address is set to NPAi.

  The “transfer execution timing” is determined by the F → B transfer unit 108 and the B → M transfer unit 110 in accordance with instructions from the F → B transfer instruction unit 522 and the B → M transfer instruction unit 523 in FIG. FIG. 4 shows the timing for actually executing the transfer described in FIG. As described above, since the transfer by the F → B transfer unit and the B → M transfer unit is executed in the order in which the channel numbers are registered in the transfer waiting queue 521, the transfer instruction 601 is output and the transfer waiting queue 521 Even if the channel number of the channel is registered, if the channel number of another channel is registered in the transfer waiting queue 521 at that time, a little after the transfer according to the registered channel number is executed. At the timing of the delayed number 611, the channel number of the channel is output from the transfer queue 521, and the corresponding transfer is performed. Similarly, the transfer of the channel number registered in the transfer queue 521 by the transfer instruction 602 is assigned number 612, the transfer of the channel number registered in the transfer queue 521 by the transfer instruction 603 is assigned number 613, and so on. In addition, the transfer is executed with a slight delay from the transfer instruction. The delay is not constant because it depends on how busy the transfer is performed in other channels. Of course, the transfer registered in the transfer queue 521 by the transfer instruction 601 is executed before the transfer instruction 602 arrives, the transfer registered in the transfer queue 521 by the transfer instruction 602 is executed before the transfer instruction 603 arrives, and so on. Thus, it is necessary to execute before the next transfer instruction comes.

  Next, timing design regarding access to the waveform memory 126 will be described.

  In the system of this embodiment, 1024 samples transferred to the transfer buffer 109 by one unit access (reading of one page data from the flash memory 125) are divided into 4 DACs, and 256 samples (512 bytes) are waveformd from the transfer buffer 109. Burst transfer is performed to the buffer of the memory 126 (FIG. 4). The burst transfer of 256 samples divided into 4 DACs is in line with the fact that 4 DACs are required for one unit access. A period obtained by excluding the burst transfer period and the refresh period of the waveform memory 126 from one DAC period is a period in which the sound source 114 reads waveform samples to generate musical sounds of each sounding channel. Therefore, in a case where a large burst transfer period must be taken, the readout period for the sounding channel must be reduced, and therefore the number of soundable channels needs to be designed accordingly. Conversely, if the burst transfer period can be further reduced, the number of soundable channels can be increased accordingly.

  Here, “bandwidth” and “total bandwidth” will be described. “Total bandwidth” means the maximum number of pages that can be read from the flash memory 125 (in other words, the playback time when one page of sample data is played back at the rate of one sample for each sampling period) The upper limit of the number of times that a transfer instruction can be issued during the basic playback period). In this embodiment, the basic playback period is 1024 DAC, and it takes 4 DAC to read one page from the flash memory 125, so the total bandwidth is 256. “Bandwidth” is the maximum number of pages read from the flash memory 125 in a certain channel during the basic playback period (the maximum number of times that channel issues a transfer instruction). For example, if a tone is generated with F number = 1 in a certain channel, if a transfer instruction is issued only once during the basic playback period 1024DAC, the basic playback is performed with 1024 samples written in the waveform memory by the single transfer. Since the reproduction of F number = 1 within the period can be covered, the bandwidth of the channel is 1. If the F number = 2, the bandwidth is 2. If F number = 1.1, 11 transfer instructions (transfer of 11 pages) are required for 10 basic playback periods, so you must issue two transfer instructions somewhere in the 10 periods. The bandwidth of the channel is 2. Therefore, the value obtained by rounding up the fractional part of the F number is the bandwidth of the channel. Also, it is necessary that the sum of the bandwidths of all channels does not exceed the total bandwidth. This is because the transfer request generated in any one of the channels cannot be processed.

  In the system of this embodiment, the CPU 101 manages the bandwidth allocated to each channel. The total bandwidth Tbw is determined in advance based on various design conditions. Also, an internal variable Abw indicating the allocated total bandwidth and an internal variable Cbw (i) indicating the bandwidth allocated to the i th ch are provided, and the CPU 101 initially sets all these internal variables to 0 at the time of initial setting. To do. When allocating a channel for sound generation, the CPU 101 compares the bandwidth bw of the channel with a value obtained by subtracting the allocated total bandwidth Abw from the total bandwidth Tbw (indicating an available bandwidth). Confirm that the former is less than or equal to the latter (if the former is larger than the latter, the bandwidth of the channel cannot be allocated). If the former is less than or equal to the latter, it means that there is a bandwidth to be allocated. Therefore, the bandwidth bw of the channel is added to the allocated total bandwidth Abw, and bw is stored in Cbw (i). When the channel is muted and released, Cbw (i) is subtracted from Abw, and Cbw (i) is reset to zero. In this way, the allocated bandwidth Abw and the assignable bandwidth Tbw-Abw are always managed. In the system of this embodiment, the F number upper limit value is not limited, and the total number of unit accesses (bandwidth) for all channels in the basic playback period is limited to the upper limit of the entire bandwidth. In short, in the basic playback period, a large number of unit accesses are required for the pitch-up ch, but conversely, the number of unit accesses can be reduced for the pitch-down ch. To the upper limit (total bandwidth).

  FIG. 7A is a flowchart of main processing executed by the CPU 101 when the system of the present embodiment is turned on or reset. In step 701, initialization is performed, and in step 702, the transfer control unit 113 is instructed to transfer the address conversion table and each waveform data to the waveform memory 126 on the first page. Also, mode information M indicating mode 1 or mode 2 is initialized in the mode register 501. As described with reference to FIG. 2, the address conversion table transferred here differs depending on the mode information M to be set. That is, in mode 1, a 16-bit input 16-bit output table is transferred, and in mode 2, a 20-bit input 20-bit output table is transferred. After the above initial setting process, an event is detected at step 703, and when there is an event, the process of executing the event process at step 705 is repeated.

  FIG. 7B is a flowchart of the note-on event process. This process is executed in step 705 when the CPU 101 inputs a MIDI note-on event from, for example, the MIDI I / O 124. In step 711, the note number and velocity are set in the registers nn and vel based on the performance information of the input MIDI note-on event. In step 712, one waveform data corresponding to nn and vel is determined (selected) from a plurality of waveform data corresponding to the currently selected tone color in the flash memory 125. In the NOR type flash memory 121 of FIG. 1, tone color data of each tone color is prepared, and the tone color data includes waveform selection information for selecting waveform data corresponding to nn and vel. In step 713, a sounding channel is assigned and the assigned channel number is set in the register a.

  In step 713, the above-described bandwidth is secured. That is, it is confirmed that bw ≦ Tbw−Abw, and Cbw (a) ← bw and Abw ← Abw + bw are set. When bw> Tbw-Abw, that is, when there is no bandwidth to be allocated to the allocatable bandwidth, the channel to be silenced is determined from the currently sounding channel, and the tone of the channel is rapidly attenuated to release the channel. Then, the bandwidth of the channel is subtracted from Abw, the Cbw of the channel is set to 0, and then the bandwidth is secured again. When there is no empty channel to be assigned, any of the sounding channels is muted and released so that it can be assigned.

  In step 714, various parameters are set in the ach area of the control register 502 of the sound source 114. The F number for controlling the pitch shift can be determined from the pitch difference (cent) when the determined waveform data is not pitch-shifted and the pitch (cent) indicated by the note number nn. The above-described parameters related to WA, PA and envelope are included in the timbre data. The BA can be determined from the assigned channel number. Finally, in step 715, an ach sounding start instruction is written in note-on NON, and the process ends.

  As described above, since data is set in the sound source register including note-on NON for ach, sound generation at ach is performed by the operation described with reference to FIGS. This sound generation process is executed by hardware from the NAND flash memory 125 to the sound source 114 in FIG. 1, and the CPU 101 is not interrupted.

  FIG. 8A shows the processing of the VP address generation unit 505 when a transfer instruction for a certain channel is received. This process is a process executed by hardware. In step 801, as described in FIG. 6, the value of “integer part upper bits” is added to WA to generate a VP address. When the mode is step 1 in step 802, or in the case of mode 2 and the first processing in step 803, the process proceeds to step 804. If it is not the first time in step 803, the process proceeds to step 806. In step 804, the real page address (P address) corresponding to the VP address is acquired with reference to the address conversion table (301 in FIG. 3A). This P address corresponds to the P1 address in the case of mode 1 or the first P2 address in the case of mode 2 shown in FIG. In step 805, the P address is written into the ch area NPAi of the NPA. In step 806, the channel number is output to the transfer queue 521.

  FIG. 8B shows the processing of the B → M transfer unit 110 when it receives a transfer instruction from the B → M transfer instruction unit 523 (except for the process of outputting the PB address being transferred to the error detection unit 524, etc.). ). This process is a process executed by hardware. In step 811, the channel number passed from the B → M transfer instruction unit 523 is acquired. In step 812, 1024 words of waveform data for one page on the transfer buffer 109 are transferred to the buffer area of the channel in the waveform memory 126 in 256 words divided into four times. The transfer timing is controlled as described with reference to 422 in FIG. Next, in the case of mode 2 in step 813, in step 814, “pointer NP to next page” on the transfer buffer 109 is written to the NPAi of the channel in the waveform memory 126.

  Next, the processing of the CPU 101 when an error occurs will be described. As described with reference to the error correction unit 111 and the error detection unit 524 in FIG. 5, in this system, (1) error correction when a correctable error occurs in the data read from the flash memory 125 and the error is corrected. The CPU 101 is notified of information, (2) error correction information indicating that an uncorrectable error has occurred in the data read from the flash memory 125, and (3) error correction information indicating that a transfer error has occurred. The error correction information includes the channel where the error has occurred and the actual page address of the flash memory 125.

  First, the case of the correctable error (1) will be described. In this case, the tone generation at that channel is continued with the corrected waveform data. Upon receiving this error notification, the CPU 101 registers the actual page address in which the error has occurred in the NOR flash 121 as the “substitution waiting page” in the interrupt process. Since tone generation is continued with the corrected waveform data, the user is not immediately notified of the occurrence of a correctable error by displaying a message or outputting a predetermined sound. However, such notification is performed after the musical tone generation process is completed. The user who has received the notification activates processing when there is registration of the “waiting page for substitution” in FIG. 9 by a predetermined operation (or automatically in the background) when there is no access to the flash memory 125.

  FIG. 9A shows the processing of the CPU 101 in mode 1. In step 901, one block including the error page registered in the “substitution waiting page” is read from the flash memory 125 via the memory I / F 107, and data correction of the error page in the block is performed on the RAM 103. Appropriate page data (2112 bytes) is obtained by attaching an error correction code to the corrected data. Note that not only an error page but also other pages of the block may be subjected to error check and correction using an error correction code. When appropriate data of the entire block is obtained, one unused real block on the flash memory 125 is selected in step 902. In step 903, the corrected one block of data is written into the selected unused block (referred to as a substitute block) via the memory I / F 107. In step 904, the real block address indicated by the virtual block address of one block including the error page in the address translation table on the flash memory 125 is changed to the real block address of the substitute block. As described above, one block including an error page can be replaced with a replacement block.

  In the case of mode 1, the same data as the address conversion table in the NAND flash 125 and management data for managing the location of unused real blocks are stored in advance in the NOR flash 121 (or on the RAM 103). Keep it. The CPU 101 always manages the usage status of each page of the waveform data of the NAND flash 125 using these data.

  FIG. 9B shows the processing of the CPU 101 in mode 2. In step 911, the error page registered in the “substitution waiting page” is read from the flash memory 125 via the memory I / F 107, and data correction of the error page is performed on the RAM 103. Appropriate page data (2112 bytes) is obtained by attaching an error correction code to the corrected data. In step 912, one unused page on the flash memory 125 is selected. In step 913, the corrected page data is written into the unused page (referred to as a substitute page), and the “next page pointer NP” of the previous page of the page is updated to indicate the substitute page. . If the error page is the first page of the waveform data, the virtual page address of the error page in the address conversion table on the flash memory 125 is replaced with the previous page “pointer NP to the next page” instead of updating the previous page. The real page address to be pointed is changed to the real page address of the substitute page. As described above, the error page can be replaced with the replacement page.

  In the case of mode 2, the same data as the address conversion table in the NAND flash 125 and management data for managing the location of unused real pages are stored in advance in the NOR flash 121 (or on the RAM 103). Keep it. The CPU 101 can obtain the actual address of the first page of the waveform data including the error page by referring to the address conversion table in the NOR flash 121, and traces the error page by following the “pointer NP to the next page” from the first page. Can specify the previous page. It should be noted that the NOR type flash 121 may be provided with management data for managing the order of actual pages (the status of links between pages) in each waveform data, thereby obtaining the previous page of the error page. If the additional information Inf includes not only the “pointer to the next page NP” but also the “pointer to the previous page”, the real address of the previous page of the error page can be immediately known, so that the previous page can be easily accessed. .

  The NAND flash memory cannot be overwritten in one operation, and is distinguished from a block of a plurality of continuous pages (for example, 32 pages and 64 pages) including a page to be written (blocks described in FIG. 2C). Therefore, it is necessary to perform writing after erasing the memory block). Therefore, in writing to the NAND flash memory 125 in the above steps 903, 904, and 913, the data of the memory block including the page to be written is once read on the RAM 103, and then the memory block is erased and read on the RAM 103. A necessary part of the data is changed, and the changed data is written back to the erased memory block.

  Next, the case of the error (2) that cannot be corrected will be described. In this case, as described above, the musical sound being generated by the channel is automatically force dumped (without an instruction from the CPU 101). Upon receiving this error notification, the CPU 101 enables the sound allocation of the channel as an open channel by interrupt processing, returns the bandwidth allocated to the channel to an allocatable bandwidth, and displays a message to that effect. The user is notified by outputting a predetermined sound. This notification may be performed after the musical tone generation process is completed, instead of immediately. The user who has received the notification requests the manufacturer to repair (the flash memory 125 seems to be defective when an uncorrectable error occurs).

  When attention is focused on one page of the flash memory 125, the probability that an uncorrectable error suddenly occurs from a normal reading state without an error is extremely low. First, a correctable error occurs several times. Usually, an uncorrectable error occurs. Therefore, when a correctable error occurs, the occurrence of an uncorrectable error can be suppressed by replacing the page in which the error has occurred with a substitute page (or substitute block).

  Next, the case of the transfer error (3) will be described. In this case, as described above, the musical sound being generated by the channel is force dumped. Receiving this error notification, the CPU 101 enables the sound allocation of the channel as an open channel by the interruption process, and returns the bandwidth allocated to the channel to an allocatable bandwidth. In addition, the value of the total bandwidth Tbw is lowered by a predetermined number so as to limit the bandwidth so that transfer errors are less likely to occur.

  In addition, the various values in the said embodiment can each be changed suitably. The page size of the flash memory 125 is not limited to 2112 bytes, and may be any size. For example, the data area may be 1024 bytes or 4096 bytes, and the additional information Inf may be any size (depending on the specifications of the flash memory 125). The data width is not limited to 8 bits, and may be 4 bits, 16 bits, or the like. The size of one block in the mode 1 described with reference to FIG. 2C is not limited to 16 pages, and may be 32 pages, 64 pages (power of 2), or the like. One block may be one page (in this case, there is no concept of a block as a result). The number of unit accesses in the basic playback period is not limited to 256, but may be any number such as 300, 450, 512 (depending on the specifications of the flash memory 125). The number of sample data read from the waveform memory 126 is not limited to 256 (2 samples per channel for 128 channels), but may be any number such as 310, 460, 512 (the sound source 114 reads waveform samples from the waveform memory 126). (It depends on the specification of how many resolution time slots can be used to read one sample.) The number of soundable channels is not limited to 128, and any number such as 64, 80, 160, etc. can be designed (under the above-described various bottleneck conditions). The number of bits of one sample is not limited to 16 bits, and may be 12 bits, 14 bits, or the like.

  In the example of FIG. 2B, the error correction code is provided after the 2048-byte waveform data, but the error correction code may be arranged at an arbitrary position or divided. For example, if the unit for performing the error correction calculation is 256 bytes, the 256-byte error correction code may be arranged after the 256-byte waveform data.

  In the above embodiment, the interpolation processing by the interpolation unit 508 is two-point interpolation, but may be interpolation between any number of points such as three-point interpolation and four-point interpolation. However, when performing four-point interpolation, for example, when reading waveform samples from the waveform memory 126 for each channel, four consecutive samples are read in one reading, so the number of soundable channels must be reduced. There are cases where it is necessary. When reading a plurality of samples from the waveform memory 126, they may be read at a high speed in a burst mode. The interpolation unit 508 may be an interpolation unit including a sample buffer.

  In the above embodiment, the reading unit 507 accesses the waveform memory 126 twice per channel during each DAC period, and reads out two samples necessary for the interpolation processing of the channel from the waveform memory 126. However, as disclosed in Japanese Patent No. 2888264, an interpolation buffer (prior application) that stores the latest n (n is the number necessary for the interpolation process) of the samples read in the past in the reading unit 507. May be provided to reduce the number of accesses to the waveform memory 126 per channel. In this case, the number of accesses to the waveform memory 126 per channel is the progression of the integer part address of each channel output by the pitch counter 504. For example, if the F number of each channel is limited to “1” or less, samples of 256 channels can be read out by 256 accesses per DAC as in the above embodiment, and therefore the tone generator LSI 100 can generate the maximum sound generation channel. The number is designed as 256. When the F number is not limited, the maximum number of soundable channels changes dynamically according to the maximum value of the sum of the rounded numbers of the F number set for each channel. In any case, it is optimal that the “bandwidth” of the flash memory 125 (256 in the embodiment) and the number of accesses to the waveform memory (256 in the embodiment) are matched. .

  In the above embodiment, in the mode 2, the conversion from the virtual address of the first page transferred from the flash memory 125 to the real address (acquisition of T (WA) of the P2 address in FIG. 6) is performed regardless of the CPU 101. Although the generation unit 505 automatically performs the processing (processing of 803 and 804 in FIG. 8A), the first address conversion may be performed by the CPU 101. For this purpose, the CPU 101 stores a real address (data corresponding to T (WA)) corresponding to the virtual address WA of each waveform data, and, for example, the waveform memory 126 via the control register 502 when a sounding start instruction is issued. The real address may be set in the NPAi. The same may be done for mode 1. When transferring the second and subsequent pages, it is important that the CPU 101 is not interrupted, and there is not much influence on the first page even if some processing is increased. An interrupt requires a large load because the CPU 101 needs to save a register.

  In the above embodiment, the waveform data is stored in the NAND flash memory. However, the storage medium is not limited to the NAND flash memory. The present invention can be widely applied to the case where waveform data is stored in various semiconductor memories that can perform page-by-page access at a high speed and cause data errors that require data correction.

  In the above embodiment, linear waveform data in which one word is one sample has been described as an example, but the waveform data may be compressed in an arbitrary format. In that case, since the number of samples per page of 1024 words varies, it is difficult to calculate the above-mentioned bandwidth accurately. The bandwidth may be calculated using

  In the above embodiment, the address conversion table is arranged in the waveform memory, but a storage unit for storing the address conversion table may be provided in the LSI 100 instead of in the waveform memory. Further, although the CPU 101 is built in the tone generator LSI 100, a CPU_I / F unit for interfacing with the CPU is incorporated instead of the CPU 101, and control is performed from the external CPU 101 ′ via the CPU_I / F unit. It is good also as a structure to be made. Further, the tone generator LSI 100 may not include any one or more of the memory I / F unit 102, the RAM 103, the display I / F unit 104, the parallel I / F unit 105, and the serial I / F unit 106. Good. Conversely, the waveform memory 126 may be changed to a static memory type and taken into the sound source LSI 100.

  101 ... CPU, 103 ... RAM, 103 ... RAM, 104 ... Display I / F, 105 ... Parallel I / F, 106 ... Serial I / F, 107 ... Memory I / F, 108 ... F → B transfer unit, 109 ... Transfer buffer, 110 ... B → M transfer unit, 111 ... Error correction unit, 112 ... Memory I / F, 113 ... Transfer control unit, 114 ... Sound source, 121 ... NOR flash memory, 122 ... Display unit, 123 ... Operation Child 124 ... MIDI I / O 125 ... NAND flash memory 126 ... Waveform memory 127 ... DAC 128 ... Sound system

Claims (5)

A musical sound generating device that has a plurality of channels and generates musical sounds on each of those channels,
An external memory storing a series of sample data of a plurality of waveform data in a plurality of continuous pages in a virtual address space, a musical sound generating unit for generating a musical sound waveform, and the musical sound generating unit according to input performance information And a control unit for controlling
The musical sound generator is
A waveform memory having a first waveform area storing sample data of the first page of each waveform data, and a buffer area for each channel;
An address conversion table storage unit for storing an address conversion table for converting a virtual page address (VP address) for specifying a page in the virtual address space into a real page address;
A control register for setting a parameter when the control unit instructs the start of sound generation, wherein at least speed information corresponding to a pitch of a musical sound to be generated and waveform data used for sound generation are set in each channel region; A control register in which a top waveform address indicating the top waveform area of the waveform memory, waveform position information indicating the position of the waveform data used for sound generation in the external memory, and amplitude control information defining the amplitude of the tone to be generated are set When,
A pitch counter that generates a count value that increases at a speed indicated by the speed information in response to a sound generation start instruction for each channel, and generates a transfer instruction every time the count value advances by one page;
For each channel, according to the count value, first, sample data on the first page of the waveform data indicated by the first waveform address is read from the waveform memory, and then sample data is repeatedly read from the buffer area of the channel. A reading unit;
For each channel, a virtual page address indicating a page to be read next in the virtual address space is generated from the external memory based on the waveform position information, and the virtual page address is referred to the address conversion table. A next page address setting unit that converts the real page address and sets the real page address in the next page address storage unit;
In response to the sound generation start instruction and the transfer instruction for each channel, a transfer waiting queue that captures the channel number of the channel,
The fetched channel number is sequentially extracted from the transfer queue in a first-in first-out manner, and sample data of the page indicated by the next page address information of the channel set in the next page address storage unit is read from the external memory. A transfer unit that performs burst reading and writes the buffer area of the channel indicated by the channel number of the waveform memory;
An amplitude control unit for controlling the amplitude of the sample data read by the reading unit according to the amplitude control information for each channel and forming sample data of a musical sound waveform;
The controller is
One of the plurality of channels is allocated according to the pitch of a new musical tone and performance information indicating the start of sound generation, and the speed information corresponding to the pitch is assigned to the channel area of the control register. The musical tone generating apparatus, wherein the head waveform address, the waveform position information, and the amplitude control information are set, and the sound generation start of the channel is instructed. In the musical sound generating apparatus according to claim 1,
The address conversion table is stored in the external memory,
A musical tone generating apparatus, wherein the address conversion table is read from the external memory and stored in the address conversion table storage unit when the apparatus is activated. In the musical sound generating device according to claim 1 or 2,
The musical tone generating apparatus, wherein the address conversion table storage unit is provided in the waveform memory. In the musical sound generating device according to any one of claims 1 to 3,
The musical sound generator is
For the page data read from the external memory by the transfer unit, an error correction code is used to detect an error in the sample data of the page, and if there is an error and there is an error, the error is corrected. An error correction unit that executes the correction when the detected error is correctable, and
An error detection unit that, when a correctable error is detected by the error correction unit, sends an error notification to the control unit to that effect and information specifying the page on the external memory where the error has occurred, and
The controller is
(1) Record information specifying the page on which the correctable error has occurred as an alternative waiting page,
(2) When there is a page recorded as the substitute waiting page, a substitute page is secured in the external memory by a background process automatically started or by a process started by a user instruction. The page data recorded as the substitution waiting page is read, and if an error occurs in the reading, error correction is performed to obtain appropriate data, the appropriate data is stored in the substitution page, and an error is detected. Replace the page where the
(3) In the conversion of the virtual page address of the substitute waiting page into the real page address, the address conversion table is modified so that the real page address of the substitute page can be acquired. In the musical sound generating apparatus according to any one of claims 1 to 4,
2. A musical sound generating apparatus according to claim 1, wherein the external memory is a NAND flash memory composed of an independent integrated circuit.

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