JP5483265B2 - Non-volatile CAM - Google Patents

Description

  The present invention relates to a CAM (Content Addressable Memory). In particular, the present invention relates to a nonvolatile CAM using a magnetoresistive element.

  The CAM compares the input data (search data) with the stored data and outputs the address of the matched stored data. In general, since the CAM performs this comparison operation on all stored data in parallel, data can be retrieved at high speed. CAMs having such functions are used in a wide range of areas, such as network routers and cache memories.

  As a CAM storage element, a CAM cell based on SRAM (Static Random Access Memory) is widely known. As the CAM cell, a cell that can store two logic states “0” and “1” and a cell that can store three logic states “0”, “1”, and “X” are known. The latter is also called a TCAM (Ternary CAM) cell. Here, the bit in the “X” state means “Don't care”, and it is regarded as a match whether “0” or “1” is input as search data. These CAM cells based on SRAM can perform data retrieval at high speed, for example, in a few ns.

  However, the SRAM-based CAM is a volatile element that loses data when the power is turned off. For this reason, in a system equipped with a volatile CAM, the operation cannot be continued from the state before the power is shut off after the power is turned on without any countermeasure.

  One technique for solving this problem is to save data in a separately prepared nonvolatile memory. Specifically, the data stored in the CAM is transferred to and stored in the nonvolatile memory before the power is shut off, and the data is written from the nonvolatile memory to the CAM after the power is turned on. As a result, the data is preserved even when the power is turned off. However, this method has a problem that it takes time to exchange data between the CAM and the nonvolatile memory. In order to increase the speed of data exchange between the CAM and the non-volatile memory, it is conceivable to increase the bus width. However, this increases the number of wires, leading to an increase in chip area and cost. Furthermore, in the case of an unexpected power reduction such as a power failure, there is a possibility that the latest data stored in the CAM cannot be transferred to the nonvolatile memory.

  As another method, there is a technique of detecting a drop in the main power source and switching from the main power source to a backup battery. Thereby, since power is always supplied to the CAM, the CAM data is stored. However, there are problems in that the power of the battery is consumed to store the data and the battery may run out, and the cost of additional parts such as the battery is increased.

  Yet another approach is to apply a non-volatile element to the CAM cell itself instead of a volatile element. Such a technique is disclosed in, for example, Patent Document 1 (Japanese Patent Laid-Open No. 2005-259206) and Patent Document 2 (Japanese Patent Publication No. 2004-525473).

  According to the magnetic associative memory described in Patent Document 1, a memory cell composed of a pseudo spin valve film cell is arranged at the intersection of a digit conductive line and a bit conductive line in a conductive line matrix. The memory cell has a structure in which a soft magnetic layer and a hard magnetic layer are opposed to each other through a nonmagnetic layer. A plurality of memory cells arranged in the column direction are electrically connected in series by a detection conductive line, thereby forming a memory cell column. The bit conductive line is used as a search data input line, and the detection conductive line is used as a read information output line. However, when the number of memory cells connected in series increases, it becomes difficult to secure a sufficient signal difference between the detection conductive line indicating “match” and the detection conductive line indicating “mismatch”. Therefore, there is a problem that it is difficult to increase the capacity.

  Patent Document 2 describes a content / addressable magnetic random access memory. The memory cell includes a pair of MTJ (Magnetic Tunnel Junction) elements, a comparison and coincidence detection circuit, a tag bit line pair, a tag program line pair, an enable line, a word line, a digit line, and a match line. Information indicating a match / mismatch between the input data to the tag bit line pair and the data stored in the cell is output to the match line. The tag program line pair and the digit line are orthogonal to each other, and the pair of MTJ elements are arranged so as to be sandwiched between each of the tag program line pair and the digit line. At the time of data writing, the MTJ element to be written can be selected by selecting the tag program line pair and the digit line. Then, a write current is supplied to both the tag program line pair and the digit line, and a magnetic field generated by the write current is applied to the selected MTJ element, whereby desired data is written to the selected MTJ element. However, in this method, the write current has a low efficiency in generating a magnetic field, and a large write current (typically several mA) is required. Accordingly, the size of a transistor used in a circuit that supplies a write current increases, and the area of a peripheral circuit increases. In addition, since one memory cell requires 14 transistors, it is difficult to reduce the cell area.

JP 2005-259206 A JP-T-2004-525473

  One object of the present invention is to provide a new nonvolatile CAM using a magnetoresistive element.

  In one aspect of the present invention, a CAM comprising a plurality of CAM cells is provided. Each of the plurality of CAM cells includes a nonvolatile storage unit that stores stored data in a nonvolatile manner, a potential holding unit, and a coincidence detection unit.

  The nonvolatile memory unit includes a write current wiring that connects between the first write bit line and the second write bit line. Here, the write current flows between the first write bit line and the second write bit line through the write current wiring. The nonvolatile storage unit further includes a first magnetoresistive element in which stored data is written by a write current, and a second magnetoresistive element in which inverted data of the stored data is written by a write current.

  The potential holding unit has a first node and a second node. The first node is connected to one end of the first magnetoresistive element and holds a first potential corresponding to stored data. Connected to one end of the second magnetoresistive element and holds a second potential according to the inverted data.

  The match detection unit determines a match between the search data and the stored data, and controls the potential of the match line according to the determination result. Specifically, the coincidence detection unit is connected to the first node, the second node, and a search line to which a potential corresponding to the search data is applied. When the search data matches the stored data, the match detection unit sets the match line to the first state. When the search data matches the inverted data, the match detection unit sets the match line to the second state.

  In another aspect of the present invention, a CAM comprising a plurality of CAM cells is provided. Each of the plurality of CAM cells includes a write current wiring, a first magnetoresistive element, a second magnetoresistive element, a first transistor, a second transistor, a first node, a second node, and a first inverter. And a second inverter, a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor.

  A write current flows through the write current wiring. With the write current, stored data is written to the first magnetoresistive element, and inverted data of the stored data is written to the second magnetoresistive element. The first transistor is interposed between the write current line and the first write bit line, and the gate thereof is connected to the write word line. The second transistor is interposed between the write current line and the second write bit line, and the gate thereof is connected to the write word line.

  The input terminal of the first inverter is connected to the second node, the output terminal is connected to the first node, the source of the PMOS transistor is connected to the power supply line, and the source of the NMOS transistor is one end of the first magnetoresistive element. It is connected to the. The input terminal of the second inverter is connected to the first node, the output terminal is connected to the second node, the source of the PMOS transistor is connected to the power supply line, and the source of the NMOS transistor is one end of the second magnetoresistive element. It is connected to the.

  The gate of the third transistor is connected to the second node, and its drain is connected to the match line. The gate of the fourth transistor is connected to the first node, and its drain is connected to the match line. The gate of the fifth transistor is connected to the first search line, its source is grounded, and its drain is connected to the source of the third transistor. The gate of the sixth transistor is connected to the second search line, its source is grounded, and its drain is connected to the source of the fourth transistor.

  According to the present invention, a new nonvolatile CAM using a magnetoresistive element is provided. According to the non-volatile CAM of the present invention, it is possible to immediately return to the state before turning off the power after the power is turned on.

The above and other objects, advantages, and features will become apparent from the embodiments of the present invention described in conjunction with the following drawings.
FIG. 1 is a block diagram schematically showing the configuration of a CAM according to an embodiment of the present invention. FIG. 2 is a circuit diagram showing a configuration of the CAM cell according to the first embodiment of the present invention. FIG. 3 is a timing chart showing a data write operation to the MTJ element and a data transfer operation from the MTJ element to the potential holding unit in the CAM cell according to the present embodiment. FIG. 4 is a timing chart showing a data write operation to the potential holding unit and a data read operation from the potential holding unit in the CAM cell according to the present embodiment. FIG. 5 is a timing chart showing a data search operation in the CAM cell according to the present embodiment. FIG. 6 is a plan view showing a first example of the MTJ configuration according to the present embodiment. FIG. 7 is a cross-sectional view showing a structure taken along line AA ′ in FIG. FIG. 8 is a plan view showing a second example of the MTJ configuration according to the present embodiment. FIG. 9 is a cross-sectional view showing a structure taken along line AA ′ in FIG. FIG. 10 is a plan view showing a third example of the MTJ configuration according to the present embodiment. FIG. 11 is a cross-sectional view showing a structure taken along line AA ′ in FIG. FIG. 12 is a cross-sectional view showing a structure taken along line BB ′ in FIG. FIG. 13 is a circuit diagram showing a modification of the CAM cell according to the present embodiment. FIG. 14 is a circuit diagram showing a modification of the CAM cell according to the present embodiment. FIG. 15 is a circuit diagram showing a configuration of a CAM cell according to the second embodiment of the present invention. FIG. 16 is a block diagram schematically showing the configuration of the CAM according to the second embodiment of the present invention. FIG. 17 is a circuit diagram showing a configuration of a TCAM cell according to the third embodiment of the present invention. FIG. 18 is a circuit diagram showing a configuration of a CAM cell according to the fourth embodiment of the present invention. FIG. 19 is a circuit diagram showing a configuration of a CAM cell according to the fifth embodiment of the present invention. FIG. 20 is a circuit diagram showing a modification of the CAM cell according to the fifth embodiment. FIG. 21 is a circuit diagram showing another modification of the CAM cell according to the fifth embodiment. FIG. 22 is a block diagram schematically showing the configuration of the CAM in the case of the CAM cell shown in FIG. FIG. 23 is a timing chart showing a data write operation to the MTJ element and a data transfer operation from the MTJ element to the potential holding unit in the CAM cell according to the fifth embodiment. FIG. 24 is a timing chart showing a data transfer operation from the MTJ element to the potential holding unit in the CAM cell according to the present embodiment.

  A CAM and a CAM cell according to an embodiment of the present invention will be described with reference to the accompanying drawings. The CAM according to the present embodiment is a non-volatile CAM in which a magnetoresistive element is applied to a CAM cell.

  FIG. 1 is a block diagram schematically showing the configuration of the CAM according to the present embodiment. The CAM according to the present embodiment includes a plurality of CAM cells 10 arranged in an array, a plurality of word lines WL, a plurality of power supply lines PL, a plurality of write word lines WWL, a plurality of match lines ML, and a plurality of search lines. A pair SL, SLB, a plurality of write bit line pairs WBL, WBLB, and a coincidence detection circuit 100 are provided. The word line WL, the power supply line PL, the write word line WWL, and the match line ML are extended in the X direction. On the other hand, the search line pair SL, SLB and the write bit line pair WBL, WBLB extend in the Y direction. The coincidence detection circuit 100 is connected to a plurality of match lines ML. During the search operation, the match detection circuit 100 detects a row that matches the input data (search data) based on the information output to the match line ML.

  Hereinafter, various forms of the CAM cell 10 will be described in detail.

1. 1. First embodiment 1-1. Cell Configuration FIG. 2 is a circuit diagram showing a configuration of the CAM cell 10 according to the first embodiment of the present invention. The CAM cell 10 shown in FIG. 2 includes a first magnetoresistive element R, a second magnetoresistive element RB, a first node D, a second node DB, NMOS transistors M3 to M6, M9 to M12, PMOS transistors M1, M2, M7 and M8 and a write current wiring (node N1) are included. The CAM cell 10 is connected to a word line WL, a match line ML, a power supply line PL, a write word line WWL, a search line pair SL, SLB, and a write bit line pair WBL, WBLB.

(Nonvolatile storage unit 20)
The magnetoresistive elements R and RB are used for storing storage data (storage bits) in the CAM cell 10 in a nonvolatile manner. As the magnetoresistive elements R and RB, for example, MTJ (Magnetic Tunnel Junction) elements are used. One end of the MTJ element R is connected to the source of the NMOS transistor M4, and one end of the MTJ element RB is connected to the source of the NMOS transistor M3. The other ends of the MTJ elements R and RB are electrically connected. In the example of FIG. 2, the other ends of the MTJ elements R and RB are both connected to the write current wiring (node N1).

  The write current wiring (node N1) connects between the write bit line pair WBL and WBLB. More specifically, in the example of FIG. 2, one end of the write current wiring is connected to the write bit line WBL via the NMOS transistor M5, and the other end of the write current wiring is connected to the write bit line WBLB via the NMOS transistor M6. It is connected to the. In other words, the NMOS transistor M5 is interposed between the write current line and the write bit line WBL, and the NMOS transistor M6 is interposed between the write current line and the write bit line WBLB. The gates of the NMOS transistors M5 and M6 are both connected to the write word line WWL.

  As will be described in detail later, when data is written to the MTJ elements R and RB, a write current Iw flows through the write current wiring. That is, the write current Iw flows between the write bit lines WBL and WBLB through the write current wiring. The direction of the write current Iw (from WBL to WBLB or from WBLB to WBL) depends on the data to be written. With this write current, storage data is written to the MTJ element R, and inverted data of the storage data is written to the MTJ element RB. That is, complementary data is written to the MTJ elements R and RB of the CAM cell 10 by the write current Iw flowing through the write current wiring of each CAM cell 10.

  The write current wiring, NMOS transistors M5 and M6, write word line WWL, and write bit line pair WBL and WBLB described above constitute a “write current supply unit”. Further, the write current supply unit and the MTJ elements R and RB constitute the “nonvolatile memory unit 20”. The nonvolatile storage unit 20 stores the storage data associated with the CAM cell 10 in a nonvolatile manner.

(Potential holding part 15)
The PMOS transistor M2 and the NMOS transistor M4 constitute a first inverter. An input terminal and an output terminal of the first inverter are connected to the second node DB and the first node D, respectively. More specifically, the gate, source, and drain of the PMOS transistor M2 are connected to the second node DB, the power supply line PL, and the first node D, respectively. The gate, source, and drain of the NMOS transistor M4 are connected to the second node DB, one end of the MTJ element R, and the first node D, respectively.

  The PMOS transistor M1 and the NMOS transistor M3 constitute a second inverter. An input terminal and an output terminal of the second inverter are connected to the first node D and the second node DB, respectively. More specifically, the gate, source, and drain of the PMOS transistor M1 are connected to the first node D, the power supply line PL, and the second node DB, respectively. The gate, source, and drain of the NMOS transistor M3 are connected to the first node D, one end of the MTJ element RB, and the second node DB, respectively.

  Thus, the first inverter and the second inverter are cross-coupled. The first node D, the second node DB, the first inverter, and the second inverter constitute the “potential holding unit 15”. The first node D is connected to one end of the MTJ element R through the NMOS transistor M4. On the other hand, the second node DB is connected to one end of the MTJ element RB via the NMOS transistor M3. As will be described in detail later, the first node D holds the first potential corresponding to the stored data written in the MTJ element R. On the other hand, the second node DB holds a second potential corresponding to the inverted data written in the MTJ element RB. One of the first potential and the second potential is at a high level, and the other is at a low level.

  The first node D is connected to the search line SL through the PMOS transistor M7. That is, one of the source / drain of the PMOS transistor M7 is connected to the search line SL, and the other is connected to the first node D. The second node DB is connected to the search line SLB via the PMOS transistor M8. That is, one of the source / drain of the PMOS transistor M8 is connected to the search line SLB, and the other is connected to the second node DB. The gates of the PMOS transistors M7 and M8 are both connected to the word line WL. As will be described in detail later, by using these word lines WL and search lines SL and SLB, the nodes D and DB can be set (charged) to desired potentials.

(Coincidence detection unit 25)
The gate, source, and drain of the NMOS transistor M9 are connected to the second node DB, the drain of the NMOS transistor M11, and the match line ML, respectively. The gate, source, and drain of the NMOS transistor M10 are connected to the first node D, the drain of the NMOS transistor M12, and the match line ML, respectively. The gate, source, and drain of the NMOS transistor M11 are connected to the search line SL, the ground line, and the source of the NMOS transistor M9, respectively. The gate, source, and drain of the NMOS transistor M12 are connected to the search line SLB, the ground line, and the source of the NMOS transistor M10, respectively.

  These NMOS transistors M9 to M12 constitute a “coincidence detection unit 25”. The coincidence detection unit 25 is connected to the first node D and the second node DB, the search line pair SL, SLB, and the match line ML of the potential holding unit 15. As will be described in detail later, in the data search operation, a potential corresponding to the search data is applied to the search line SL, and a potential corresponding to the inverted data of the search data is applied to the search line SLB. The first node D holds a first potential corresponding to the stored data, and the second node DB holds a second potential corresponding to the inverted data of the stored data. Based on these potentials, the match detection unit 25 can determine whether the search data matches the stored data. Then, the coincidence detection unit 25 controls the potential of the match line ML according to the determination result. Specifically, when the search data matches the stored data, the match detection unit 25 sets the match line ML to the first state. On the other hand, when the search data does not match the stored data (when the search data matches the inverted data), the match detection unit 25 sets the match line ML to the second state.

1-2. Operation Next, the operation of the CAM cell 10 according to the present embodiment will be described in detail. The operation of the CAM cell 10 includes (1) data writing to the MTJ element, (2) data transfer from the MTJ element to the potential holding unit 15, (3) data writing to the potential holding unit 15, and (4) potential holding. Data reading from the unit 15 and (5) data retrieval are included.

(1) Data Writing to MTJ Element A data writing operation to the MTJ element in the CAM cell 10 will be described with reference to a period T1 shown in FIG. In FIG. 3, a solid line represents a potential state related to a selected cell and a broken line represents a potential state related to a non-selected cell. In the following description, “high level potential” may be simply referred to as “high level”, and “low level potential” may be simply referred to as “low level”.

  A high level is applied to the write word line WWL, and the NMOS transistors M5 and M6 are turned on. Complementary potentials are applied to the write bit lines WBL and WBLB in accordance with write data (stored data). For example, when the write data is “0”, a low level is applied to WBL and a high level is applied to WBLB. As a result, the write current Iw flows from the write bit line WBLB to the write bit line WBL through the NMOS transistor M6, the write current wiring (node N1), and the NMOS transistor M5. With this write current Iw, data “0” (corresponding to the low resistance state) is written to the MTJ element R, and inverted data “1” (corresponding to the high resistance state) is written to the MTJ element RB. On the other hand, when the write data is “1”, the write current Iw flows in the reverse direction, data “1” is written to the MTJ element R, and inverted data “0” is written to the MTJ element RB. A configuration in which complementary data is written in the MTJ elements R and RB in this way will be exemplified later.

(2) Data Transfer from MTJ Element to Potential Holding Unit 15 Data transfer from the MTJ element to the potential holding unit 15 in the CAM cell 10 will be described with reference to a period T2 shown in FIG. A low level is applied to the write word line WWL, and the NMOS transistors M5 and M6 are turned OFF. A low level is applied to the word line WL, and the PMOS transistors M7 and M8 are turned on. A high level is applied to the power supply line PL. A high level is applied to both search lines SL and SLB. Match line ML is set to a high impedance state. As a result, both the first node D and the second node DB are charged to a high level. Also, the NMOS transistors M3 and M4 are turned on.

  After charging, a high level is applied to the word line WL, and the PMOS transistors M7 and M8 are turned off. Subsequently, a high level is applied to the write word line WWL, and the NMOS transistors M5 and M6 are turned on. As a result, the charge accumulated in the first node D is discharged to the write bit lines WBL and WBLB through the NMOS transistor M4, the MTJ element R, and the NMOS transistors M5 and M6. Further, the charge accumulated in the second node DB is discharged to the write bit lines WBL and WBLB through the NMOS transistor M3, the MTJ element RB, and the NMOS transistors M5 and M6.

  Here, the PMOS transistors M1 and M2 are transistors having the same size and the same characteristics, and the NMOS transistors M3 and M4 are transistors having the same size and the same characteristics. Therefore, the difference in discharge speed between the first node D and the second node DB depends on the difference in resistance value between the MTJ elements R and RB. For example, when the stored data is “0”, the MTJ element R is in the low resistance state, and the MTJ element RB is in the high resistance state. Therefore, the first node D is discharged more quickly than the second node DB, and the potential drops earlier. When the potential of the first node D decreases and the PMOS transistor M1 starts to turn on, the second node DB is charged by the PMOS transistor M1, and the potential decrease at the second node DB is suppressed. As a result, the PMOS transistor M2 is less likely to be turned on than the PMOS transistor M1. That is, feedback acts in the direction in which the potential further decreases at the first node D and in the direction in which the potential increases at the second node DB. As a result, the potential of the first node D becomes low level, and the potential of the second node DB becomes high level. Conversely, when the stored data is “1”, the potential of the first node D is at a high level and the potential of the second node DB is at a low level.

  In this way, the stored data is transferred from the MTJ element to the potential holding unit 15. The first node D holds a potential corresponding to the storage data written in the MTJ element R. On the other hand, the second node DB holds a second potential corresponding to the inverted data written in the MTJ element RB.

(3) Data Writing to the Potential Holding Unit 15 In addition to transferring data from the MTJ element to the potential holding unit 15, data can be directly written to the potential holding unit 15 in the same manner as a normal SRAM. Direct data writing to the potential holding unit 15 will be described with reference to a period T3 shown in FIG. A high level is applied to the write word line WWL, and the NMOS transistors M5 and M6 are turned on. A low level is applied to both the write bit lines WBL and WBLB. A high level is applied to the power supply line PL. Complementary potentials corresponding to write data are applied to the search lines SL and SLB. For example, when the write data is “0”, a low level is applied to SL and a high level is applied to SLB. When the low level is applied to the word line WL, the PMOS transistors M7 and M8 are turned on. As a result, the potential of the first node D becomes low level, and the potential of the second node DB becomes high level. Thereafter, a high level is applied to the word line WL, and the PMOS transistors M7 and M8 are turned OFF.

(4) Data Reading from Potential Holding Unit 15 Data reading from the potential holding unit 15 will be described with reference to a period T4 shown in FIG. A high level is applied to the write word line WWL, and the NMOS transistors M5 and M6 are turned on. A low level is applied to both the write bit lines WBL and WBLB. A high level is applied to the power supply line PL. When the low level is applied to the word line WL, the PMOS transistors M7 and M8 are turned on. As a result, the potential of the first node D is applied to the search line SL, and the potential of the second node DB is applied to the search line SLB. A sense amplifier (not shown) connected to the search lines SL and SLB senses stored data based on these potentials.

(5) Data Search During the data search operation, each CAM cell 10 compares the stored data (stored bit) with the search data (search bit) to determine whether the data matches or does not match. Information indicating the result is output to the match line ML. The data search operation in the CAM cell 10 will be described with reference to the period T5 shown in FIG. In FIG. 5, the solid line represents “match” and the broken line represents “mismatch”.

  During the data search operation, a high level is applied to the write word line WWL, and the NMOS transistors M5 and M6 are turned on. A low level is applied to both the write bit lines WBL and WBLB. A high level is applied to the power supply line PL. A high level is applied to the word line WL, and the PMOS transistors M7 and M8 are turned off. The first node D holds a first potential corresponding to stored data, and the second node DB holds a second potential corresponding to inverted data.

  First, the match line ML is precharged to a high level, and then the match line ML is set to a high impedance state. Next, a potential corresponding to the search data is applied to the search lines SL and SLB. For example, when the search data is “0”, a low level is applied to the search line SL and a high level is applied to the search line SLB. As a result, the NMOS transistor M11 is turned off and the NMOS transistor M12 is turned on.

  Here, when the storage data of the CAM cell 10 is “0”, that is, when the search data matches the storage data, the first node D is at the low level and the second node DB is at the high level. Therefore, the NMOS transistor M10 is turned off and the NMOS transistor M9 is turned on. In this case, the match line ML is maintained at a high level. This state (first state) represents “match”.

  On the other hand, when the stored data of the CAM cell 10 is “1”, that is, when the search data does not match the stored data (when the search data matches the inverted data), the first node D is at the high level, The node DB is at a low level. Therefore, the NMOS transistor M10 is turned on and the NMOS transistor M9 is turned off. In this case, since the match line ML is connected to the ground line through the NMOS transistors M10 and M12, the potential of the match line ML becomes low level. This state (second state) represents “mismatch”.

1-3. Effect As described above, according to the present embodiment, data can be stored in the MTJ element of each CAM cell 10 in a nonvolatile manner. After the power is turned on, the stored data can be transferred from the MTJ element to the potential holding unit 15 to immediately return to the state before the power is shut off.

  Further, the MTJ element and the potential holding unit 15 are integrally formed. Therefore, data can be transferred at high speed without any limitation on the bus width.

  Furthermore, the risk of data loss is reduced if the latest data is always written to the MTJ element even in the case of an unexpected power decrease such as a power failure.

  Furthermore, the non-volatile MTJ element can be formed in the upper wiring layer of the transistor formation portion where the potential holding portion 15 is formed. Therefore, an increase in area can be suppressed.

  Furthermore, since the power can be turned off when not in use, power consumption during standby can be reduced.

  Furthermore, since the NMOS transistors M5 and M6 are provided, the leakage current during standby of the CAM cell 10 is reduced as compared with the conventional case.

  Furthermore, the CAM cell 10 according to the present embodiment is composed of 12 transistors. On the other hand, the CAM cell described in Patent Document 2 is composed of 14 transistors. Since the number of transistors is reduced, the cell area is reduced.

1-4. MTJ configuration 1-4-1. First Example FIG. 6 is a plan view showing a first example of the MTJ configuration. FIG. 7 is a cross-sectional view showing a structure taken along line AA ′ in FIG. As shown in FIG. 6, the write current wiring 30 is formed so as to connect the NMOS transistors M5 and M6. The write current wiring 30 connects the first wiring part 31 connected to the NMOS transistor M5, the second wiring part 32 connected to the NMOS transistor M6, and the first wiring part 31 and the second wiring part 32. Includes connections. Both the first wiring part 31 and the second wiring part 32 are formed in parallel to each other so as to extend in the Y direction.

  The MTJ elements R and RB are formed on the write current wiring 30. More specifically, the MTJ element RB is formed on the first wiring part 31, and the MTJ element R is formed on the second wiring part 32. As shown in FIG. 7, each MTJ element includes a magnetization fixed layer 41, an insulating layer 42, and a magnetization free layer 43. The magnetization fixed layer 41 and the magnetization free layer 43 are ferromagnetic layers, and the insulating layer 42 is sandwiched between these two ferromagnetic layers. The magnetization direction of the magnetization fixed layer 41 is substantially fixed in one direction. On the other hand, the magnetization direction of the magnetization free layer 43 can be reversed, and is allowed to be parallel or antiparallel to the magnetization direction of the magnetization fixed layer 41. When the magnetization direction is parallel, it corresponds to a low resistance state (data “0”), and when the magnetization direction is antiparallel, it corresponds to a high resistance state (data “1”).

  Further, as shown in FIG. 6, each MTJ element is patterned in an elliptical shape. Due to the shape magnetic anisotropy, the magnetization of the magnetization free layer 43 is easily oriented in the direction along the major axis direction. The magnetization of the magnetization fixed layer 41 is fixed in the direction along the major axis direction. Further, each MTJ element is arranged such that its long axis direction is inclined 45 degrees from the Y direction (the longitudinal direction of the wiring portions 31 and 32, that is, the direction of the write current Iw). Thereby, the magnetization of the magnetization free layer 43 can be efficiently reversed.

  At the time of data writing, a write current Iw flows in the direction corresponding to the write data through the write current wiring 30. A magnetic field generated by the write current Iw is applied to the MTJ elements R and RB, thereby reversing the magnetization direction of the magnetization free layer 43 of each MTJ element. In particular, in this example, the direction of the write current Iw is reversed between the first wiring portion 31 and the second wiring portion 32. Accordingly, the direction of the applied magnetic field is reversed between the MTJ element RB and the MTJ element R. Therefore, complementary data is written to the MTJ elements R and RB.

  The write current wiring 30 is formed adjacent to the MTJ elements R and RB. Accordingly, the write current Iw required for the magnetization reversal of the magnetization free layer 43 can be reduced. For example, the write current Iw can be reduced to 1 mA or less. When the write current Iw decreases, the sizes of the NMOS transistors M5 and M6 that limit the maximum value of the write current Iw that can be supplied to the cell can be reduced. Therefore, the size of the CAM cell 10 can be reduced.

1-4-2. Second Example FIG. 8 is a plan view showing a second example of the MTJ configuration. FIG. 9 is a cross-sectional view showing a structure taken along line AA ′ in FIG. A write current wiring 50 is formed so as to connect between the NMOS transistors M5 and M6. The write current wiring 50 includes magnetization free layers 53-1 and 53-2 and magnetization fixed layers 54 to 56 formed on the same plane. The magnetization fixed layer 55 is connected to the NMOS transistor M5, and the magnetization fixed layer 56 is connected to the NMOS transistor M6. The magnetization free layer 53-1 is sandwiched between the magnetization fixed layers 54 and 55, and the magnetization free layer 53-2 is sandwiched between the magnetization fixed layers 54 and 56.

  The magnetization free layer 53-1 is a part of the MTJ element RB. The MTJ element RB includes the magnetization free layer 53-1, the magnetization fixed layer 51-1, and the magnetization fixed layer 51-1 and the magnetization free layer 53-1. An insulating layer 52-1 is sandwiched. The magnetization free layer 53-2 is a part of the MTJ element R. The MTJ element R includes a magnetization free layer 53-2, a magnetization fixed layer 51-2, a magnetization fixed layer 51-2, and a magnetization free layer 53-2. An insulating layer 52-2 sandwiched is provided.

  The magnetization free layer 53 and the magnetization fixed layers 51 and 54 to 56 are formed of, for example, a perpendicular magnetization film having perpendicular magnetic anisotropy. For example, the magnetization directions of the magnetization fixed layers 51-1 and 51-2 are fixed in the −Z direction. In addition, the magnetization direction of the magnetization fixed layer 54 is fixed in the −Z direction, and the magnetization directions of the magnetization fixed layers 55 and 56 are fixed in the opposite + Z direction. The magnetization directions of the magnetization free layers 53-1 and 53-2 can be reversed and are opposite to each other.

  In this example, data writing is performed by a spin injection domain wall motion method. For example, when the write data is “0”, the write current Iw is supplied in the −X direction. In this case, spin electrons flow in the + X direction, and as a result of the spin injection, the magnetization direction of the magnetization free layer 53-1 becomes the + Z direction, and the magnetization direction of the magnetization free layer 53-2 becomes the -Z direction. That is, the MTJ element R is in a low resistance state (data “0”), and the MTJ element RB is in a high resistance state (data “1”). When the write data is “1”, the write current Iw flows in the + X direction.

  In the case of a write method using spin torque, the write current Iw can be reduced. For example, the write current Iw is reduced to several hundred μA. When the write current Iw decreases, the sizes of the NMOS transistors M5 and M6 that limit the maximum value of the write current Iw that can be supplied to the cell can be reduced. Therefore, the size of the CAM cell 10 can be reduced.

1-4-3. Third Example FIG. 10 is a plan view showing a third example of the MTJ configuration. 11 and 12 are cross-sectional views showing structures along line AA ′ and line BB ′ in FIG. 10, respectively. The MTJ element RB includes a magnetization fixed layer 61-1, a magnetization free layer 63-1, and an insulating layer 62-1 sandwiched between the magnetization fixed layer 61-1 and the magnetization free layer 63-1. The MTJ element R includes a magnetization fixed layer 61-2, a magnetization free layer 63-2, and an insulating layer 62-2 sandwiched between the magnetization fixed layer 61-2 and the magnetization free layer 63-2. The MTJ elements R and RB are formed apart on the wiring 70.

  A write current wiring 60 is formed to connect between the NMOS transistors M5 and M6. The write current wiring 60 includes a magnetization free layer 64 and magnetization fixed layers 65 and 66 formed on the same plane. The magnetization fixed layer 65 is connected to the NMOS transistor M5, and the magnetization fixed layer 66 is connected to the NMOS transistor M6. The magnetization free layer 64 is sandwiched between the magnetization fixed layers 65 and 66.

  For example, the magnetization free layer 64 and the magnetization fixed layers 65 and 66 are formed of a perpendicular magnetization film having perpendicular magnetic anisotropy. The magnetization directions of the magnetization fixed layers 65 and 66 are fixed in opposite directions. For example, the magnetization direction of the magnetization fixed layer 65 is fixed in the + Z direction, and the magnetization direction of the magnetization fixed layer 66 is fixed in the −Z direction. Further, the magnetization direction of the magnetization free layer 64 can be reversed. On the other hand, the magnetization fixed layer 61 and the magnetization free layer 63 of the MTJ element are formed of an in-plane magnetization film having in-plane magnetic anisotropy. For example, the magnetization directions of the magnetization fixed layers 61-1 and 61-2 are both fixed in the -Y direction. The magnetization directions of the magnetization free layers 63-1 and 63-2 can be reversed and are opposite to each other. Further, the magnetization free layers 63-1 and 63-2 are magnetically coupled to the magnetization free layer 64. Therefore, when the magnetization direction of the magnetization free layer 64 is reversed, the magnetization directions of the magnetization free layers 63-1 and 63-2 are also reversed.

  The magnetization reversal of the magnetization free layer 64 is realized by a spin injection domain wall motion method. For example, when the write data is “0”, the write current Iw flows in the −X direction in the write current wiring 60. In this case, the spin electrons flow in the + X direction, and as a result of the spin injection, the magnetization direction of the magnetization free layer 64 becomes the + Z direction. Furthermore, the magnetization directions of the magnetization free layers 63-1 and 63-2 that are magnetically coupled to the magnetization free layer 64 are the + Y direction and the -Y direction, respectively. As a result, the MTJ element R enters a low resistance state (data “0”), and the MTJ element RB enters a high resistance state (data “1”). When the write data is “1”, the write current Iw flows in the + X direction.

  According to this example, the same effect as the second example can be obtained. Furthermore, in this example, the MTJ element is formed of an in-plane magnetization film. In the case of the MTJ element using the in-plane magnetization film, the resistance ratio (MR ratio) between the low resistance state and the high resistance state is larger than that of the MTJ element using the perpendicular magnetization film. Therefore, the reliability of data transfer from the MTJ element to the potential holding unit 15 is improved.

  In the case of the configuration shown in FIGS. 10 to 12, the end portions of the MTJ elements R and RB are not electrically connected to the node N1 (write current wiring 60) as shown in FIG. It may be connected to a ground line. Even in this case, the end portions of the MTJ elements R and RB are electrically connected to each other.

1-5. Modified Example As shown in FIG. 14, the CAM cell 10 may include a PMOS transistor M13. The gate of the PMOS transistor M13 is connected to the word line WL, one of the source / drain thereof is connected to the first node D, and the other of the source / drain is connected to the second node DB. The PMOS transistor M13 serves as a switch for electrically connecting or disconnecting the first node D and the second node DB. The functions of the CAM cell 10 are limited to (1) data writing to the MTJ element, (2) data transfer from the MTJ element to the potential holding unit 15, and (5) data search, but the PMOS transistor shown in FIG. M7 and M8 may be omitted. Thereby, the number of transistors included in one CAM cell 10 is further reduced.

2. Second Embodiment In the second embodiment of the present invention, one of the NMOS transistors M5 and M6 of the nonvolatile memory unit 20 is shared by a plurality of CAM cells 10. FIGS. 15 and 16 show examples of the CAM cell 10 and the CAM according to the second embodiment, respectively. 15 and 16, the NMOS transistor M6 is shared between a plurality of adjacent CAM cells 10-0 to 10-n. The gate of the common NMOS transistor M6 is connected to the common write word line CWWL, and can be selected by using the common write word line CWWL instead of the write word line WWL. Other configurations and operations of the CAM cell 10 are the same as those in the first embodiment, and a description thereof will be omitted.

  According to the present embodiment, the same effect as in the first embodiment can be obtained. In addition, the total number of transistors is further reduced as compared with the first embodiment. As a result, the cell area is further reduced.

3. Third Embodiment In the third embodiment, a TCAM cell 10 capable of storing three logic states “0”, “1”, and “X” is proposed. A bit in the “X” state means “Don't care”, and is regarded as a match regardless of whether “0” or “1” is input as search data.

  FIG. 17 is a circuit diagram showing a configuration example of the TCAM cell 10 according to the third embodiment. The TCAM cell 10 includes two potential holding units 15x and 15y, two nonvolatile storage units 20x and 20y, and a coincidence detection unit 25. The configuration of each of the potential holding units 15x and 15y is the same as that of the potential holding unit 15 in the first embodiment. The configuration of each of the nonvolatile storage units 20x and 20y is the same as that of the nonvolatile storage unit 20 in the first embodiment. The overlapping description is omitted as appropriate.

  The potential holding unit 15x includes PMOS transistors M1 and M2, NMOS transistors M3 and M4, a first node Dx, and a second node DBx. The PMOS transistors M1 and M2 are connected to the power supply line PLx. The first node Dx is connected to the search line SL via the PMOS transistor M7, and the second node DBx is connected to the search line SLB via the PMOS transistor M8. The gates of the PMOS transistors M7 and M8 are connected to the word line WLx.

  The nonvolatile memory unit 20x includes MTJ elements Rx and RBx, a write current wiring N1, and NMOS transistors M5 and M6. The gates of the NMOS transistors M5 and M6 are connected to the write word line WWLx. Complementary data is written in the MTJ elements Rx and RBx. The first node Dx holds a potential corresponding to the stored data written to the MTJ element Rx, and the second node DBx holds a potential corresponding to the inverted data written to the MTJ element RBx.

  The potential holding unit 15y includes PMOS transistors M21 and M22, NMOS transistors M23 and M24, a first node Dy, and a second node DBy. The PMOS transistors M21 and M22 are connected to the power supply line PLy. The first node Dy is connected to the search line SL via the PMOS transistor M27, and the second node DBy is connected to the search line SLB via the PMOS transistor M28. The gates of the PMOS transistors M27 and M28 are connected to the word line WLy.

  The nonvolatile memory unit 20y includes MTJ elements Ry and RBy, a write current wiring N21, and NMOS transistors M25 and M26. The gates of the NMOS transistors M25 and M26 are connected to the write word line WWLi. Complementary data is written in the MTJ elements Ry and RBy. The first node Dy holds a potential corresponding to the stored data written in the MTJ element Ry, and the second node DBy holds a potential corresponding to the inverted data written in the MTJ element RBy.

  In the coincidence detection unit 25 according to the present embodiment, the gate of the NMOS transistor M9 is connected to the second node DBx of the potential holding unit 15x. The gate of the NMOS transistor M10 is connected to the first node Dy of the potential holding unit 15y. Other connection relationships are the same as those in the first embodiment.

  When the stored data is “0”, the first node Dy is at a low level and the second node DBx is at a high level. When the stored data is “1”, the first node Dy is at a high level and the second node DBx is at a low level. When the stored data is “X”, the first node Dy and the second node DBx are both at the same low level. The data search operation is as follows.

  During the data search operation, a high level is applied to the write word lines WWLx and WWLi, and the NMOS transistors M5, M6, M25, and M26 are turned on. A low level is applied to both the write bit lines WBL and WBLB. A high level is applied to the power supply lines PLx and PLy. A high level is applied to the word lines WLx, WLy, and the PMOS transistors M7, M8, M27, M28 are turned off.

  First, the match line ML is precharged to a high level, and then the match line ML is set to a high impedance state. Next, a potential corresponding to the search data is applied to the search lines SL and SLB. For example, when the search data is “0”, a low level is applied to the search line SL and a high level is applied to the search line SLB. As a result, the NMOS transistor M11 is turned off and the NMOS transistor M12 is turned on.

  When the stored data of the CAM cell 10 is “0”, that is, when the search data matches the stored data, the first node Dy is at a low level and the second node DBx is at a high level. Therefore, the NMOS transistor M10 is turned off and the NMOS transistor M9 is turned on. In this case, the match line ML is maintained at a high level. This state (first state) represents “match”.

  When the stored data of the CAM cell 10 is “1”, that is, when the search data does not match the stored data (when the search data matches the inverted data), the first node Dy is at the high level and the second node DBx Is low level. Therefore, the NMOS transistor M10 is turned on and the NMOS transistor M9 is turned off. In this case, since the match line ML is connected to the ground line through the NMOS transistors M10 and M12, the potential of the match line ML becomes low level. This state (second state) represents “mismatch”.

  When the stored data of the CAM cell 10 is “X”, both the first node Dy and the second node DBx are at the same low level. Therefore, both the NMOS transistors M9 and M10 remain OFF, and the match line ML is maintained at the high level. This state (first state) is the same as the state where the search data matches the stored data. That is, the bit in the “X” state means “Don't care”, and it is regarded as a match regardless of whether “0” or “1” is input as search data.

  According to the present embodiment, the same effect as in the first embodiment can be obtained. Further, a TCAM cell that can store an “X” state suitable for the search operation is realized. As long as there is no contradiction, it is possible to combine the present embodiment and the above-described embodiment.

4). Fourth Embodiment FIG. 18 is a circuit diagram showing a configuration example of a CAM cell 10 according to a fourth embodiment. In the present embodiment, the CAM cell 10 includes a plurality of nonvolatile storage units 20, and each nonvolatile storage unit 20 can store 1-bit data.

  In the example of FIG. 18, the CAM cell 10 includes two nonvolatile storage units 20-1 and 20-2, and can store 2-bit data as a whole. The nonvolatile memory unit 20-1 includes MTJ elements R and RB, NMOS transistors M5 and M6, a write current wiring (node N1), and a write word line WWL-1. The nonvolatile memory unit 20-2 includes MTJ elements R2 and RB2, NMOS transistors M25 and M26, a write current wiring (node N2), and a write word line WWL-2. The connection relationship between each nonvolatile memory unit 20 and the potential holding unit 15 is the same as that in the first embodiment.

  According to the present embodiment, it is possible to select one non-volatile storage unit 20 to be used by activating only one of the write word lines WWL-1 and WWL-2. That is, one of the plurality of nonvolatile storage units 20 is activated, and data is transferred from the activated nonvolatile storage unit 20 to the potential holding unit 15. Each operation is the same as that of the first embodiment.

  According to the present embodiment, the same effect as in the first embodiment can be obtained. Furthermore, it is possible to store a plurality of different types of stored data in the plurality of nonvolatile storage units 20. Any of the plurality of types of stored data can be transferred to the potential holding unit 15. That is, the stored data as the CAM cell 10 can be switched at high speed. And since structures other than the non-volatile memory | storage part 20 are shared between several types of memory | storage data, the area as the whole CAM is reduced. As long as there is no contradiction, it is possible to combine the present embodiment and the above-described embodiment.

5. Fifth Embodiment In the fifth embodiment, another modification will be described.

  As shown in FIG. 14 described above, the CAM cell 10 may include a PMOS transistor M13. The gate of the PMOS transistor M13 is connected to the word line WL, one of the source / drain thereof is connected to the first node D, and the other of the source / drain is connected to the second node DB. The PMOS transistor M13 serves as a switch for electrically connecting or disconnecting the first node D and the second node DB.

  As shown in FIG. 19, the CAM cell 10 may include two precharging PMOS transistors M14 and M15. The drain of the PMOS transistor M14 is connected to the second node DB, its source is connected to the power supply line, and its gate is connected to the word line WL. The drain of the PMOS transistor M15 is connected to the first node D, its source is connected to the power supply line, and its gate is connected to the word line WL. The PMOS transistors M14 and M15 are switches controlled by the word line WL, and are used to precharge the first node D and the second node DB to a high level during data transfer from the MTJ element to the potential holding unit 15. It is done. As a result, it is possible to obtain a high tolerance against the data transfer operation margin from the MTJ element to the potential holding unit 15, that is, the element variation of the transistor and the MTJ element.

  As shown in FIG. 20, the CAM cell 10 may include a pull-down NMOS transistor M16. The drain of the NMOS transistor M16 is connected to the node N1, its source is connected to the ground line, and its gate is connected to the pull-down line PD. The NMOS transistor M16 is a switch controlled by a pull-down line PD. During standby and data search operation, a high level is applied to the pull-down line PD, and the NMOS transistor M16 is turned on. During a data write operation to the MTJ element and during data transfer from the MTJ element to the potential holding unit 15, a low level is applied to the pull-down line PD in the selected row, and the NMOS transistor M16 of the selected cell is turned off. Thereby, when the operation mode is changed, the number of control lines whose voltage changes is reduced, and power consumption can be suppressed.

  For example, in the first embodiment, when the operation mode changes from “standby” to “data writing to the MTJ element”, all the write word lines WWL in the non-selected rows change from the high level to the low level. . Therefore, the number of control lines on which the voltage changes is large. The write word line WWL of the selected row remains at the high level. On the other hand, in the case of FIG. 20, there are two control lines whose voltage changes with respect to the same change in the operation mode: the write word line WWL of the selected row and the pull-down line PD of the selected row. As described above, since the number of control lines whose voltage changes can be reduced, power consumption during operation can be suppressed.

  The pull-down NMOS transistor M16 may be shared by a plurality of CAM cells 10. For example, as shown in FIG. 21 and FIG. 22, the NMOS transistors M6 and M16 are connected to the sub bit line SWBLB and are shared between a plurality of adjacent CAM cells 10-0 to 10-n. The gate of the NMOS transistor M6 is connected to the common write word line CWWL. Thereby, the number of transistors can be reduced, and the area of the memory cell can be reduced.

  Next, the operation will be described in detail by taking the CAM cell 10 shown in FIG. 21 as an example. The same applies to the case shown in FIGS. 19 and 20. The operation of the CAM cell 10 includes (1) data writing to the MTJ element, data transfer from the MTJ element to the potential holding unit 15, (2) data transfer from the MTJ element to the potential holding unit 15, and (3 ) Data search can be mentioned.

  (1) The data write operation to the MTJ element in the CAM cell 10 and the data transfer from the MTJ element to the potential holding unit 15 will be described with reference to the period T1 shown in FIG.

  A low level is applied to the pull-down line PD of the cell group including the selected cell, and the NMOS transistor M16 is turned OFF. A high level is applied to the write word line WWL and the common write word line CWWL of the selected cell, and the NMOS transistors M5 and M6 are turned on. Complementary voltages are applied to the write bit lines WBL and WBLB according to the write data. As a result, the write current Iw flows between the write bit lines WBL and WBLB via the NMOS transistors M5 and M6 corresponding to the selected cell. Thereby, data writing to the MTJ element is performed. At this time, the potential of the sub bit line SWBLB does not rise to such a high level that the data in the potential holding unit 15 is destroyed. For this reason, data of unselected cells in the same cell group as the selected cell is not destroyed.

  Subsequent to the data writing, data transfer from the MTJ element to the potential holding unit 15 is performed. A low level is applied to the write word line WWL and the common write word line CWWL, and the NMOS transistors M5 and M6 are turned off. Further, a high level is applied to the pull-down line PD, and the NMOS transistor M16 is turned on. As a result, the potential of the sub bit line SWBLB becomes low enough not to destroy the data in the potential holding unit 15.

  Further, a low level is applied to the word line WL connected to the selected cell, and the PMOS transistors M13 to M15 are turned on. As a result, both the first node D and the second node DB are charged to a high level. A tunnel current corresponding to the stored data flows through the MTJ elements R and RB, and a small potential difference corresponding to the stored data is generated between the first node D and the second node DB. At this time, the potential of the sub bit line SWBLB is sufficiently low so as not to destroy the data in the potential holding unit 15 of the non-selected cell.

  Thereafter, a high level is applied to the word line WL, and the PMOS transistors M13 to M15 are turned off. The charge accumulated in the first node D is discharged through the NMOS transistor M4, the MTJ element R, and the NMOS transistor M16. The charge accumulated in the second node DB is discharged through the NMOS transistor M3, the MTJ element RB, and the NMOS transistor M16. As a result, data transfer from the MTJ element to the potential holding unit 15 is realized as in the above-described embodiment.

  In this manner, data writing can be performed without destroying data of non-selected cells in the cell group including the selected cell.

  (2) FIG. 24 is a timing chart showing data transfer from the MTJ element to the potential holding unit 15 in the CAM cell 10. This is the same as the data transfer operation subsequent to the data writing to the MTJ element described above, and the description thereof is omitted.

  When power is turned on, it is preferable to transfer data simultaneously in all cells included in a plurality of cell groups. This can be realized by controlling a plurality of word lines WL. As a result, when power is turned on, data transfer can be performed simultaneously in a plurality of cell groups, and data can be restored immediately. However, the power consumption in this case is larger than when data transfer is performed only on the selected row. For this reason, it is preferable that the number of bits for performing data transfer can be changed at the time of data transfer following data writing to the MTJ element and at the time of power-on.

  (3) During the data search operation, the node N1 (sub-bit line SWBLB) is set to the low level using the pull-down NMOS transistor M16 instead of using the write word line WWL and the write bit line WBL. Other than that, it is the same as the above-described embodiment, and the description thereof is omitted.

  As long as there is no contradiction, it is possible to combine the fifth embodiment and the above-described embodiment.

  The embodiments of the present invention have been described above with reference to the accompanying drawings. However, the present invention is not limited to the above-described embodiments, and can be appropriately changed by those skilled in the art without departing from the scope of the invention.

This application claims priority based on Japanese Patent Application 2009-130268 filed on May 29, 2009 and Japanese Patent Application 2009-143694 filed on June 16, 2009. , The entire disclosure of which is incorporated herein.

Claims (4)

A CAM comprising a plurality of CAM cells arranged in a matrix ,
Each of the plurality of CAM cells includes:
A write current wiring through which a write current flows; and
A first magnetoresistive element to which stored data is written by the write current;
A second magnetoresistive element to which inverted data of the stored data is written by the write current;
A first transistor interposed between the write current line and the first write bit line and having a gate connected to the write word line;
A second transistor interposed between the write current line and the second write bit line and having a gate connected to the write word line;
A first node;
A second node;
An input terminal is connected to the second node, an output terminal is connected to the first node, a source of the PMOS transistor is connected to a power supply line, and a source of the NMOS transistor is connected to one end of the first magnetoresistive element. A first inverter;
An input terminal is connected to the first node, an output terminal is connected to the second node, a source of the PMOS transistor is connected to the power supply line, and a source of the NMOS transistor is connected to one end of the second magnetoresistive element. A second inverter,
A third transistor having a gate connected to the second node and a drain connected to the match line;
A fourth transistor having a gate connected to the first node and a drain connected to the match line;
A fifth transistor having a gate connected to the first search line, a source grounded, and a drain connected to the source of the third transistor;
A sixth transistor having a gate connected to the second search line, a source grounded, and a drain connected to the source of the fourth transistor ;
A precharge signal line;
A precharge switch that is turned on or off according to a voltage level supplied to the precharge signal line, and is turned on when the voltage level is a first voltage level, and the first node and the second node are turned on. for example Bei and the pre-charge switch to pre-charge,
The first write bit line and the second write bit line extend in a column direction;
The precharge signal line is a CAM extending in a row direction perpendicular to the column direction . The CAM according to claim 1, wherein
A power supply voltage supply unit for supplying a power supply voltage to the first node and the second node;
The precharge switch is
A first precharge transistor having a source connected to the power supply voltage supply unit, a drain connected to the first node, and a gate connected to the precharge signal line;
A second precharge transistor having a source connected to the power supply voltage supply unit, a drain connected to the second node, and a gate connected to the precharge signal line;
including
CAM. The CAM according to claim 1 or 2 ,
A CAM in which the other end of the first magnetoresistive element and the other end of the second magnetoresistive element are electrically connected to each other. The CAM according to any one of claims 1 to 3 ,
Each CAM cell further includes a switch for electrically connecting or disconnecting the first node and the second node.

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