JP5478993B2 - 高耐圧半導体装置及びその製造方法 - Google Patents
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
- H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
- H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
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- Insulated Gate Type Field-Effect Transistor (AREA)
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Description
高耐圧半導体装置10は、第1導電型であるp型の半導体基板100上に形成された第2導電型であるn型のソース領域200と、半導体基板100の表面領域に高濃度の第2導電型であるn型で形成された高濃度拡散層310を有し、半導体基板100の表面から高深度領域まで形成された第2導電型であるn型の電界緩和層300と、電界緩和層300の領域内においてソース領域200から遠い領域の上層領域に形成されたドレイン領域400と、ドレイン領域400とソース領域200の間で半導体基板100の表面の活性領域に形成されたゲート酸化膜500と、ドレイン領域400とゲート酸化膜500の間の半導体層表面に形成されたLOCOS酸化膜600と、ゲート酸化膜500上からLOCOS酸化膜600上に張り出して形成されたゲート電極510と、を有して構成されている。
図2は、本発明の実施の形態に係る高耐圧半導体装置10の工程図である。以下では、n型MOSFETの構成の場合について製造工程(プロセス)の説明を行なう。半導体基板100上に、ウエル形成(電界緩和層、拡散形成)工程(Step1)、高濃度拡散層形成工程(Step2)、LOCOS酸化膜形成工程(Step3)、ゲート酸化膜、電極形成工程(Step4)、ソース、ドレイン形成工程(Step5)、電極形成工程(Step6)を順次行なう。ただし、上記の工程順序は変更可能な範囲で順序を入れ替えて行なってもよい。以下、図3A〜図3Cに従い、各製造工程を説明する。
本発明の実施の形態によれば、電界緩和層300の拡散深さを大きくすることにより、高耐圧と低オン抵抗の両方の特性を両立する高耐圧半導体装置が可能となる。従来技術では、電界緩和層300の拡散深さを3μm程度としているが、本発明の実施の形態では5μm以上とする。これにより種々の効果が得られる。
100…半導体基板
200…ソース領域
300…電界緩和層
310…高濃度拡散層
400…ドレイン領域
500…ゲート酸化膜
510…ゲート電極
550…チャネル
600…LOCOS酸化膜
601、602…バーズビーク
650…コンタクトプラグ
660…配線層
670…層間絶縁膜
680…パシベーション層
700、702、706、712…レジスト
Claims (4)
- 第1導電型の半導体基板上に、
前記半導体基板の表面から高深度領域まで、第2導電型の電界緩和層を形成するウエル形成工程と、
前記電界緩和層の領域内の表面領域に、高濃度の第2導電型の高濃度拡散層を形成する高濃度拡散層形成工程と、
LOCOS酸化膜形成工程と、
ドレイン領域とソース領域の間で前記半導体基板の表面の活性領域にゲート酸化膜を形成し、前記ゲート酸化膜上から前記LOCOS酸化膜上に張り出してゲート電極を形成するゲート酸化膜及び電極形成工程と、
前記ゲート酸化膜を挟んで対向して、ソース領域、及び、電界緩和層の領域内にドレイン領域を形成するソース、ドレイン形成工程と、
前記ゲート酸化膜の下部に第1導電型でチャネルを形成するチャネル形成工程と、を有し、
前記高濃度拡散層は前記LOCOS酸化膜の直下に形成され、前記高濃度拡散層の端部から前記チャネルの端部までの離間した距離を製造パラメータとして設定することによりオン抵抗値を所定の抵抗値に制御することを特徴とする高耐圧半導体装置の製造方法。 - 前記オン抵抗値は、前記高濃度拡散層の端部から前記チャネルの端部までの距離に対してリニアな関係であることを特徴とする請求項1に記載の高耐圧半導体装置の製造方法。
- 前記高濃度拡散層の端部から前記チャネルの端部までの距離は、1μmであることを特徴とする請求項1又は2に記載の高耐圧半導体装置の製造方法。
- 前記電界緩和層の高深度領域は、5μm以上8μm以下であることを特徴とする請求項1から3のいずれか1項に記載の高耐圧半導体装置の製造方法。
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US9299831B2 (en) | 2012-10-16 | 2016-03-29 | Asahi Kasei Microdevices Corporation | Field effect transistor and semiconductor device |
CN103413831A (zh) * | 2013-08-30 | 2013-11-27 | 电子科技大学 | 一种横向高压器件及其制造方法 |
CN104332501B (zh) * | 2014-09-30 | 2017-10-24 | 上海华虹宏力半导体制造有限公司 | Nldmos器件及其制造方法 |
CN105140289A (zh) * | 2015-09-22 | 2015-12-09 | 上海华虹宏力半导体制造有限公司 | N型ldmos器件及工艺方法 |
JP6887244B2 (ja) * | 2016-12-09 | 2021-06-16 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
CN107863379A (zh) * | 2017-10-30 | 2018-03-30 | 济南大学 | 一种带有场板辅助掺杂区的n型ldmos结构 |
CN108550628B (zh) * | 2018-04-28 | 2021-10-22 | 桂林电子科技大学 | 一种具有表面电荷区结构的功率器件 |
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