JP5477140B2 - Liquid crystal display - Google Patents

Description

  The present invention relates to a liquid crystal display device having a wide viewing angle.

  Liquid crystal display devices are desired to have a wide viewing angle. For this purpose, the pixel is divided into two regions, and the viewing angle characteristics of the two regions are made different from each other by making the voltage value applied to the liquid crystal different in one region and the other region. It is considered to obtain a wide viewing angle in which the viewing angle characteristics are synergistic.

  As this type of liquid crystal display device, for example, there is one in which a first pixel electrode connected to a first thin film transistor and a second pixel electrode connected to a second thin film transistor are formed for each pixel.

  In this liquid crystal display device, the first thin film transistor and the second thin film transistor are connected to the same data signal line and scanning signal line. The scanning signal line is wired so as to extend between the first pixel electrode and the second pixel electrode.

  In this liquid crystal display device, different values of voltage are applied to the liquid crystal in the one region and the liquid crystal in the other region by making the charging capability of the first thin film transistor different from the charging capability of the second thin film transistor. Like to do.

Japanese Patent Laid-Open No. 7-152013

  By the way, since the liquid crystal display device is manufactured through various processes, even if it is the same type of liquid crystal display device, the visual field between the display devices is different due to an error such as an insulating film thickness or a substrate gap generated in the manufacturing process. It may cause corner variations. In the conventional liquid crystal display device, since it is difficult to correct the variation in viewing angle, a liquid crystal display device having a predetermined viewing angle cannot be obtained with a high yield.

  An object of the present invention is to provide a liquid crystal display device capable of easily correcting variations in viewing angles.

In order to achieve the above object, according to one embodiment of the liquid crystal display device of the present invention, a first pixel electrode connected to a first thin film transistor and a second pixel electrode connected to a second thin film transistor are formed for each pixel. The first thin film transistor and the second thin film transistor are connected to the same data signal line and scanning signal line, and between the first pixel electrode and the common electrode and between the second pixel electrode and the common electrode. A liquid crystal display device having a liquid crystal layer formed thereon, the first capacitor electrode forming a first compensation capacitor with a first dielectric layer interposed between the first pixel electrode, the second pixel electrode, A second capacitor electrode that forms a second compensation capacitor with a second dielectric layer interposed therebetween, a connection portion that electrically connects the second thin film transistor and the second pixel electrode, and the connection portion A third dielectric layer is interposed between Applying a first voltage identical to the voltage applied to the common electrode to the third capacitor electrode forming the third compensation capacitor, the first capacitor electrode and the second capacitor electrode, e Bei and means for applying a different second voltage from said first voltage, said first, second and third respective capacitor electrodes are formed on the same surface, and characterized in that To do.

In order to achieve the above object, according to one embodiment of the liquid crystal display device of the present invention, a first pixel electrode connected to a first thin film transistor and a second pixel electrode connected to a second thin film transistor are formed for each pixel. The first thin film transistor and the second thin film transistor are connected to the same data signal line and scanning signal line, and between the first pixel electrode and the common electrode and between the second pixel electrode and the common electrode. A liquid crystal display device having a liquid crystal layer formed thereon, the first capacitor electrode forming a first compensation capacitor with a first dielectric layer interposed between the first pixel electrode, the second pixel electrode, A second capacitor electrode that forms a second compensation capacitor with a second dielectric layer interposed therebetween, a connection portion that electrically connects the second thin film transistor and the second pixel electrode, and the connection portion A third dielectric layer is interposed between Applying a first voltage identical to the voltage applied to the common electrode to the third capacitor electrode forming the third compensation capacitor, the first capacitor electrode and the second capacitor electrode, Means for applying a second voltage different from the first voltage, and the first capacitor electrode has an entire circumference of the first pixel electrode so as to overlap all sides of the first pixel electrode. The second capacitor electrode is formed in a continuous shape over the entire circumference of the second pixel electrode so as to overlap all sides of the second pixel electrode. , characterized in that.

  According to the present invention, the viewing angle can be finely adjusted only by controlling the value of the second voltage applied to the third capacitor electrode, and accordingly, the variation in viewing angle can be easily corrected.

1 is a configuration diagram of a liquid crystal display device showing a first embodiment of the present invention. FIG. The top view of the liquid crystal display element in a 1st Example. The side view of the said liquid crystal display element. The top view of a part of 1st board | substrate of the said liquid crystal display element. The enlarged view of one pixel part of FIG. The expanded sectional view which follows the VI-VI arrow line of FIG. The expanded sectional view which follows the VII-VII arrow line of FIG. The expanded sectional view which follows the VIII-VIII arrow line of FIG. The expanded sectional view which follows the IX-IX arrow line of FIG. Sectional drawing which shows the initial alignment state of the liquid crystal molecule of the said liquid crystal display element. FIG. 3 is a circuit diagram of one pixel of the liquid crystal display element. FIG. 6 is a waveform diagram of a scanning signal, a data signal, and first and second voltages for driving the liquid crystal display element. The figure which shows the relationship between said 1st voltage and 2nd voltage. The figure which shows the voltage applied between the 1st pixel electrode and common electrode in the 1st area | region of the said pixel. The figure which shows the voltage applied between the 2nd pixel electrode and common electrode in the 2nd area | region of the said pixel. The voltage-transmittance characteristic view in the liquid crystal layer of the first region and the second region. The top view which shows typically the orientation state of the liquid crystal molecule at the time of the voltage application in the liquid crystal display device of a 1st Example. The top view of one pixel part of the 1st board | substrate which shows the liquid crystal display device of a comparative example. FIG. 13 is a waveform diagram illustrating an example in which the scanning signal, the data signal, and the second voltage of the first and second voltages in FIG. 12 are rectangular wave AC voltages. FIG. 13 is a waveform diagram showing an example in which the scanning signal, the data signal, and the second voltage of the first and second voltages in FIG. 12 are changed to other rectangular wave AC voltages. The top view of one pixel part of the 1st board | substrate of the liquid crystal display element which shows 2nd Example of this invention. The expanded sectional view which follows the XXII-XXII arrow line of FIG. The expanded sectional view which follows the XXIII-XXIII arrow line of FIG. Sectional drawing of the part corresponding to FIG. 23 of the liquid crystal display element which shows 3rd Example of this invention. The top view of a part of 1st board | substrate of the liquid crystal display element which shows 4th Example of this invention. The top view of a part of 1st board | substrate of the liquid crystal display element which shows 5th Example of this invention.

[First embodiment]
As shown in FIG. 1, the liquid crystal display device according to the first embodiment of the present invention includes a liquid crystal display element 1 and a driving means 35 for driving the liquid crystal display element 1.

  The liquid crystal display element 1 is an active matrix type liquid crystal display element using a thin film transistor (hereinafter referred to as TFT) as a switching element, and a plurality of pixels 32 are arranged in a row direction (left and right direction in the figure) as shown in FIG. They are arranged in a row direction (vertical direction in the figure).

  As shown in FIGS. 2 to 10, the liquid crystal display element 1 includes a transparent first substrate 3 and a second substrate 4 that are arranged to face each other. A plurality of transparent pixel electrodes 5 are arranged in a row direction and a column direction on the surface of the first substrate (for example, the substrate opposite to the display surface side) 3 facing the second substrate 4, On the surface of the second substrate 4 facing the first substrate 3, a single-film transparent common electrode 6 facing each pixel electrode 5 is provided.

  Each of the pixel electrodes 5 includes a first pixel electrode 5a and a second pixel electrode 5b that are electrically separated from each other. In this embodiment, the first pixel electrode 5a and the second pixel electrode 5b have the same horizontal width (width in the row direction), and the first pixel electrode 5a has a vertical width (width in the column direction) that is the horizontal width. The second pixel electrode 5b is formed in a square shape having approximately the same vertical and horizontal width.

  Further, the first substrate 3 has a plurality of scanning signal lines 7 extended in the row direction for each row of the pixel electrodes 5 and extended in the column direction for each column of the pixel electrodes 5. A plurality of data signal lines 8 are provided.

  The scanning signal line 7 is disposed so as to extend between the first pixel electrode 5a and the second pixel electrode 5b. The data signal line 8 is arranged in a region on one side of the pixel electrode 5 in each column so as to extend in the column direction.

  The first substrate 3 includes a first TFT 9a connected to the first pixel electrode 5a and a second TFT 9b connected to the second pixel electrode 5b so as to correspond to each pixel electrode 5. Has been placed. The first TFT 9a and the second TFT 9b are arranged side by side in the extending direction of the data signal line 8 in the region between the first pixel electrode 5a and the second pixel electrode 5b.

  The first TFT 9a and the second TFT 9b are respectively formed on the gate electrode 10 formed on the first substrate 3 and on the entire area of the first substrate 3 as shown in FIGS. A transparent gate insulating film 11 formed so as to cover the gate electrode 10, a semiconductor thin film 12 made of genuine amorphous silicon formed on the gate insulating film 11 so as to face the gate electrode 10, and an upper surface of the semiconductor thin film 12 Formed on the one side and the other side of the channel protective film 13 provided in the center of the semiconductor thin film 12 via the contact layer 14 made of n-type amorphous silicon. The source electrode 15 and the drain electrode 16 are formed.

  The first TFT 9a and the second TFT 9b are formed in opposite shapes. That is, the first TFT 9a is formed in a shape in which the drain electrode 16 is provided on the side facing the first pixel electrode 5a and the source electrode 15 is provided on the opposite side. The second TFT 9b is formed in a shape in which the drain electrode 16 is provided on the side facing the second pixel electrode 5b and the source electrode 15 is provided on the opposite side.

  The gate electrode 10 of the first TFT 9a and the gate electrode 10 of the second TFT 9b are connected to the scanning signal line 7 arranged so as to extend between the first pixel electrode 5a and the second pixel electrode 5b. ing.

  The scanning signal line 7 is integrally formed with the gate electrode 10 on the first substrate 3 by the same metal film as the gate electrode 10 of the first and second TFTs 9a and 9b. In this embodiment, the scanning signal line 7 is formed to extend linearly between the first pixel electrode 5a and the second pixel electrode 5b, and the first and second TFTs 9a, 9b The gate electrode 10 of each of the TFTs 9a and 9b is formed on the signal line 7, and includes portions corresponding to the first TFT 9a and the second TFT 9b of the scanning signal line 7.

  Further, the source electrode 15 of the first TFT 9a and the source electrode 15 of the second TFT 9b are connected to a data signal line 8 arranged so as to extend on one side of the first pixel electrode 5a and the second pixel electrode 5b. ing.

  The data signal line 8 is formed on the gate insulating film 11 integrally with the source electrodes 15 and 15 by the same metal film as the source and drain electrodes 15 and 16 of the first and second TFTs 9a and 9b. ing.

  The data signal line 8 is integrally formed with a plurality of branch lines 8a extending toward a region between the first pixel electrode 5a and the second pixel electrode 5b of the pixel electrode 5 in each row. The branch line 8a passes through the source electrode 15 side of the first TFT 9a disposed on the side close to the data signal line 8 of the first TFT 9a and the second TFT 9b formed in opposite shapes, and further The second TFT 9b disposed on the side far from the data signal line 8 is bent to reach the source electrode 15 side. The data signal line 8 is integrally connected to the source electrode 15 of the first TFT 9a and the source electrode 15 of the second TFT 9b via the branch line 8a.

  In this embodiment, the first TFT 9a and the second TFT 9b, the scanning signal line 7 and the data signal line 8 form the gate electrode 10 and the scanning signal line 7 on the first substrate 3, and further, the gate insulating film 11 and the semiconductor thin film. 12 and a channel protective film 13 are sequentially formed, and the channel protective film 13 is patterned into a shape covering the central portion of the semiconductor thin film 12, and then a contact layer 14 and a metal film are sequentially formed. The contact layer 14 and the semiconductor thin film 12 are formed by patterning the source electrode 15 and the drain electrode and the data signal line 8 together. Therefore, the data signal line 8 is formed on a base layer composed of the semiconductor thin film 12 and the contact layer 14 in the laminated film constituting the first TFT 9a and the second TFT 9b.

  Further, on the gate insulating film 11, a first pixel electrode connecting portion 17 for electrically connecting the drain electrode 16 of the first TFT 9a and the first pixel electrode 5a, and the drain electrode 16 of the second TFT 9b and the first electrode A second pixel electrode connection portion 18 that electrically connects the two pixel electrodes 5b is formed.

  The first pixel electrode connection portion 17 extends from the drain electrode 16 of the first TFT 9a in the direction of the first pixel electrode 5a so as to overlap the side adjacent to the scanning signal line 7 of the first pixel electrode 5a. Has been. The second pixel electrode connection portion 18 has a length overlapping the side adjacent to the scanning signal line 7 of the second pixel electrode 5b from the drain electrode 16 of the second TFT 9b toward the second pixel electrode 5b. It has been extended.

  Note that the scanning signal line 7 and the first and second TFTs 9a and 9b are arranged at a position offset toward the first pixel electrode 5a side from the center of the interval between the first pixel electrode 5a and the second pixel electrode 5b. Yes. Therefore, the second pixel electrode connection portion 18 is extended longer than the first pixel electrode connection portion 17.

  The first pixel electrode connection portion 17 and the second pixel electrode connection portion 18 are formed simultaneously with the formation of the source and drain electrodes 15 and 16 of the first TFT 9a and the second TFT 9b. Accordingly, the pixel electrode connection portions 17 and 18 are formed on the base layer composed of the semiconductor thin film 12 and the contact layer 14.

  Further, a transparent covering insulating film 19 is provided on the gate insulating film 11 so as to cover the TFTs 9a and 9b, the first pixel electrode connecting portion 17, the second pixel electrode connecting portion 18 and the data signal line 8. On the covering insulating film 19, the first pixel electrode 5a and the second pixel electrode 5b are formed of an ITO film. 4 and 5, the covering insulating film 19 is omitted.

  Of the first and second pixel electrodes 5a and 5b formed on the covering insulating film 19, the first pixel electrode 5a is connected to the drain electrode 16 of the first TFT 9a via the first pixel electrode connection portion 17. The second pixel electrode 5b is connected to the drain electrode 16 of the second TFT 9b via the second pixel electrode connection portion 18.

  The covering insulating film 19 includes a first contact hole 20 formed in a portion overlapping the first pixel electrode 5 a of the first pixel electrode connection portion 17 and a second contact of the second pixel electrode connection portion 18. A second contact hole 21 is formed in a portion overlapping with the pixel electrode 5b.

  The first pixel electrode 5a is connected to the first pixel electrode connection portion 17 extended from the drain electrode 16 of the first TFT 9a in the first contact hole 20, and the second pixel electrode 5b is connected to the second contact hole. 21 is connected to the second pixel electrode connecting portion 18 extended from the drain electrode 16 of the second TFT 9b.

  Thus, in the liquid crystal display element 1, the first pixel electrode 5a connected to the first TFT 9a and the second pixel electrode 5b connected to the second TFT 9b are formed for each pixel 32, and the first TFT 9a The second TFT 9 b is connected to the same data signal line 8 and scanning signal line 7.

  Therefore, each pixel 32 includes a first region 32a in which the first pixel electrode 5a is provided and a second pixel electrode 5b at a portion between the first pixel electrode 5a and the second pixel electrode 5b. It is divided into the provided second region 32b.

  The first TFT 9a and the second TFT 9b are controlled to be turned on and off by the scanning signal from the same scanning signal line 7, and the data signal supplied from the same data signal line 8 is supplied to the first pixel electrode 5a and the second pixel electrode. 5b is applied simultaneously.

  The first substrate 3 includes a first capacitor electrode 22 that forms a first compensation capacitor Cs1 by interposing a first dielectric layer between each pixel 32 and the first pixel electrode 5a, and a second capacitor electrode 22a. A second capacitor electrode 23 is provided between the pixel electrode 5b and a second dielectric layer to form a second compensation capacitor Cs2.

  The first capacitor electrode 22 is formed in a rectangular frame shape continuous over the entire circumference of the first pixel electrode 5a so as to overlap all sides of the first pixel electrode 5a. The second capacitor electrode 23 is formed in a rectangular frame shape that is continuous over the entire circumference of the second pixel electrode 5b so as to overlap all sides of the second pixel electrode 5b. Hereinafter, the first and second pixel electrodes 5a, 5a of the first capacitor electrode 22 that overlap the sides of the first pixel electrode 5a and the second capacitor electrode 23 that overlap the sides of the second pixel electrode 5b. The portions that overlap two sides along the extending direction of the scanning signal line 7 of 5b are referred to as horizontal side portions, respectively. Further, the portions of the first and second pixel electrodes 5a and 5b that overlap two sides along the extending direction of the data signal line 8 are referred to as vertical sides.

  Further, the first capacitor electrode 22 is formed in a shape in which the outer edges of the horizontal side portion and the vertical side portion that overlap each side of the first pixel electrode 5a protrude outward from the first pixel electrode 5a, respectively. The capacitor electrode 23 is formed in a shape in which the outer edges of the horizontal side portion and the vertical side portion that overlap each side of the second pixel electrode 5b protrude outward from the second pixel electrode 5b.

  The first capacitor electrode 22 of each pixel 32 has one side of the first capacitor electrodes 22 and 22 adjacent to each other for each row (the side on the opposite side to the side adjacent to the scanning signal line 7 in the figure). ) Are continuously connected to each other to form a common connection. In addition, the second capacitor electrode 23 of each pixel 32 has, for each row, one horizontal side portion of the adjacent second capacitor electrodes 23 and 23 (the horizontal side opposite to the side adjacent to the scanning signal line 7 in the figure). Are connected in common by forming the end portions of the portion) continuously.

  Further, a third dielectric layer is interposed on the first substrate 3 between each pixel 32 and a connection portion that electrically connects the second TFT 9b and the second pixel electrode 5b. A third capacitor electrode 24 for forming Cs3 is provided.

  The connecting portion between the second TFT 9b and the second pixel electrode 5b is a second pixel electrode connecting portion 18 extended from the drain electrode 16 of the second TFT 9b, and the third capacitor electrode 24 is connected to the scanning signal line 7 and The scanning signal line 7 and the second pixel electrode in the second pixel electrode connection portion 18 are spaced from the second pixel electrode 5b with a space between the scanning signal line 7 and the second pixel electrode 5b. It arrange | positions so that it may overlap with the part corresponding to the area | region between 5b.

  The outer edges of the respective sides of the first capacitor electrode 22 and the second capacitor electrode 23 protrude outward from the first pixel electrode 5a and the second pixel electrode 5b. Therefore, the third capacitor electrode 24 is spaced from the scan signal line 7 and the second capacitor electrode 23 with a gap between the scan signal line 7 and the second capacitor electrode 23. The connection portion 18 is disposed so as to overlap with a portion corresponding to a region between the scanning signal line 7 and the second capacitance electrode 23.

The third capacitor electrode 24 is formed in a shape extending in a predetermined direction, said third capacitor electrode 2 4 overlaps part 18a of the second pixel electrode connection portion 18, the third capacitor electrode 2 4 It is formed in a long shape along the stretching direction. Hereinafter, a portion 18a overlapping the third capacitor electrode 2 4 of the second pixel electrode connection portion 18 of the capacitance formation section.

  In this embodiment, the third capacitor electrode 24 is formed by extending in a direction parallel to the extending direction of the scanning signal line 7, and the capacitor forming portion 18 a of the second pixel electrode connecting portion 18 is formed by the third capacitor electrode. Along the extending direction of 24, the second pixel electrode 5 b is formed in a horizontally long shape having the same length as the side adjacent to the third capacitor electrode 24. The third capacitor electrode 24 of each pixel 32 is commonly connected by continuously forming the end portions of the adjacent third capacitor electrodes 24 and 24 for each row.

  The first, second, and third capacitor electrodes 22, 23, and 24 are arranged on the same plane. In this embodiment, each of the capacitance electrodes 22, 23, 24 is on the same surface as the formation surface of the scanning signal line 7 and the gate electrodes 10 of the TFTs 9a, 9b, that is, on the first substrate 3. And the same metal film as that of the gate electrode 10 and is covered with the gate insulating film 11.

  The first capacitor electrode 22 is opposed to each side of the entire circumference of the first pixel electrode 5a via a first dielectric layer composed of a two-layer film of the gate insulating film 11 and the covering insulating film 19. The first compensation capacitor Cs1 is formed between the first pixel electrode 5a.

  The second capacitor electrode 23 is opposed to each side of the entire circumference of the second pixel electrode 5b through a second dielectric layer composed of a two-layer film of the gate insulating film 11 and the covering insulating film 19. The second compensation capacitor Cs2 is formed between the second pixel electrode 5b.

  Further, the third capacitor electrode 24 is a second layer film composed of the gate insulating film 11 and the covering insulating film 19 with respect to the horizontally long capacitor forming portion 18 a formed in the second pixel electrode connecting portion 18. A third compensation capacitor Cs3 is formed between the second pixel electrode connection portion 18 and the second pixel electrode connection portion 18 so as to face each other via three dielectric layers.

  On the other hand, on the second substrate 4, as shown in FIGS. 6 to 9, three color filters of a red filter 25R, a green filter 25G, and a blue filter 25B are alternately arranged for each column of the pixels 32. Yes. Further, the second substrate 4 includes a light shielding film corresponding to a region between adjacent pixels 32 and 32 in each row and each column and a region between the first region 32a and the second region 32b of each pixel 32. 26 is formed.

  In this embodiment, the light shielding film 26 is made of, for example, a photosensitive resin to which a black pigment is added, and the three color filters 25R, 25G, and 25B are formed on the second substrate 4. It is formed in the area without. The common electrode 6 is formed on the color filters 25R, 25G, 25B and the light shielding film 26 over the entire arrangement region of the pixels 32.

  Further, the first substrate 3 is provided with a first alignment film 27 covering the first pixel electrode 5a and the second pixel electrode 5b, and the second substrate 4 is provided with a second alignment film covering the common electrode 6. 28 is provided. In FIGS. 4 and 5, the first alignment film 27 is omitted.

  As shown in FIGS. 2 and 3, the first substrate 3 and the second substrate 4 are arranged to face each other with a predetermined gap, and are bonded together via a frame-shaped sealing material 29 surrounding the screen area 1a. The liquid crystal layer 2 is provided between the first pixel electrode 5 a and the common electrode 6 and between the second pixel electrode 5 b and the common electrode 6. The liquid crystal layer 2 is formed by sealing liquid crystal in a region surrounded by the sealing material 29 in the gap between the first substrate 3 and the second substrate 4.

  A first polarizing plate 30 is disposed on the outer surface of the first substrate 3 with its absorption axis directed in a predetermined direction, and a second polarizing plate 31 is disposed on the outer surface of the second substrate 4. Are arranged in a predetermined direction.

  The liquid crystal display element 1 of this embodiment is a vertical alignment type liquid crystal display element, and the first alignment film 27 and the second alignment film 28 are made of a vertical alignment film. The liquid crystal layer 2 has negative dielectric anisotropy, and when no voltage is applied between the first and second pixel electrodes 5a and 5b and the common electrode 6, the liquid crystal molecules 2a are shown in FIG. The liquid crystal molecules 2a are aligned perpendicular to the surfaces of the substrates 3 and 4 and voltage is applied between the first and second pixel electrodes 5a and 5b and the common electrode 6 so that the liquid crystal molecules 2a It consists of nematic liquid crystals that are tilted and oriented with respect to the surface.

  The first polarizing plate 30 and the second polarizing plate 31 are normally black when the applied voltage between the first pixel electrode 5a and the second pixel electrode 5b and the common electrode 6 is 0V. The absorption axes (not shown) of the polarizing plates 30 and 31 are arranged so as to be orthogonal to each other so as to constitute a mode liquid crystal display element.

  Further, as shown in FIGS. 2 and 3, for example, a driver mounting portion 3 a that extends outward from the second substrate 4 is formed on the first substrate 3 at one end side in the vertical direction (column direction) of the screen area 1 a. The driver mounting portion 3a is mounted with a driver element 33 made of an LSI having a plurality of input terminals, a plurality of scanning signal output terminals, and a plurality of data signal output terminals (not shown).

  Each scanning signal line 7 is connected to each scanning signal output terminal of the driver element 33 while bypassing the outside of the screen area 1a, and each data signal line 8 is connected to each data signal of the driver element 33. It is connected to each output terminal.

  Further, the driver mounting portion 3a is formed with one first voltage input terminal 34a and one second voltage input terminal 34b. The common electrode 6 is connected to the first voltage input terminal 34a via a cross connection portion (not shown) provided at the substrate bonding portion by the frame-shaped sealing material 29.

  Although not shown in the figure, the first substrate 3 has one first voltage supply line connected to the first voltage input terminal 34a outside the screen area 1a, and the second substrate 3a. One second voltage supply line connected to the voltage input terminal 34 b is wired in parallel with the data signal line 8.

  The first capacitor electrodes 22 of all the rows commonly connected to each row and the second capacitor electrodes 23 of all the rows commonly connected to each row are connected to the one first voltage supply line. The first voltage input terminal 34a is connected to the common electrode 6 through the first voltage supply line.

  Further, the third capacitor electrodes 24 of all the rows commonly connected for each row are connected to the one second voltage supply line, and are connected to the second voltage input terminal 34b through the second voltage supply line. It is connected.

  The liquid crystal display element 1 sequentially selects the rows of the pixels 32 (hereinafter referred to as pixel rows) one by one, and for each pixel row, the first pixel electrode 5a and the second pixel electrode 5b of each pixel 32 in the row. The common electrode 6 is driven by applying a voltage, and the transmission of light in the first region 32a and the second region 32b of the pixel 32 is controlled by changing the alignment state of the liquid crystal molecules by the application of the voltage. To display an image. A surface light source (not shown) that irradiates light with uniform illuminance toward the entire area of the screen area 1a is disposed behind the liquid crystal display element 1 (on the side opposite to the display surface).

  Next, driving means 35 for driving the liquid crystal display element 1 will be described. As shown in FIG. 1, the driving unit 35 includes an image memory 36 that temporarily stores image data input from the outside, and a scanning signal line that applies a scanning signal to each scanning signal line 7 of the liquid crystal display element 1. A drive circuit 37 and a data signal line drive circuit 34 for applying a data signal to each data signal line 8 of the liquid crystal display element 1 are provided. The scanning signal line driving circuit 37 and the data signal line driving circuit 38 are formed in the driver element 33 mounted on the driver mounting portion 3a of the liquid crystal display element 1.

  Further, the driving means 35 includes a first voltage generating circuit 39, a second voltage generating circuit 40, the scanning signal line driving circuit 37, a data signal line driving circuit 38, a first voltage generating circuit 39, and a second voltage generating. A control unit 41 that controls the circuit 40 is provided.

  The scanning signal line drive circuit 37 applies a scanning signal for turning on and off the first TFT 9a and the second TFT 9b to each scanning signal line 7 based on a control signal such as a synchronizing clock signal from the control unit 41. To do.

  In FIG. 12, t1, t2, t3, t4,... Tn are one frame for displaying one screen (each pixel row from the first row to the last row is sequentially selected and assigned to each pixel 32 of all pixel rows. Is a selection period of each pixel row divided by the number of rows of each pixel, t1 is the selection period of the first row, t2 is the selection period of the second row, and t3 is the first selection period. The selection period for three rows, t4 is the selection period for the fourth row, t5 is the selection period for the fifth row, and tn is the selection period for the last row (n rows).

  In FIG. 12, G1, G2, G3, G4,... Gn are scanning signals applied to the respective scanning signal lines 7, G1 is a scanning signal applied to the first row of scanning signal lines 7, and G2 Is a scanning signal applied to the scanning signal line 7 of the second row, G3 is a scanning signal applied to the scanning signal line 7 of the third row, G4 is a scanning signal applied to the scanning signal line 7 of the fourth row, G5 is a scanning signal applied to the scanning signal line 7 in the fifth row, and Gn is a scanning signal applied to the scanning signal line 7 in the last row (n-th row).

  These scanning signals are supplied to the first TFT 9a at the start of writing, which is delayed by a predetermined time from the start of the selection period t1, t2, t3, t4,... Tn of the pixel row corresponding to the scanning signal line 7 to which the scanning signal is applied. The first TFT 9a and the second TFT 9b are turned off at the end of writing for a predetermined time earlier than the end of the selection period t1, t2, t3, t4,. The off-potential signal is a waveform signal that is kept at the off-voltage during other periods.

  The data signal line driving circuit 38 takes in the image data temporarily stored in the image memory 36 through the control unit 41 for each pixel row based on a control signal from the control unit 41. In each selection period, a data signal corresponding to the gradation value of each image data for one row of pixels is applied to each data signal line 8.

  The first voltage generation circuit 39 generates the first voltage V <b> 1 based on the control signal from the control unit 41. The first voltage V1 is supplied to the common electrode 6, the first capacitor electrode 22 and the second capacitor electrode 23 in each row through a first voltage input terminal 34a formed in the driver mounting portion 3a of the liquid crystal display element 1. And applied.

  That is, the voltage V <b> 1 applied to the first capacitor electrode 22 and the second capacitor electrode 23 in each row is the same voltage as the voltage applied to the common electrode 6. Hereinafter, the voltage applied to the common electrode 6 in the voltage V1 is referred to as a common signal Vcom.

  The first voltage V1 applied from the first voltage generation circuit 39 to the common electrode 6 and the first capacitor electrode 22 and the second capacitor electrode 23 in each row is a rectangular wave AC voltage whose voltage level is inverted at a predetermined cycle. is there.

  In this embodiment, as shown in FIG. 12, the voltage level of the first voltage V1 is inverted every selection period t1, t2, t3, t4,. This is a rectangular wave AC voltage that is inverted every frame.

  The data signal D shown in FIG. 12 is a signal applied to each data signal line 8 from the scanning signal line driving circuit 37 during the selection period of one pixel row of each pixel row. Each data signal D applied to each data signal line 8 for each row selection period t1, t2, t3, t4,... Tn is a common electrode for each selection period t1, t2, t3, t4,. 6 is a rectangular wave signal whose potential changes so that the potential difference from the common signal Vcom (= V1) applied to 6 becomes a value corresponding to the gradation value of each image data.

  On the other hand, the second voltage generation circuit 40 generates a second voltage V2 different from the first voltage V1 based on a control signal from the control unit 41. As shown in FIG. 12, the second voltage V2 is a DC voltage of a certain level, and the third voltage of each row is supplied via the second voltage input terminal 34b formed in the driver mounting portion 3a of the liquid crystal display element 1. Applied to the capacitive electrode 24.

In this embodiment, the second voltage V2 is a voltage between the high level value V1 _H and the low level value V1 _{L of} the first voltage V1, for example, each level value V1 _{H as shown in FIG.} , V1 _{L is} an intermediate voltage value.

  As described above, the driving unit 35 forms the second compensation capacitor Cs2 between the first capacitor electrode 22 that forms the first compensation capacitor Cs1 between the first pixel electrode 5a and the second pixel electrode 5b. The first voltage V1 that is the same as the voltage applied to the common electrode 6 (common signal Vcom) is applied to the second capacitor electrode 23, and the connection portion between the second TFT 9b and the second pixel electrode 5b (the drain of the second TFT 9b). A second voltage V2 different from the first voltage V1 is applied to the third capacitor electrode 24 forming the third compensation capacitor Cs3 with the second pixel electrode connection portion 18 extended from the electrode 16). .

In this liquid crystal display device, each pixel 32 of the liquid crystal display element 1 can be represented by a circuit as shown in FIG. That is, the first region 32a of one pixel 32 includes a first pixel capacitor C _LC 1 including the first pixel electrode 5a, the common electrode 6 and the liquid crystal layer 2 therebetween, and the first pixel electrode 5a and the first capacitor. A first compensation capacitor Cs1 composed of an electrode 22 and a first dielectric layer therebetween (a two-layer film of a gate insulating film 11 and a covering insulating film 19) is connected at the first pixel electrode 5a, and the first pixel electrode 5a The first TFT 9a is connected to the circuit.

The second region 32b of the pixel 32 includes a second pixel capacitor C _{LC 2} consisting of the second pixel electrode 5b and the common electrode 6 and the LC layer 2 which, the second pixel electrode 5b and the second capacitor electrode 23 and a second compensation capacitor Cs2 composed of a second dielectric layer (a two-layer film of the gate insulating film 11 and the covering insulating film 19) between them is connected at the second pixel electrode 5b, and is connected to the second pixel electrode 5b. A second TFT 9b is connected, and between the second TFT 9b and the second pixel electrode 5b, a connection portion 18 between the second TFT 9b and the second pixel electrode 5b, a third capacitor electrode 24, and a third dielectric layer therebetween. It consists of a circuit to which a third compensation capacitor Cs3 composed of (a two-layer film of a gate insulating film 11 and a covering insulating film 19) is connected.

A common signal Vcom whose voltage level is inverted between a high level value V1 _H and a low level value V1 _L is applied to the common electrode 6 for each selection period of each pixel row. The second capacitor electrode 23 is applied with the same first voltage V1 as the common signal Vcom, and the third capacitor electrode 24 is applied with a second voltage different from the first voltage V1 (for example, the first voltage V1). DC voltage values between the high level value V1 _H and the low level value V1 _L) V2 is applied.

  Further, the data signal D supplied from the data signal line 8 is respectively applied to the first pixel electrode 5a and the second pixel electrode 5b of each pixel 32 of the selected pixel row by turning on the first TFT 9a and the second TFT 9b. Applied.

A voltage applied between the first pixel electrode 5a and the common electrode 6 and between the second pixel electrode 5b and the common electrode 6 (hereinafter referred to as a write voltage) is the first voltage V1 and the common electrode 6, respectively. The voltage has a value corresponding to the voltage difference with the data signal D, and the write voltage is charged to the first pixel capacitor C _LC 1 and the second pixel capacitor C _LC 2.

  In addition, since the voltage applied to the first capacitor electrode 22 and the second capacitor electrode 23 is the same first voltage V1 as the common signal Vcom applied to the common electrode 6, the first pixel electrode 5a and the first capacitor electrode The first compensation capacitor Cs1 between the capacitor electrode 22 and the second compensation capacitor Cs2 between the second pixel electrode 5b and the second capacitor electrode 23 are respectively charged with the same voltage as the write voltage.

  On the other hand, since the voltage applied to the third capacitor electrode 24 is the second voltage V2 different from the first voltage V1, the connection 18 between the second TFT 9b and the second pixel electrode 5b and the third capacitor electrode 24 The third compensation capacitor Cs3 is charged with a voltage different from the write voltage (a voltage having a voltage difference corresponding to the difference between the first voltage V1 and the second voltage V2 with respect to the write voltage).

  Note that a parasitic capacitance (hereinafter referred to as a first parasitic capacitance) such as a gate-source capacitance and a drain-source capacitance of the first TFT 9a is provided between the first pixel electrode 5a and the scanning signal line 7 and the data signal line 8. ) Exists. Further, between the second pixel electrode 5b and the scanning signal line 7 and the scanning signal line 7, parasitic capacitances (hereinafter referred to as second parasitic capacitance) such as a gate-source capacitance and a drain-source capacitance of the second TFT 9b. ) Exists.

Therefore, the first TFT9a and second TFT9b is turned off, the writing is completed, the charge voltage to the first pixel capacitance C _{LC 1} and the second compensation capacitor Cs2 is, to some extent by the retraction of a voltage to the first parasitic capacitance drop, and the voltage which is charged with the second pixel capacitance C _{LC 2} second compensation capacitor Cs2 and the third compensation capacitor Cs3 is, to some extent lowered by retraction of a voltage to the second parasitic capacitance.

The liquid crystal in the first region 32a of the pixel 32 is driven by the charge voltage of the first pixel capacitor C _LC 1 (voltage between the first pixel electrode 5a and the common electrode 6). The liquid crystal in the second region 32b of the pixel 32 is driven by the second pixel capacitor C _{LC 2} charge voltage (voltage between the second pixel electrode 5b and the common electrode 6).

FIG. 14 shows a voltage applied between the first pixel electrode 5a and the common electrode 6 in the first region 32a of one pixel 32 of the pixels 32 in the first row, and FIG. The voltage applied between the second pixel electrode 5b and the common electrode 6 in the second region 32b of 32 is shown. In FIG. 14, V _P 1 is the potential of the first pixel electrode 5a. In FIG. 15, V _P 2 is the potential of the second pixel electrode 5b. In FIGS. 14 and 15, the rising and falling edges of the first and second pixel electrodes 5a and 5b are inclined so that the potentials V _P1 and V _{P2 of} the first pixel electrode 5a and the common signal Vcom can be easily distinguished. I am letting.

  As shown in FIG. 14, the voltage between the first pixel electrode 5a and the common electrode 6 is applied to the data signal line 8 during the ON period of the first and second TFTs 9a and 9b in the selection period t1 of the first row. To the write voltage Va corresponding to the potential difference between the data signal D applied to the first pixel electrode 5a via the first TFT 9a and the common signal Vcom applied to the common electrode 6.

  When the first TFT 9a is turned off, the voltage between the first pixel electrode 5a and the common electrode 6 becomes a voltage Va1 that is reduced by the pull-in voltage ΔV1 due to the first parasitic capacitance with respect to the write voltage Va. Hereinafter, this voltage Va1 is referred to as a first holding voltage.

Further, the voltage level of the common signal Vcom applied to the common electrode 6 is inverted every selection period t1, t2, t3, t4,... Tn of each pixel row, but the common signal Vcom and the first capacitance electrode 22 are applied. since the first voltage V1 to be applied are the same voltage, it is inverted voltage level of the common signal Vcom, the charge voltage of the first pixel capacitance C _{LC 1} and the first compensation capacitor Cs1 is not changed. Therefore, the voltage between the first pixel electrode 5a and the common electrode 6 is maintained at the first holding voltage Va1 in the selection period lines t2, t3, t4,. It is.

  Therefore, the first holding voltage Va1 between the first pixel electrode 5a and the common electrode 6 is the end of one frame from the end of writing in the selection period t1 of the first row regardless of the voltage level inversion of the common signal Vcom. During this period, the voltage is maintained substantially the same as the first holding voltage Va1 in the selection period t1 of the first row, and the voltage is applied as an effective voltage of one frame to the liquid crystal in the first region 32a.

  Further, as shown in FIG. 15, the voltage between the second pixel electrode 5b and the common electrode 6 is a data signal during the ON period of the first and second TFTs 9a and 9b in the selection period t1 of the first row. The write voltage Va corresponds to the potential difference between the data signal D applied to the second pixel electrode 5b from the line 8 via the second TFT 9b and the common signal Vcom applied to the common electrode 6. The write voltage Va is a voltage having the same value as the write voltage Va applied between the first pixel electrode 5a and the common electrode 6.

  Then, when the second TFT 9b is turned off, the voltage between the second pixel electrode 5b and the common electrode 6 becomes a voltage Va2 that is lowered from the write voltage Va by the pull-in voltage ΔV2 due to the second parasitic capacitance. Hereinafter, this voltage Va2 is referred to as a second holding voltage. The pull-in voltage ΔV2 due to the second parasitic capacitance is the same as the pull-in voltage ΔV1 due to the first parasitic capacitance, and therefore the second holding voltage Va2 is a voltage having the same value as the first holding voltage Va1. .

  On the other hand, the first voltage V1, which is the voltage applied to the second capacitor electrode 23, is the same voltage as the common signal Vcom applied to the common electrode 6 (the voltage for each selection period t1, t2, t3,... Tn of each pixel row). The second voltage V2, which is a voltage applied to the third capacitor electrode 24, is a DC voltage at a constant level different from the first voltage V1.

Therefore, when the voltage level of the common signal Vcom is inverted with respect to the voltage level of the selection period t1 of the first row, the second pixel is accompanied by a decrease in the voltage value between the common electrode 6 and the third capacitance electrode 24. each of the charge voltage of the capacitance _{C LC} 2 and the second compensating capacitor Cs2 and the third compensation capacitor Cs3 is stepped down at a rate corresponding to these _C LC 2, Cs2, the capacitance value of Cs3.

Further, the voltage level of the common signal Vcom is the same as the first line of the voltage level of the selection period t1, the second pixel capacitance C _{LC 2} and the second charge voltage of the compensation capacitor Cs2 and the charge voltage of the third compensation capacitor Cs3 Are voltages after completion of writing in the selection period t1 of the first pixel row (voltages after the second TFT 9b is turned off).

  Therefore, the voltage between the second pixel electrode 5b and the common electrode 6 is the selection period of the even-numbered pixel rows of the pixel rows below the second row (the voltage level of the common signal Vcom is selected in the first row). During the selection period t2, t4,... Inverted with respect to the voltage level of the period t1, the voltage Va3 is stepped down from the second holding voltage Va2, and the selection period of the odd-numbered pixel row (the voltage of the common signal Vcom) In the selection period (t3, t5,... In which the level is the same as the voltage level of the selection period t1 of the first row), the voltage returns to substantially the same voltage as the second holding voltage Va2.

  Therefore, the liquid crystal in the second region 32b has an effective voltage of one frame obtained by averaging the voltages Va2 and Va3 applied alternately every selection period t1, t2, t3,. As applied.

  The second holding voltage Va2 and the voltage Va3 obtained by stepping down the second holding voltage Va2 can be obtained by the following equations (1) and (2).

_{Va2 = (C ic + C 2} ) × (V pix -V comL) + C 3 × (V pix -C 3)
_{+ C ds × (V pix -V} sigH) + C gs × (V pix -V gL) ... (1)
_{Va3 = (C ic + C 2} ) × (V pix -V comH) + C 3 × (V pix -C 3)
+ C _ds × (V _pix −V _sigL ) + C _gs × (V _pix −V _gL ) (2)
C _lc ; capacitance value of the second pixel capacitor C _LC 2; C ₂ ; capacitance value of the second compensation capacitor Cs ₂ ; C ₃ ; capacitance value of the third compensation capacitor Cs ₃ ; C _gs ; gate-source capacitance C _{ds of} the second TFT 9 b; The drain-source capacitance V _{sigH of} the second _{TFT 9b} ; the potential V _sigL of the data signal in the selection period of the first pixel row; the potential V _gL of the data signal in the selection period of the second pixel row; the off-voltage V _{pix of the} scanning signal; Potential V _commL of the second pixel electrode 5b; low level value (V1 _L ) of the common signal Vcom
V _comH ; high level value (V1 _H ) of the common signal Vcom
The effective voltage for one frame applied to the liquid crystal in the second region 32b can be obtained by the following equation (3).

Effective voltage = {(Va2 ² + Va3 ² ) / 2} ^1/2 (3)
As described above, the effective voltage of one frame in the second region 32 b of each pixel 32 is a voltage obtained by stepping down the effective voltage of one frame of the first region 32 a of the same pixel 32. Then, the liquid crystal molecules 2a in the first region 32a are tilted and aligned corresponding to the strength of the effective voltage of one frame of the first region 32a, and the liquid crystal molecules 2a in the second region 32b are aligned in the second region 32a. It tilts and aligns corresponding to the strength of the effective voltage of one frame.

  Accordingly, the tilt angle of the liquid crystal molecules 2a with respect to the data signal having the same gradation value (the angle of the molecular major axis of the liquid crystal molecules 2a with respect to the normal direction of the substrates 3 and 4) differs between the first region 32a and the second region 32b. . That is, the liquid crystal molecules 2a in the second region 32b are tilted at an angle smaller than the tilt angle of the liquid crystal molecules 2a in the first region 32a.

  Therefore, the voltage-transmittance characteristic in the liquid crystal layer 2 in the second region 32b of each pixel 32 is different from the voltage-transmittance characteristic in the liquid crystal layer 2 in the first region 32a. FIG. 16 shows voltage-transmittance characteristics of the first region 32a and the second region 32b in the normally black mode liquid crystal display element 1. FIG. As shown in FIG. 16, the voltage-transmittance characteristic of the second region 32b is a characteristic shifted to the high voltage side with respect to the voltage-transmittance property of the first region 32a.

  Accordingly, the layer thickness of the liquid crystal layer 2 (the gap between the first substrate 1 and the second substrate 2) and the like are set such that the voltage-transmittance characteristic of the first region 32a becomes a characteristic that provides a predetermined viewing angle. Further, the second voltage V2 is designed so that the voltage-transmittance characteristic of the second region 32b is shifted by a predetermined amount with respect to the voltage-transmittance property of the first region 32a, that is, the first region. By setting so as to obtain a viewing angle different from the viewing angle of 32a, it is possible to obtain a wide viewing angle in which the viewing angle characteristics of the first region 32a and the viewing angle property of the second region 32b are synergistic. it can.

  The viewing angle in which the viewing angle characteristics of the first region 32a and the viewing angle characteristics of the second region 32b are synergistic is the area ratio between the first region 32a and the second region 32b (the first pixel electrode 5a and the second region 32b). Corresponding to the pixel electrode 5b). Accordingly, a viewing angle having a predetermined width can be obtained by selecting an area ratio area ratio between the first region 32a and the second region 32b.

  In the liquid crystal display device of the above embodiment, the viewing angle can be finely adjusted only by controlling the voltage value applied to the third capacitor electrode 24. Therefore, even if the viewing angle varies between display devices due to errors such as the insulation film thickness and the substrate gap generated in the manufacturing process, the viewing angle variation can be easily corrected.

  That is, in the liquid crystal display device of the above embodiment, the first voltage V1 that is the same as the voltage applied to the common electrode 6 is applied to the first capacitor electrode 22 and the second capacitor electrode 23, and the third capacitor electrode 24 is Since the second voltage V2 different from the first voltage V1 is applied, the voltage of the second region 32b is controlled by controlling the value of the second voltage V2 applied to the third capacitor electrode 24. The transmittance characteristic can be changed.

  As shown in FIG. 16, the voltage-transmittance characteristic of the second region 32b is a characteristic shifted to the high voltage side with respect to the voltage-transmittance property of the first region 32a. This corresponds to the difference between the first voltage V1 applied to the second capacitor electrode 23 and the second voltage V2 applied to the third capacitor electrode 24.

  In this embodiment, the shift amount of the voltage-transmittance characteristic of the second region 32b with respect to the voltage-transmittance property of the first region 32a is accompanied by decreasing the difference between the second voltage V2 and the first voltage V1. The voltage decreases and increases as the difference between the first voltage V1 and the second voltage V2 increases.

  As described above, the liquid crystal display device can change the voltage-transmittance characteristic of the second region 32b, and thus can arbitrarily adjust the viewing angle characteristic of the second region 32b. Accordingly, the viewing angle obtained by synthesizing the viewing angle characteristics of the first area 32a and the viewing angle characteristics of the second area 32b is finely adjusted to a predetermined value to correct the viewing angle variation between the display devices. be able to. The correction of the viewing angle variation can be easily performed only by controlling the second voltage V2 applied to the third capacitor electrode 24.

  In the above embodiment, the common signal Vcom applied to the common electrode 6 and the first voltage V1 (Vcom = V1) applied to the first capacitance electrode 22 are a rectangular wave AC voltage whose voltage level is inverted at a predetermined cycle, For example, a rectangular wave AC voltage whose voltage level is inverted every selection period t1, t2, t3, t4,. Therefore, a constant effective voltage corresponding to the first holding voltage Va1 is applied to the liquid crystal in the first region 32a of each pixel 32 during the period from the end of writing in the selection period t1 of the first row to the end of one frame. Can be applied.

Further, in the above embodiment, the first voltage (rectangular wave AC voltage) V 1 that is the same as the voltage applied to the common electrode 6 and the first capacitor electrode 22 is applied to the second capacitor electrode 23, and the third capacitor electrode 24 is applied. , applies a second voltage V2 being a DC voltage having a value between the predetermined level, for example, the first voltage high level value V1 to form a V1 _H and the low level value V1 _L.

  Therefore, as shown in FIG. 15, the voltage between the second pixel electrode 5b and the common electrode 6 is alternately changed to the second holding voltage Va2 and the voltage Va3 lower than the second holding voltage Va2, and the second voltage of each pixel 32 is changed. An effective voltage having an average value of the two voltages Va2 and Va3 can be applied to the liquid crystal in the region 32b during the period from the end of writing in the selection period t1 of the first row to the end of one frame.

  In the liquid crystal display device, the first capacitor electrode 22 that forms the first compensation capacitor Cs1 between the first pixel electrode 5a and the first pixel electrode 5a overlaps all sides of the first pixel electrode 5a. The second capacitor electrode 23 that is formed in a continuous shape over the entire circumference of the electrode 5a and forms the second compensation capacitor Cs2 between the second pixel electrode 5b overlaps all sides of the second pixel electrode 5b. As described above, since the second element electrode 5b is continuously formed over the entire circumference, the capacitance value of the first compensation capacitor Cs1 and the capacitance value of the second compensation capacitor Cs2 are sufficiently increased. be able to.

  Further, the liquid crystal display device has the third capacitor electrode 24 formed in a shape extending in a predetermined direction (in the embodiment, a direction parallel to the extending direction of the scanning signal line 7), and the second TFT 9b and the second pixel. A capacitance forming portion 18 a overlapping with the third capacitance electrode 24 of the connection portion (second pixel electrode connection portion extended from the drain electrode 16 of the second TFT 9 b) 18 with the electrode 5 b is formed in the extending direction of the third capacitance electrode 24. Since it is formed in a long shape along, it is possible to sufficiently secure the capacitance value of the third compensation capacitor Cs3.

  In the above embodiment, since the capacitor forming portion 18a is formed to have the same length as the side adjacent to the third capacitor electrode 24 of the second pixel electrode 5b, the capacitance value of the third compensation capacitor Cs3 is made sufficiently large. can do.

  Furthermore, in the above embodiment, since the first, second and third capacitive electrodes 22, 23, 24 are arranged on the same plane, these capacitive electrodes 22, 23, 24 are simultaneously put together. Can be formed. In the above-described embodiment, each of the capacitor electrodes 22, 23, 24 is placed on the same surface (on the first substrate 3) as the scanning signal line 7 and the gate electrode 10 of each TFT 9a, 9b. 7 and the gate electrode 10, the capacitor electrodes 22, 23 and 24 can be formed simultaneously with the formation of the scanning signal line 7 and the gate electrode 10.

  Moreover, in the above embodiment, the capacitor electrodes 22, 23, 24 are formed on the same surface (on the first substrate 3) as the gate electrode 10 of the first and second TFTs 9a, 9b, and the second The pixel electrode connection portion 18 is formed on the gate insulating film 11 of each TFT 9a, 9b, and the first and second pixel electrodes 5a, 5b are provided so as to cover the TFT 9a, 9b and the second pixel electrode connection portion 18. By forming on the insulating film 19, the first dielectric layer of the first compensation capacitor Cs1 and the second dielectric layer of the second compensation capacitor Cs2 are formed into a two-layer film of the gate insulating film 11 and the covering insulating film 19. The third dielectric layer of the third compensation capacitor Cs3 is formed by the gate insulating film 11. Therefore, the first, second, and third compensation capacitors Cs1, Cs2, and Cs3 can be formed by using the steps of forming the TFTs 9a and 9b and the first and second pixel electrodes 5a and 5b.

  In the liquid crystal display device, the outer edge of the portion of the first capacitor electrode 22 that overlaps each side of the first pixel electrode 5a protrudes outward from the first pixel electrode 5a. A lateral electric field is generated between each side of 5a and the outer edge of each side of the first capacitor electrode 22. This lateral electric field is an electric field having the same strength over the entire circumference of the first pixel electrode 5a.

  In addition, the outer edges of the portions of the second capacitor electrode 23 that overlap the sides of the second pixel electrode 5b protrude outward from the second pixel electrode 5b. A lateral electric field is generated between the outer edges of the respective sides of the two-capacitance electrode 23. This lateral electric field is an electric field having the same strength over the entire circumference of the second pixel electrode 5b.

  Therefore, when a voltage is applied between the first pixel electrode 5a and the second pixel electrode 5b and the common electrode 6, the liquid crystal molecules 2a in the first region 32a are separated from each side of the first pixel electrode 5a as shown in FIG. The liquid crystal molecules 2a in the second region 32b are oriented so as to fall down toward the center of the first pixel electrode 5a, and fall down from each side of the second pixel electrode 5b toward the center of the second pixel electrode 5b. Orient.

  On the other hand, the liquid crystal display device of the comparative example shown in FIG. 18 includes a third compensation capacitor Cs13 for making the voltage-transmittance characteristic of the second region 32b different from the voltage-transmittance characteristic of the first region 32a. This is formed by a third capacitor electrode 124 provided so as to overlap a predetermined side of the second pixel electrode 5b. In FIG. 18, components corresponding to the liquid crystal display device of the above embodiment are given the same reference numerals, and the description of the same components is omitted. Also in FIG. 18, the coating insulating film 19 and the first alignment film 27 are omitted.

  In this comparative example, the scanning signal line 7 and the first and second TFTs 9a and 9b are arranged at an intermediate position between the first pixel electrode 5a and the second pixel electrode 5b, and the drain electrode 16 of the first TFT 9a. The first pixel electrode connection portion 17 extended from the second pixel electrode connection portion 18 extended from the drain electrode 16 of the second TFT 9b is formed to have the same length. The second pixel electrode connecting portion 18 is formed in a shape that does not have the capacitance forming portion 18a as in the above embodiment.

  And the 1st capacity | capacitance electrode 122 which forms 1st compensation capacity | capacitance Cs11 between the 1st pixel electrodes 5a is formed in the shape which followed the perimeter of the 1st pixel electrode 5a similarly to the said Example. The first pixel electrode 5a is opposed to the first dielectric layer which is a two-layer film of the gate insulating film 11 and the covering insulating film 19.

  Meanwhile, the third capacitor electrode 124 forming the third compensation capacitor Cs13 is formed so as to overlap a predetermined one of the sides of the second pixel electrode 5b, for example, a side adjacent to the scanning signal line 7, It faces the second pixel electrode 5b through a third dielectric layer composed of a two-layer film of a gate insulating film 11 and a covering insulating film 19. The second capacitor electrode 123 that forms the second compensation capacitor Cs2 between the second pixel electrode 5b and the third capacitor electrode 124 is spaced apart from the second pixel electrode 5b. And the second pixel electrode 5b is opposed to the second pixel electrode 5b through a third dielectric layer formed of a two-layer film of the gate insulating film 11 and the covering insulating film 19.

  The first capacitor electrode 122 is formed in a shape in which the outer edge of each side portion thereof protrudes outward from the first pixel electrode 5a, and the second capacitor electrode 123 and the third capacitor electrode 124 are The outer edge is formed in a shape protruding outward from the second pixel electrode 5b.

  Also in this comparative example, the first voltage V1 that is the same as the voltage applied to the common electrode 6 (see FIGS. 6 to 9) is applied to the first capacitor electrode 122 and the second capacitor electrode 123, and the third capacitor By applying a second voltage V2 different from the first voltage V1 to the electrode 124, the voltage-transmittance characteristics in the liquid crystal layer 2 of the first region 32a of each pixel 32, and the liquid crystal of the second region 32b. It is possible to obtain a wide viewing angle in which the voltage-transmittance characteristics in the layer 2 are different and the viewing angle characteristics of both are synergistic.

  Further, the lateral electric field generated between each side of the first pixel electrode 5a and the outer edge of each side part of the first capacitor electrode 122 is an electric field having the same strength over the entire circumference of the first pixel electrode 5a. Therefore, in the first region 32a, the liquid crystal molecules 2a are aligned so as to fall from the respective sides of the first pixel electrode 5a toward the center of the first pixel electrode 5a, as in the above-described embodiment.

  However, in the second region 32b, since the first voltage V1 applied to the second capacitor electrode 123 and the second voltage V2 applied to the third capacitor electrode 124 are different, the three sides of the second pixel electrode 5b A lateral electric field generated between the outer edge of each side portion of the second capacitor electrode 123 and a lateral electric field generated between the other side of the second pixel electrode 5b and the outer edge of the third capacitor electrode 124 are , Electric fields of different strengths.

  Therefore, in the liquid crystal display device of the comparative example, the liquid crystal molecules 2a in the second region 32b of each pixel 32 are disturbed in the tilting direction, and there is a difference in the light transmittance of each part of the second region 32b correspondingly. As a result, the display quality is degraded.

  Compared to the comparative example, the liquid crystal display device of the above embodiment has a third compensation capacitor Cs3 for making the voltage-transmittance characteristic of the second region 32b different from the voltage-transmittance characteristic of the first region 32a. Since the third capacitor electrode 24 is disposed so as to overlap the connection portion 18 between the second TFT 9b and the second pixel electrode 5b, the second compensation capacitor Cs2 is formed between the second TFT electrode 9b and the second pixel electrode 5b. The second capacitor electrode 23 to be formed can be formed in a continuous shape over the entire circumference of the second pixel electrode 5b.

  Therefore, the liquid crystal display device of the above embodiment has the same strength over the entire circumference of the first pixel electrode 5a between each side of the first pixel electrode 5a and the outer edge of each side of the first capacitor electrode 22. A horizontal electric field of the same length and between the sides of the second pixel electrode 5b and the outer edges of the sides of the second capacitor electrode 23 have the same strength over the entire circumference of the second pixel electrode 5b. A transverse electric field can be generated.

  Therefore, in the liquid crystal display device of the above embodiment, as shown in FIG. 17, in the first region 32 a of each pixel 32, the liquid crystal molecules 2 a extend from each side of the first pixel electrode 5 a to the first pixel electrode 5 a. While tilting toward the center, the liquid crystal molecules 2a are also tilted and oriented from each side of the second pixel electrode 5b toward the center of the second pixel electrode 5b in the second region 32b. Therefore, the display quality is not deteriorated due to the tilted alignment disorder of the liquid crystal molecules 2a as in the comparative example, and an image with good quality can be displayed.

In the liquid crystal display device of the above embodiment, the second voltage V2 applied to the third capacitor electrode 24, the high level value V1 _H and the low of the first voltage V1 applied to the first and second capacitor electrodes 22 and 23 The voltage is not limited to a voltage between the level value V1 _L and may be a DC voltage having an arbitrary value. In this case, the liquid crystal in the second region 32b is also connected to the selection periods t1, t2, t3, t4,. An effective voltage having a value different from the effective voltage of the first region 32a, which is obtained by averaging two voltage values that alternately change every time, can be applied.

  The second voltage V2 applied to the third capacitor electrode 24 is not limited to a constant level of DC voltage, but the voltage level is inverted in the same cycle as the first voltage V1, and the amplitude is the first voltage V1. It may be a rectangular wave AC voltage smaller than the amplitude of.

  FIG. 19 shows an example in which the second voltage V2 is a rectangular wave AC voltage. The second voltage V2 is a rectangular wave AC voltage having the same phase as the first voltage V1 and having an amplitude smaller than that of the first voltage V1.

  FIG. 20 shows another example in which the second voltage V2 is a rectangular wave AC voltage. The second voltage V2 is a rectangular wave AC voltage having an opposite phase to the first voltage V1 and having an amplitude smaller than that of the first voltage V1.

  Even if the second voltage V2 having any waveform in FIG. 19 or FIG. 20 is applied to the third capacitor electrode 24, the voltage between the second pixel electrode 5b and the common electrode 6 is equal to the second holding voltage Va2. The voltage can be alternately changed to a voltage stepped down. Therefore, the effective voltage having a value different from the effective voltage of the first region 32a is applied to the liquid crystal in the second region 32b of each pixel 32 during the period from the end of writing in the selection period t1 of the first row to the end of one frame. Can be applied.

[Second Example]
Next, a second embodiment of the present invention will be described with reference to FIGS. In addition, in this 2nd Example, the same code | symbol is attached | subjected to the thing corresponding to the said 1st Example, and the description is abbreviate | omitted about the same thing.

  In the second embodiment, the first TFT 9a and the second TFT 9b are composed of the same laminated film as in the first embodiment. The scanning signal line 7 is formed on the first substrate 3 and is covered with the gate insulating films 11 of the first TFT 9a and the second TFT 9b. The data signal line 8 is formed on the gate insulating film 11. Also in this second embodiment, the data signal line 8 is formed on the base layer composed of the semiconductor thin film 12 and the contact layer 14 in the laminated film constituting the first and second TFTs 9a and 9b. Yes.

  On the other hand, a first capacitor electrode 22 that forms a first compensation capacitor Cs1 between the first pixel electrode 5a and a second capacitor electrode 23 that forms a second compensation capacitor Cs2 between the second pixel electrode 5b, A third compensation capacitor Cs3 is formed between a connection portion (second pixel electrode connection portion extended from the drain electrode 16 of the second TFT 9b) 18 that electrically connects the second TFT 9b and the second pixel electrode 5b. The third capacitor electrode 24 is formed in the same shape as the first embodiment on the transparent first covering insulating film 19a provided on the gate insulating film 11 so as to cover the TFTs 9a and 9b and the data signal line 8. Has been.

  The first pixel electrode 5a and the second pixel electrode 5b are formed on a transparent second covering insulating film 19b provided on the first covering insulating film 19a so as to cover the capacitor electrodes 22, 23, 24. It is formed in the same shape as the first embodiment. In FIG. 21, the second covering insulating film 19b is omitted.

  The first covering insulating film 19a and the second covering insulating film 19b are formed in portions overlapping the first pixel electrode 5a of the first pixel electrode connecting portion 17 extended from the drain electrode 16 of the first TFT 9a. The first contact hole 20a and the second contact hole 21a formed in the portion overlapping the second pixel electrode 5b of the second pixel electrode connection portion 18 extended from the drain electrode 16 of the second TFT 9b are formed. .

  The first pixel electrode 5a is connected to the first pixel electrode connection portion 17 extended from the drain electrode 16 of the first TFT 9a in the first contact hole 20a, and the second pixel electrode 5b is connected to the second contact hole. In 21a, it is connected to the second pixel electrode connection portion 18 extended from the drain electrode 16 of the second TFT 9b.

  That is, in this second embodiment, the first dielectric layer between the first pixel electrode 5a and the first capacitor electrode 22 and the second dielectric layer between the second pixel electrode 5b and the second capacitor electrode 23 are The second covering insulating film 19b. The third dielectric layer between the second pixel electrode connecting portion 18 and the third capacitor electrode 24 is composed of the first covering insulating film 19a.

  Further, in this second embodiment, the portion of the first pixel electrode 5a that enters the first contact hole 20a (connection portion with the first pixel electrode connection portion 17) does not short-circuit with the first capacitance electrode 22. As described above, the first capacitor electrode 22 is formed in a shape in which a portion where the first contact hole 20a is formed is cut out larger than the planar shape of the first contact hole 20a. In addition, the second capacitance is set so that the portion of the second pixel electrode 5 b that has entered the second contact hole 21 a (connection portion with the second pixel electrode connection portion 18) is not short-circuited with the second capacitance electrode 23. The electrode 23 is formed in a shape in which a portion where the second contact hole 21a is formed is cut out larger than the planar shape of the second contact hole 21a.

  Further, the liquid crystal display device of the second embodiment is of a vertical alignment type, and the first alignment film 27 and the second alignment film 28 are made of a vertical alignment film. In FIG. 21, the first alignment film 27 is omitted. Further, the liquid crystal layer 2 has negative dielectric anisotropy, and when no voltage is applied between the first and second pixel electrodes 5 a and 5 b and the common electrode 6, the liquid crystal molecules 2 a are transferred to the substrate 3. The liquid crystal molecules 2a are tilted with respect to the substrates 3 and 4 by applying a voltage between the first and second pixel electrodes 5a and 5b and the common electrode 6. It consists of nematic liquid crystal.

  Also in the liquid crystal display device of the second embodiment, the first voltage V1 that is the same as the voltage applied to the common electrode 6 is applied to the first capacitor electrode 22 and the second capacitor electrode 23, and the third capacitor electrode 24 is By applying the second voltage V2 different from the one voltage V1, the variation in viewing angle can be easily corrected as in the first embodiment.

  Also in this second embodiment, the first capacitor electrode 22 is formed in a continuous shape over the entire circumference of the first pixel electrode 5a so as to overlap all sides of the first pixel electrode 5a. Since the second capacitor electrode 23 is formed in a continuous shape over the entire circumference of the second pixel electrode 5b so as to overlap all sides of the second pixel electrode 5b, The capacitance value and the capacitance value of the second compensation capacitor Cs2 can be sufficiently increased.

  Further, the third capacitor electrode 24 is formed in a shape extending in a predetermined direction (a direction parallel to the extending direction of the scanning signal line 7), and a connection portion (second TFT 9b) between the second TFT 9b and the second pixel electrode 5b. The capacitor forming portion 18a that overlaps the third capacitor electrode 24 of the second pixel electrode connecting portion 18) extended from the drain electrode 16 is formed in a long shape along the extending direction of the third capacitor electrode 24. Therefore, a sufficient capacitance value of the third compensation capacitor Cs3 can be secured. Also in this second embodiment, since the capacitance forming portion 18a is formed to have the same length as the side adjacent to the scanning signal line 7 of the second pixel electrode 5b, the capacitance of the second compensation capacitance Cs2. The value can be made sufficiently large.

  In the second embodiment, the first, second, and third capacitor electrodes 22, 23, and 24 are arranged on the same surface (on the first covering insulating film 19a). The electrodes 22, 23, and 24 can be simultaneously formed simultaneously.

  In the second embodiment, the second pixel electrode connection portion 18 is formed on the gate insulating film 11 of each TFT 9a, 9b, and covers the capacitance electrodes 22, 23, 24 and the second pixel electrode connection portion 18. The first and second pixel electrodes 5a and 5b are formed on the first covering insulating film 19b provided so as to cover the capacitor electrodes 22, 23 and 24. The first dielectric layer of the first compensation capacitor Cs1 and the second dielectric layer of the second compensation capacitor Cs2 are formed by the second coating insulating film 19b, and the third compensation capacitor Cs3 has a third dielectric layer. A dielectric layer is formed by the first covering insulating film 19a. Therefore, the first, second, and third compensation capacitors Cs1, Cs2, and Cs3 can be formed by using the steps of forming the TFTs 9a and 9b and the first and second pixel electrodes 5a and 5b.

  Further, also in the second embodiment, the outer edges of the portions of the first capacitor electrode 22 that overlap the respective sides of the first pixel electrode 5a protrude outward from the first pixel electrode 5a, respectively. The outer edge of the part which overlaps each side of 23 2nd pixel electrode 5b has protruded to the outward of said 2nd pixel electrode 5b, respectively. Therefore, a lateral electric field having the same strength is generated across the entire circumference of the first pixel electrode 5a between each side of the first pixel electrode 5a and the outer edge of each side of the first capacitance electrode 22. A lateral electric field having the same strength can be generated across the entire circumference of the second pixel electrode 5b between each side of the second pixel electrode 5b and the outer edge of each side portion of the second capacitor electrode 23.

  Accordingly, when a voltage is applied between the first pixel electrode 5a and the second pixel electrode 5b and the common electrode 6, the liquid crystal molecules 2a of the liquid crystal layer 2 in the first region 32a are transferred from each side of the first pixel electrode 5a. The liquid crystal molecules 2a of the liquid crystal layer 2 in the second region 32b are aligned so as to fall toward the center of the first pixel electrode 5a, and the liquid crystal molecules 2a of the second region 32b are directed from the sides of the second pixel electrode 5b toward the center of the second pixel electrode 5b. Since the liquid crystal molecules 2a are aligned so as to fall down, the display quality is not deteriorated due to the disorder of the falling down alignment of the liquid crystal molecules 2a, and an image of good quality can be displayed.

[Third embodiment]
The third embodiment shown in FIG. 24 is the first, second and third capacitor electrodes 22, 23, 24 (first capacitor electrode 22 and third capacitor electrode) in the liquid crystal display device of the second embodiment. 24 is not shown) is formed by a metal film 201 and a transparent conductive film 202 such as an ITO film laminated on the metal film 201.

In this embodiment, the first and second capacitor electrodes 22 and 23 have the metal film 201 overlapped with each side of the first and second pixel electrodes 5a and 5b, and the outer edges are the first and second pixel electrodes. 5a stack, formed into a shape projecting outward of 5b, the transparent conductive film 2 02 was formed thereon to a width projecting in the direction of the first and second pixel electrodes 5a, 5b over the metal film 201 It consists of a membrane. The third capacitor electrode 24 is formed of a laminated film formed of a metal film 201 and the transparent conductive film 2 02 in the same shape.

According to the third embodiment, the transparent conductive film 2 02 of the metal film 201 and the transparent conductive film 2 02 to form the first and second capacitor electrodes 22 and 23, first and second pixel electrodes Since the first and second compensation capacitors Cs1 and Cs2 having sufficient capacitance values can be formed by overlapping with 5a and 5b with a predetermined width, the first and second pixel electrodes 5a of the metal film 201 are formed. , 5b can be reduced, and the aperture ratio of the pixel 32 can be increased.

  FIG. 24 shows an example in which the capacitor electrodes 22, 23, 24 in the liquid crystal display device of the second embodiment are formed of the laminated film, but each capacitor in the liquid crystal display device of the first embodiment is shown. The electrodes 22, 23, and 24 may be formed of the laminated film.

In the third embodiment, all of the first, second, and third capacitor electrodes 22, 23, and 24 are formed of the laminated film. However, the first capacitor electrode 22 and the second capacitor electrode 23 are formed by the laminated film, a third capacitor electrode 24 may be formed of only the metal film.

[Fourth embodiment]
In the fourth embodiment shown in FIG. 25, the first capacitor electrode 22 is formed such that the vertical sides of the first capacitor electrodes 22 and 22 adjacent to each other in the extending direction of the scanning signal line 7 extend over the entire length of the vertical side. The second capacitor electrode 23 is formed so that the vertical sides of the second capacitor electrodes 23 and 23 adjacent to each other in the extending direction of the scanning signal line 7 extend over the entire length of the vertical side. It is formed in the shape connected integrally, and the other structure is the same as the said 2nd Example. The fourth embodiment is not limited to the second embodiment, but can be applied to the liquid crystal display device of the first embodiment.

[Fifth Example]
In the fifth embodiment shown in FIG. 26, the first capacitance electrode 22 of one pixel 32 and the second capacitance electrode 23 of the other pixel 32 among the pixels 32 and 32 adjacent to each other in the extending direction of the data signal line 8 Are formed in an integrally connected shape, and other configurations are the same as in the second embodiment.

  According to the fifth embodiment, the application of the first voltage V1 to the first capacitance electrode 22 of one pixel 32 and the second capacitance electrode 23 of the other pixel 32 of the adjacent pixels 32, 32 is performed at once. Can be done.

  The fifth embodiment is not limited to the second embodiment, but can be applied to the liquid crystal display device of the first embodiment. Further, in the fifth embodiment, as in the third embodiment, the vertical sides of the second capacitive electrodes 23 and 23 adjacent to each other in the extending direction of the scanning signal line 7 extend over the entire length of the vertical sides. The present invention can also be applied to the case of forming a shape that is integrally connected.

[Other embodiments]
Although the liquid crystal display devices of the above-described embodiments are of the vertical alignment type, the present invention is not limited to the vertical alignment type, but is applicable to liquid crystal display devices such as TN type, STN type, and non-twisted homogeneous alignment type. Can also be applied.

  In that case, the first and second capacitor electrodes 22 and 23 may be formed in a shape overlapping with predetermined portions of the first and second pixel electrodes 5a and 5b. In addition, it is not necessary to project outward from the second pixel electrodes 5a and 5b.

  However, in the liquid crystal display devices other than the vertical alignment type, the first and second capacitor electrodes 22 and 23 are extended over the entire circumferences of the first and second pixel electrodes 5a and 5b as in the above embodiments. It is desirable to form it in a continuous shape, and by doing so, the capacitance values of the first and second compensation capacitors Cs1, Cs2 can be made sufficiently large.

  DESCRIPTION OF SYMBOLS 1 ... Liquid crystal display element, 2 ... Liquid crystal layer, 3, 4 ... Substrate, 5a ... 1st pixel electrode, 5b ... 2nd pixel electrode, 6 ... Common electrode, 7 ... Scanning signal line, 8 ... Data signal line, 9a ... 1st TFT, 9b ... 2nd TFT, 10 ... gate electrode, 11 ... gate insulating film, 12 ... semiconductor thin film, 13 ... channel protective film, 14 ... contact layer, 15 ... source electrode, 16 ... drain electrode, 17 ... first One pixel electrode connection portion, 18 ... second pixel electrode connection portion, 18a ... capacitance forming portion, 22 ... first capacitance electrode, 23 ... second capacitance electrode, 24 ... third capacitance electrode, Cs1 ... first compensation capacitance, Cs2 ... second compensation capacitor, Cs3 ... third compensation capacitor, 19 ... covering insulating film, 19a ... first covering insulating film, 19b ... second covering insulating film, 20, 20a, 21, 21a ... contact hole, 32 ... pixel, 32a ... first region, 32b ... second region, 35 ... driving Means

Claims (13)

A first pixel electrode connected to the first thin film transistor and a second pixel electrode connected to the second thin film transistor are formed for each pixel,
The first thin film transistor and the second thin film transistor are connected to the same data signal line and scanning signal line,
A liquid crystal display device in which a liquid crystal layer is formed between the first pixel electrode and the common electrode and between the second pixel electrode and the common electrode,
A first capacitor electrode that forms a first compensation capacitor with a first dielectric layer interposed between the first pixel electrode;
A second capacitance electrode having a second dielectric layer interposed between the second pixel electrode and forming a second compensation capacitance;
A connection part for electrically connecting the second thin film transistor and the second pixel electrode;
A third capacitance electrode that forms a third compensation capacitance by interposing a third dielectric layer between the connection portion and the connection portion;
A first voltage that is the same as the voltage applied to the common electrode is applied to the first capacitor electrode and the second capacitor electrode, and a second voltage different from the first voltage is applied to the third capacitor electrode. Means to
Bei to give a,
The first, second, and third capacitor electrodes are formed on the same surface,
A liquid crystal display device characterized by the above. A first pixel electrode connected to the first thin film transistor and a second pixel electrode connected to the second thin film transistor are formed for each pixel,
The first thin film transistor and the second thin film transistor are connected to the same data signal line and scanning signal line,
A liquid crystal display device in which a liquid crystal layer is formed between the first pixel electrode and the common electrode and between the second pixel electrode and the common electrode,
A first capacitor electrode that forms a first compensation capacitor with a first dielectric layer interposed between the first pixel electrode;
A second capacitance electrode having a second dielectric layer interposed between the second pixel electrode and forming a second compensation capacitance;
A connection part for electrically connecting the second thin film transistor and the second pixel electrode;
A third capacitance electrode that forms a third compensation capacitance by interposing a third dielectric layer between the connection portion and the connection portion;
A first voltage that is the same as the voltage applied to the common electrode is applied to the first capacitor electrode and the second capacitor electrode, and a second voltage different from the first voltage is applied to the third capacitor electrode. Means to
With
The first capacitor electrode is formed in a continuous shape over the entire circumference of the first pixel electrode so as to overlap all sides of the first pixel electrode, and the second capacitor electrode is formed on the second pixel. It is formed in a continuous shape over the entire circumference of the second pixel electrode so as to overlap all sides of the electrode.
A liquid crystal display device characterized by the above. The third capacitor electrode, according to claim 1 or 2, characterized in that it is arranged so as to overlap in a portion corresponding to the region between the second pixel electrode and the scanning signal line of said connecting portion A liquid crystal display device according to 1. The third capacitor electrode, according to claim 3, characterized in that it is arranged so as to overlap in a portion corresponding to the region between the second capacitor electrode and the scanning signal line of said connecting portion Liquid crystal display device. The third capacitor electrode is formed in a shape extending in a predetermined direction, and a portion of the connection portion that overlaps the third capacitor electrode is formed in an elongated shape along the extension direction of the third capacitor electrode. The liquid crystal display device according to claim 4 . 6. The liquid crystal according to claim 5 , wherein a portion of the connection portion that overlaps the third capacitance electrode is formed to have the same length as a side of the second pixel electrode adjacent to the third capacitance electrode. Display device. The first capacitor electrode is formed in a continuous shape over the entire circumference of the first pixel electrode so as to overlap all sides of the first pixel electrode, and the second capacitor electrode is formed on the second pixel. The liquid crystal display device according to claim 1 , wherein the liquid crystal display device is formed in a continuous shape over the entire circumference of the second pixel electrode so as to overlap all sides of the electrode. The liquid crystal layer has negative dielectric anisotropy, and liquid crystal molecules are vertically aligned when no voltage is applied between the first and second pixel electrodes and the common electrode, It consists of nematic liquid crystal that is tilted and aligned by applying a voltage between the first and second pixel electrodes and the common electrode,
The first capacitor electrode is formed in a shape in which an outer edge of a portion overlapping each side of the first pixel electrode protrudes outward from the first pixel electrode, and the second capacitor electrode includes the second pixel 8. The liquid crystal display device according to claim 2, wherein an outer edge of a portion overlapping each side of the electrode is formed in a shape projecting outward from the second pixel electrode. 9. The first and second thin film transistors include a gate electrode, a gate insulating film formed so as to cover the gate electrode, a semiconductor thin film formed on the gate insulating film so as to face the gate electrode, and the semiconductor The capacitor electrode is formed on the same surface as the gate electrode forming surface, the connecting portion is formed on the gate insulating film, and includes a source electrode and a drain electrode formed on a thin film. The first and second pixel electrodes are formed on a covering insulating film provided to cover the first and second thin film transistors and the connection portion, and the first dielectric layer and the second dielectric layer are formed on the gate. made a two-layer film of the coating insulating film and the insulating film, the third dielectric layer, a liquid crystal display device according to claim 1 or 2, characterized in that it consists of the gate insulating film. The first and second thin film transistors include a gate electrode, a gate insulating film formed so as to cover the gate electrode, a semiconductor thin film formed on the gate insulating film so as to face the gate electrode, and the semiconductor It comprises a source electrode and a drain electrode formed on a thin film, the connection portion is formed on the gate insulating film, and each capacitance electrode is provided to cover the first and second thin film transistors and the connection portion. The first and second pixel electrodes are formed on a second covering insulating film provided to cover the capacitor electrodes, and the first dielectric layer and the first covering insulating film are formed on the first covering insulating film. It said second dielectric layer is made of the second coating insulating film, the third dielectric layer, a liquid crystal display device according to claim 1 or 2, characterized in that it consists of the first coating insulating film. The first capacitor electrode of one pixel and the second capacitor electrode of the other pixel, which are adjacent to each other in a direction intersecting the extending direction of the scanning signal line, are integrally formed. the liquid crystal display device according to any one of 10 claims 1 to. Wherein the first voltage is a rectangular wave AC voltage whose voltage level is inverted at a predetermined period, the second voltage is one the preceding claims, characterized in that a constant level of the DC voltage 1 1 A liquid crystal display device according to claim 1. The first voltage is a rectangular wave AC voltage whose voltage level is inverted at a predetermined cycle, and the second voltage is inverted at the same cycle as the first voltage, and the amplitude is the amplitude the liquid crystal display device according to claim 1 1 1, wherein the first is a small rectangular wave AC voltage than the amplitude of the voltage.

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