JP5459291B2 - Composite electronic components - Google Patents

Description

  The present invention relates to a composite electronic component and a manufacturing method thereof, and more particularly, to a composite electronic component configured by combining a common mode filter and an electrostatic discharge (ESD) protection element and a manufacturing method thereof.

  In recent years, standards such as USB and HDMI are widely used as high-speed signal transmission interfaces, and are used in many digital devices such as personal computers and digital high-definition televisions. Unlike the single-ended transmission method that has been common for a long time, these interfaces employ a differential signal method that transmits a differential signal (differential mode signal) using a pair of signal lines.

  The differential transmission system has an excellent feature that not only the radiation electromagnetic field generated from the signal line is small compared to the single-end transmission system, but also it is less susceptible to external noise. For this reason, it is easy to reduce the amplitude of the signal, and by shortening the rise time and the fall time due to the small amplitude, it becomes possible to perform signal transmission at a higher speed than the single-ended transmission method.

  FIG. 14 is a circuit diagram of a general differential transmission circuit.

  The differential transmission circuit shown in FIG. 14 includes a pair of signal lines 1 and 2, an output buffer 3 that supplies a differential mode signal to the signal lines 1 and 2, and an input buffer that receives a differential mode signal from the signal lines 1 and 2. 4 is provided. With this configuration, the input signal IN given to the output buffer 3 is transmitted to the input buffer 4 via the pair of signal lines 1 and 2 and reproduced as the output signal OUT. Such a differential transmission circuit has a feature that the radiated electromagnetic field generated from the signal lines 1 and 2 is small as described above, but noise (common mode noise) common to the signal lines 1 and 2 is present. When superposed, a relatively large radiated electromagnetic field is generated. In order to reduce the radiated electromagnetic field generated by the common mode noise, it is effective to insert a common mode filter (common mode choke coil) 5 in the signal lines 1 and 2 as shown in FIG.

  The common mode filter 5 has a characteristic that the impedance to the differential component (differential mode signal) transmitted through the signal lines 1 and 2 is low, and the impedance to the in-phase component (common mode noise) is high. For this reason, by inserting the common mode filter 5 into the signal lines 1 and 2, it is possible to block the common mode noise transmitted through the pair of signal lines 1 and 2 without substantially attenuating the differential mode signal.

  In the latest high-speed digital interface such as HDMI, an IC that is very sensitive to static electricity is used in order to handle a minute signal with a high transfer rate, and static electricity becomes a big problem. In order to prevent such electrostatic breakdown of the IC, it is effective to connect an ESD protection element between the signal line and the ground. Recently, the common mode filter and the ESD protection element are housed in one package. A composite electronic component has also been proposed (see Patent Document 1).

JP 2010-141642 A

  The conventional composite electronic component described in Patent Document 1 is a laminated body in which a common mode choke coil portion and an electrostatic protection portion are stacked between a pair of magnetic layers. The common mode choke coil portion is formed by laminating a non-magnetic layer and a coil conductor pattern to form a transformer. The electrostatic protection part is formed on the surface of the insulating resin layer so that the ground electrode and the discharge electrode are spaced from each other, and a voltage-dependent resistance material is formed across the ground electrode and the discharge electrode. It is. The common mode choke coil portion and the electrostatic protection portion are connected via an external electrode surface plated on the outer peripheral surface of the laminate.

  However, conduction failure may occur on the external electrode surface due to wear during solder connection, scratches on the electrode surface, or the like. Further, since the tin plating layer on the surface of the external electrode has a relatively high resistance, there is a problem that the electrostatic absorption performance is deteriorated.

  The present invention has been made to solve the above-described problems, and an object of the present invention is a composite electronic component capable of preventing poor connection between a common mode filter and an ESD protection element and improving electrostatic absorption performance. And a manufacturing method thereof.

  In order to solve the above problems, a composite electronic component according to the present invention includes a substrate, a functional layer provided on the substrate, and a plurality of external terminal electrodes electrically connected to the functional layer, The layer includes a planar coil layer including a planar coil pattern and an ESD protection layer including an ESD protection element, and the ESD protection layer includes a gap electrode including a terminal electrode portion and a ground electrode portion facing each other through a gap. And an electrostatic absorption layer formed on the gap electrode, an inorganic insulating layer covering the gap electrode through the electrostatic absorption layer, and a plating electrode formed on the surface of the terminal electrode portion of the gap electrode Including a terminal electrode contact and a ground contact made of a plating electrode formed on a surface of the ground electrode portion of the gap electrode, wherein the electrostatic absorption layer is insulated A composite in which a conductive inorganic material is dispersed in a matrix of an inorganic material, and the terminal electrode contact and the ground contact penetrate through the inorganic insulating layer and are selected from the plurality of external terminal electrodes. It is electrically connected to each external terminal electrode.

  According to the present invention, a contact penetrating the inorganic insulating layer of the ESD protective layer can be easily formed. Thereby, it is not necessary to connect the common mode filter and the ESD protection element via the electrode surface plated on the side surface of the chip, and the reliability of electrical connection between them can be improved.

  In order to solve the above problems, a method for manufacturing a composite electronic component according to the present invention includes a step of forming a functional layer on a substrate and a step of forming an external terminal electrode electrically connected to the functional layer. The step of forming the functional layer includes a step of forming a planar coil layer including a planar coil pattern and a step of forming an ESD protective layer including an ESD protection element, and the step of forming the ESD protective layer includes a gap A step of forming a gap electrode including a terminal electrode portion and a ground electrode portion that are opposed to each other via a gap, a step of forming an electrostatic absorption layer on the gap electrode, and the terminal electrode portion and the ground electrode of the gap electrode Forming the terminal electrode contact and the ground contact made of a plating electrode on the surface of the part, and the gap through the electrostatic absorption layer. A step of forming an inorganic insulating layer covering the electrode; and a step of planarizing a surface of the inorganic insulating layer by grinding or polishing to expose an upper end of the terminal electrode contact and an upper end of the ground contact, respectively. To do.

  According to the present invention, it is possible to easily form a contact penetrating the inorganic insulating layer without drilling the inorganic insulating layer of the ESD protective layer. Thereby, it is not necessary to connect the common mode filter and the ESD protection element via the electrode surface plated on the side surface of the chip, and the reliability of electrical connection between them can be improved.

  In the present invention, the ESD protective layer preferably includes a loop-shaped ground pattern including the ground electrode portion of the gap electrode. According to this configuration, it is possible to have a plurality of electrical connection paths with the ground contact (ground external electrode). Therefore, even if one part of the path connecting the ground electrode portions is cut, the ground function can be secured through another path.

  In the present invention, it is preferable that the planar coil layer is provided on a surface of the substrate, and the ESD protection layer is provided on an upper layer of the planar coil layer. According to this configuration, since the inorganic insulating layer is interposed between the planar coil layer and the ESD protective layer, it is possible to prevent damage to the common mode filter due to electrostatic breakdown of the ESD protective layer without providing a special layer. Can do. According to the present invention, even when such an inorganic insulating layer exists, the common mode filter and the ESD protection element do not have to be connected via the electrode surface plated on the side surface of the chip. It is possible to improve the reliability of electrical connection between the two.

  In the present invention, the spiral conductor includes first and second spiral conductors magnetically coupled to each other, the gap electrode includes first to fourth gap electrodes, and the terminal electrode contact includes first to second. 4 terminal electrode contacts, wherein the first terminal electrode contact is electrically connected to an inner peripheral end of the first spiral conductor, and the second terminal electrode contact is connected to the first spiral conductor. The third terminal electrode contact is electrically connected to the outer peripheral end of the conductor, the third terminal electrode contact is electrically connected to the inner peripheral end of the second spiral conductor, and the fourth terminal electrode contact is It is preferable that the second spiral conductor is electrically connected to the outer peripheral end.

  In the present invention, the external terminal electrode includes first to fourth external terminal electrodes, and the first to fourth terminal electrode contacts are electrically connected to the first to fourth external terminal electrodes, respectively. It is preferable that In this case, the external terminal electrode further includes fifth and sixth external terminal electrodes, the ground contact includes first to fourth ground contacts, and the first and second ground contacts include Preferably, the third external terminal electrode is connected to the fifth external terminal electrode, and the third and fourth ground contacts are connected to the sixth external terminal electrode.

  In the present invention, the planar coil layer includes first and second lead conductors connected to inner peripheral ends of the first and second spiral conductors, respectively, and the first lead conductors via the first lead conductors. A first terminal electrode connected to the inner peripheral end of the spiral conductor, connected to the first external terminal electrode, and an outer peripheral end of the first spiral conductor, and the second external electrode A second terminal electrode connected to the terminal electrode and a second terminal electrode connected to the inner peripheral end of the second spiral conductor via the second lead conductor and connected to the third external terminal electrode 3, and a fourth terminal electrode connected to the outer peripheral end of the second spiral conductor and connected to the fourth external terminal electrode, the first to fourth terminal electrodes The contacts are the first to fourth contacts It is preferably connected respectively to the child electrodes.

  In the present invention, the planar coil layer further includes first to third insulating layers, and each of the first to fourth terminal electrodes includes a laminate including at least the first to third insulating layers. It is preferable to be provided so as to penetrate. In this case, the first spiral conductor is formed on the surface of the first insulating layer, and the second spiral conductor is formed on the surface of the second insulating layer, and The first and second lead conductors are formed on the surface of the third insulating layer, and an inner peripheral end of the first spiral conductor passes through the second and third insulating layers. An inner peripheral end of the second spiral conductor is connected to the first lead conductor via a contact hole conductor, and the second spiral conductor penetrates the third insulating layer to pass through the second contact hole conductor. It is preferable to be connected to two lead conductors.

  In the present invention, the planar coil layer further includes first and second ground patterns formed on a surface of the third insulating layer, and the first and second ground contacts are the first ground. The third and fourth ground contacts are connected to the sixth external terminal electrode via the second ground pattern, and are connected to the fifth external terminal electrode via a pattern. Preferably it is.

  In the present invention, the external terminal electrode is preferably a bump electrode provided on a surface of the functional layer. In this case, it is preferable that a part of the bump electrode overlaps the spiral conductor in plan view. By using bump electrodes made of thick plating electrodes as external terminal electrodes, the step of forming external electrode surfaces on the side surfaces and upper and lower surfaces of the chip component can be omitted, and external electrodes can be formed easily and with high accuracy. be able to. In addition, since a part of the bump electrode overlaps the spiral conductor in plan view, it is possible to provide a bump electrode having a wide electrode surface while ensuring a desired loop size of the spiral conductor. Miniaturization can be achieved.

  In the present invention, the planar coil layer further includes a ground pattern provided closer to the external terminal electrode than the planar coil pattern, and the planar coil layer includes the plurality of external terminal electrodes and the ESD protection layer. And at least a part of the ground contact is provided at a position outside the spiral conductor and not overlapping in plan view, and the ground electrode portion is interposed between the ground contact and the ground pattern. It is preferable to be connected to the external terminal electrode. According to this configuration, even if the ground electrode portion of the gap electrode and the external terminal electrode have different positions in the planar direction, the plating electrode is directly raised from the ground electrode portion and externally formed on the upper layer of the planar coil pattern such as a spiral conductor. It can be connected to a terminal electrode. Therefore, the ground electrode portion and the plating electrode can be arranged at optimum positions without being restricted by the formation region of the spiral conductor. In particular, even when a bump electrode is used as the external terminal electrode and a part of the bump electrode overlaps the spiral conductor in plan view, the ground electrode portion and the bump electrode are connected without being restricted by the positional relationship between them. Can be connected easily.

  In the present invention, it is preferable that the planar coil pattern is a circular spiral conductor, and the ground contact has a portion overlapping with an arc-shaped corner portion of the circular spiral conductor in a plan view. According to this configuration, the ground contact can be efficiently laid out while ensuring a sufficient loop size of the spiral conductor.

  ADVANTAGE OF THE INVENTION According to this invention, the composite electronic component which can prevent the poor connection of a common mode filter and an ESD protection element, and can improve electrostatic absorption performance, and its manufacturing method can be provided.

FIG. 1 is a schematic perspective view showing an external configuration of a composite electronic component 100 according to the first embodiment of the present invention. FIG. 2 is a circuit diagram illustrating a configuration of the composite electronic component 100. FIG. 3 is a schematic exploded perspective view showing an example of the layer structure of the composite electronic component 100 in detail. FIG. 4 is a schematic plan view showing the configuration of the conductor pattern including the gap electrodes 34A to 34D. FIG. 5 is a schematic plan view showing the positional relationship between the components of the ESD protection layer 12B and the spiral conductors 20 and 21. As shown in FIG. FIG. 6 is a schematic cross-sectional view partially showing a structure in the vicinity of the gap electrode 34 </ b> A of the composite electronic component 100. 7A and 7B are diagrams illustrating an example of a layer structure in the vicinity of the first gap electrode 34A in the ESD protective layer 12B, where FIG. 7A is a schematic plan view and FIG. 7B is a schematic cross-sectional view. FIG. 8 is a schematic diagram for explaining the principle of the ESD protection element. FIG. 9 is a flowchart illustrating an example of a manufacturing process of the composite electronic component 100. FIG. 10 is a schematic cross-sectional view showing a part of the manufacturing process of the composite electronic component 100. FIG. 11 is a schematic cross-sectional view showing another example of the method for forming the terminal electrode contact 39 and the ground contact 40 that penetrates the inorganic insulating layer 36. FIG. 12 is a schematic exploded perspective view showing in detail the layer structure of the composite electronic component 200 according to the second embodiment of the present invention. FIG. 13 is a schematic cross-sectional view showing the configuration of the composite electronic component 200. FIG. 14 is a circuit diagram of a general differential transmission circuit.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

  FIG. 1 is a schematic perspective view showing an external configuration of a composite electronic component 100 according to the first embodiment of the present invention.

  As shown in FIG. 1, the composite electronic component 100 includes a substrate 11, a functional layer 12 provided on one main surface of the substrate 11, and six bump electrodes 13 a to 13 f provided on the main surface of the functional layer 12. And a magnetic resin layer 14 provided on the main surface of the functional layer 12 excluding the formation positions of the bump electrodes 13a to 13f.

  The composite electronic component 100 is a substantially rectangular parallelepiped surface-mounted chip component, and has an upper surface 10a, a bottom surface 10b, and four side surfaces 10c to 10f (outer peripheral surface). The composite electronic component 100 in FIG. 1 has a bottom surface 10b (mounting surface) facing upward, and is flipped up and down during actual mounting and is used with the bump electrodes 13a to 13f facing downward.

  The substrate 11 secures the mechanical strength of the composite electronic component 100 and, when a magnetic material is used, serves as a closed magnetic path for the composite electronic component. Sintered ferrite is preferably used as the material of the substrate 11, but other ceramic materials such as forsterite can also be used. Although not particularly limited, when the chip size is 0.9 × 0.7 × 0.4 (mm), the thickness of the substrate 11 can be about 0.25 to 0.3 mm.

  The functional layer 12 is a layer including a common mode filter and an ESD protection element, and is provided between the substrate 11 and the magnetic resin layer 14. Although details will be described later, the common mode filter has a multilayer structure formed by alternately laminating insulating layers and conductor patterns. As described above, the composite electronic component 100 according to the present embodiment includes a so-called thin film type common mode filter, and is distinguished from a winding type having a structure in which a conducting wire is wound around a magnetic core. is there.

  The first to sixth bump electrodes 13a to 13f are external terminal electrodes of the common mode filter element, and are formed so as to have an exposed surface not only from the upper surface 10a of the multilayer body but also from the outer peripheral surface. Among these, the two bump electrodes 13a and 13c are exposed from the first side face 10c parallel to the longitudinal direction of the laminate including the substrate 11, the functional layer 12, and the magnetic resin layer 14, and the other two bump electrodes. 13b and 13d are exposed from the second side face 10d facing the first side face 10c. Further, the fifth bump electrode 13e is exposed from the third side face 10e orthogonal to the first and second side faces 10c, 10d, and the sixth bump electrode 13f is a fourth face facing the third side face 10e. It is exposed from the side surface 10f.

  In the present specification, the “bump electrode” is a thick film plating electrode formed by a plating process, different from the one formed by thermocompression bonding of metal balls such as Cu and Au using a flip chip bonder. Means. Although not particularly limited, Cu is preferably used as a material for the bump electrode. The thickness of the bump electrode is equal to or greater than the thickness of the magnetic resin layer 14 and can be about 0.08 to 0.1 mm. That is, the bump electrodes 13 a to 13 f are thicker than the conductor pattern in the functional layer 12, and in particular, have a thickness five times or more that of the conductor pattern in the functional layer 12.

  The magnetic resin layer 14 is a layer that constitutes the mounting surface (bottom surface) of the composite electronic component 100, and protects the functional layer 12 together with the substrate 11 and plays a role as a closed magnetic circuit of the coil that constitutes the common mode filter. It is. However, since the mechanical strength of the magnetic resin layer 14 is smaller than that of the substrate 11, it has an auxiliary role in terms of strength. The magnetic resin layer 14 is provided so as to fill the periphery of the bump electrodes 13a to 13f. As the magnetic resin layer 14, an epoxy resin (composite ferrite) containing ferrite powder can be used. Although not particularly limited, when the chip size is 0.9 × 0.7 × 0.4 (mm), the thickness of the magnetic resin layer 14 may be about 0.08 to 0.13 mm. it can.

  FIG. 2 is a circuit diagram illustrating a configuration of the composite electronic component 100.

  As shown in FIG. 2, the composite electronic component 100 includes a common mode filter 15 including first and second inductor elements 15a and 15b, and ESD protection elements 16a to 16d, and includes the inductor elements 15a and 15b. One end is connected to the first and third terminal electrodes 17a and 17c, and the other end is connected to the second and fourth terminal electrodes 17b and 17d. One end of each of the ESD protection elements 16a and 16b is connected to the first and second terminal electrodes 17a and 17b, respectively, and the other end is connected to the fifth terminal electrode 17e. One ends of the ESD protection elements 16c and 16d are connected to the third and fourth terminal electrodes 17c and 17d, respectively, and the other ends are connected to the sixth terminal electrode 17f. That is, the fifth terminal electrode 17e is a terminal electrode common to the ESD protection elements 16a and 16b, and the sixth terminal electrode 17f is a terminal electrode common to the ESD protection elements 16c and 16d. The first to sixth terminal electrodes 17a to 17f correspond to the first to sixth bump electrodes 13a to 13f in FIG. 1, respectively.

  The composite electronic component 100 is mounted on a pair of signal lines. At this time, the first and third terminal electrodes 17a and 17c are connected to the input side of the signal line, and the second and fourth terminal electrodes 17b and 17d. Is connected to the output side of the signal line. The fifth and sixth terminal electrodes 17e and 17f are connected to the ground line. Since the composite electronic component 100 according to this embodiment is a symmetrical circuit in which a pair of ESD protection elements are provided on both the input side and the output side, the first and third terminal electrodes 17a and 17c are connected to the signal line. The circuit configuration is the same whether it is connected to the input side or the output side.

  FIG. 3 is a schematic exploded perspective view showing the layer structure of the composite electronic component 100 in detail.

  As shown in FIG. 3, the composite electronic component 100 includes a functional layer 12 sandwiched between a substrate 11 and a magnetic resin layer 14, and the functional layer 12 is formed by a common mode filter layer 12A and an ESD protective layer 12B. It is configured. In the present embodiment, the ESD protection layer 12B is first formed on the surface of the substrate 11, and the common mode filter layer 12A is formed thereon. However, these layers may be stacked in reverse order as described later.

  The common mode filter layer 12A includes four insulating layers 19a to 19d stacked in order from the substrate 11 side to the magnetic resin layer 14 side, and a first spiral conductor 20 formed on the surface of the first insulating layer 19a. A second spiral conductor 21 formed on the surface of the second insulating layer 19b, first and second lead conductors 22 and 23 and a ground pattern 24 formed on the surface of the third insulating layer 19c, 25.

  The insulating layers 19a to 19d serve to insulate and separate the conductor patterns and ensure the flatness of the base surface on which the conductor patterns are formed. As a material of the insulating layers 19a to 19d, it is preferable to use a resin that is excellent in electrical and magnetic insulation and has good workability, and it is preferable to use a polyimide resin or an epoxy resin. As the conductor pattern, it is preferable to use Cu, Al or the like excellent in conductivity and workability. The conductor pattern can be formed by an etching method using photolithography or an additive method (plating).

  An opening 26 penetrating the insulating layers 19a to 19d is formed in the central region of the insulating layers 19a to 19d and inside the first and second spiral conductors 20 and 21, and inside the opening 26, A magnetic core 27 for forming a magnetic path is provided. As the material of the magnetic core 27, it is preferable to use a magnetic powder-containing resin (composite ferrite). The magnetic core 27 is preferably formed simultaneously and integrally with the magnetic resin layer 14 made of the same material.

  Four penetrations penetrating the first to third insulating layers 19a to 19c are provided on the outer periphery of the first to third insulating layers 19a to 19c and below the first to fourth bump electrodes 13a to 13d. Holes are formed, and the first to fourth terminal electrodes 28a to 28d are formed by embedding a part of the conductor pattern inside each through hole. The end surfaces of the first to fourth terminal electrodes 28a to 28d are exposed on the outer peripheral surface of the multilayer body.

  Furthermore, on the outer peripheral portion of the fourth insulating layer 19d and below the first to sixth bump electrodes 13a to 13f, six through holes penetrating the fourth insulating layer 19d are formed, respectively. The first to sixth terminal electrodes 28a to 28f are formed by embedding a part of the conductor pattern inside each through hole. End surfaces of the first to sixth terminal electrodes 28a to 28f are exposed on the outer peripheral surface of the multilayer body. These terminal electrodes 28a to 28f can be part of the bump electrodes 13a to 13f by being formed simultaneously with the bump electrodes 13a to 13f.

  The first to sixth bump electrodes 13a to 13f are connected to corresponding terminal electrodes 28a to 28f of the common mode filter layer 12A, respectively. Therefore, each terminal electrode 28a-28f can be regarded as a part of corresponding bump electrode 13a-13f, and, thereby, the exposed area of the side surface of bump electrode 13a-13f can be expanded.

  The first spiral conductor 20 corresponds to the inductor element 15a shown in FIG. The inner peripheral end of the first spiral conductor 20 is connected to the first terminal electrode 28a via the first contact hole conductor 29 and the first lead conductor 22 that penetrate the insulating layers 19b and 19c. Further, the outer peripheral end of the first spiral conductor 20 is connected to the second terminal electrode 28b via the lead portion 20a.

  The second spiral conductor 21 corresponds to the inductor element 15b shown in FIG. The inner peripheral end of the second spiral conductor 21 is connected to the third terminal electrode 28 c through a second contact hole conductor 30 and a second lead conductor 23 that penetrate the insulating layer 19 c. The outer peripheral end of the second spiral conductor 21 is connected to the fourth terminal electrode 28d through the lead portion 21a.

  The first and second spiral conductors 20 and 21 have the same planar shape, and are provided at the same position in plan view. Since the first and second spiral conductors 20 and 21 overlap each other, a strong magnetic coupling is generated between them. With the above configuration, the conductor pattern in the common mode filter layer 12A constitutes a common mode filter.

  Both the first and second spiral conductors 20 and 21 are oval spiral patterns. A circular or oval spiral pattern can be preferably used as a high-frequency inductance because of its low attenuation characteristics at high frequencies.

  4 which penetrates the first to third insulating layers 19a to 19c in the vicinity of the corners of the first to third insulating layers 19a to 19c and outside the first and second spiral conductors 20 and 21. Four through-holes are formed, and four ground contacts 31a to 31d are formed by embedding a part of the conductor pattern inside each through-hole.

  These ground contacts 31a to 31d are located immediately above each ground contact 40 of the ESD protection layer 12B described later, and their lower ends are connected to the upper ends of the ground contacts 40 on the ESD protection layer 12B side. Furthermore, the upper ends of the first and second ground contacts 31a and 31b are connected to the fifth terminal electrode 28e via the ground pattern 24, and the upper ends of the third and fourth ground contacts 31c and 31d are The ground terminal 25 is connected to the sixth terminal electrode 28f.

  The above is the description of the common mode filter layer 12A. Next, the ESD protective layer 12B will be described.

  The ESD protection layer 12B includes a base insulating layer 33, an electrode layer 34 including first to fourth gap electrodes 34A to 34D formed on the surface of the base insulating layer 33, and first to fourth gap electrodes 34A to 34A. The electrostatic absorption layer 35 formed in the gap region 34D, and the inorganic insulating layer 36 covering the entire surface of the base insulating layer 33 on which the gap electrodes 34A to 34D and the electrostatic absorption layer 35 are formed.

  The number of gap electrodes is four, which matches the number of input / output terminals of the common mode filter 15. That is, the gap electrode is provided at each input / output terminal of the common mode filter 15 which is a four-terminal circuit. The two gap electrodes 34A and 34C are provided on one side of two sides parallel to the longitudinal direction of the substrate 11, and the other two gap electrodes 34B and 34D are provided on the other side.

  The layer structure in the vicinity of the gap portion of the first to fourth gap electrodes 34A to 34D is a portion that functions as the first to fourth ESD protection elements 16a to 16d shown in FIG. Each of the first to fourth gap electrodes 34A to 34D is composed of a combination of a terminal electrode portion 37 provided on the outer peripheral side and a ground electrode portion 38 provided on the inner side, and the terminal electrode portion 37 and the ground electrode The part 38 constitutes parallel electrodes facing each other through a gap.

  A terminal electrode contact 39 made of a plating electrode that penetrates the inorganic insulating layer 36 is formed on the surface of the terminal electrode portion 37 of each gap electrode 34 </ b> A to 34 </ b> D. The terminal electrode portions 37 of the gap electrodes 34A to 34D are connected to the first to fourth terminal electrodes 28a to 28d on the common mode filter layer 12A side through corresponding terminal electrode contacts 39, respectively. The first to fourth bump electrodes 13a to 13d are electrically connected to the first spiral conductor 20 or the second spiral conductor 21 through the first to fourth terminal electrodes 28a to 28d, respectively. Connected.

  A ground contact 40 made of a plating electrode that penetrates the inorganic insulating layer 36 is formed on the surface of the ground electrode portion 38 of each gap electrode 34 </ b> A to 34 </ b> D. The ground electrode portions 38 of the gap electrodes 34A to 34D are connected to the ground contacts 31a to 31d on the common mode filter layer 12A side via the corresponding ground contacts 40. Further, the ground contacts 31a to 31d and the first and It is electrically connected to the fifth or sixth bump electrode 13e, 13f via the second ground pattern 24, 25.

  FIG. 4 is a schematic plan view showing the configuration of the conductor pattern including the gap electrodes 34A to 34D.

  As shown in FIG. 4, a wiring pattern 38 a is formed on the surface of the base insulating layer 33 together with the terminal electrode portion 37 and the ground electrode portion 38 of each gap electrode 34 </ b> A to 34 </ b> D. The four ground electrode portions 38 are electrically connected to each other via the wiring pattern 38a, whereby the ground electrode portion 38 and the wiring pattern 38a constitute one loop pattern. When the entire ground pattern including each ground electrode portion 38 is formed in such a loop shape, it is possible to have a plurality of electrical connection paths to the ground contact (ground external electrode). Therefore, for example, even when the connection between the bump electrode 13e and the ground line is broken, the four ground electrode portions 38 can secure the ground connection through the path on the bump electrode 13f side. .

  Further, the ground electrode portion 38 and the wiring pattern 38a forming the loop pattern do not have a portion overlapping the magnetic core 27 in plan view. That is, since the ground electrode portion 38 and the wiring pattern 38a are provided at positions avoiding the magnetic core 27 (under the magnetic path passage region), the generation of eddy currents can be prevented and the common mode is resistant to noise. A filter can be realized.

  FIG. 5 is a schematic plan view showing the positional relationship between the components of the ESD protection layer 12B and the spiral conductors 20 and 21. As shown in FIG.

  As shown in FIG. 5, most of the ground electrode portions 38 of the first to fourth gap electrodes 34 </ b> A to 34 </ b> D are disposed outside the first and second spiral conductors 20 and 21. Accordingly, the ground contact 40 is also arranged outside the first and second spiral conductors 20 and 21 so as not to substantially overlap with the first and second spiral conductors 20 and 21 in plan view. Has been. Therefore, the ground contacts 31a to 31d can be pulled straight up from the position of each ground contact 40 to above the insulating layer 19c of the common mode filter layer 12A without being obstructed by the first and second spiral conductors 20 and 21. The first and second ground patterns 24 and 25 can be connected to the fifth or sixth bump electrodes 13e and 13f.

  Each of the bump electrodes 13a to 13f has a portion overlapping the spiral conductors 20 and 21 in plan view. According to this configuration, it is possible to provide the bump electrode having a wide electrode surface while ensuring a desired loop size of the spiral conductors 20 and 21, thereby reducing the size of the chip component.

  FIG. 6 is a schematic cross-sectional view partially showing a structure in the vicinity of the gap electrode 34 </ b> A of the composite electronic component 100. Since the structure in the vicinity of the other gap electrodes 34B to 34D is basically the same as that of the bump electrode 13a, the description thereof is omitted.

  As shown in FIG. 6, a terminal electrode contact 39 penetrating the inorganic insulating layer 36 is formed on the terminal electrode portion 37 of the gap electrode 34A, and a terminal electrode 28a is provided thereabove. Therefore, the terminal electrode portion 37 of the ESD protection layer 12B is connected to the bump electrode 13a via the terminal electrode contact 39 and the terminal electrode 28a.

  A ground contact 40 penetrating the inorganic insulating layer 36 is formed on the ground electrode portion 38 of the gap electrode 34A, and a ground contact 31a is provided thereabove. Therefore, the ground electrode portion 38 of the ESD protection layer 12B is connected to the bump electrode 13e via the ground contact 40, the ground contact 31a, and the ground pattern 24.

  As described above, in the present embodiment, the ESD protection layer 12B and the common mode filter layer 12A are electrically connected using the terminal electrode contact 39 and the ground contact 40 made of a plating electrode that penetrates the inorganic insulating layer 36 of the ESD protection layer 12B. Thus, the connection failure and the deterioration of the electrostatic absorption performance do not occur unlike the conventional external terminal electrode. Therefore, a composite electronic component having high connection reliability between the common mode filter 15 and the ESD protection elements 16a to 16d can be realized.

  7A and 7B are diagrams showing an example of the layer structure in the vicinity of the first gap electrode 34A in the ESD protective layer 12B, where FIG. 7A is a schematic plan view and FIG. 7B is a schematic cross-sectional view. The configuration of the second to fourth gap electrodes 34B to 34D is the same as that of the first gap electrode 34A.

  The ESD protection layer 12B includes a base insulating layer 33 formed on the surface of the substrate 11, a pair of electrodes 41a and 41b constituting the gap electrodes 34A to 34D, and static electricity disposed between the electrodes 41a and 41b. An absorption layer 35 and an inorganic insulating layer 36 formed on the upper surface of the electrostatic absorption layer 35 are provided. In the ESD protection layer 12B, the electrostatic absorption layer 35 functions as a low voltage discharge type electrostatic protection material. When an overvoltage such as static electricity is applied, the electrostatic absorption layer 35 is initially connected between the electrodes 41a and 41b via the electrostatic absorption layer 35. Designed to ensure electrical discharge.

  The base insulating layer 33 is made of an insulating material, and covers the entire surface of the substrate 11 in the present embodiment for ease of manufacturing. It is not always necessary to cover the entire surface.

  As a specific example of the base insulating layer 33, for example, the surface of the first substrate 11 is made of a low dielectric constant material having a dielectric constant of 50 or less, preferably 20 or less, such as NiZn ferrite, alumina, silica, magnesia, and aluminum nitride. What formed the insulating film which becomes can be used suitably. The formation method of the base insulating layer 33 is not particularly limited, and a known method such as a vacuum evaporation method, a reactive evaporation method, a sputtering method, an ion plating method, a vapor phase method such as CVD or PVD can be applied. The film thickness of the base insulating layer 33 can be set as appropriate.

  On the surface of the base insulating layer 33, a pair of electrodes 41a and 41b are disposed apart from each other. The pair of electrodes 41a and 41b correspond to the terminal electrode portion 37 and the ground electrode portion 38 in FIG. In the present embodiment, the pair of electrodes 41 a and 41 b are arranged to face each other with a gap distance ΔG at a predetermined position on the base insulating layer 33.

  Examples of the material constituting the electrodes 41a and 41b include at least one metal selected from Ni, Cr, Al, Pd, Ti, Cu, Ag, Au, Pt, and the like, or alloys thereof. However, it is not particularly limited to these. In the present embodiment, the electrodes 41a and 41b are formed in a rectangular shape in plan view, but the shape is not particularly limited, and may be formed in a comb shape or a saw shape, for example. .

  The gap distance ΔG between the electrodes 41a and 41b may be appropriately set in consideration of desired discharge characteristics, and is not particularly limited, but is usually about 0.1 to 50 μm and ensures low voltage initial discharge. From the viewpoint, it is more preferably about 0.1 to 20 μm, and further preferably about 0.1 to 10 μm. The thickness of the electrodes 41a and 41b can be appropriately set and is not particularly limited, but is usually about 0.05 to 10 μm.

  An electrostatic absorption layer 35 is disposed between the electrodes 41a and 41b. In the present embodiment, the electrostatic absorption layer 35 is laminated on the surface of the base insulating layer 33 and the electrodes 41a and 41b described above. The dimension and shape of the electrostatic absorption layer 35 and the position of the electrostatic absorption layer 35 are not particularly limited as long as the electrostatic discharge layer 35 is designed so as to ensure initial discharge between the electrodes 41a and 41b through itself when an overvoltage is applied.

  The electrostatic absorption layer 35 is a sea-island structure composite in which aggregates of island-shaped conductive inorganic materials 43 are dispersed in a planar and discontinuous manner in a matrix of an insulating inorganic material 42. In the present embodiment, the electrostatic absorption layer 35 is formed by performing sequential sputtering. More specifically, the conductive inorganic material 43 is sputtered partially (incompletely) on the insulating surface of the base insulating layer 33 and / or on the electrodes 41a and 41b, and then the insulating property continues. By sputtering the inorganic material 42, a composite of a so-called laminated structure of a layer of the conductive inorganic material 43 scattered in an island shape and a layer of the insulating inorganic material 42 covering this is formed.

Specific examples of the insulating inorganic material 42 constituting the matrix include, but are not limited to, metal oxides and metal nitrides. In consideration of insulation and cost, Al ₂ O ₃ , TiO ₂ , SiO ₂ , ZnO, In ₂ O ₃ , NiO, CoO, SnO ₂ , V ₂ O ₅ , CuO, MgO, ZrO ₂ , AlN, BN and SiC is preferred. These may be used alone or in combination of two or more. Among these, it is more preferable to use Al ₂ O ₃ , SiO ₂ or the like from the viewpoint of imparting a high degree of insulation to the insulating matrix. On the other hand, from the viewpoint of imparting semiconductivity to the insulating matrix, it is more preferable to use TiO ₂ or ZnO. By imparting semiconductivity to the insulating matrix, an ESD protection element having excellent discharge start voltage and clamp voltage can be obtained. The method for imparting semiconductivity to the insulating matrix is not particularly limited. For example, these TiO ₂ and ZnO may be used alone, or these may be used in combination with other insulating inorganic materials 42. In particular, TiO ₂ tends to lose oxygen during sputtering in an argon atmosphere and tends to have high electrical conductivity. Therefore, it is particularly preferable to use TiO ₂ to impart semiconductivity to the insulating matrix. . The insulating inorganic material 42 functions as a protective layer that protects the pair of electrodes 41 a and 41 b and the conductive inorganic material 43 from an arbitrary upper layer (for example, the insulating layer 19 a) together with the inorganic insulating layer 36. is there.

  The insulating inorganic material 42 is preferably the same material as the inorganic insulating layer 36, and is preferably formed simultaneously and integrally with the inorganic insulating layer 36. When the insulating inorganic material 42 is formed as a part of the inorganic insulating layer 36, the manufacturing process can be simplified.

  Specific examples of the conductive inorganic material 43 include, but are not limited to, metals, alloys, metal oxides, metal nitrides, metal carbides, metal borides, and the like. In consideration of conductivity, C, Ni, Cu, Au, Ti, Cr, Ag, Pd and Pt, or an alloy thereof is preferable.

As a combination of the electrodes 41a and 41b, the insulating inorganic material 42, and the conductive inorganic material 43, a combination of Cu, SiO ₂ and Au is particularly preferable. An ESD protection element made of these materials is not only excellent in electrical characteristics but also extremely advantageous in terms of workability and cost. In particular, a sea-island structure composite in which aggregates of island-like conductive inorganic materials 43 are discontinuously scattered can be formed with high accuracy and easily.

  The total thickness of the electrostatic absorption layer 35 is not particularly limited and can be set as appropriate. However, from the viewpoint of achieving further thinning, the thickness is preferably 10 nm to 10 μm, and 15 nm to 1 μm. Is more preferable, and it is more preferable that it is 15-500 nm. When the so-called so-called island-like layers of the conductive inorganic material 43 and the matrix layer of the insulating inorganic material 42 are formed as in this embodiment, the thickness of the layer of the conductive inorganic material 43 is formed. Is preferably 1 to 10 nm, and the thickness of the layer of the insulating inorganic material 42 is preferably 10 nm to 10 μm, more preferably 10 nm to 1 μm, and more preferably 10 to 500 nm.

  The method for forming the electrostatic absorption layer 35 is not limited to the sputtering method described above. By applying a known thin film forming method to the insulating surface of the base insulating layer 33 and / or the electrodes 41a and 41b, the insulating inorganic material 42 and the conductive inorganic material 43 described above are applied, thereby absorbing static electricity. Layer 35 can be formed.

  In the ESD protection layer 12B of the present embodiment, the electrostatic absorption layer 35 including the island-shaped conductive inorganic material 43 that is discontinuously scattered in the matrix of the insulating inorganic material 42 is a low-voltage discharge type electrostatic protection material. Function as. By adopting such a configuration, a high-performance ESD protection element having a small capacitance, a low discharge start voltage, and excellent discharge resistance is realized. Moreover, a composite composed of at least an insulating inorganic material 42 and a conductive inorganic material 43 is employed as the electrostatic absorption layer 35 that functions as a low-voltage discharge type electrostatic protection material. For this reason, the heat resistance is improved as compared with the conventional organic-inorganic composite film, and the characteristics hardly change depending on the external environment such as temperature and humidity. As a result, the reliability is improved. Furthermore, the electrostatic absorption layer 35 can be formed by a sputtering method, thereby further improving productivity and economy. In the ESD protection element of this embodiment, as a result of applying part of the electrodes 41a and 41b into the electrostatic absorption layer 35 by applying a voltage between the electrodes 41a and 41b, the electrostatic absorption layer 35 becomes the electrodes 41a and 41b. The structure which contains the raw material which comprises may be sufficient.

  FIG. 8 is a schematic diagram for explaining the principle of the ESD protection element.

  As shown in FIG. 8, when a discharge voltage due to static electricity is applied between the pair of electrodes 41a and 41b, the discharge current is scattered discontinuously in the matrix of the insulating inorganic material 42 as shown by the arrows. It flows from the electrode 41a toward the electrode 41b (ground) through an arbitrary path constituted by the island-shaped conductive inorganic material 43. At this time, the conductive inorganic material 43 at the point where the energy concentration in the current path is large is destroyed together with the insulating inorganic material 42, and the electrostatic discharge energy is absorbed. Although the destroyed path becomes non-conductive, as shown in the figure, a large number of current paths are formed by the conductive inorganic material 43 in the form of islands scattered in a discontinuous manner, so that electrostatic absorption can be performed many times. is there.

  As described above, the composite electronic component 100 according to the present embodiment incorporates a low-voltage type ESD protection element that has a small capacitance, a low discharge start voltage, and excellent discharge resistance, heat resistance, and weather resistance. Therefore, a high-performance composite electronic component that functions as a common mode filter having an electrostatic protection function can be realized.

  Further, the composite electronic component 100 according to the present embodiment secures electrical connection between the ESD protection element and the common mode filter using the plating electrode that penetrates the inorganic insulating layer 36 of the ESD protection layer 12B. As in the case of the external electrode surface, there is no conduction failure due to wear during solder connection, scratches on the electrode surface, or the like. Therefore, the ESD protection element and the common mode filter can be reliably connected. In addition, it is possible to avoid deterioration of electrostatic absorption performance caused by the surface of the external electrode surface being a high resistance tin plating layer.

  Further, the composite electronic component 100 according to the present embodiment is thin because the substrate 11 is provided only on one side of the functional layer 12, the insulating substrate on the opposite side is omitted, and the magnetic resin layer 14 is provided instead. Chip components can be provided at low cost. Further, by providing the bump electrodes 13a to 13f having the same thickness as the magnetic resin layer 14, the step of forming the external electrode surface on the side surface and the upper and lower surfaces of the chip component can be omitted, and the external electrode can be easily formed. In addition, it can be formed with high accuracy. Furthermore, according to the present embodiment, since a part of the bump electrodes 13a to 13f is provided so as to overlap with the spiral conductors 20 and 21 in plan view, a desired loop size of the spiral conductors 20 and 21 is ensured. However, it is possible to provide a bump electrode having a wide electrode surface, thereby reducing the size of the chip component.

  In the composite electronic component 100 according to the present embodiment, the ground electrode is raised from the ground electrode portion of each of the gap electrodes 34A to 34D, and the first and second spiral conductors 20 are bump electrodes above the spiral conductors 20 and 21. Therefore, even when the planar positions of the ground electrode portion and the ground bump electrode of the gap electrode are different, the coil forming region is not isolated while the ground electrode portion is disposed at an appropriate position.

  Next, a method for manufacturing the composite electronic component 100 will be described. In the manufacture of the composite electronic component 100, a large number of chip components are manufactured by forming a large number of common mode filter elements (coil conductor patterns) on a single large substrate (magnetic wafer) and then cutting each element individually. A mass production process is carried out.

  FIG. 9 is a flowchart illustrating an example of a manufacturing process of the composite electronic component 100. FIG. 10 is a schematic cross-sectional view illustrating an example of a method for forming the terminal electrode contact 39 and the ground contact 40 that penetrates the inorganic insulating layer 36 as a part of the manufacturing process of the composite electronic component 100.

  In the manufacture of the composite electronic component 100, first, the substrate 11 is prepared (step S11), the ESD protection layer 12B is formed on the substrate 11 (steps S12 to S17), and the common mode filter layer 12A is further formed on the ESD protection layer 12B. Form (steps S18 to S23).

  In the formation of the ESD protection layer 12B, first, the base insulating layer 33 is formed on the surface of the substrate 11 (step S12), and then gap electrodes 34A to 34D are formed on the surface of the base insulating layer 33 (step S13). As described above, each of the gap electrodes 34 </ b> A to 34 </ b> D includes the terminal electrode portion 37 and the ground electrode portion 38. Furthermore, a wiring pattern 38 a that connects the ground electrode portions 38 of the gap electrodes 34 </ b> A to 34 </ b> D is also formed on the surface of the base insulating layer 33.

  Next, the conductive inorganic material 43 of the electrostatic absorption layer 35 is selectively formed on the first to fourth gap electrodes 34A to 34D by sputtering (step S14). The selective formation is performed by forming a resist mask on the entire surface of the base surface excluding the region where the conductive inorganic material 43 is formed, then sputtering the conductive inorganic material 43 on the entire surface, and then removing the resist mask. be able to.

  Next, as shown in FIG. 10A, the terminal electrode portion 37 and the ground electrode portion 38 of the gap electrodes 34A to 34D are plated and grown to form the terminal electrode contact 39 and the ground contact 40 each made of a plated electrode. (Step S15).

  Next, as shown in FIG. 10B, an insulating inorganic material for the electrostatic absorption layer 35 and the inorganic insulating layer 36 is applied to the entire surface of the base insulating layer 33 on which the conductive inorganic material 43 and the plating electrode are formed. Form (step S16). As a result, the terminal electrode contact 39 and the ground contact 40 are covered with the inorganic insulating layer 36, and the upper surface of the inorganic insulating layer 36 is an uneven surface.

  Next, as shown in FIG. 10C, the upper surface of the inorganic insulating layer 36 is planarized by CMP (Chemical Mechanical Polishing) to expose the upper ends of the terminal electrode contact 39 and the ground contact 40 (step S17). ). Thus, the ESD protective layer 12B is completed.

  Next, the common mode filter layer 12A is formed on the ESD protection layer 12B (steps S18 to S23).

  In the formation of the common mode filter layer 12A, first, the first insulating layer 19a is formed (step S18). The first insulating layer 19a has a magnetic core opening pattern 26 provided in the center thereof, and through holes for forming terminal electrodes 28a to 28d and ground contacts 31a to 31d.

  Next, a conductor pattern including the first spiral conductor 20 is formed on the surface of the first insulating layer 19a (step S18). At this time, terminal electrodes 28a to 28d and ground contacts 31a to 31d are formed by embedding a conductor pattern in each through hole.

  Next, the second insulating layer 19b is formed on the surface of the first insulating layer 19a on which the first spiral conductor 20 and the like are formed (step S19). The second insulating layer 19b has a magnetic core opening pattern 26 provided in the center thereof, through holes for forming the terminal electrodes 28a to 28d, the first contact hole conductor 29, and the ground contacts 31a to 31d. have.

  Next, a conductor pattern including the second spiral conductor 21 is formed on the surface of the second insulating layer 19b (step S19). At this time, the terminal electrodes 28a to 28d, the first contact hole conductor 29, and the ground contacts 31a to 31d are formed by embedding a conductor pattern in each through hole.

  Next, the third insulating layer 19c is formed on the surface of the second insulating layer 19b on which the conductor pattern such as the second spiral conductor 21 is formed (step S20). The third insulating layer 19c forms a magnetic core opening pattern 26 provided at the center thereof, terminal electrodes 28a to 28d, first and second contact hole conductors 29 and 30, and ground contacts 31a to 31d. Through-holes.

  Next, a conductor pattern including the first and second lead conductors 22 and 23 and the first and second ground patterns 24 and 25 is formed on the surface of the third insulating layer 19c (step S20). At this time, terminal electrodes 28a to 28d, first and second contact hole conductors 29 and 30 and ground contacts 31a to 31d are formed by embedding a conductor pattern in each through hole.

  Next, a fourth insulating layer 19d is formed on the surface of the third insulating layer 19c on which conductor patterns such as the first and second lead conductors 22 and 23 are formed (step S21). The fourth insulating layer 19d has a magnetic core opening pattern 26 provided in the center thereof and through holes for forming the first to sixth terminal electrodes 28a to 28f.

  Next, bump electrodes 13a to 13f are formed on the insulating layer 19d (step S22). As a method of forming the bump electrodes 13a to 13f, first, a base conductive film such as Cu is formed on the entire surface of the insulating layer 19d by sputtering, and then a sheet resist is attached. The underlying conductive film may be formed by electroless plating or vapor deposition. At this time, the underlying conductive film also enters the opening pattern of the insulating layer 19d. Next, by exposing and developing the sheet resist, the sheet resist at the position where the bump electrodes 13a to 13f are to be formed is selectively removed, and the bump electrode formation region on the insulating layer 19d is exposed.

  Next, bump electrodes 13a to 13f are formed in the bump electrode formation region by electroplating. At this time, the base conductive film is also plated and grown inside the through hole of the insulating layer 19d for forming the terminal electrodes 28a to 28d, and the bump electrode material is buried. Thereafter, the sheet resist is removed and the entire surface is etched to remove unnecessary underlying conductive films, whereby substantially columnar bump electrodes 13a to 13f are formed.

  Next, the common mode filter layer 12A on which the bump electrodes 13a to 13f are formed is filled with a composite ferrite paste and cured to form the magnetic resin layer 14 (step S23). At this time, the inside of the magnetic core opening pattern 26 provided in each of the insulating layers 19a to 19d is filled with the composite ferrite, thereby penetrating the loops of the first and second spiral conductors 20 and 21. The magnetic core 27 is formed. Furthermore, in order to reliably form the magnetic resin layer 14, a large amount of paste is filled, whereby the bump electrodes 13a to 13f are buried in the resin. Therefore, the magnetic resin layer 14 is polished to a predetermined thickness and the surface is smoothed until the upper surfaces of the bump electrodes 13a to 13f are exposed. Further, the substrate 11 is also polished so as to have a predetermined thickness.

  Furthermore, after barrel-polishing chip parts to remove edges, electroplating is performed to smooth the surfaces of the bump electrodes 13 a to 13 f and the terminal electrodes 28 a to 28 f exposed on the side surfaces of the functional layer 12. As described above, by barrel polishing the outer surface of the chip component, it is possible to manufacture a coil component that is unlikely to be damaged such as chip chipping. Moreover, since the surface of bump electrode 13a-13f exposed to the outer peripheral surface of a chip component is plated, the surface of bump electrode 13a-13f can be made into a smooth surface.

  As described above, in the method for manufacturing the composite electronic component 100 according to the present embodiment, after the plating electrodes are formed on the surfaces of the terminal electrode portion 37 and the ground electrode portion 38 of each gap electrode 34A to 34D, the inorganic insulating layer 36 is used. Further, the terminal electrode contact 39 and the ground contact 40 penetrating the inorganic insulating layer 36 are formed by polishing and planarizing the surface of the inorganic insulating layer 36 until the upper surface of the plating electrode is exposed. Since the inorganic insulating layer 36 has a certain thickness so that breakage at the time of electrostatic absorption does not affect the common mode filter layer 12A, it is difficult to perform drilling. However, according to the present embodiment, it is not necessary to make a hole in the inorganic insulating layer 36, and a contact penetrating the inorganic insulating layer 36 can be easily formed. Thereby, it is not necessary to connect the common mode filter and the ESD protection element via the electrode surface plated on the side surface of the chip, and the reliability of electrical connection between them can be improved.

  FIG. 11 is a schematic cross-sectional view showing another example of the method for forming the terminal electrode contact 39 and the ground contact 40 that penetrates the inorganic insulating layer 36.

  First, as shown in FIG. 11A, an insulating inorganic material for the electrostatic absorption layer 35 and the inorganic insulating layer 36 is formed on the entire surface of the base insulating layer 33 on which the conductive inorganic material 43 is formed (step). S16). As a result, the terminal electrode portion 37 and the ground electrode portion 38 of the gap electrodes 34 </ b> A to 34 </ b> D are covered with the inorganic insulating layer 36.

  Next, as shown in FIG. 11B, the inorganic insulating layer 36 is patterned by an ion milling method. Thereby, an opening penetrating the inorganic insulating layer 36 is formed, and the electrode surfaces of the terminal electrode portion 37 and the ground electrode portion 38 of the gap electrodes 34A to 34D are exposed in the region where the terminal electrode contact 39 and the ground contact 40 are formed. It becomes a state.

  Thereafter, as shown in FIG. 11C, the terminal electrode portion 37 and the ground electrode portion 38 of the gap electrodes 34A to 34D are grown by plating, and the terminal electrode contact 39 and the ground contact 40 each made of a plating electrode are selectively formed. To do. As described above, the terminal electrode contact 39 and the ground contact 40 penetrating the inorganic insulating layer 36 can be formed.

  FIG. 12 is a schematic exploded perspective view showing in detail the layer structure of the composite electronic component 200 according to the second embodiment of the present invention. FIG. 13 is a schematic cross-sectional view showing the configuration of the composite electronic component 200.

  As shown in FIGS. 12 and 13, the composite electronic component 200 is characterized in that the stacking order of the common mode filter layer 12A and the ESD protection layer 12B is reversed. That is, the common mode filter layer 12A is first formed on the surface of the substrate 11, and the ESD protection layer 12B is formed thereon, which is different from the composite electronic component 100 according to the first embodiment.

  Furthermore, in the present embodiment, a ground contact 40 penetrating the inorganic insulating layer 36 is provided immediately below the fifth and sixth bump electrodes 13e and 13f, and the ground contact 40 is directly connected to the bump electrode 13e or 13f. Has been.

According to the present embodiment, since the common mode filter layer 12A is not interposed between the ESD protection layer 12B and the bump electrodes 13a to 13f, the ground contacts 31a to 31d penetrating the insulating layers 19a to 19c of the common mode filter layer 12A. In addition, the ground patterns 24 and 25 formed on the surface of the third insulating layer 19c are unnecessary, and the ground contact 40 of the ESD protection layer 12B and the bump electrode 13e or 13f are directly connected without passing through them. Can do.

  The preferred embodiments of the present invention have been described above. However, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention. Needless to say, it is included in the present invention.

  For example, in the above embodiment, the magnetic resin layer 14 made of composite ferrite is formed on the main surface of the functional layer 12, but a simple insulating resin layer having no magnetism may be formed. When a nonmagnetic resin layer is used, parasitic capacitance components can be reduced. Moreover, in the said embodiment, although bump electrode 13a-13f is used as an external terminal electrode, this invention is not limited to a bump electrode. However, when the bump electrode is used, since the vertical electrical connection from the ESD protection layer 12B to the external terminal electrode is performed by the plating electrode, the ESD absorption performance can be sufficiently improved. .

  Moreover, in the said embodiment, although the magnetic core 27 is provided, the magnetic core 27 is not essential in this invention. For example, when a nonmagnetic resin layer is used instead of the magnetic resin layer 14, the magnetic core 27 is not necessary. However, since the magnetic core 27 can be formed of the same material as the magnetic resin layer 14, the magnetic core 27 and the magnetic resin layer 14 can be simultaneously formed without going through a special process as long as the opening 26 is formed. Can be formed.

  In the above embodiment, the common mode filter layer 12A including the spiral conductors 20 and 21 has been described as an example. However, the present invention is not limited to the common mode filter layer, and a planar coil layer including a planar coil pattern. If it is.

1, 2 Signal line 3 Output buffer 4 Input buffer 5 Common mode filter 10a Upper surface 10b Bottom surface 10c to 10f Side surface 11 Substrate 12 Functional layer 12A Common mode filter layer 12B ESD protection layers 13a to 13f Bump electrode 14 Magnetic resin layer 15 Common mode filter 15a, 15b Inductor elements 16a-16d ESD protection elements 17a-17f Terminal electrodes 19a-19d Insulating layers 20, 21 Spiral conductors 20a, 21a Lead portions 22, 23 Conductors 24, 25 Ground pattern 26 Openings 27 Magnetic cores 28a-28f Terminal electrodes 29, 30 Contact hole conductors 31a to 31d Ground contact 33 Underlying insulating layer 34 Electrode layers 34A to 34D Gap electrode 35 Electrostatic absorption layer 36 Inorganic insulating layer 37 Terminal electrode portion 38 Ground electrode portion 38a Wiring pad Over emissions 39 terminal electrode contacts 40 the ground contacts 41a, 41b electrode 42 insulating inorganic material 43 conductive inorganic material 100, 200 composite electronic component

Claims (13)

A substrate,
A functional layer provided on the substrate;
A plurality of external terminal electrodes electrically connected to the functional layer,
The functional layer is
A planar coil layer including first and second spiral conductors magnetically coupled to each other ;
An ESD protection layer including the first to fourth ESD protection elements,
Each of the first to fourth ESD protection elements includes:
A gap electrode including a terminal electrode portion and a ground electrode portion facing each other through a gap;
An electrostatic absorption layer formed on the gap electrode;
An inorganic insulating layer covering the gap electrode through the electrostatic absorption layer;
A terminal electrode contact made of a plating electrode formed on the surface of the terminal electrode portion of the gap electrode;
A ground contact made of a plating electrode formed on the surface of the ground electrode portion of the gap electrode,
The electrostatic absorption layer is a composite in which a conductive inorganic material is dispersed in a matrix of an insulating inorganic material.
The ground electrode portions of the first to fourth ESD protection elements are connected to each other via a wiring pattern to form a loop pattern,
The composite electronic component according to claim 1, wherein the ground electrode portion and the wiring pattern are provided at a position avoiding a passage region of a magnetic path inside the first and second spiral conductors . The planar coil layer is provided on the surface of the substrate,
The composite electronic component according to claim 1 , wherein the ESD protection layer is provided on an upper layer of the planar coil layer. A terminal electrode contact of the first ESD protection element is electrically connected to an inner peripheral end of the first spiral conductor;
A terminal electrode contact of the second ESD protection element is electrically connected to an outer peripheral end of the first spiral conductor;
A terminal electrode contact of the third ESD protection element is electrically connected to an inner peripheral end of the second spiral conductor;
3. The composite electronic component according to claim 1 , wherein a terminal electrode contact of the fourth ESD protection element is electrically connected to an outer peripheral end of the second spiral conductor. The external terminal electrode includes first to fourth external terminal electrodes,
4. The composite electronic component according to claim 3 , wherein terminal electrode contacts of the first to fourth ESD protection elements are electrically connected to the first to fourth external terminal electrodes, respectively. The external terminal electrode further includes fifth and sixth external terminal electrodes,
The ground contacts of the first and second ESD protection elements are connected to the fifth external terminal electrode,
5. The composite electronic component according to claim 4 , wherein ground contacts of the third and fourth ESD protection elements are connected to the sixth external terminal electrode. The planar coil layer is
First and second lead conductors respectively connected to the inner peripheral ends of the first and second spiral conductors;
A first terminal electrode connected to the inner peripheral end of the first spiral conductor via the first lead conductor and connected to the first external terminal electrode;
A second terminal electrode connected to an outer peripheral end of the first spiral conductor and connected to the second external terminal electrode;
A third terminal electrode connected to the inner peripheral end of the second spiral conductor via the second lead conductor and connected to the third external terminal electrode;
A fourth terminal electrode connected to the outer peripheral end of the second spiral conductor and connected to the fourth external terminal electrode;
6. The composite electronic component according to claim 5 , wherein terminal electrode contacts of the first to fourth ESD protection elements are respectively connected to the first to fourth terminal electrodes. The planar coil layer is
Further comprising first to third insulating layers;
7. The composite electronic component according to claim 6 , wherein each of the first to fourth terminal electrodes is provided so as to penetrate through a laminate including at least the first to third insulating layers. . The first spiral conductor is formed on a surface of the first insulating layer;
The second spiral conductor is formed on a surface of the second insulating layer;
The first and second lead conductors are formed on the surface of the third insulating layer,
An inner peripheral end of the first spiral conductor is connected to the first lead conductor via a first contact hole conductor penetrating the second and third insulating layers,
The inner peripheral end of the second spiral conductor, to claim 7, characterized in that via the second contact hole conductors penetrating the third insulating layer being connected to said second lead conductor The composite electronic component described. The planar coil layer further includes first and second ground patterns formed on a surface of the third insulating layer,
Ground contacts of the first and second ESD protection elements are connected to the fifth external terminal electrode through the first ground pattern,
9. The composite electron according to claim 8 , wherein ground contacts of the third and fourth ESD protection elements are connected to the sixth external terminal electrode through the second ground pattern. parts. 10. The composite electronic component according to claim 1 , wherein the external terminal electrode is a bump electrode provided on a surface of the functional layer. The planar coil layer further includes a ground pattern provided closer to the external terminal electrode than the first and second spiral conductors ,
The planar coil layer is provided between the plurality of external terminal electrodes and the ESD protection layer,
At least a part of the ground contact is provided at a position outside the spiral conductor and not overlapping in plan view,
11. The composite electronic component according to claim 1, wherein the ground electrode portion is connected to the external terminal electrode through the ground contact and the ground pattern. The first and second spiral conductors are oval spiral conductors;
The composite electronic component according to claim 11 , wherein the ground contact has a portion overlapping with an arc-shaped portion of the oval spiral conductor in a plan view. The external terminal electrode is a bump electrode provided on the surface of the functional layer,
The composite electronic component according to claim 11 , wherein a part of the bump electrode overlaps the spiral conductor in a plan view.

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