JP5415069B2 - スレッドレベルの投機実行を拡張するためのプリミティブ - Google Patents
スレッドレベルの投機実行を拡張するためのプリミティブ Download PDFInfo
- Publication number
- JP5415069B2 JP5415069B2 JP2008518482A JP2008518482A JP5415069B2 JP 5415069 B2 JP5415069 B2 JP 5415069B2 JP 2008518482 A JP2008518482 A JP 2008518482A JP 2008518482 A JP2008518482 A JP 2008518482A JP 5415069 B2 JP5415069 B2 JP 5415069B2
- Authority
- JP
- Japan
- Prior art keywords
- memory
- thread
- instruction
- execution
- block
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000000034 method Methods 0.000 claims description 64
- 238000012544 monitoring process Methods 0.000 claims description 28
- 239000000872 buffer Substances 0.000 claims description 24
- 230000008569 process Effects 0.000 claims description 19
- 230000004044 response Effects 0.000 claims description 16
- 230000003139 buffering effect Effects 0.000 claims description 8
- 239000012536 storage buffer Substances 0.000 claims description 7
- 238000012545 processing Methods 0.000 description 46
- 238000013459 approach Methods 0.000 description 19
- 238000010586 diagram Methods 0.000 description 17
- 230000007246 mechanism Effects 0.000 description 13
- 230000006870 function Effects 0.000 description 9
- 230000006399 behavior Effects 0.000 description 8
- 238000005192 partition Methods 0.000 description 5
- 230000001360 synchronised effect Effects 0.000 description 4
- 230000007704 transition Effects 0.000 description 4
- 230000009471 action Effects 0.000 description 3
- 230000008901 benefit Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000000638 solvent extraction Methods 0.000 description 3
- 230000008859 change Effects 0.000 description 2
- 230000008520 organization Effects 0.000 description 2
- 101100221836 Arabidopsis thaliana CPL3 gene Proteins 0.000 description 1
- 101100065702 Arabidopsis thaliana ETC3 gene Proteins 0.000 description 1
- 238000004590 computer program Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000013500 data storage Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 230000010365 information processing Effects 0.000 description 1
- 230000001343 mnemonic effect Effects 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 230000002459 sustained effect Effects 0.000 description 1
- 230000001960 triggered effect Effects 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/52—Program synchronisation; Mutual exclusion, e.g. by means of semaphores
- G06F9/526—Mutual exclusion algorithms
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30076—Arrangements for executing specific machine instructions to perform miscellaneous control operations, e.g. NOP
- G06F9/30087—Synchronisation or serialisation instructions
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30098—Register arrangements
- G06F9/30101—Special purpose registers
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3824—Operand accessing
- G06F9/3834—Maintaining memory consistency
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
- G06F9/3842—Speculative instruction execution
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
- G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Multimedia (AREA)
- Advance Control (AREA)
- Executing Machine-Instructions (AREA)
- Debugging And Monitoring (AREA)
- Memory System (AREA)
Description
として表す)及びトランザクション・スタータス・レジスタ952(本明細書及び特許請求の範囲では「TSR」として表す)を含む。トランザクション制御レジスタは、AMT106及びAUT108に対する更新を制御する。トランザクション・ステータス・レジスタはAMT及びAUTの状態を通知することができ、トランザクション障害を示すこともできる。
AMTのリセットの強制
AMTの直接更新
メモリ書き込みの直接バッファリング(AUTへの更新)
少なくとも1つの実施例の場合、複数の挙動を単一ビットによって示すことができる。例えば、トランザクション制御レジスタ951における単一ビットは、AUT及びAMTをリセットすべきである旨を表すことができる。
トランザクション障害の理由(障害が生じた場合) このフィールドの値はオーバフロー、衝突等を含み得る。
トラップがトランザクション障害を引き起こしたか否か
特定の一実施例の場合、トランザクション・ステータス・レジスタ952(「TSR」)は、AMT、AUT及び現在のトランザクションの一般的な状態についてのステータス情報を、何れかの特定の時点においてフィールドに記憶されている値に応じて提供し得るフィールドを含む読み出し専用レジスタである。当然、その他の実施例は、より多くの、又はより少ないビットを利用することができる。トランザクション・ステータス・レジスタ952の実施例の場合、フィールドは以下のように定義することができる。特定のビット番号は例証の目的でのみ記載しており、限定的に解されないものとする。任意の容量のレジスタにおいて、後述のビット・フィールドを実現する実施例の場合、以下に記載されていない更なるフィールドは「予約済」であることがあり得る。前述の予約済ビットは、書き込み無視、読み出しゼロとして実現することができる。
図7に示すマルチシーケンサ・システム900のSMT実施例の場合、「シーケンサ」の語は、スレッド・コンテキストの少なくとも次命令ポインタ及びフェッチ・ロジック320、及び、そのスレッド・コンテキストの関連したアーキテクチャ状態の少なくとも一部を包含する。SMTシステム900のシーケンサは対称でなくてよい。例えば、同じ物理コア904の2つのSMTシーケンサは、それぞれが維持するアーキテクチャ状態情報の量において異なり得る。
Claims (3)
- 装置であって、
複数のスレッドを同時に実行するための複数のスレッド・ユニットと、
前記複数のスレッド・ユニットのうちの一スレッド・ユニットに関連付けられた制御記憶領域であって、前記制御記憶領域は第1の直接更新フィールド及び第2の直接更新フィールドを含み、前記制御記憶領域は、メモリ読み出し及びメモリ書き込みの少なくとも一方を監視すべきか否かを示す旨のユーザレベル命令の実行に応じて更新されることができる制御記憶領域と、
メモリ書き込みを監視すべき旨を示す第1の値を前記第1の直接更新フィールドが保持していることに応じて、当該スレッド・ユニットの第1のスレッドに関連付けられた、実行中に受けるメモリ書き込み命令のデータを保持するためのメモリ・バッファ記憶領域と、
前記第1のスレッドによって出されるメモリ読み出し命令のメモリ・アドレスを記憶するためのアドレス記憶領域とを備え、別のスレッドから前記メモリ・アドレスへのメモリ書き込みは、前記メモリ読み出しを監視すべき旨を示す第2の値を前記第2の直接更新フィールドが保持していることに応じて監視される装置。 - 方法であって、
複数のスレッドを実行するためにプロセッサの複数のスレッド・ユニットのうちの第1のスレッド・ユニットによって実行される投機的スレッドから受け取られた更新制御レジスタ・ユーザレベル命令を実行する工程であって、
前記更新制御レジスタ・ユーザレベル命令は、前記投機的スレッドのメモリ読み出し及びメモリ書き込みの少なくとも一方を監視すべきか否かを示す監視値を、更新制御レジスタの第1の直接更新フィールド及び第2の直接更新フィールドが保持するよう、前記第1のスレッド・ユニットに関連付けられた前記更新制御レジスタを更新するものである、工程と、 メモリ命令を前記投機的スレッドによって実行する工程であって、 前記メモリ書き込みを監視すべき旨を示す第1の値を前記第1の直接更新フィールドが保持していることに応じて、前記メモリ命令を監視して前記第1のスレッド・ユニットによって維持される記憶バッファに前記第1のスレッドのメモリ書き込み命令のデータをバッファリングするサブ工程と、 前記メモリ読み出しを監視すべき旨を示す第2の値を前記第2の直接更新フィールドが保持していることに応じて、前記投機的スレッドからのメモリ読み出し命令の1つ又は複数のメモリ・アドレスを前記第1のスレッド・ユニットによって維持されるアドレス記憶領域に記憶して前記複数のスレッドのうちの別のスレッドからのメモリ書き込みを検出するよう前記1つ又は複数のメモリ・アドレスが監視されるサブ工程を含む工程、 を含む方法。 - システムであって、
複数のスレッドのソフトウェア命令を記憶するためのメモリと、
前記複数のスレッドを同時に実行するための複数のスレッド・ユニットと、
前記複数のスレッド・ユニットのうちの一スレッド・ユニットに関連付けられ、前記複数のスレッドの投機的スレッドを実行するための制御レジスタであって、前記制御レジスタは第1の直接更新フィールド及び第2の直接更新フィールドを含み、前記制御レジスタは、ユーザレベル命令の実行に応じて更新されることができる制御レジスタと、
メモリ書き込みを監視すべき旨を示す第1の値を前記第1の直接更新フィールドが保持していることに応じて、当該スレッド・ユニットに関連付けられた、実行中に受けるメモリ書き込み命令のデータを保持するためのメモリ・バッファ記憶領域と、
メモリ読み出し命令を監視すべき旨を示す第2の値を前記直接更新フィールドが保持していることに応じて、前記投機的スレッドの命令のアトミック・ブロックの実行中に受けるメモリ読み出し命令のアドレスを保持するためのアドレス記憶領域とを備え、前記メモリ読み出し命令の前記アドレスは、前記複数のスレッドのうちの別のスレッドからのメモリ書き込みを検出するよう監視されるシステム。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/165,639 US7882339B2 (en) | 2005-06-23 | 2005-06-23 | Primitives to enhance thread-level speculation |
US11/165,639 | 2005-06-23 | ||
PCT/US2006/024727 WO2007002550A2 (en) | 2005-06-23 | 2006-06-23 | Primitives to enhance thread-level speculation |
Related Child Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2011177640A Division JP5479416B2 (ja) | 2005-06-23 | 2011-08-15 | スレッドレベルの投機実行を拡張するためのプリミティブ |
JP2013083679A Division JP2013168168A (ja) | 2005-06-23 | 2013-04-12 | スレッドレベルの投機実行を拡張するためのプリミティブ |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2009501366A JP2009501366A (ja) | 2009-01-15 |
JP5415069B2 true JP5415069B2 (ja) | 2014-02-12 |
Family
ID=37433515
Family Applications (4)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2008518482A Expired - Fee Related JP5415069B2 (ja) | 2005-06-23 | 2006-06-23 | スレッドレベルの投機実行を拡張するためのプリミティブ |
JP2011177640A Expired - Fee Related JP5479416B2 (ja) | 2005-06-23 | 2011-08-15 | スレッドレベルの投機実行を拡張するためのプリミティブ |
JP2013083679A Pending JP2013168168A (ja) | 2005-06-23 | 2013-04-12 | スレッドレベルの投機実行を拡張するためのプリミティブ |
JP2015010769A Pending JP2015111439A (ja) | 2005-06-23 | 2015-01-23 | スレッドレベルの投機実行を拡張するためのプリミティブ |
Family Applications After (3)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2011177640A Expired - Fee Related JP5479416B2 (ja) | 2005-06-23 | 2011-08-15 | スレッドレベルの投機実行を拡張するためのプリミティブ |
JP2013083679A Pending JP2013168168A (ja) | 2005-06-23 | 2013-04-12 | スレッドレベルの投機実行を拡張するためのプリミティブ |
JP2015010769A Pending JP2015111439A (ja) | 2005-06-23 | 2015-01-23 | スレッドレベルの投機実行を拡張するためのプリミティブ |
Country Status (6)
Country | Link |
---|---|
US (4) | US7882339B2 (ja) |
JP (4) | JP5415069B2 (ja) |
CN (2) | CN101203831B (ja) |
DE (2) | DE112006004265A5 (ja) |
GB (2) | GB2457181B (ja) |
WO (1) | WO2007002550A2 (ja) |
Families Citing this family (124)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8607241B2 (en) * | 2004-06-30 | 2013-12-10 | Intel Corporation | Compare and exchange operation using sleep-wakeup mechanism |
US7882339B2 (en) * | 2005-06-23 | 2011-02-01 | Intel Corporation | Primitives to enhance thread-level speculation |
US7865894B1 (en) * | 2005-12-19 | 2011-01-04 | Nvidia Corporation | Distributing processing tasks within a processor |
US8683143B2 (en) * | 2005-12-30 | 2014-03-25 | Intel Corporation | Unbounded transactional memory systems |
US7350027B2 (en) * | 2006-02-10 | 2008-03-25 | International Business Machines Corporation | Architectural support for thread level speculative execution |
US8180967B2 (en) * | 2006-03-30 | 2012-05-15 | Intel Corporation | Transactional memory virtualization |
US8180977B2 (en) * | 2006-03-30 | 2012-05-15 | Intel Corporation | Transactional memory in out-of-order processors |
US7620850B2 (en) * | 2006-06-09 | 2009-11-17 | Sun Microsystems, Inc. | Breakpoints in a transactional memory-based representation of code |
US8307346B2 (en) * | 2006-06-09 | 2012-11-06 | Oracle America, Inc. | Atomic groups for debugging |
US7809926B2 (en) * | 2006-11-03 | 2010-10-05 | Cornell Research Foundation, Inc. | Systems and methods for reconfiguring on-chip multiprocessors |
US8190859B2 (en) * | 2006-11-13 | 2012-05-29 | Intel Corporation | Critical section detection and prediction mechanism for hardware lock elision |
US8719807B2 (en) * | 2006-12-28 | 2014-05-06 | Intel Corporation | Handling precompiled binaries in a hardware accelerated software transactional memory system |
US7681015B2 (en) * | 2007-01-30 | 2010-03-16 | Nema Labs Ab | Generating and comparing memory access ranges for speculative throughput computing |
US20080222616A1 (en) * | 2007-03-05 | 2008-09-11 | Innaworks Development Limited | Software translation |
US8095741B2 (en) * | 2007-05-14 | 2012-01-10 | International Business Machines Corporation | Transactional memory computing system with support for chained transactions |
US8095750B2 (en) * | 2007-05-14 | 2012-01-10 | International Business Machines Corporation | Transactional memory system with fast processing of common conflicts |
US9009452B2 (en) | 2007-05-14 | 2015-04-14 | International Business Machines Corporation | Computing system with transactional memory using millicode assists |
US8117403B2 (en) * | 2007-05-14 | 2012-02-14 | International Business Machines Corporation | Transactional memory system which employs thread assists using address history tables |
US20090133022A1 (en) * | 2007-11-15 | 2009-05-21 | Karim Faraydon O | Multiprocessing apparatus, system and method |
US8407425B2 (en) | 2007-12-28 | 2013-03-26 | Intel Corporation | Obscuring memory access patterns in conjunction with deadlock detection or avoidance |
US9081687B2 (en) * | 2007-12-28 | 2015-07-14 | Intel Corporation | Method and apparatus for MONITOR and MWAIT in a distributed cache architecture |
US8447962B2 (en) * | 2009-12-22 | 2013-05-21 | Intel Corporation | Gathering and scattering multiple data elements |
US10387151B2 (en) | 2007-12-31 | 2019-08-20 | Intel Corporation | Processor and method for tracking progress of gathering/scattering data element pairs in different cache memory banks |
US7984273B2 (en) | 2007-12-31 | 2011-07-19 | Intel Corporation | System and method for using a mask register to track progress of gathering elements from memory |
US20090177871A1 (en) * | 2008-01-08 | 2009-07-09 | Von Praun Christoph | Architectural support for software thread-level speculation |
US9128750B1 (en) * | 2008-03-03 | 2015-09-08 | Parakinetics Inc. | System and method for supporting multi-threaded transactions |
US8239843B2 (en) * | 2008-03-11 | 2012-08-07 | Oracle America, Inc. | Value predictable variable scoping for speculative automatic parallelization with transactional memory |
BRPI0920541A2 (pt) | 2008-11-24 | 2018-11-06 | Intel Corp | sistemas, métodos e aparelho para decompor um programa sequencial em multicadeias, executar as ditas cadeias, e reconstruir a execução sequencial |
US10621092B2 (en) | 2008-11-24 | 2020-04-14 | Intel Corporation | Merging level cache and data cache units having indicator bits related to speculative execution |
US9672019B2 (en) | 2008-11-24 | 2017-06-06 | Intel Corporation | Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program to multiple parallel threads |
US9189233B2 (en) | 2008-11-24 | 2015-11-17 | Intel Corporation | Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program to multiple parallel threads |
US9785462B2 (en) * | 2008-12-30 | 2017-10-10 | Intel Corporation | Registering a user-handler in hardware for transactional memory event handling |
US8131984B2 (en) * | 2009-02-12 | 2012-03-06 | Via Technologies, Inc. | Pipelined microprocessor with fast conditional branch instructions based on static serializing instruction state |
US8521996B2 (en) * | 2009-02-12 | 2013-08-27 | Via Technologies, Inc. | Pipelined microprocessor with fast non-selective correct conditional branch instruction resolution |
US8281185B2 (en) * | 2009-06-30 | 2012-10-02 | Oracle America, Inc. | Advice-based feedback for transactional execution |
US8566524B2 (en) * | 2009-08-31 | 2013-10-22 | International Business Machines Corporation | Transactional memory system with efficient cache support |
US8255626B2 (en) * | 2009-12-09 | 2012-08-28 | International Business Machines Corporation | Atomic commit predicated on consistency of watches |
US8316194B2 (en) | 2009-12-15 | 2012-11-20 | Intel Corporation | Mechanisms to accelerate transactions using buffered stores |
US8095824B2 (en) | 2009-12-15 | 2012-01-10 | Intel Corporation | Performing mode switching in an unbounded transactional memory (UTM) system |
US8464035B2 (en) | 2009-12-18 | 2013-06-11 | Intel Corporation | Instruction for enabling a processor wait state |
US10175990B2 (en) | 2009-12-22 | 2019-01-08 | Intel Corporation | Gathering and scattering multiple data elements |
JP5673666B2 (ja) * | 2010-02-23 | 2015-02-18 | 富士通株式会社 | マルチコアプロセッサシステム、割込プログラム、および割込方法 |
CN104794006A (zh) * | 2010-02-23 | 2015-07-22 | 富士通株式会社 | 多核处理器系统、中断程序、以及中断方法 |
US8739164B2 (en) * | 2010-02-24 | 2014-05-27 | Advanced Micro Devices, Inc. | Automatic suspend atomic hardware transactional memory in response to detecting an implicit suspend condition and resume thereof |
US9626187B2 (en) | 2010-05-27 | 2017-04-18 | International Business Machines Corporation | Transactional memory system supporting unbroken suspended execution |
CN101882091A (zh) * | 2010-06-22 | 2010-11-10 | 北京北大众志微系统科技有限责任公司 | 线程局部存储实现方法和装置 |
US20110320781A1 (en) | 2010-06-29 | 2011-12-29 | Wei Liu | Dynamic data synchronization in thread-level speculation |
US8407389B2 (en) * | 2010-07-20 | 2013-03-26 | International Business Machines Corporation | Atomic operations with page migration in PCIe |
US20120079245A1 (en) * | 2010-09-25 | 2012-03-29 | Cheng Wang | Dynamic optimization for conditional commit |
US9052890B2 (en) * | 2010-09-25 | 2015-06-09 | Intel Corporation | Execute at commit state update instructions, apparatus, methods, and systems |
US8424015B2 (en) * | 2010-09-30 | 2013-04-16 | International Business Machines Corporation | Transactional memory preemption mechanism |
US8713259B2 (en) * | 2010-11-17 | 2014-04-29 | Advanced Micro Devices, Inc. | Method and apparatus for reacquiring lines in a cache |
US8904109B2 (en) | 2011-01-28 | 2014-12-02 | Freescale Semiconductor, Inc. | Selective cache access control apparatus and method thereof |
GB2489000B (en) * | 2011-03-14 | 2019-09-11 | Advanced Risc Mach Ltd | Diagnosing code using single step execution |
US9043796B2 (en) * | 2011-04-07 | 2015-05-26 | Microsoft Technology Licensing, Llc | Asynchronous callback driven messaging request completion notification |
US8756405B2 (en) * | 2011-05-09 | 2014-06-17 | Freescale Semiconductor, Inc. | Selective routing of local memory accesses and device thereof |
WO2013048468A1 (en) | 2011-09-30 | 2013-04-04 | Intel Corporation | Instruction and logic to perform dynamic binary translation |
US10387324B2 (en) * | 2011-12-08 | 2019-08-20 | Intel Corporation | Method, apparatus, and system for efficiently handling multiple virtual address mappings during transactional execution canceling the transactional execution upon conflict between physical addresses of transactional accesses within the transactional execution |
US8892946B2 (en) | 2011-12-15 | 2014-11-18 | International Business Machines Corporation | Verifying speculative multithreading in an application |
US20150032998A1 (en) * | 2012-02-02 | 2015-01-29 | Ravi Rajwar | Method, apparatus, and system for transactional speculation control instructions |
CN104303142B (zh) | 2012-06-02 | 2019-03-08 | 英特尔公司 | 使用索引阵列和有限状态机的分散 |
US8972697B2 (en) | 2012-06-02 | 2015-03-03 | Intel Corporation | Gather using index array and finite state machine |
US10437602B2 (en) * | 2012-06-15 | 2019-10-08 | International Business Machines Corporation | Program interruption filtering in transactional execution |
US9384004B2 (en) | 2012-06-15 | 2016-07-05 | International Business Machines Corporation | Randomized testing within transactional execution |
US9348642B2 (en) | 2012-06-15 | 2016-05-24 | International Business Machines Corporation | Transaction begin/end instructions |
US20130339680A1 (en) | 2012-06-15 | 2013-12-19 | International Business Machines Corporation | Nontransactional store instruction |
US9448796B2 (en) | 2012-06-15 | 2016-09-20 | International Business Machines Corporation | Restricted instructions in transactional execution |
US9772854B2 (en) | 2012-06-15 | 2017-09-26 | International Business Machines Corporation | Selectively controlling instruction execution in transactional processing |
US9336046B2 (en) | 2012-06-15 | 2016-05-10 | International Business Machines Corporation | Transaction abort processing |
US9740549B2 (en) | 2012-06-15 | 2017-08-22 | International Business Machines Corporation | Facilitating transaction completion subsequent to repeated aborts of the transaction |
US8682877B2 (en) | 2012-06-15 | 2014-03-25 | International Business Machines Corporation | Constrained transaction execution |
US8688661B2 (en) | 2012-06-15 | 2014-04-01 | International Business Machines Corporation | Transactional processing |
US9361115B2 (en) | 2012-06-15 | 2016-06-07 | International Business Machines Corporation | Saving/restoring selected registers in transactional processing |
US9436477B2 (en) | 2012-06-15 | 2016-09-06 | International Business Machines Corporation | Transaction abort instruction |
CN105760140B (zh) * | 2012-06-29 | 2019-09-13 | 英特尔公司 | 用于测试事务性执行状态的指令和逻辑 |
US9430166B2 (en) * | 2012-08-10 | 2016-08-30 | International Business Machines Corporation | Interaction of transactional storage accesses with other atomic semantics |
US9361103B2 (en) * | 2012-11-02 | 2016-06-07 | Advanced Micro Devices, Inc. | Store replay policy |
CN104813277B (zh) * | 2012-12-19 | 2019-06-28 | 英特尔公司 | 用于处理器的功率效率的向量掩码驱动时钟门控 |
US9547594B2 (en) * | 2013-03-15 | 2017-01-17 | Intel Corporation | Instructions to mark beginning and end of non transactional code region requiring write back to persistent storage |
US9460145B2 (en) | 2013-03-26 | 2016-10-04 | International Business Machines Corporation | Transactional lock elision with delayed lock checking |
US9891936B2 (en) | 2013-09-27 | 2018-02-13 | Intel Corporation | Method and apparatus for page-level monitoring |
US9311260B2 (en) * | 2013-12-09 | 2016-04-12 | Jack Mason | Context preservation during thread level speculative execution |
US9678834B2 (en) * | 2014-10-20 | 2017-06-13 | Ab Initio Technology, Llc | Recovery and fault-tolerance under computational indeterminism |
JP5867630B2 (ja) * | 2015-01-05 | 2016-02-24 | 富士通株式会社 | マルチコアプロセッサシステム、マルチコアプロセッサシステムの制御方法、およびマルチコアプロセッサシステムの制御プログラム |
US9749548B2 (en) | 2015-01-22 | 2017-08-29 | Google Inc. | Virtual linebuffers for image signal processors |
GB2535212B (en) | 2015-02-13 | 2021-08-04 | Advanced Risc Mach Ltd | An apparatus and method for controlling debugging of program instructions including a transaction |
GB2535213B (en) | 2015-02-13 | 2021-10-06 | Advanced Risc Mach Ltd | An apparatus and method for controlling debugging of program instructions including a transaction |
US9772852B2 (en) | 2015-04-23 | 2017-09-26 | Google Inc. | Energy efficient processor core architecture for image processor |
US9785423B2 (en) | 2015-04-23 | 2017-10-10 | Google Inc. | Compiler for translating between a virtual image processor instruction set architecture (ISA) and target hardware having a two-dimensional shift array structure |
US9756268B2 (en) | 2015-04-23 | 2017-09-05 | Google Inc. | Line buffer unit for image processor |
US10291813B2 (en) | 2015-04-23 | 2019-05-14 | Google Llc | Sheet generator for image processor |
US9965824B2 (en) | 2015-04-23 | 2018-05-08 | Google Llc | Architecture for high performance, power efficient, programmable image processing |
US10095479B2 (en) * | 2015-04-23 | 2018-10-09 | Google Llc | Virtual image processor instruction set architecture (ISA) and memory model and exemplary target hardware having a two-dimensional shift array structure |
US9769356B2 (en) | 2015-04-23 | 2017-09-19 | Google Inc. | Two dimensional shift array for image processor |
US20160378488A1 (en) * | 2015-06-26 | 2016-12-29 | Microsoft Technology Licensing, Llc | Access to target address |
US10346168B2 (en) | 2015-06-26 | 2019-07-09 | Microsoft Technology Licensing, Llc | Decoupled processor instruction window and operand buffer |
US10303477B2 (en) * | 2015-06-26 | 2019-05-28 | Intel Corporation | Persistent commit processors, methods, systems, and instructions |
US9858074B2 (en) * | 2015-06-26 | 2018-01-02 | International Business Machines Corporation | Non-default instruction handling within transaction |
US11755484B2 (en) | 2015-06-26 | 2023-09-12 | Microsoft Technology Licensing, Llc | Instruction block allocation |
US10776115B2 (en) * | 2015-09-19 | 2020-09-15 | Microsoft Technology Licensing, Llc | Debug support for block-based processor |
US10313641B2 (en) | 2015-12-04 | 2019-06-04 | Google Llc | Shift register with reduced wiring complexity |
US9830150B2 (en) | 2015-12-04 | 2017-11-28 | Google Llc | Multi-functional execution lane for image processor |
JP6512087B2 (ja) * | 2015-12-09 | 2019-05-15 | 株式会社デンソー | 車両用制御装置 |
US10318295B2 (en) * | 2015-12-22 | 2019-06-11 | Intel Corporation | Transaction end plus commit to persistence instructions, processors, methods, and systems |
US9898351B2 (en) | 2015-12-24 | 2018-02-20 | Intel Corporation | Method and apparatus for user-level thread synchronization with a monitor and MWAIT architecture |
CN111858256B (zh) * | 2015-12-25 | 2024-05-28 | 北京忆芯科技有限公司 | 命令队列监控电路、数据交换方法及其设备 |
US11188336B2 (en) * | 2015-12-28 | 2021-11-30 | Qualcomm Incorporated | Replay of partially executed instruction blocks in a processor-based system employing a block-atomic execution model |
US10387988B2 (en) | 2016-02-26 | 2019-08-20 | Google Llc | Compiler techniques for mapping program code to a high performance, power efficient, programmable image processing hardware platform |
US10204396B2 (en) | 2016-02-26 | 2019-02-12 | Google Llc | Compiler managed memory for image processor |
US10380969B2 (en) | 2016-02-28 | 2019-08-13 | Google Llc | Macro I/O unit for image processor |
US10546211B2 (en) | 2016-07-01 | 2020-01-28 | Google Llc | Convolutional neural network on programmable two dimensional image processor |
US20180007302A1 (en) | 2016-07-01 | 2018-01-04 | Google Inc. | Block Operations For An Image Processor Having A Two-Dimensional Execution Lane Array and A Two-Dimensional Shift Register |
US20180005059A1 (en) | 2016-07-01 | 2018-01-04 | Google Inc. | Statistics Operations On Two Dimensional Image Processor |
US20180005346A1 (en) | 2016-07-01 | 2018-01-04 | Google Inc. | Core Processes For Block Operations On An Image Processor Having A Two-Dimensional Execution Lane Array and A Two-Dimensional Shift Register |
CN109508239A (zh) * | 2017-09-15 | 2019-03-22 | 北京国双科技有限公司 | 进程的控制方法及装置 |
EP3462312B1 (en) * | 2017-09-29 | 2022-08-17 | ARM Limited | Permitting unaborted processing of transaction after exception mask update instruction |
US10853223B2 (en) * | 2018-01-19 | 2020-12-01 | Arm Limited | Simulation of transactions |
CN109324838B (zh) * | 2018-08-31 | 2022-05-10 | 深圳市元征科技股份有限公司 | 单片机程序的执行方法、执行装置及终端 |
US10761822B1 (en) * | 2018-12-12 | 2020-09-01 | Amazon Technologies, Inc. | Synchronization of computation engines with non-blocking instructions |
US10521383B1 (en) * | 2018-12-17 | 2019-12-31 | Micron Technology, Inc. | Handling operation collisions in a non-volatile memory |
US20220300610A1 (en) * | 2019-06-20 | 2022-09-22 | Technion Research & Development Foundation Limited | Secured speculative execution processor |
CN110960857B (zh) * | 2019-12-03 | 2023-06-02 | 米哈游科技(上海)有限公司 | 一种游戏数据监控方法、装置、电子设备及存储介质 |
US11954465B2 (en) * | 2021-12-13 | 2024-04-09 | Intel Corporation | Apparatuses, methods, computer programs, and data carriers for indicating and detecting atomic operations |
WO2023205387A1 (en) * | 2022-04-21 | 2023-10-26 | Microchip Technology Incorporated | Atomic instruction set and architecture with bus arbitration locking |
Family Cites Families (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4819234A (en) * | 1987-05-01 | 1989-04-04 | Prime Computer, Inc. | Operating system debugger |
US5428761A (en) * | 1992-03-12 | 1995-06-27 | Digital Equipment Corporation | System for achieving atomic non-sequential multi-word operations in shared memory |
JPH0615138U (ja) * | 1992-07-22 | 1994-02-25 | 株式会社熊谷組 | 中央処理装置 |
US5751985A (en) | 1995-02-14 | 1998-05-12 | Hal Computer Systems, Inc. | Processor structure and method for tracking instruction status to maintain precise state |
KR100500002B1 (ko) * | 1996-08-27 | 2005-09-08 | 마츠시타 덴끼 산교 가부시키가이샤 | 복수의명령흐름을독립적으로처리하고,명령흐름단위로처리성능을유연하게제어하는멀티스레드프로세서 |
UA55489C2 (uk) * | 1997-10-07 | 2003-04-15 | Каналь+ Сосьєте Анонім | Пристрій для багатопотокової обробки даних (варіанти) |
US6795966B1 (en) * | 1998-05-15 | 2004-09-21 | Vmware, Inc. | Mechanism for restoring, porting, replicating and checkpointing computer systems using state extraction |
US6401155B1 (en) * | 1998-12-22 | 2002-06-04 | Philips Electronics North America Corporation | Interrupt/software-controlled thread processing |
US6892258B1 (en) * | 2001-10-26 | 2005-05-10 | Lsi Logic Corporation | Hardware semaphores for a multi-processor system within a shared memory architecture |
US6799236B1 (en) * | 2001-11-20 | 2004-09-28 | Sun Microsystems, Inc. | Methods and apparatus for executing code while avoiding interference |
US7657880B2 (en) | 2003-01-31 | 2010-02-02 | Intel Corporation | Safe store for speculative helper threads |
US6862664B2 (en) * | 2003-02-13 | 2005-03-01 | Sun Microsystems, Inc. | Method and apparatus for avoiding locks by speculatively executing critical sections |
US20040163082A1 (en) | 2003-02-13 | 2004-08-19 | Marc Tremblay | Commit instruction to support transactional program execution |
US7418577B2 (en) | 2003-02-13 | 2008-08-26 | Sun Microsystems, Inc. | Fail instruction to support transactional program execution |
US7269717B2 (en) * | 2003-02-13 | 2007-09-11 | Sun Microsystems, Inc. | Method for reducing lock manipulation overhead during access to critical code sections |
WO2005062170A2 (en) * | 2003-12-18 | 2005-07-07 | Koninklijke Philips Electronics N.V. | Method and compilation system for translating source code into executable code |
US7984248B2 (en) * | 2004-12-29 | 2011-07-19 | Intel Corporation | Transaction based shared data operations in a multiprocessor environment |
US7882339B2 (en) * | 2005-06-23 | 2011-02-01 | Intel Corporation | Primitives to enhance thread-level speculation |
-
2005
- 2005-06-23 US US11/165,639 patent/US7882339B2/en not_active Expired - Fee Related
-
2006
- 2006-06-23 GB GB0907512A patent/GB2457181B/en not_active Expired - Fee Related
- 2006-06-23 GB GB0721281A patent/GB2441665B/en not_active Expired - Fee Related
- 2006-06-23 CN CN200680022486.2A patent/CN101203831B/zh not_active Expired - Fee Related
- 2006-06-23 DE DE112006004265T patent/DE112006004265A5/de not_active Withdrawn
- 2006-06-23 CN CN201010175491.5A patent/CN101833475B/zh not_active Expired - Fee Related
- 2006-06-23 WO PCT/US2006/024727 patent/WO2007002550A2/en active Application Filing
- 2006-06-23 JP JP2008518482A patent/JP5415069B2/ja not_active Expired - Fee Related
- 2006-06-23 DE DE112006001698T patent/DE112006001698T5/de not_active Ceased
-
2010
- 2010-12-16 US US12/970,040 patent/US20110087867A1/en not_active Abandoned
-
2011
- 2011-08-15 JP JP2011177640A patent/JP5479416B2/ja not_active Expired - Fee Related
- 2011-12-08 US US13/314,826 patent/US8332619B2/en active Active
-
2012
- 2012-11-13 US US13/675,910 patent/US20130073835A1/en not_active Abandoned
-
2013
- 2013-04-12 JP JP2013083679A patent/JP2013168168A/ja active Pending
-
2015
- 2015-01-23 JP JP2015010769A patent/JP2015111439A/ja active Pending
Also Published As
Publication number | Publication date |
---|---|
DE112006001698T5 (de) | 2008-04-30 |
US20120084536A1 (en) | 2012-04-05 |
US20060294326A1 (en) | 2006-12-28 |
JP2009501366A (ja) | 2009-01-15 |
CN101833475B (zh) | 2014-04-16 |
DE112006004265A5 (de) | 2013-07-04 |
JP2015111439A (ja) | 2015-06-18 |
GB0721281D0 (en) | 2007-12-12 |
JP2011227934A (ja) | 2011-11-10 |
JP2013168168A (ja) | 2013-08-29 |
GB2441665B (en) | 2009-12-09 |
GB2441665A (en) | 2008-03-12 |
WO2007002550A2 (en) | 2007-01-04 |
US8332619B2 (en) | 2012-12-11 |
CN101833475A (zh) | 2010-09-15 |
US20130073835A1 (en) | 2013-03-21 |
CN101203831B (zh) | 2011-09-14 |
GB0907512D0 (en) | 2009-06-10 |
WO2007002550A3 (en) | 2007-05-31 |
CN101203831A (zh) | 2008-06-18 |
US20110087867A1 (en) | 2011-04-14 |
JP5479416B2 (ja) | 2014-04-23 |
GB2457181A (en) | 2009-08-12 |
GB2457181B (en) | 2009-12-23 |
US7882339B2 (en) | 2011-02-01 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5415069B2 (ja) | スレッドレベルの投機実行を拡張するためのプリミティブ | |
US6675192B2 (en) | Temporary halting of thread execution until monitoring of armed events to memory location identified in working registers | |
US9069605B2 (en) | Mechanism to schedule threads on OS-sequestered sequencers without operating system intervention | |
US9626187B2 (en) | Transactional memory system supporting unbroken suspended execution | |
US7584332B2 (en) | Computer systems with lightweight multi-threaded architectures | |
US20060117316A1 (en) | Hardware multithreading systems and methods | |
US20120079246A1 (en) | Apparatus, method, and system for providing a decision mechanism for conditional commits in an atomic region | |
JP2002508564A (ja) | 実行パイプラインの外部に複数のプログラム・カウンタとトレース・バッファを有するプロセッサ | |
CN107003896B (zh) | 具有共享事务处理资源的装置和数据处理方法 | |
JP2002508568A (ja) | 不適正順序マルチスレッド実行を実行するロード命令およびストア命令を順序付けるシステム | |
JP2002508567A (ja) | 誤推論後の命令再実施のためのアウトオブパイプライン・トレース・バッファ | |
AU2011305091A1 (en) | Apparatus, method, and system for dynamically optimizing code utilizing adjustable transaction sizes based on hardware limitations | |
CN111133418B (zh) | 在例外屏蔽更新指令之后允许未中止的事务处理 | |
GB2563116B (en) | Apparatus and method for determining a recovery point from which to resume instruction execution following handling of unexpected change in instruction flow | |
US10346196B2 (en) | Techniques for enhancing progress for hardware transactional memory | |
US20050283783A1 (en) | Method for optimizing pipeline use in a multiprocessing system | |
US10275250B2 (en) | Defer buffer |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20110215 |
|
A601 | Written request for extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A601 Effective date: 20110513 |
|
A602 | Written permission of extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A602 Effective date: 20110520 |
|
A601 | Written request for extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A601 Effective date: 20110610 |
|
A602 | Written permission of extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A602 Effective date: 20110617 |
|
A601 | Written request for extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A601 Effective date: 20110712 |
|
A602 | Written permission of extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A602 Effective date: 20110720 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20110815 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20120515 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20120815 |
|
A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20130108 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20130412 |
|
A911 | Transfer to examiner for re-examination before appeal (zenchi) |
Free format text: JAPANESE INTERMEDIATE CODE: A911 Effective date: 20130423 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20130702 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20130911 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20131015 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20131113 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
LAPS | Cancellation because of no payment of annual fees |