JP5396224B2 - Liquid crystal display - Google Patents

Description

  The present invention relates to a liquid crystal display device, and more particularly to a liquid crystal display device called a lateral electric field method.

  A liquid crystal display device referred to as a horizontal electric field method is configured to rotate liquid crystal molecules in a plane parallel to the planes of a pair of substrates that sandwich the liquid crystal, and has excellent so-called wide viewing angle characteristics. be able to.

  FIG. 5 is a cross-sectional view of a pixel showing an example of such a liquid crystal display device. Of the first substrate SUB1 and the second substrate SUB2 that are disposed to face each other with the liquid crystal LC interposed therebetween, the pixel electrode PX and the counter electrode CT that are disposed on the liquid crystal LC side surface of the first substrate SUB1 via the insulating film IN. And are arranged. The counter electrode CT is formed as a planar pattern, for example, in the lower layer of the insulating film IN, and the pixel electrode PX is formed as a plurality of linear patterns arranged in parallel on the upper layer of the insulating film IN. Note that a first alignment film ORI1 that determines the initial alignment direction of the molecules of the liquid crystal LC is formed on the pixel electrode PX. An electric field is generated between the pixel electrode PX and the counter electrode CT, and the molecules of the liquid crystal LC are driven by this electric field.

  FIG. 5 is a diagram drawn corresponding to FIG. 1 showing an embodiment of the present invention. For this reason, refer to the description in FIG. 1 for the configuration other than the configuration described above in FIG.

  As a document related to the present invention, for example, a liquid crystal display device shown in Patent Document 1 below is known. Patent Document 1 discloses a configuration in which the insulating film IN between adjacent pixel electrodes PX is removed in the configuration shown in FIG. 5 until the underlying counter electrode CT is exposed.

JP 2007-183299 A

  However, in the liquid crystal display device shown in FIG. 5, the equivalent circuit shown in FIG. 6 is formed in the vicinity of the first alignment film ORI1 by the capacitance and resistance of the first alignment film ORI1. In FIG. 6, the equivalent circuit shows, for example, the interface resistance R1 between the pixel electrode PX and the first alignment film ORI1 along the electric field lines (indicated by an arrow EF in FIG. 5) of the electric field from the pixel electrode PX to the counter electrode CT. The parallel connection body of the capacitor C4 of the first alignment film ORI1 and the resistor R4, the parallel connection body of the resistor R2 of the first alignment film ORI1 and the capacitor C2 of the liquid crystal LC, and the capacitance C4 and the resistor R4 of the first alignment film ORI1 The parallel connection body and the capacitor C3 of the insulating film IN are grasped as a circuit connected in series.

  For this reason, a DC current I flows in the first alignment film ORI1, and charges are accumulated (residual DC) in the insulating film IN by the DC current I. When such residual DC is accumulated in the insulating film IN, so-called burning or flicker occurs.

  In this case, the generation of the DC current can be suppressed by increasing the resistance of the first alignment film ORI1. However, in the case where a DC current is generated in the insulating film IN, there arises a disadvantage that the residual DC is difficult to be removed and the burn-in is difficult to disappear.

  Further, by adopting the configuration shown in Patent Document 1 described above, the above-described burn-in can be reduced, but unevenness due to a step between the surface of the counter electrode CT and the surface of the pixel electrode PX becomes large, and the liquid crystal LC The flattening of the side surface will be impaired. This means that the unevenness is reflected on the surface of the first alignment film ORI1 formed over the counter electrode CT and the pixel electrode PX, and a reliable rubbing process cannot be performed, resulting in an alignment failure.

  An object of the present invention is to provide a liquid crystal display device in which image sticking is greatly reduced without impairing the flatness of the surface on the liquid crystal side.

  In the liquid crystal display device of the present invention, the first alignment film ORI1 described above is formed in, for example, a two-layer structure, and the resistance of the layer on the pixel electrode PX side is made larger than the resistance of the layer on the liquid crystal LC side. It is.

  The configuration of the present invention can be as follows, for example.

(1) A liquid crystal display device of the present invention includes a first substrate and a second substrate that are disposed to face each other with a liquid crystal interposed therebetween.
Oite in a pixel region of the liquid crystal-side surface of the first substrate, wherein together with first providing the first electrode to form on the substrate side, on the surface of the liquid crystal side of the first electrode is formed via an insulating film Providing a second electrode having a plurality of linear patterns ,
With the one pixel electrode of the first electrode and the second electrode, the other one is configured as a counter electrode,
A liquid crystal display device comprising a first alignment film that is formed in contact with the liquid crystal covering the second electrode,
In the first alignment film ,
It is a layer provided on the second electrode side, covering the entire surface on the liquid crystal side of the second electrode and the entire surface on the liquid crystal side of the insulating film between the plurality of second electrodes. A first layer;
A second layer that is provided on the liquid crystal side and overlaps the entire surface of the first layer on the liquid crystal side, and is formed in contact with the liquid crystal on the liquid crystal side;
Provided,
The resistance of the first layer, characterized by greater than the resistance of the second layer.

(2) The liquid crystal display device of (1), the first alignment film, the resistance of the first layer, and the order of from 1,015 to 1,016 (Omega · cm), the second layer the resistor, characterized in that is obtained by the order of 1013~1014 (Ω · cm).

(3) The liquid crystal display device of the present invention, Oite in (2), a second alignment film formed in contact with the liquid crystal to a surface of the liquid crystal side of the second substrate, the second alignment film Is characterized by being formed on the order of 1013 to 1014 (Ω · cm).

(4) In the liquid crystal display device of the present invention, in (1), the first electrode is configured as a counter electrode, and is configured to be electrically connected to a first electrode of an adjacent pixel, and the second electrode is The pixel electrode is configured to be electrically separated from the second electrode of the adjacent pixel.

(5) In the liquid crystal display device of the present invention, in (1), the first electrode is configured as a pixel electrode, and is configured to be electrically separated from the first electrode of an adjacent pixel, and the second electrode is It is configured as a counter electrode, and is configured to be electrically connected to a second electrode of an adjacent pixel.

(6) The liquid crystal display device of the present invention is characterized in that, in (1), each of the first electrode and the second electrode is formed of a light-transmitting conductive film.

  The above-described configuration is merely an example, and the present invention can be modified as appropriate without departing from the technical idea. Further, examples of the configuration of the present invention other than the above-described configuration will be clarified from the entire description of the present specification or the drawings.

  The liquid crystal display device configured as described above can significantly reduce image sticking without impairing the flatness of the liquid crystal side surface.

  Other effects of the present invention will become apparent from the description of the entire specification.

FIG. 3 is a configuration diagram illustrating a liquid crystal display device according to a first embodiment of the present invention, and is a cross-sectional view taken along the line II of FIG. It is a top view which shows the outline of the liquid crystal display device of this invention. It is a top view which shows the structure of the pixel of the liquid crystal display device of this invention. It is an equivalent circuit diagram for demonstrating the effect of the liquid crystal display device of this invention. It is a block diagram which shows the example of the conventional liquid crystal display device, and is sectional drawing shown corresponding to FIG. It is an equivalent circuit diagram which shows the inconvenience of the conventional liquid crystal display device.

  Embodiments of the present invention will be described with reference to the drawings. In each drawing and each example, the same or similar components are denoted by the same reference numerals and description thereof is omitted.

<Overall configuration>
FIG. 2 is a plan view schematically showing Example 1 of the liquid crystal display device of the present invention. In FIG. 2, there are a first substrate SUB1 and a second substrate SUB2 that are arranged to face each other with a liquid crystal (not shown) interposed therebetween. The second substrate SUB2 is arranged on the viewer side. A backlight (not shown) is arranged on the back surface of the first substrate SUB1. The second substrate SUB2 has a slightly smaller area than the first substrate SUB1, and the lower side SD of the first substrate SUB1 in the figure is exposed. A semiconductor device (chip) SEC is mounted on the lower side SD of the first substrate SUB1 in the drawing. The semiconductor device SEC is a control circuit that drives each pixel in a display area AR described later. A sealing material SL for fixing the first substrate SUB1 is formed around the second substrate SUB2, and the sealing material SL also has a function of sealing liquid crystal.

  A region surrounded by the sealing material SL is a display region AR. On the liquid crystal side surface of the display area AR of the first substrate SUB1, gate signal lines GL extending in the x direction in the drawing and juxtaposed in the y direction, and extending in the y direction in the drawing and aligned in the x direction. A drain signal line DL is provided. A region surrounded by a pair of adjacent gate signal lines GL and a pair of adjacent drain signal lines DL constitutes a pixel region. As a result, the display area AR has a large number of pixels arranged in a matrix.

  In each pixel region, as shown in FIG. A which is an equivalent circuit diagram within a dotted elliptic frame in the figure, a thin film transistor TFT which is turned on by a signal (scanning signal) from the gate signal line GL, and a drain through this thin film transistor TFT A pixel electrode PX to which a signal (video signal) from the signal line DL is supplied and a counter electrode CT for generating an electric field between the pixel electrode PX are formed. The electric field has a component parallel to the surface of the first substrate SUB1, and the alignment state of the molecules of the liquid crystal changes while remaining horizontal to the surface of the first substrate SUB1. This type of liquid crystal display device is called, for example, a horizontal electric field method. The counter electrode CT is supplied with a reference signal serving as a reference for the video signal, for example, via a common signal line CL that runs parallel to the gate signal line GL.

Note that the gate signal line GL, the drain signal line DL, and the common signal line CL are connected to the semiconductor device SEC by unillustrated lead lines, respectively. The gate signal line GL has a scanning signal, and the drain signal line DL has a video signal. The reference signal is supplied to the common signal line CL.

<Pixel configuration>
FIG. 3 is a plan view of the pixel formed on the liquid crystal side of the first substrate SUB1, showing the configuration of the pixel shown in FIG. 2A. FIG. 1 is a cross-sectional view taken along the line II in FIG. 3 and is drawn together with the second substrate SUB2.

  In FIG. 3, a gate signal line GL extending in the x direction and arranged in parallel in the y direction is formed on the liquid crystal side surface (front surface) of the first substrate SUB1 (see FIG. 1). These gate signal lines GL define pixel regions together with drain signal lines DL described later. The gate signal line GL is formed with a protruding portion PJ protruding to the pixel region side, and this protruding portion PJ constitutes a gate electrode GT of a thin film transistor TFT described later.

  An insulating film GI (see FIG. 1) is formed on the surface of the first substrate SUB1 so as to cover the gate signal line GL (gate electrode GT). This insulating film GI functions as a gate insulating film of the thin film transistor TFT in the formation region of the thin film transistor TFT, and functions as an interlayer insulating film of these signal lines at the intersection of the gate signal line GL and the drain signal line DL. ing.

  An island-shaped semiconductor layer AS made of, for example, amorphous silicon is formed on the upper surface of the insulating film GI at least at a position overlapping with the gate electrode GT. The semiconductor layer AS is a semiconductor layer of the thin film transistor TFT. By forming the drain electrode DT and the source electrode ST so as to face each other on the upper surface of the semiconductor layer AS, a so-called bottom gate structure MIS (Metal Insulator Semiconductor) type thin film transistor TFT is formed.

  Here, the drain electrode DT and the source electrode ST are formed simultaneously with the formation of the drain signal line DL, for example. The drain signal line DL extends in the y direction in the drawing and is formed side by side in the x direction, and the drain electrode DT is formed by extending a part of the drain signal line DL on the semiconductor layer AS. Yes. The source electrode ST extends to the outside of the region where the semiconductor layer AS is formed, and is formed integrally with a pad portion PD disposed adjacent to the semiconductor layer AS. The pad portion PD has a relatively large area, and functions as a contact portion with a pixel electrode PX described later.

  A protective film PAS is formed on the surface of the first substrate SUB1 so as to cover the drain signal line DL, the thin film transistor TFT, and the pad portion PD. This protective film PAS avoids direct contact with the liquid crystal of the thin film transistor TFT, and stabilizes the characteristics of the thin film transistor TFT. The protective film PAS is formed, for example, by sequentially stacking a first protective film PAS1 made of an inorganic insulating film and a second protective film PAS2 made of an organic insulating film. By using an organic insulating film that can be formed by coating on the upper layer of the protective film PAS, the surface can be planarized.

  On the upper surface of the protective film PAS, for example, a counter electrode CT made of a light-transmitting conductive film made of ITO (Indium Tin Oxide) is formed. The counter electrode CT is formed over the entire display area AR, and is formed as an electrode to which a common signal (reference signal) is supplied to each pixel. However, the counter electrode CT has an opening OP so as to overlap the region where the pad portion PD is formed. Since the pad portion PD serves as a contact portion with the pixel electrode PX as described above, a short circuit between the pixel electrode PX and the counter electrode CT in this portion is prevented by the opening OP. Yes. The counter electrode CT formed in this way is formed in a planar pattern in each pixel.

  An insulating film IN is formed on the surface of the first substrate SUB1 so as to cover the counter electrode CT. This insulating film IN functions as an interlayer insulating film between the counter electrode CT and a pixel electrode PX described later.

  On the insulating film IN in the pixel region, a pixel electrode PX made of, for example, an ITO (Indium Tin Oxide) translucent conductive film is formed. The pixel electrode PX is formed by, for example, a linear pattern of electrodes extending in the y direction in the figure and arranged in parallel (for example, four) in the x direction. Each electrode of the pixel electrode PX is formed as a pattern connected to each other at both ends. The end of the pixel electrode PX on the thin film transistor TFT side is formed so as to cover the formation part of the pad part PD, and is connected to the pad part PD through the through hole TH formed in the insulating film IN and the protective film PAS. It has become so. As a result, the pixel electrode PX is electrically connected to the source electrode ST of the thin film transistor TFT. The through hole TH is formed in the opening OP of the counter electrode CT so that the counter electrode CT is not exposed on the side wall of the through hole TH.

  A first alignment film ORI1 is formed on the surface of the first substrate SUB1 so as to cover the pixel electrode PX. Here, in the first embodiment, the first alignment film ORI1 is, for example, 2 of the upper alignment film URI disposed on the liquid crystal layer side and the lower alignment film DRI disposed on the first substrate side (or the pixel electrode PX side). It is formed as a layer structure. In the first alignment film ORI1, the lower alignment film (indicated by symbol DRI in the drawing) on the pixel electrode PX side is a material having a higher resistance than the upper alignment film (indicated by symbol URI in the drawing) on the liquid crystal LC side. Is formed. For example, the resistance of the upper alignment film URI is on the order of 1013 to 1014 (Ω · cm), whereas the resistance of the lower alignment film DRI is high on the order of 1015 to 1016 (Ω · cm).

  The first alignment film ORI1 is formed by, for example, forming a lower alignment film DRI by applying a high-resistance resin film, and then forming an upper alignment film URI by applying a low-resistance resin film, and then the surface of the upper alignment film URI Is formed by rubbing. In this case, the resin film having a high resistance can be formed by, for example, applying a soluble polyimide, and the resin film having a low resistance is formed by, for example, applying a resin containing polyamic acid and then baking the resin. Can do.

  Note that the first substrate SUB1 configured in this manner is arranged so that the second substrate SUB2 is opposed to the liquid crystal LC via the liquid crystal LC, and the surface of the second substrate SUB2 on the liquid crystal LC side is in contact with the liquid crystal LC. A two-alignment film ORI2 is formed. The resistance of the second alignment film ORI2 is, for example, on the order of 1013 to 1014 (Ω · cm), and is substantially the same as the resistance of the upper alignment film URI of the first alignment film ORI1. A black matrix, a color physical, and the like are usually formed on the surface of the second substrate SUB2 shown in FIG. 1 on the liquid crystal LC side, but these drawings are omitted.

  FIG. 4 shows an equivalent circuit of the first alignment film ORI1 along the electric field line EF of the electric field from the pixel electrode PX to the counter electrode CT, for example, in the liquid crystal display device configured as described above. In FIG. 4, the first alignment film ORI1 including the lower alignment film DRI and the upper alignment film URI is indicated by a dotted line. As shown in FIG. 4, the equivalent circuit includes an interface resistance R1 between the pixel electrode PX and the lower alignment film DRI, a capacitance C1 of the lower alignment film DRI, a resistance R2 of the upper alignment film URI, and a parallel connection of the capacitance C2 of the liquid crystal. It can be grasped as a circuit in which the capacitor C1 of the lower alignment film DRI and the capacitor C3 of the insulating film IN are connected in series. In this case, since the lower alignment film DRI has a high resistance as described above, it can be assumed that there is no resistance shown in FIG. 6 in this portion, and the flow of the DC current shown in FIG. 6 is generated. It can be configured without making it. For this reason, residual DC is not accumulated in the insulating film IN, and so-called burning or flicker generation can be suppressed. Further, even if a DC current is generated in the insulating film IN, the residual DC generated in the insulating film IN can pass through the upper alignment film URI having a low resistance, and the baking is likely to disappear. (Recover).

  In the first embodiment described above, the first alignment film ORI1 has a two-layer structure, and the lower alignment film DRI is formed in the high resistance layer and the upper alignment film URI is formed in the low resistance layer. However, the first alignment film ORI1 is not necessarily limited to the two-layer structure, and may be formed in a multilayer rather than two layers. In this case, an effect similar to that shown in the first embodiment can be obtained by making a layer having higher resistance in the layer on the pixel electrode PX side than the layer on the liquid crystal LC side.

  In addition, when the first alignment film ORI1 is configured in a multilayer structure in this way, the resistance is accompanied by a step change at the interface of each layer. However, even when the resistance on the pixel electrode PX side is smoothly larger than the resistance on the liquid crystal LC side, the first alignment film ORI1 can achieve the same effect as shown in the first embodiment. For this reason, the first alignment film ORI1 does not necessarily have to be composed of multiple layers as long as a smooth resistance distribution can be formed in the film thickness direction.

  In the first embodiment described above, the pixel of the liquid crystal display device has a configuration in which the pixel electrode PX having a plurality of linear patterns is provided on the upper surface of the counter electrode CT having a planar pattern via the insulating film IN. It is. However, the present invention is not limited thereto, and the electrode configured as the above-described planar pattern may be configured as the pixel electrode PX, and the electrode configured as the above-described plurality of linear patterns may be configured as the counter electrode CT. This is because there is no change in the distribution of the electric field generated between the pixel electrode PX and the counter electrode CT regardless of which of the planar pattern electrode and the plurality of linear pattern electrodes is the pixel electrode PX. In this case, since an independent video signal is supplied to each pixel, the pixel electrode PX is configured to be electrically separated from the pixel electrode PX of an adjacent pixel, and the counter electrode CT is common to each pixel. Since the reference signal is supplied, it is configured to be electrically connected to the counter electrode CT of the adjacent pixel. Further, both the pixel electrode PX and the counter electrode CT may be linear electrodes.

  The present invention has been described using the embodiments. However, the configurations described in the embodiments so far are only examples, and the present invention can be appropriately changed without departing from the technical idea. Further, the configurations described in the respective embodiments may be used in combination as long as they do not contradict each other.

SUB1 ... first substrate, SUB2 ... second substrate, SL ... seal material, AR ... display region, SEC ... semiconductor device (chip), GL ... gate signal line, DL ... drain signal line, CL ...... Common signal line, TFT ... Thin film transistor, PX ... Pixel electrode, CT ... Counter electrode, GI ... Insulating film, PAS ... Protective film, PAS1 ... Inorganic insulating film, PAS2 ... Organic insulating film, IN ...... Insulating film, ORI1 ... first alignment film, URI ... upper alignment film, DRI ... lower alignment film, LC ... liquid crystal, ORI2 ... second alignment film, EF ... electric field lines.

Claims (7)

A first substrate and a second substrate disposed to face each other with a liquid crystal sandwiched therebetween,
Oite in a pixel region of the liquid crystal-side surface of the first substrate, wherein together with first providing the first electrode to form on the substrate side, on the surface of the liquid crystal side of the first electrode is formed via an insulating film Providing a second electrode having a plurality of linear patterns ,
With the one pixel electrode of the first electrode and the second electrode, the other one is configured as a counter electrode,
A liquid crystal display device comprising a first alignment film that is formed in contact with the liquid crystal covering the second electrode,
In the first alignment film ,
It is a layer provided on the second electrode side, covering the entire surface on the liquid crystal side of the second electrode and the entire surface on the liquid crystal side of the insulating film between the plurality of second electrodes. A first layer;
A second layer that is provided on the liquid crystal side and overlaps the entire surface of the first layer on the liquid crystal side, and is formed in contact with the liquid crystal on the liquid crystal side;
Provided,
The liquid crystal display device, wherein a resistance of said first layer is greater than the resistance of the second layer. The first alignment film includes:
The resistance of the first layer is on the order of 1015 to 1016 (Ω · cm) ,
The liquid crystal display device according to claim 1 in which the resistance of the second layer, and characterized in that that the order of 1013~1014 (Ω · cm). A second alignment film formed in contact with the liquid crystal is provided on the liquid crystal side surface of the second substrate, and the resistance of the second alignment film is formed on the order of 1013 to 1014 (Ω · cm) . The liquid crystal display device according to claim 2 . The first electrode is configured as a counter electrode, and is configured to be electrically connected to a first electrode of an adjacent pixel, and the second electrode is configured as a pixel electrode, and the second electrode of the adjacent pixel is The liquid crystal display device according to claim 1 , wherein the liquid crystal display device is configured to be electrically separated . The first electrode is configured as a pixel electrode, and is configured to be electrically separated from a first electrode of an adjacent pixel, and the second electrode is configured as a counter electrode, and the second electrode of the adjacent pixel is The liquid crystal display device according to claim 1 , wherein the liquid crystal display device is configured to be electrically connected . The liquid crystal display device according to claim 1, wherein each of the first electrode and the second electrode is made of a light-transmitting conductive film . The liquid crystal display device according to claim 1, wherein the first electrode is formed in a planar pattern, and the second electrode is formed in a linear pattern .

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