JP5382158B2 - Organic EL pixel circuit - Google Patents

Description

  The present invention relates to a pixel circuit including a light emitting element such as an organic EL element, and more particularly to a layout thereof.

  Conventionally, an organic EL panel using an organic EL element is known, and development thereof is progressing. In this organic EL panel, organic EL elements are arranged in a matrix and display is performed by individually controlling the light emission of the organic EL elements. In particular, an active matrix type organic EL panel has a display control TFT for each pixel, and the light emission for each pixel can be controlled by the operation control of the TFT. Therefore, display with very high accuracy can be performed.

  FIG. 12 shows an example of a pixel circuit in an active matrix type organic EL panel. The data line DL to which the data voltage indicating the luminance of the pixel is supplied is connected to the gate of the driving TFT 12 via the n-channel selection TFT 10 whose gate is connected to the gate line GL. In addition, one end of the storage capacitor 14 whose other end is connected to the capacitor line SC is connected to the gate of the drive TFT 12 to hold the gate voltage of the drive TFT 12.

  The source of the driving TFT 12 is connected to the EL power supply line, the drain is connected to the anode of the organic EL element 16, and the cathode of the organic EL element 16 is connected to the cathode power supply.

  Such pixel circuits are arranged in a matrix. At a predetermined timing, the gate line provided for each horizontal line becomes H, and the selection TFT 10 in that row is turned on. In this state, since the data voltage is sequentially supplied to the data line, the data voltage is supplied and held in the holding capacitor 14, and the voltage at that time is held even if the gate line becomes L.

  Then, according to the voltage held in the holding capacitor 14, the driving TFT 12 operates and a corresponding driving current flows to the cathode power source through the organic EL element 16 from the EL power source, and the organic EL element 16 becomes the data voltage. It emits light in response.

  Then, the gate lines are sequentially set to H, and the input video signals are sequentially supplied as data voltages to the corresponding pixels, so that the organic EL elements 16 arranged in a matrix emit light according to the data voltages, and the video An indication about the signal is made.

  Here, in such a pixel circuit, if the threshold voltage of the driving TFTs of the pixel circuits arranged in a matrix varies, there is a problem that the luminance varies and the display quality is deteriorated. It is difficult to make the characteristics of the TFTs constituting the pixel circuit of the entire display panel the same, and it is difficult to prevent the on / off threshold value from varying.

Therefore, for example, the following Patent Documents 1 and 2 have been proposed as a circuit for preventing the influence on the fluctuation of the threshold value of the TFT.
Special table 2002-514320 gazette JP-A-2005-128521

  However, these proposals require two or more control lines for controlling each pixel circuit. That is, in the circuit of FIG. 5 described above, only the gate line may be used as the other control line of the data line and the power supply line extending in the vertical direction. However, in Patent Documents 1 and 2, at least two controls other than the gate line are required. Need a line.

  Accordingly, there is a problem that not only this control line but also a connection line between the control line and the transistor is increased and the aperture ratio is decreased.

  Therefore, it is desired to efficiently arrange the wiring and maintain the aperture ratio relatively high.

The present invention is a display device in which pixels are arranged in a matrix, and each pixel is turned on / off by a selection signal from a gate line, and one end of the pixel is connected to the data line to control reception of a data signal from the data line. A selection transistor; and a driving transistor that has one end connected to the power supply line and applies a voltage according to the data signal received through the selection transistor to the gate, thereby causing a current from the power supply line to flow according to the data signal. The light emitting element connected to the other end side of the driving transistor and emitting light according to the current flowing through the driving transistor, and one end connected to the path where the voltage according to the data signal is applied to the gate of the driving transistor, It is turned on / off by a signal from a capacitance set line that is commonly provided for pixels in one row. A potential control transistor, a short-circuit transistor that is turned on and off by a signal from the gate line and short-circuits between the gate of the drive transistor and the other end of the drive transistor, and is disposed between the other end of the drive transistor and the light-emitting element. A drive control transistor that is turned on and off by a signal from a light emission set line that is provided in common to the pixels of the pixel, and the short-circuit transistor and the drive control transistor are connected to each other by a semiconductor layer that forms the transistor, a short-circuit transistor is connected to the same gate line, the gate line is characterized Rukoto disposed between the light-emitting set line and capacitance set line.

  In particular, the semiconductor layer is preferably formed on the lower side in the thickness direction in the space between the power supply line and the data line.

The gate of the driving transistor is connected to the capacitor, the capacitor, it is also preferable that the same layer as the gate electrode of the selection transistor and the semiconductor layer forming the selection transistor is formed by opposing, further The effect is also exhibited by forming this capacitor so as to overlap the power supply line .

  Furthermore, it is also preferable to form both the semiconductor layers constituting the selection transistor and the short-circuit transistor so as to extend in parallel with the gate line.

  As described above, according to the present invention, two control lines other than the gate lines arranged in parallel to the gate lines are arranged with the gate lines interposed therebetween. As a result, the wiring can be arranged efficiently, and the aperture ratio can be made relatively large. In particular, by disposing at least one contact with the power supply line in the space between the gate line and the control line where no pixel electrode exists, a decrease in the aperture ratio can be suppressed.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 shows a configuration of a pixel circuit according to the embodiment. The data line DL extends in the vertical direction and supplies a data signal (data voltage Vsig) about the display luminance of the pixel to the pixel circuit. One data line DL is provided for one column of pixels, and sequentially supplies the data voltage Vsig of the pixel to the pixels in the vertical direction.

  The data line DL is connected to the drain of an n-channel selection transistor T1, and the source of the selection transistor T1 is connected to one end of a capacitor Cs. The gate of the selection transistor T1 is connected to a gate line GL extending in the horizontal direction.

  In addition, a capacitance set line CS is provided for one row of pixels, and the gate of a p-channel potential control transistor T2 is connected to the capacitance set line CS. The capacitance set line CS becomes L level shortly before the gate line GL becomes H level, and returns to L level after the gate line GL returns to L level. Accordingly, the potential control transistor T2 is turned off when the selection transistor T1 is on, and the potential control transistor T2 is turned on when the selection transistor T1 is off. The source of the potential control transistor T2 is connected to the power supply line PVdd, and the drain is connected to the capacitor Cs and the source of the selection transistor T1. The power supply line PVdd also extends in the vertical direction, and supplies the power supply voltage PVdd to each pixel in the vertical direction.

  The other end of the capacitor Cs is connected to the gate of the p-channel drive transistor T4. The source of the drive transistor T4 is connected to the power supply line PVdd, and the drain is connected to the drain of the n-channel drive control transistor T5. The source of the drive control transistor T5 is connected to the anode of the organic EL element EL, and the gate is connected to the light emission set line ES extending in the horizontal direction. The cathode of the organic EL element EL is connected to a low voltage cathode power source CV.

  Furthermore, the drain of the n-channel short-circuit transistor T3 is connected to the gate of the drive transistor T4, the source of the short-circuit transistor T3 is connected to the drain of the drive transistor T4, and the gate is connected to the gate line GL. .

  As described above, in the present embodiment, two lines of the data line DL and the power supply line PVdd are arranged in the vertical direction, and in addition to the gate line GL, the capacitor set line CS and the light emission set line ES are arranged in the horizontal direction. Two control lines are arranged.

  Next, the operation of this pixel circuit will be described.

  As shown in FIG. 2, this pixel circuit includes (i) discharge (GL = H level, CS = depending on the state (H level, L level) of the gate line GL, the capacitor set line CS, and the light emission set line ES. L level, ES = H level), (ii) reset (GL = H level, CS = L level, ES = L level), (iii) potential fixed (GL = L level, CS = H level, ES = L level) ), (Iv) There are four states of light emission (GL = L level, CS = H level, ES = H level), which are repeated. That is, in a state where the data on the data line DL is valid, (i) discharge is performed, and then (ii) the charging voltage of the capacitor Cs is determined by reset, and the gate voltage Vg is fixed in (iii) (v ) The organic EL element EL emits light with a driving current corresponding to the fixed gate voltage. The capacitance set line CS is at the L level when the gate line GL is at the H level as described above, and is at the H level when the gate line GL is at the L level. Thus, the selection transistor T1 and the potential control transistor T2 are prevented from being turned on simultaneously by returning to the H level after returning to the L level of the gate line GL.

  Further, as shown in the drawing, the data in the data line DL becomes valid before (i) the discharge process, and (iii) becomes invalid after the fixing process. Therefore, valid data is set in the data line from (i) the discharge process to (iii) the fixing process.

Hereinafter, each state will be described. Note that the off transistors in FIGS. 3 to 6 are indicated by broken lines.
(I) Discharge (GL = H level, CS = L level, ES = H level)
First, in a state where the data voltage Vsig is supplied to the data line DL, both the gate line GL and the light emission set line ES are set to H level (high level), and the capacitor set line CS is set to L level. As a result, the selection transistor T1, the drive control transistor T5, and the short-circuit transistor T3 are turned on, and the potential control transistor T2 is turned off. Therefore, as shown in FIG. 3, in the state where the voltage Vn = Vsig on the selection transistor T1 side of the capacitor Cs, the current from the power supply line PVdd passes through the drive transistor T4, the drive control transistor T5, and the organic EL element EL, and the cathode power supply CV. As a result, the charge held at the gate of the drive transistor T4 is extracted. As a result, the gate voltage Vg of the drive transistor T4 becomes a predetermined low voltage.
(Ii) Reset (GL = H level, CS = L level, ES = L level)
The light emission set line ES is changed to L level (low level) from the above discharge state. As a result, as shown in FIG. 4, the drive control transistor T5 is turned off, and the gate voltage Vg = Vg0 = PVdd− | Vtp | of the drive transistor T4 is reset. Here, Vtp is the threshold voltage of the drive transistor T4. That is, since the gate of the drive transistor T4 is short-circuited between the gate and the drain by the short circuit transistor T3 in a state where the source is connected to the power source PVdd, the gate voltage of the drive transistor T4 from the power source PVdd is | It is set to a voltage lower by Vtp | and turned off. At this time, the potential Vn of the capacitor Cs on the side of the selection transistor T1 = Vsig, and the capacitor Cs is charged with a voltage of | Vsig− (PVdd− | Vtp |) |.
(Iii) Potential fixed (GL = L level, CS = H level, ES = L level)
Next, the gate line GL is set to L level, the selection transistor T1 and the short-circuit transistor T3 are turned off, and then the capacitance set line CS is set to H level to turn on the potential control transistor T2. Thereby, as shown in FIG. 5, the gate of the drive transistor T4 is disconnected from the drain. When the potential control transistor T2 is turned on, Vn = PVdd. Therefore, the gate potential Vg of the driving transistor T4 shifts according to the change in Vn. Since a parasitic capacitance Cp exists between the gate and source of the drive transistor T4, the gate potential Vg is affected by this Cp.
(Iv) Light emission (GL = L level, CS = H level, ES = H level)
Next, by setting the light emission set line ES to the H level, as shown in FIG. 6, the drive control transistor T5 is turned on, whereby the drive current from the drive transistor T4 flows to the organic EL element EL. The drive current at this time is the drain current of the drive transistor T4, which is determined by the gate voltage of the drive transistor T4. This drain current is not related to the threshold voltage Vtp of the drive transistor T4. It is possible to suppress fluctuations in the amount of light emission accompanying fluctuations in threshold voltage.

  This will be described with reference to FIG.

  As described above, (ii) After resetting, Vn (= Vsig) is a value between Vsig (max) and Vsig (min), and Vg is driven from PVdd, as indicated by ◯ in the figure. The voltage Vg0 is reduced by the threshold voltage Vtp of the transistor T4. That is, Vg = Vg0 = PVdd + Vtp (Vtp <0) and Vn = Vsig.

  Then, when the potential is fixed at (iii), Vn changes from Vsig to PVdd, so that the change amount ΔVg takes into account the capacity of Cs and Cp, and ΔVg = Cs (PVdd−Vsig) / (Cs + Cp ).

  Therefore, Vn and Vg are Vn = PVdd, Vg = Vtp + ΔVg = PVdd + Vtp + Cs (PVdd−Vsig) / (Cs + Cp), as indicated by ● in the figure.

  Here, since Vgs = Vg−PVdd, Vgs = Vtp + Cs (PVdd−Vsig) / (Cs + Cp).

On the other hand, the drain current I is expressed as I = (1/2) β (Vgs−Vtp) ^2. By substituting the above equation, the drain current I is expressed as follows.
I = (1/2) β {Vtp + Cs (PVdd−Vsig) / (Cs + Cp) −Vtp} ²
= (1/2) β {Cs (PVdd−Vsig) / (Cs + Cp)} ²
= (1/2) βα (Vsig-PVdd) ²
Here, α = {Cs / (Cs + Cp)} ² , β is the drive transistor T4 amplification factor, β = μεGw / Gl, μ is the carrier mobility, ε is the dielectric constant, Gw is the gate width, Gl Is the gate length.

  Thus, Vtp is not included in the expression of the drain current I, and is proportional to the square of Vsig−PVdd. Therefore, it is possible to achieve light emission according to the data voltage Vsig by eliminating the influence of the variation in threshold voltage of the drive transistor T4.

  In the above description, only the operation for one pixel has been described. Actually, the display panel has pixels arranged in a matrix, and for each of them, the data voltage Vsig corresponding to the corresponding luminance signal is supplied to cause each organic EL element to emit light. That is, as shown in FIG. 8, the display panel is provided with a horizontal switch circuit HSR and a vertical switch VSR, and these outputs change the states of the data line DL, gate line GL, and other light emission set lines ES. Be controlled. In particular, one gate line GL is associated with each pixel in the horizontal direction, and the gate lines GL are sequentially activated one by one by the vertical switch VSR. Next, in one horizontal period in which one gate line GL is activated, the horizontal switch HSR supplies data voltages to all the data lines DL in a dot-sequential manner, and this writes data to the pixel circuits for one horizontal line. . Each pixel circuit emits light according to the data voltage written until after one vertical period.

  Next, a data writing procedure for each pixel in one horizontal line will be described with reference to FIG.

  First, after the L level of the enable signal ENB indicating the start of one horizontal period, the data voltage Vsig is written dot-sequentially to all the data lines DL. That is, a capacitor or the like is connected to the data line DL, and the data voltage Vsig is held in the data line DL by setting a voltage signal. Therefore, the data voltage Vsig for the pixels in each column is sequentially set to the corresponding data line DL, thereby setting the data voltage Vsig to all the data lines DL.

  Then, at the stage where this data setting is completed, Hout is set to H level and the gate line GL is activated to H level, and operation is performed for each pixel in the one horizontal direction described above, and data writing and light emission in each pixel are performed. Done.

  In this way, a normal video signal (data voltage Vsig) can be sequentially written into the data line DL, and this can be set in the pixel circuit to emit light.

  Next, another method will be described with reference to FIG. In this example, during the period when the enable line ENB is at the L level, the light emission set line ES is set to the L level, and when the enable line ENB rises to the H level, the gate line GL is set to the H level (activation). In this state, the data voltage Vsig is sequentially set to the data line DL. When the data voltage Vsig is set to all the data lines DL, the light emission set line ES is set to the H level, the above discharge is performed, and then the light emission set line ES is returned to the L level. The gate line GL returns to the L level in synchronization with the fall of the enable line ENB, and returns the enable line ENB to the H level when the enable line ENB is at the L level. As a result, the same operation as in the above example is performed. Note that the capacitance set line CS is at the L level during the period when the gate line GL is at the H level, goes to the L level slightly earlier than the rising edge of the gate line GL, and returns to the H level slightly later than the falling edge.

  FIG. 11 shows a layout of a display panel using the pixel circuit described in FIG.

  First, the capacitor set line CS extends along the upper end of the pixels in each row. In the pixel in the figure, a data line DL extends in the column direction at the right end portion of each pixel. A power supply line PVdd extends in the column direction substantially parallel to the left side of each data line DL. In the pixel in the lower stage of the illustrated pixel, the data line DL and the power supply line PVdd are arranged at the left end portion of each pixel.

  In addition, a gate line GL extends across the pixel at a slightly upper part of the pixel. A light emission set line ES is disposed along the lower end of each pixel.

  A portion of the gate line GL close to the right end of the pixel is provided with a protruding portion upward, and this is the gate electrode T1g of the n-channel selection transistor T1. That is, a semiconductor layer 112 is provided below the gate electrode T1g in the thickness direction through a gate insulating film. The semiconductor layer 112 extends along the gate line GL, and the right end thereof is connected to the data line DL by a contact. Has been.

  In addition, the semiconductor layer 112 extends to the left below the gate electrode T1g, and spreads in a substantially square shape in the direction of the capacitance set line CS. A capacitor electrode SC having the same layer as the gate electrode is formed through the gate insulating film in the rectangular portion, and a portion corresponding to the semiconductor layer 112 through the gate insulating film is formed in the capacitor electrode SC. It has become.

  A part of the semiconductor layer 112 constituting the capacitor Cs extends to the right along the capacitor set line CS, and is connected to the power supply line PVdd by a contact. Further, a protruding portion from the capacitor set line CS is located above the intermediate portion of the semiconductor layer 112 on the capacitor Cs side and the power supply line PVdd side, and this protruding portion is located on the semiconductor via a gate insulating film. This is an n-channel potential control transistor T2 located above the layer 112 in the thickness direction.

  A contact is provided immediately above the gate line GL at the center of the pixel of the capacitor Cs, and a metal wiring 118 is connected by this contact. The metal wiring 118 crosses the gate line GL and reaches the lower side of the gate line GL. The semiconductor layer 120 is connected by a contact.

  This semiconductor layer 120 extends rightward once, then extends downward along the data line DL and the power supply line PVdd, and is provided with a branch portion extending to the left at the middle portion, and before the light emitting set line ES. And turn left. A protruding portion extending from the gate line GL is provided above the thickness direction of the portion extending rightward along the gate line GL of the semiconductor layer 120 via a gate insulating film, and this is provided on the gate electrode T3g of the n-channel short-circuit transistor T3. It has become. That is, this portion constitutes a short-circuit transistor T3 that connects between the gate and source of the drive transistor T4.

  The metal wiring 118 is connected to a gate wiring on the same layer as the gate line GL by a contact below the contact connected to the short-circuit transistor T3, and this gate wiring extends in parallel with the power supply line PVdd, which is a p-channel driving transistor. This is the gate electrode T4g of T4. That is, a semiconductor layer 132 extending in the vertical direction is provided below the gate electrode T4g in the thickness direction through a gate insulating film, and one end (drain: upper side in the figure) of the semiconductor layer 132 is connected to the power supply line PVdd by a contact. It is connected. The lower side of the semiconductor layer 132 in the drawing is once bent to the left side, and then connected to a metal wiring by a contact, and is connected to a branch part extending from the intermediate portion of the semiconductor layer 120 to the left side by the contact with the metal wiring.

  Further, the lower end portion of the semiconductor layer 120 extends to the left along the light emission set line ES, and a part of the light emission set line ES protrudes through the gate insulating film above the thickness direction of this portion, and the n-channel A gate electrode T5g of the drive control transistor T5 is formed, and the drive control transistor T5 is formed here. A pixel electrode is connected to a left end portion of the lower end of the semiconductor layer 120 through a contact. Then, a cathode common to all the pixels is formed above the pixel electrode in the thickness direction via the organic light emitting layer to form an organic EL element.

  As for the thickness direction, a TFT is formed on a transparent substrate such as glass, a transparent electrode (anode) for each pixel is formed thereon, and a cathode such as aluminum common to all pixels is formed thereon via an organic light emitting layer. Is formed. In the TFT, a buffer layer is first formed on a glass substrate, and semiconductor layers 112, 120, and 132 are formed at predetermined positions thereon. A gate insulating film is formed so as to cover the semiconductor layer, and a gate line GL, a capacitor electrode, and the like are formed thereon with molybdenum, chromium, or the like. An interlayer insulating film is formed so as to cover the layer such as the gate line GL, and metal (for example, aluminum) wiring such as the power line PVdd and the data line DL are formed thereon. Then, a flattening layer such as an acrylic resin is formed so as to cover these metal wirings, and a transparent electrode (pixel electrode) such as ITO or IZO is formed thereon.

  As described above, according to the present embodiment, the capacitor set line CS is disposed on the upper side in the pixel diagram, the light emission set line ES is disposed on the lower side in the pixel diagram, and the gate line GL extends from the capacitor set line CS. It is arranged slightly below.

  With such an arrangement, the potential control transistor T2 and the selection transistor T1 can be arranged above the gate line GL. In particular, by arranging the selection transistor T1 along the gate line GL, the protruding portion of the gate line GL can be used as the gate electrode T1g of the selection transistor T1. On the other hand, since the potential control transistor T2 is formed along the capacitor set line CS, the gate electrode T2g can be easily formed. Further, the contact of the potential control transistor T2 with the power supply line PVdd is also located at the corner of the pixel, so that the arrangement is efficient. The capacitor Cs can be formed in the space between the potential control transistor T2 and the selection transistor T1, and the space above the gate line GL can be effectively used.

  In addition, since the short-circuit transistor T3 is disposed along the lower side of the gate line GL and the drive control transistor T5 is formed along the light emission set line ES, the gate electrodes T3g and T5g of the short-circuit transistor T3 and the drive control transistor T5 can be easily provided. Can be formed. Further, since the connection between the short-circuit transistor T3 and the drive control transistor T5 is the semiconductor layer 120, and this is disposed on the lower side in the thickness direction of the space between the power supply line PVdd and the data line DL, the influence of this wiring on the aperture ratio is affected. Less. Further, since the drive transistor T4 is arranged along the power supply line PVdd, the reduction in the aperture ratio is suppressed and the arrangement is efficient.

  Further, the layout as shown in FIG. 11 can be similarly applied to a circuit in which two horizontal control lines exist in addition to the gate lines. For example, the present invention can be applied to a circuit described in Patent Document 1.

It is a figure which shows the structure of the pixel circuit which concerns on embodiment. It is a chart figure explaining operation. It is a figure explaining a discharge process. It is a figure explaining a reset process. It is a figure explaining an electric potential fixing process. It is a figure explaining a light emission process. It is a figure explaining the state of the potential change in a potential fixing process from reset. It is a figure which shows the whole structure of a panel. It is a figure which shows the example of a timing of a data set. It is a figure which shows the other timing example of a data set. It is a figure which shows the layout of the pixel circuit of embodiment. It is a figure which shows an example of the conventional pixel circuit.

  T1 selection transistor, T2 potential control transistor, T3 short-circuit transistor, T4 drive transistor, T5 drive control transistor, 112, 120, 132 semiconductor layer, 118 metal wiring, CS capacitor set line, Cs capacitor, DL data line, EL organic EL element , ES light emission set line, GL gate line, PVdd power line.

Claims (6)

A display device in which pixels are arranged in a matrix,
Each pixel is
A selection transistor that is turned on and off by a selection signal from the gate line, one end of which is connected to the data line and controls reception of the data signal from the data line;
One end is connected to a power supply line, and a voltage according to the data signal received through the selection transistor is applied to the gate, thereby causing a drive transistor to flow a current from the power supply line according to the data signal;
A light emitting element that is connected to the other end of the driving transistor and emits light in response to a current flowing through the driving transistor;
A potential control transistor having one end connected on a path through which a voltage corresponding to the data signal is applied to the gate of the drive transistor, and being turned on / off by a signal from a capacitance set line provided in common to pixels in one row; ,
A short-circuit transistor that is turned on and off by a signal from the gate line and short-circuits between the gate of the drive transistor and the other end of the drive transistor;
A drive control transistor that is disposed between the other end of the drive transistor and the light emitting element and is turned on and off by a signal from a light emission set line provided in common to pixels in one row;
Including
The short-circuit transistor and the drive control transistor are connected to each other by a semiconductor layer forming the transistor ,
The selection transistor and the short-circuit transistor is connected to the same the gate line, the gate line, a display device according to claim Rukoto disposed between the said capacitive load lines emission set line. The display device according to claim 1,
The display device, wherein the semiconductor layer is formed on a lower side in a thickness direction in a space between the power line and the data line. The display device according to claim 1 or 2,
A display device, wherein a gate of the driving transistor is connected to a capacitor. The display device according to claim 3 ,
The capacity display device, characterized in that the same layer as the gate electrode of the selection transistor and the semiconductor layer forming the selection transistor is formed by opposed. The display device according to claim 4 ,
The display device, wherein the capacitor is formed so as to overlap with a power supply line . The display device according to any one of claims 1 to 5,
The semiconductor device which comprises the said selection transistor and the said short circuit transistor extends in parallel with the said gate line, The display apparatus characterized by the above-mentioned.