JP5342027B2 - Non-volatile memory - Google Patents

Description

  The present invention relates to a non-volatile memory that achieves a higher reading speed.

  FIG. 9 is a circuit diagram showing a configuration example of a sense amplifier of a conventional flash memory (nonvolatile memory). In this figure, P channel (hereinafter referred to as Pch) transistors 1a and 2a constitute a precharge circuit 101a, and Pch transistors 3a and 4a constitute a load circuit 102a. Pch transistors 1a and 3a are switching transistors, and 2a and 4a are load transistors. The transistor 2a is for quick charging, and the gate width of the transistor is set to 2a> 4a. Further, the transistor 5a has an N-channel (hereinafter referred to as Nch) transistor having a threshold value of approximately zero volts, to which a bias signal BIAS1 of about 1.0 V is input to the gate, and 6a is a column gate signal CG selected by a column address. Nch transistor 7a is a memory cell to which a word line WL selected by a row address is input to the gate. Similarly, a circuit composed of the transistors 1b to 6b and the reference cell 7b is made symmetrical. In this case, the reference cell 7b is a memory cell for comparison with the memory cell 7a, and the reference voltage RefWL is input to the gate. A circuit composed of the Nch transistor 6b and the reference cell 7b is referred to as REFCELL1.

  Outputs SAIN and REFIN of these circuits are input to a differential amplifier circuit 104 composed of Pch transistors 8, 9 and 10 and Nch transistors 11 and 12. Reference numeral 13 denotes a discharge Nch transistor for fixing the differential output SAOUT to a reference voltage for a certain period, and reference numeral 103 denotes a buffer inverter for amplifying the differential output SAOUT. The connection point between the column gate transistor 6a and the bias transistor 5a is connected to the data line HON1. Data is read from the plurality of memory cells 7a to the data line HON1 through a plurality of column gates 6a selected by a column decoder (not shown). Similarly, the connection point between the transistor 5b and the transistor 6b is connected to the reference line REF1.

  As described above, in a general sense amplifier having no page mode function, a circuit on the memory cell side and a circuit on the reference side are provided on a one-to-one basis with respect to the differential amplifier circuit 104 in order to balance the capacitance.

  FIG. 10 is a circuit in which an Nch transistor 3001 for equalizing the data line HON1 and the reference line REF1 is provided in the above circuit, and the transistor 3001 is turned on at the precharge timing to perform equalization. Uniformity and speeding up of operations at the time of reading are attempted.

  By the way, in recent years, with an increase in the functionality of the system, there is an increasing demand for speeding up the memory used. Therefore, in a flash memory, a function such as a page mode or a burst mode is added to continuously read a large amount of data. However, when the page mode function or the like is adopted, for example, when the page function of 8 words is adopted, normally only 16 sense amplifiers for word reading require 16 × 8 pages = 128, and the above-mentioned reference side is required. Since 128 circuits (101b, 102b, 5b, REFCELL1) are also required, the area of the sense amplifier becomes very large. For this reason, as shown in FIG. 11, one REFCELL 1 is provided for four sense amplifiers, and a method of reducing the area of a configuration for supplying a reference current to the sense amplifiers 1 to 4 has been taken.

  Next, the operation of the circuit shown in FIG. 11 will be described. FIG. 12 shows the waveform of each part. When the precharge signal / PRE and the activation signal / SEN become Low, precharge starts and SAIN and REFIN are charged. Since the transistors 1a and 1b are for quick charging, SAIN and REFIN are quickly charged to the level of Vcc-Vthp. The data lines HON1 to HON4 and REF1 are charged to the level of about BIAS1 through the bias transistors 5a and 5b. When the precharge is completed, / PRE becomes High, the switching transistors 1a and 1b are turned off, and SAIN, HON1, and REFIN and REF1 are the load transistor 4a and the memory cell 7a or the load transistor 4b and the reference cell 7b. The potential is determined by.

  In FIG. 12, when the memory cell 7a is on (“1”), SAIN (“1”) and HON1 (“1”) are set. When the memory cell 7a is off (“0”), SAIN ("0"), HON1 ("0"), and the reference cell 7b is set so that an intermediate current flows, and thus has a waveform as shown in FIG. When the precharge is just finished, the gate voltage SENa of the discharging transistor 13 becomes Low, and the output SAOUT of the differential amplifier circuit 104 is output. The differential output SAOUT is amplified by the inverter 103, and a BUFOUT signal is output. The precharge time is t1, and the time t2 from the end of precharge until the output of BUFOUT is the read speed of the sense amplifier. Note that SAIN and REFIN rise immediately after the end of precharge due to coupling noise when the transistors 1a and 1b are turned off.

According to the configuration described above, the chip area can be reduced as compared with the case where REFCELL1 (reference numerals 6b and 7b) is provided corresponding to the memory cells. In the configuration described above, the sizes of the input side transistors 9 and 11 and the reference side transistors 10 and 12 of the differential amplifier circuit 104 are set to 3: 1 in order to achieve a certain amount of capacitance balance and speed up of the differential output SAOUT. The degree is set.
Patent Document 1 is known as a prior art document.

JP 2005-285215 A

The circuit of FIG. 11 described above has the following problems.
(1) Since the memory cell side and the reference cell side are configured to be unbalanced, the equalization method as in the circuit of FIG. 10 cannot be adopted. Therefore, when the bit line is precharged, the charging speed of the data line HON1 and the reference line REF1 varies, and the inputs SAIN and REFIN of the differential amplifier circuit 104 also vary. For this reason, there is a difference between HON1 and REF1, and SAIN and REFIN at the start of sensing after precharge ends, and it is necessary to wait for the difference to be reduced, so the read time t2 is delayed.

(2) Since the data line HON1 and the reference line REF1 are charged through the bias transistor 5a or 5b from the precharge circuit 101a or 101b, the precharge circuit 101a, 101b and bias transistors 5a and 5b need to be enlarged. In this case, a large transistor must be placed in a sense amplifier having a complicated layout, which increases the sense amplifier area and the wiring distance. It gets worse.

  The present invention has been made in view of the above circumstances, and an object thereof is to provide a nonvolatile memory capable of reducing the chip area on the reference side and performing high-speed reading.

The present invention has been made to solve the above-described problems. In the nonvolatile memory according to the present invention, a plurality of sense amplifiers and a bit line selected from a plurality of bit lines are connected, and the memory cells in the memory cell array are connected. each of a plurality of data lines data is connected to the sense amplifier to be read out, the which is connected to the sense amplifier, and Le reference line data of the reference cell is read, and the reference line and the plurality of data lines A first precharge circuit for charging the plurality of data lines and the reference line, one common line, a second precharge circuit for charging the common line, and each of the data lines, a first transistor provided between between the common line, a second transitional provided between the common line and the Le reference line And a motor, wherein the first transistor and the second transistor is turned on, the all of the data lines and the reference line connected to the sense amplifier, the second charging and equalization to a common voltage at the same time and it executes the pre-charge circuit, by the first precharge circuit is charging the data line and the reference line, the charging and equalization by the second pre-charge circuit the first transistor and the second transistor is turned off After the termination, the charging by the first precharge circuit is terminated after a predetermined time .

In the nonvolatile memory according to the present invention, the predetermined time is a time for recovering a drop in voltage received by the data line and the reference line due to coupling noise when the first transistor and the second transistor are turned off. It is characterized by being.
The nonvolatile memory of the present invention converts the first signal supplied from the outside into a signal that changes between a power supply voltage and a constant voltage that is lower than the power supply voltage for turning off the first transistor and the second transistor. And a level converting circuit for converting.

The nonvolatile memory of the present invention is characterized in that the first transistor and the second transistor have a threshold value of approximately zero volts.
The nonvolatile memory according to the present invention is characterized in that the precharge circuit is arranged in the vicinity of a central portion in the length direction of the data line and the reference line.

  According to the present invention, the charging circuit for equalization and charging is provided, and the data line and the reference line are equalized and charged immediately before the data of the memory cell is read. Therefore, all the data lines and the reference line are equalized and charged at the same time. Thus, even when there is an imbalance between the memory cell side and the reference side, high-speed and stable operation can be achieved. As a result, the number of circuits on the reference side can be reduced to minimize the chip area, and high-speed and stable reading can be achieved. As a result, a sense amplifier having a high-speed operation margin can be realized.

It is a block diagram which shows the structure of the charging circuit used in the non-volatile memory by 1st Embodiment of this invention. It is a wave form diagram for demonstrating operation | movement of the charging circuit. It is a wave form diagram for demonstrating operation | movement of the charging circuit. It is a block diagram which shows the structure of the principal part of the charging circuit used in the non-volatile memory by 2nd Embodiment of this invention. It is a block diagram which shows the structure of the charging circuit used in the non-volatile memory by 3rd Embodiment of this invention. It is a wave form diagram for demonstrating operation | movement of the charging circuit. It is a block diagram which shows the structure of the charging circuit used in the non-volatile memory by 4th Embodiment of this invention. FIG. 6 is a component layout diagram of a nonvolatile memory according to first to fourth embodiments of the present invention. It is a circuit diagram which shows the structural example of the sense amplifier of the conventional non-volatile memory. It is a circuit diagram which shows the other structural example of the sense amplifier of the conventional non-volatile memory. It is a circuit diagram which shows the further another structural example of the sense amplifier of the conventional non-volatile memory. FIG. 12 is a waveform diagram for explaining the operation of the sense amplifier shown in FIG. 11.

Hereinafter, a first embodiment of the present invention will be described with reference to the drawings. In the flash memory (nonvolatile memory) according to this embodiment, 128 circuits of the same sense amplifier as the sense amplifier 1 shown in FIG. 11 are provided, and the same REFCELL as the REFCELL 1 (reference numerals 6b and 7b in FIG. One circuit is provided per amplifier, for a total of 32 circuits.
FIG. 1 is a block diagram showing a configuration of a charging circuit 11 provided in the flash memory. In this figure, data lines HON1, HON2,..., HON128, reference lines REF1, REF2,. , Lines connected to the 128 sense amplifiers and 32 REFCELLs described above. The configuration so far is the same as the conventional one.

  In the figure, reference numerals 201 to 328 and R201 to R232 denote equalizing Nch transistors (FETs). The drains of the transistors 201 to 328 are connected to the data lines HON1 to HON128, respectively, and the drains of the transistors R201 to R232 are respectively reference. Connected to lines REF1 to REF32. The sources of the transistors 201 to 328 and R201 to R232 are connected to the common line COM, and the common line COM is connected to the source of the transistor EQ202 of the precharge circuit 401. The gates of the transistors 201 to 328 and R201 to R232 are commonly connected, and a signal EQ is externally applied to this common connection point.

  The precharge circuit 401 includes a Pch transistor EQ201 and the Nch transistor EQ202 described above. The drain of the transistor EQ201 is connected to the positive power supply terminal (voltage: Vcc), and the source is connected to the drain of the transistor EQ202. The gate of the transistor EQ201 is grounded, so that the transistor EQ201 functions as a load resistor. The transistor EQ202 is a transistor having a threshold value of zero volts, and a bias voltage BIAS1 (see FIG. 11) is applied to the gate thereof.

  FIG. 2 shows operation waveforms of each part of the charging circuit 11. Although / PRE, / SEN, and SENa are the same as those in FIG. 12, the precharge period t11 is set shorter than the precharge period t1 in FIG. The signal EQ rises simultaneously with the start of precharge and ends in a period t33 shorter than the precharge signal / PRE. The data lines HON1, HON2,..., HON128, and reference lines REF1, REF2,..., REF32 are connected to the precharge circuits 101a and 101b shown in FIG. The precharge circuit 401 is quickly charged. Further, since they are equalized by being commonly connected through the transistors 201 to 328 and R201 to R232, they are sufficiently charged in the period t11, and the data line HON and the reference line REF are equally charged. As is apparent from FIG. 12, the data line HON and the reference line REF are not uniformly charged in the conventional one, resulting in variations in the charging time, and therefore it takes a lot of time for precharging.

  In addition, since the data lines HON1, HON2,..., HON128 and the reference lines REF1, REF2,..., REF32 are charged uniformly and at high speed, the sense amplifier input signals SAIN, REFIN (FIG. 11). ) Is stably charged at high speed, and as a result, the read period t22 (FIG. 2) after the precharge is completed is read at a higher speed in a shorter time than the conventional read period t2 (FIG. 12).

  Here, the reason for setting t33 <t11 will be described with reference to the enlarged view of FIG. In FIG. 3, when equalization and quick charge are finished and the signal EQ becomes low, the data lines HON1, HON2,..., HON128, the reference line REF1 are coupled with the gates of the transistors 201 to 328 and R201 to R232. , REF2,..., REF32 receive coupling noise, causing a drop of about ΔV1 = 0.01V. We have some time to recover from this drop.

Next, a second embodiment of the present invention will be described with reference to FIG. In the second embodiment, the above-described coupling noise is reduced.
In the second embodiment, the signal EQ in FIG. 1 is not directly applied to the gates of the transistors 201 to 328 and R201 to R232, but the transistors 201 to 328 and R201 are connected via the EQ signal generation circuit 12 shown in FIG. ˜R232 is added to each gate.

  In FIG. 4, as the EQ signal generation circuit 12, Nch transistors 503 and 504, each having a gate connected to its own drain, are connected in series on the ground side of an inverter composed of a Pch transistor 501 and an Nch transistor 502. . The Nch transistor 505 is a transistor to which a reset signal RESET output from a reset circuit (not shown) is applied to the gate as necessary. Inverter 601 inverts signal EQ and outputs the inverted signal to the gates of transistors 501 and 502.

  In the above configuration, the signal EQ has an amplitude between the power supply voltage Vcc (for example, 3.0 V) and GND (0 V). For this reason, in the case of the configuration of FIG. 1, 3.0 V noise is applied as coupling noise. In the second embodiment, the high level is Vcc (3.0 V), but the low level is 2. × VthN (VthN is a threshold value of the Nch transistor). When VthN = 0.7V, the voltage is about 1.4V. As a result, the signal EQ2 output from the EQ signal generation circuit 12 becomes a signal having an amplitude between 3.0 V and 1.4 V, and the coupling noise is reduced to about half.

  Here, the precharge level of the data line HON is suppressed to about 1 V for the protection (reliability) of the memory cell and the high-speed charging. That is, since the level of the bias signal BIAS1 (FIGS. 1 and 11) is set to about 1V and the difference between the “1” level and the “0” level of the data line HON is about 0.1V, equalization and quick charge end When the signal EQ2 becomes 1.4V later, the equalizing transistors 201 to 328 and R201 to R232 are cut off. Therefore, even if the above EQ signal generating circuit 12 is inserted, there is no problem in operation.

Next, a third embodiment of the present invention will be described with reference to FIGS. This embodiment further reduces coupling noise.
In FIG. 5, reference numeral 13 is a circuit diagram showing the configuration of the charging circuit used in the flash memory according to the present embodiment. As shown in the figure, Nch transistors 701 and 702 having a threshold value of approximately zero volts between the common line COM and each data line HON1, HON2,..., HON128, reference lines REF1, REF2,. ,..., 828, R701, R702,. A bias signal BIAS2 is applied to the gates of these transistors, and a load transistor 901 for charging is connected to the common line COM.

  Reference numeral 1001 denotes a bias generation circuit that generates the bias signal BIAS2, and 1002 denotes a bias generation circuit that generates the bias signal BIAS1. These bias generation circuits 1001 and 1002 have the same configuration. The bias generation circuit 1002 is the same as the conventional one, and generates a bias signal BIAS1 of about 1 V and outputs it to each sense amplifier (FIG. 11). On the output side of the bias generation circuit 1001, there is provided an Nch transistor 1003 having a drain connected to the same output, a source connected to GND, and a signal CUT input to the gate. The output of the bias generation circuit 1001 is BIAS2. Applied to the gates of transistors 701-828 and R701-R732. Note that the Nch transistor 1003 is set very small (on-resistance is large).

  The waveform of each part of the circuit described above is shown in FIG. The precharge time is t111. In a period t333 where t333 ≦ t111, the CUT signal becomes low level, the transistor 1003 is turned off, and the bias signal BIAS2 becomes the same level as the bias signal BIAS1. Thereby, the transistors 701 to 828 and R701 to R732 are turned on, and the data lines HON1 to HON128 and the reference lines REF1 to REF32 are equalized and precharged. Next, when the signal CUT becomes high level, the transistor 1003 is turned on and the level of the bias signal BIAS2 is lowered. However, since the transistor 1003 is set very small, the capability of the bias generation circuit 1001 is surpassed and the level is lowered. The minute ΔV2 is about 0.1V.

  When the precharge is completed, the levels of the data lines HON1, HON2,..., HON128, the reference lines REF1, REF2, ..., REF32 are about 1.0 V, and the zero level of the data line HON is Since it becomes about 0.9 V, the transistors 701 to 828 and R701 to R732 are cut off. In this case, the coupling noises of the transistors 701 to 828 and R701 to R732 are so small that they are hardly affected, and if this embodiment is used, high speed can be realized without being influenced by the coupling noise.

Next, a fourth embodiment of the present invention will be described with reference to FIG.
In the figure, the charging circuit 14 has the same configuration as the charging circuit 3 shown in FIG. However, the bias signal BIAS3 is applied to the gates of the transistors 701 to 828 and R701 to R732. Reference numeral 2001 denotes a bias circuit that outputs a conventional bias signal BIAS1. Reference numeral 2002 denotes a bias circuit that outputs a bias signal BIAS3 (BIAS3 <BIAS1) that is slightly lower in level than the bias signal BIAS1. For example, BIAS1 = 1.0V and BIAS3 = 0.9V are set.

In this embodiment, when charging proceeds through the transistors 701 to 828 and R701 to R732, and the data line HON and the reference line REF are charged to about 0.9 V, the transistors 701 to 828 and R701 to R732 are automatically turned on. Since it is cut off, quick charging is possible without generating coupling noise.
Next, still another embodiment of the present invention will be described.

  In the first to fourth embodiments described so far, the case where the memory cell side and the reference side are imbalanced by the left and right inputs of the differential amplifier circuit 104 has been described as shown in FIG. The present invention is effective even in the case of a balanced type in which the left and right sides have the same configuration. That is, the data line HON and the reference line REF are equalized even if the charging circuits 11, 13, and 14 of FIGS. 1, 5, and 7 are connected to the data line HON and the reference line REF of the sense amplifier shown in FIG. While charging quickly.

  In addition, the above charging circuits 11, 13, and 14 can be applied to a flash memory using a sense amplifier provided with the equalizing Nch transistor 3001 shown in FIG. In this case, it may be combined with the circuit of FIG. 1, but the circuit of FIG. 5 is preferable because the area can be reduced.

  The gist of the present invention is to provide a circuit for performing rapid charging directly on the data line HON and the reference line REF, or to provide a circuit for applying equalization to the data line HON and the reference line REF. It is intended to reduce the area and increase the speed, and combinations of the embodiments are possible within the scope of this gist.

  FIG. 8 is an optimum layout diagram of each circuit block of the flash memory according to each of the above embodiments. A bit line (not shown) is selected from the memory cell array by a column gate and connected to the data lines HON1 to HON128. At the same time, reference data read from a reference circuit (not shown) is connected to the reference lines REF1 to REF32. The data lines HON1 to HON128 and the reference lines REF1 to REF32 are input to the sense amplifiers 1 to 128. The sense amplifiers are equally arranged 1 to 64 on the left side of the chip and 65 to 128 on the right side of the chip. The charging circuits 11, 13, and 14 according to the above embodiments are arranged in the vicinity of the center so that the left and right sides are as even as possible in consideration of the wiring resistance of the data lines.

  The embodiment of the present invention has been described in detail with reference to the drawings. However, the specific configuration is not limited to this embodiment, and includes design and the like within a scope not departing from the gist of the present invention.

  The present invention is mainly used for flash memories.

  The present invention includes a data line from which data of a memory cell is read and a reference line from which data of a reference cell is read, and a nonvolatile memory having one common reference line for the plurality of data lines. A charging circuit for equalizing and charging the data line and the reference line immediately before reading data of the memory cell is provided, and the charging circuit includes one common line, the common line, and each of the plurality of data lines. A plurality of first bias transistors for connecting the common line and the reference line, a second bias transistor for connecting the reference line, a precharge circuit for charging the capacitance of the common line, and a first signal supplied from the outside Power supply voltage, and the first bias transistor and the second bias transistor are turned off. And a level conversion circuit that converts the signal into a signal that changes between a constant voltage that is lower than the power supply voltage, and the first bias transistor and the second bias transistor are turned on by the first signal. By connecting the data line and the common line, connecting the reference line and the common line, equalizing the data line and the reference line, and the capacitance of the data line and the reference line A non-volatile memory characterized by charging.

  The present invention includes a data line from which data of a memory cell is read and a reference line from which data of a reference cell is read, and a nonvolatile memory having one common reference line for the plurality of data lines. A charging circuit for equalizing and charging the data line and the reference line immediately before reading data of the memory cell is provided, and the charging circuit includes one common line, the common line, and each of the plurality of data lines. A plurality of first bias transistors connected to each other, a second bias transistor connecting the common line and the reference line, and a precharge circuit for charging a capacitance of the common line, and the first bias transistor and The second bias transistor is driven by a first signal supplied from the outside. Connecting the data line and the common line, connecting the reference line and the common line, equalizing the data line and the reference line, and the data line and the reference line. The first bias transistor and the second bias transistor have a threshold value of approximately zero volts, a load element inserted between the common line and a power source, the first bias transistor, A bias circuit for applying a bias voltage to the gate of the two-bias transistor, wherein the bias circuit turns on the first bias transistor and the second bias transistor when the common line is before charging, and the common circuit When the capacitance of the line is charged, the first bias transistor and the second bias transistor A bias voltage for turning off the star is applied to the gates of the first bias transistor and the second bias transistor.

  The present invention is characterized in that the charging circuit is arranged in the vicinity of the central portion in the length direction of the data line and the reference line.

  The present invention includes a differential amplifier circuit that reads data in a memory cell by comparing voltages between the data line and the reference line.

DESCRIPTION OF SYMBOLS 11, 13, 14 ... Charging circuit 12 ... EQ signal generation circuit 201-328, R201-R232, 502-505, 1003 ... Nch transistor 401 ... Precharge circuit 601 ... Inverter 501, 901, EQ201 ... Pch transistor 701-828, R701 to R732, EQ202 ... Nch transistors 1001, 1002, 2001, 2002 ... Bias circuit with zero bias voltage

Claims (5)

Multiple sense amplifiers,
Bit lines selected from a plurality of bit lines are connected, and a plurality of data lines connected to the sense amplifier from which data of memory cells in the memory cell array is read,
Wherein is connected to the sense amplifier, and Le reference line data of the reference cell is read out,
A first precharge circuit that is provided on each of the plurality of data lines and the reference line and charges the plurality of data lines and the reference line;
One common line,
A second precharge circuit for charging the common line;
A first transistor provided between each of the data lines and the common line;
And a second transistor provided between the common line and the Le reference line,
The second precharge circuit performs charging and equalization in which the first transistor and the second transistor are turned on, and all the data lines and the reference lines connected to the sense amplifier are simultaneously set to a common voltage. In addition, the data line and the reference line are charged by the first precharge circuit, the first transistor and the second transistor are turned off, and charging and equalization by the second precharge circuit are terminated. The nonvolatile memory is characterized in that the charging by the first precharge circuit is terminated after a predetermined time . The predetermined time is a time for recovering a drop in a voltage received by the data line and the reference line due to coupling noise when the first transistor and the second transistor are turned off. The non-volatile memory according to 1. A level conversion circuit that converts a first signal supplied from the outside into a signal that changes between a power supply voltage and a constant voltage that is lower than the power supply voltage for turning off the first transistor and the second transistor; The nonvolatile memory according to claim 1 , wherein the nonvolatile memory is provided. 4. The nonvolatile memory according to claim 1, wherein a threshold value of the first transistor and the second transistor is approximately zero volts. 5. Wherein the precharge circuit, the nonvolatile memory according to any one of claims 1 to 4, characterized in that arranged in the central longitudinal portion near the data line and the reference line.

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