JP5330040B2 - Semiconductor device, semiconductor device, semiconductor wafer, and semiconductor crystal growth method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor element, a semiconductor device, a semiconductor wafer, and a method of growing semiconductor crystal such that warpage of a substrate is suppressed and an influence of interface reflection is reduced to achieve high light extraction efficiency and high internal light emission efficiency. <P>SOLUTION: The semiconductor element includes a sapphire substrate 105 which has a principal surface 106 comprising a (c) plane, and also has a recessed portion 110a formed on the principal surface, a first buffer layer 110 which is provided on the principal surface of the sapphire substrate and made of crystalline AlN, and a semiconductor layer 190 which is provided on the first buffer layer and made of a nitride semiconductor. The first buffer layer has a cavity 110a provided over the recessed portion of the sapphire substrate, and the first buffer layer has a first region 110e and a second region 110f provided between the first region and the sapphire substrate and having higher carbon concentration than the first region. <P>COPYRIGHT: (C)2010,JPO&amp;INPIT

Description

  The present invention relates to a semiconductor element, a semiconductor device, a semiconductor wafer, and a semiconductor crystal growth method.

  Nitride semiconductors are used in various semiconductor elements such as semiconductor light emitting elements and HEMT (High Electron Mobility Transistor) elements. In such a nitride semiconductor, for example, there is a problem that the wafer is warped or cracked due to a difference in thermal expansion coefficient between the sapphire substrate used and the nitride semiconductor formed thereon.

  A near-ultraviolet LED (Light Emitting Diode) element (for example, an emission wavelength of less than 400 nm, for example), which is a semiconductor light-emitting element using a nitride semiconductor, is expected as a phosphor excitation light source such as a white LED. Is a problem.

  One of the reasons for the low efficiency is a high density threading transition due to lattice mismatch between the sapphire substrate and the GaN crystal. On the other hand, the present inventor, instead of conventional low-temperature grown AlN or GaN, etc., includes a high-temperature-grown single-crystal AlN (including AlGaN having an Al composition) containing carbon or hydrogen at a high concentration on the substrate interface side. ) As a buffer layer, it has been found that the crystal quality of the GaN layer grown thereon can be greatly improved, and a highly efficient light-emitting device can be produced (for example, see Patent Document 1). In an element manufactured using this method, an internal luminous efficiency exceeding 70%, which is comparable to a visible LED, is realized.

  However, even in this case, since the refractive index is different between sapphire and the GaN-based mixed crystal, light emitted obliquely to the interface is reflected, and as a result, the efficiency is reduced to nearly half.

  On the other hand, in a visible LED such as a blue LED, on a sapphire substrate formed with unevenness arranged two-dimensionally on the surface, a low-temperature growth thin film such as AlN, GaN or AlGaN is provided via a low-temperature growth buffer layer. By growing a GaN layer and forming an element portion on a flattened surface, the influence of interface reflection is reduced and high efficiency is achieved (for example, see Patent Document 2).

  However, it is difficult to apply this technique using a low-temperature growth buffer layer to a thick high-temperature growth single crystal buffer layer. That is, AlN and AlGaN have low selectivity in the growth direction, and as a result, crystals grown in different orientations grow on an uneven crystal plane having surfaces in different directions, so that the grown crystal becomes polycrystalline.

  As described above, a technique for forming a high-temperature thick single-crystalline AlN layer (including AlGaN having a high Al composition) on a sapphire substrate on which unevenness arranged two-dimensionally on the surface is formed is as follows. It is not known, and it has not been possible to realize a semiconductor device with high internal light emission efficiency while reducing the influence of interface reflection and increasing light extraction efficiency.

Japanese Patent No. 3648386 US Pat. No. 6,870,191B2

  The present invention provides a semiconductor element, a semiconductor device, a semiconductor wafer, and a semiconductor crystal growth method capable of suppressing the warpage of a substrate and reducing the influence of interface reflection to realize high light extraction efficiency and high internal light emission efficiency.

According to one aspect of the present invention has a main surface formed of the c-plane, and the sapphire substrate recess in said main surface is provided, is provided on the front Symbol major surface, the first consisting of crystalline AlN 1 A buffer layer; and a semiconductor layer made of a nitride semiconductor and provided on the first buffer layer, the first buffer layer having a cavity provided on the recess of the sapphire substrate. The first buffer layer includes a first region, and a second region that is provided between the first region and the sapphire substrate and has a carbon concentration higher than that of the first region. A semiconductor element is provided in which the surface of the first buffer layer that is blocked and faces the semiconductor layer of the first buffer layer is flat.

According to another aspect of the invention, the semiconductor layer is provided on the first buffer layer, and is provided on the second buffer layer made of GaN or AlGaN, and on the second buffer layer. A semiconductor device comprising: an n-type semiconductor layer; a light-emitting layer provided on the n-type semiconductor layer; and a p-type semiconductor layer provided on the light-emitting layer, and emitting from the semiconductor device There is provided a semiconductor device comprising: a wavelength conversion layer that absorbs the emitted light and emits light having a wavelength different from that of the light.

Further, according to another aspect of the present invention has a main surface formed of the c-plane, and the sapphire substrate with a recess provided in the main surface, provided on the main surface, of a crystalline AlN A semiconductor wafer provided with a first buffer layer and a semiconductor layer formed on the first buffer layer and made of a nitride semiconductor , wherein the first buffer layer is formed on the concave portion of the sapphire substrate. The first buffer layer includes a first region and a second region having a higher carbon concentration than the first region, the first region being provided between the first region and the sapphire substrate; Have
The cavity is closed in the first buffer layer, and a surface of the first buffer layer facing the semiconductor layer is flat. Thus, a semiconductor wafer is provided.

According to another aspect of the present invention, a first surface of 1150 ° C. to 1200 ° C. is provided on the main surface of the sapphire substrate having a main surface composed of a c-plane and having a recess formed on the main surface. A first layer made of AlN is epitaxially grown by metalorganic vapor phase epitaxy using a temperature of 1 and a first group V / group III ratio of 0.7 to 50, and 1270 ° C. to A second layer made of AlN is epitaxially grown by metal organic vapor phase epitaxy using a second temperature of 1330 ° C. and a second group V / III ratio of 250 to 10,000, and on the second layer, Epitaxially growing a third layer made of AlN by metal organic vapor phase epitaxy using a third temperature that is 10 ° C. to 30 ° C. higher than the second temperature and a third group V / III ratio of 50 to 250 Forming a cavity above the recess, and Method for growing a semiconductor crystal, characterized in that the covering of three layers is provided.

  ADVANTAGE OF THE INVENTION According to this invention, the growth method of the semiconductor element which can suppress the curvature of a board | substrate, can reduce the influence of interface reflection, and can implement | achieve high light extraction efficiency and high internal light emission efficiency is provided. The

1 is a schematic cross-sectional view illustrating the configuration of a semiconductor element according to a first embodiment of the invention. FIG. 3 is a micrograph illustrating the configuration of a main part of the semiconductor element according to the first embodiment of the invention. It is a microscope picture figure which illustrates the surface state of the AlN layer of a 1st comparative example. It is a microscope picture figure which illustrates the surface state of the AlN layer of a 2nd comparative example, and a GaN layer. It is a microscope picture figure which illustrates the surface state of the AlN layer of the 3rd comparative example. FIG. 6 is a schematic view illustrating the operation of the semiconductor element according to the first embodiment of the invention. FIG. 6 is a schematic cross-sectional view illustrating the configuration of another semiconductor element according to the first embodiment of the invention. FIG. 6 is a schematic cross-sectional view illustrating the configuration of another semiconductor element according to the first embodiment of the invention. FIG. 6 is a schematic cross-sectional view illustrating the configuration of a semiconductor device according to a second embodiment of the invention. FIG. 6 is a schematic cross-sectional view illustrating the configuration of a semiconductor wafer according to a third embodiment of the invention. It is a flowchart figure which illustrates the growth method of the semiconductor crystal which concerns on the 4th Embodiment of this invention.

Embodiments of the present invention will be described below with reference to the drawings.
Note that the drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the ratio coefficient of the size between the parts, and the like are not necessarily the same as actual ones. Further, even when the same part is represented, the dimensions and ratio coefficient may be represented differently depending on the drawing.
Further, in the present specification and each drawing, the same reference numerals are given to the same elements as those described above with reference to the previous drawings, and detailed description thereof will be omitted as appropriate.

(First embodiment)
Below, the case where the 1st Embodiment of this invention is applied to a semiconductor light-emitting device is demonstrated.
FIG. 1 is a schematic cross-sectional view illustrating the configuration of a semiconductor element according to the first embodiment of the invention.
As shown in FIG. 1, the semiconductor element 11 according to the first embodiment of the present invention includes a sapphire substrate 105, a first buffer layer 110 provided on the main surface 106 of the sapphire substrate 105, and a first And a semiconductor layer 190 made of a nitride semiconductor provided on the buffer layer 110.

  In this specific example, the semiconductor layer 190 includes a second buffer layer 120 provided on the first buffer layer 110, an n-type semiconductor layer 140 provided on the second buffer layer 120, and an n-type semiconductor layer. The light emitting layer 150 provided on the light emitting layer 150 and the p-type semiconductor layer 160 provided on the light emitting layer 150 are included.

  The semiconductor element 11 includes a first electrode (n-side electrode 140e) electrically connected to the n-type semiconductor layer 140 and a second electrode (p-side electrode 160e) electrically connected to the p-type semiconductor layer 160. ) And.

  The main surface 106 of the sapphire substrate 105 is a c-plane of sapphire. That is, the main surface 106 is substantially parallel to the c-plane of sapphire.

  Here, in the present specification, “parallel” and “vertical” include strictly parallel and vertical, respectively, and include, for example, variations in the manufacturing process, and are substantially parallel and substantially vertical. Includes state.

  Desirable conditions regarding the angle between the normal line of the main surface 106 of the sapphire substrate 105 and the normal line of the c-plane of sapphire will be described later.

  The sapphire substrate 105 has a recess 105 a provided in the main surface 106. The recess 105 a is two-dimensionally arranged on the main surface 106.

  The first buffer layer 110 is made of crystalline AlN. However, AlN doped with, for example, GaN may be used. That is, for the first buffer layer 110, crystalline AlN containing AlGaN with a high Al composition is used. As will be described later, the first buffer layer 110 functions as a buffer layer.

  The first buffer layer 110 has a cavity 110a. The cavity 110 a is provided at a position corresponding to the recess 105 a of the sapphire substrate 105. That is, the cavity 110a is provided on the recess 105a.

  The upper surface of the first buffer layer 110 (the surface opposite to the main surface 106) is substantially flat. That is, the cavity 110a is provided on the lower surface of the first buffer layer 110 (the surface on the main surface 106 side), and the lower surface of the first buffer layer 110 has irregularities, but the upper surface of the first buffer layer 110 is The buffer layer 110 is flat without being affected by the presence of the cavity 110a on the lower surface side. For example, the upper surface of the first buffer layer 110 is planarized at the atomic level.

  That is, the cavity 110 a is closed by the upper surface of the first buffer layer 110. On the upper surface of the first buffer layer 110, the cavity 110a is not substantially open, and for example, the upper surface of the first buffer layer 110 is substantially free of irregularities due to the cavity 110a.

  The carbon concentration of the first buffer layer 110 on the sapphire substrate 105 side is higher than the concentration of the first buffer layer 110 on the side opposite to the sapphire substrate 105.

  That is, the first buffer layer 110 includes a first region 110e and a second region 110f provided between the first region 110e and the sapphire substrate 105 and having a higher carbon concentration than the first region 110e. In this specific example, the first region 110e is the second layer 112 and the third layer 113 illustrated in FIG. 1, and the second region 110f is the first layer 111 illustrated in FIG.

  The second buffer layer 120 is made of GaN or AlGaN. The second buffer layer 120 relaxes lattice distortion between the first buffer layer 110 and the n-type semiconductor layer 140.

Hereinafter, a specific example of the semiconductor element 11 will be described.
As the sapphire substrate 105, a sapphire substrate having a c-plane as the main surface 106 is used. The difference in angle between the normal of the c-plane and the normal of the sapphire substrate 105 is preferably 0.05 degrees or less, for example. On the main surface 106 of the sapphire substrate 105, for example, recesses 105a having a diameter of 2.0 μm (micrometer) and a depth of 1 μm are provided at an interval of 1.5 μm, for example.

A first buffer layer 110 is provided on the main surface 106 of the sapphire substrate 105.
The first buffer layer 110 includes, for example, a first layer 111, a second layer 112 provided on the first layer 111, and a third layer 113 provided on the second layer 112.

The first layer 111 is a first AlN buffer layer having a high carbon concentration. The carbon concentration in the first layer 111 is, for example, 1 × 10 ¹⁹ cm ^{−3 to} 5 × 10 ²⁰ cm ^−3, and the thickness of the first layer 111 is, for example, 3 nm (nanometer) to 20 nm.

The second layer 112 is a high purity first AlN buffer layer. The carbon concentration in the second layer 112 is, for example, 1 × 10 ¹⁶ cm ⁻³ to 1 × 10 ¹⁹ cm ^−3, and the thickness of the second layer 112 is, for example, 0.2 μm to 0.5 μm.

The third layer 113 is a high purity second AlN buffer layer. The carbon concentration in the third layer 113 is, for example, 1 × 10 ¹⁶ cm ⁻³ to 1 × 10 ¹⁹ cm ^−3, and the thickness of the third layer 113 is, for example, 1.5 μm to 3.0 μm.

  A second buffer layer 120 is provided on the first buffer layer 110. The second buffer layer 120 is a non-doped GaN buffer layer. The thickness of the second buffer layer 120 is 2 μm, for example.

An n-type semiconductor layer 140 is provided on the second buffer layer 120. The n-type semiconductor layer 140 includes a Si-doped n-type GaN contact layer 141 provided on the second buffer layer 120 and a Si-doped n-type Al _0.13 provided on the Si-doped n-type GaN contact layer 141. A Ga _0.87 N cladding layer 142.

The Si concentration in the Si-doped n-type GaN contact layer 141 is, for example, 1 × 10 ¹⁹ cm ⁻³ to 2 × 10 ¹⁹ cm ^−3, and the thickness of the Si-doped n-type GaN contact layer 141 is, for example, 4 μm. .

The Si concentration in the Si-doped n-type Al _0.13 Ga _0.87 N cladding layer 142 is, for example, 2 × 10 ¹⁸ cm ^−3, and the thickness of the Si-doped n-type Al _0.13 Ga _0.87 N cladding layer 142 is For example, the thickness is 0.02 μm.

  A part of the surface of the Si-doped n-type GaN contact layer 141 is exposed, and an n-side electrode 140e described later is provided.

The light emitting layer 150 is provided on the Si-doped n-type Al _0.13 Ga _0.87 N cladding layer 142. The light emitting layer 150 has a multiple quantum well structure in which Si-doped n-type Al _0.08 Ga _0.91 In _0.01 N barrier layers 152 and GaInN well layers 151 are alternately stacked for eight periods.

The Si concentration in the Si-doped n-type Al _0.08 Ga _0.91 In _0.01 N barrier layer 152 is, for example, 1.2 × 10 ¹⁹ cm ^{−3 to} 2.1 × 10 ¹⁹ cm ^−3. The thickness of the n-type Al _0.08 Ga _0.91 In _0.01 N barrier layer 152 is, for example, 9.0 nm.

  The peak wavelength of the emission wavelength in the GaInN well layer 151 is 383 nm, for example, and the thickness of the GaInN well layer 151 is 4.5 nm, for example.

As the final barrier layer on the side opposite to the sapphire substrate 105 of the light emitting layer 150, a Si-doped n-type Al _0.08 Ga _0.91 In _0.01 N barrier layer 153 is provided.
The Si concentration in the Si-doped n-type Al _0.08 Ga _0.91 In _0.01 N barrier layer 153 is, for example, 1.2 × 10 ¹⁹ cm ^{−3 to} 2.1 × 10 ¹⁹ cm ^−3. The thickness of the n-type Al _0.08 Ga _0.91 In _0.01 N barrier layer 153 is, for example, 4.5 nm.

  The peak wavelength of the emission wavelength of the light emitting layer 150 is 370 nm or more and less than 400 nm.

In this specific example, a low Si concentration Al _0.08 Ga _0.91 In _0.01 N spacer layer 155 is provided on the light emitting layer 150. The Si concentration in the low Si concentration Al _0.08 Ga _0.91 In _0.01 N spacer layer 155 is, for example, 1 × 10 ¹⁵ cm ^{−3 to} 3 × 10 ¹⁸ cm ^−3, and the low Si concentration Al _0.08. The thickness of the Ga _0.91 In _0.01 N spacer layer 155 is, for example, 4.5 nm.

A p-type semiconductor layer 160 is provided on the low Si concentration Al _0.08 Ga _0.91 In _0.01 N spacer layer 155. The p-type semiconductor layer 160 includes an Mg-doped p-type Al _0.26 Ga ₀₇₄ N cladding layer 161 provided on the low Si concentration Al _0.08 Ga _0.91 In _0.01 N spacer layer 155, and an Mg-doped layer. and an Mg-doped p-type GaN contact layer 162 provided on the p-type Al _0.26 Ga ₀₇₄ N clad layer 161.

The Mg concentration on the lower side of the Mg-doped p-type Al _0.26 Ga ₀₇₄ N cladding layer 161 (the sapphire substrate 105 side, that is, the light emitting layer 150 side) is, for example, 2 × 10 ¹⁹ cm ⁻³ , and the upper side ( The Mg concentration on the side opposite to the sapphire substrate 105, that is, on the side of the Mg-doped p-type GaN contact layer 162) is 1 × 10 ¹⁹ cm ⁻³ . The thickness of the Mg-doped p-type Al _0.26 Ga ₀₇₄ N clad layer 161 is, for example, 24 nm.

The Mg concentration on the lower side (side of the sapphire substrate 105) of the Mg-doped p-type GaN contact layer 162 is, for example, 5 × 10 ¹⁸ cm ⁻³ , and the Mg concentration on the upper side (side opposite to the sapphire substrate 105) is are ^{5 × 10 19 cm -3 ~9 ×} 10 19 cm -3. The thickness of the Mg-doped p-type GaN contact layer 162 is, for example, 0.3 μm.

  Each of these layers is sequentially stacked on the sapphire substrate 105 using, for example, a metal organic chemical vapor deposition method.

The first buffer layer 110 (first to third layers 111 to 113) serves to alleviate the difference in crystal type from the sapphire substrate 105, and particularly reduces screw dislocations. That is, the surface of the sapphire substrate 105 including the recess 105a is planarized at the atomic level, and the defect reduction and strain relaxation effects in the second buffer layer 120 (GaN lattice strain relaxation layer) grown on the first buffer layer 110 are obtained. To maximize.
Therefore, the thickness of the first buffer layer 110 is desirably 1.0 μm or more, and more desirably greater than 2.0 μm.

  On the other hand, in order to prevent warping due to distortion between the sapphire substrate 105 and the first buffer layer 110, the thickness of the first buffer layer 110 is desirably 6 μm or less.

  As illustrated in FIG. 1, a cavity 110 a caused by the recess 105 a of the sapphire substrate 105 is formed on the lower surface of the first buffer layer 110. The cavity 110a is expanded toward the sapphire substrate 105 side. That is, the side surface 110s of the cavity 110a has an inversely tapered shape.

  The diameter of the cavity 110a becomes narrower toward the upper side. That is, the width of the cavity 110 a when the cavity 110 a is cut in a plane parallel to the main surface 106 is narrower on the side opposite to the sapphire substrate 105 than on the sapphire substrate 105 side. That is, the cavity 110 a has a shell shape, and the shape of the shell is a shape in which the tip of the shell faces the side opposite to the sapphire substrate 105.

  The diameter of the cavity 110a on the sapphire substrate 105 side is, for example, equal to or smaller than the diameter of the recess 105a provided in the sapphire substrate 105. That is, for example, when the diameter of the recess 105a is 2.0 μm, the diameter of the cavity 110a on the sapphire substrate 105 side is 1.3 μm, for example. The length of the cavity 110a (the length in the direction perpendicular to the main surface 106 of the sapphire substrate 105) is, for example, 1.5 to 4.5 μm.

  The curvature of the surface on the upper side of the cavity 110a (the side opposite to the sapphire substrate 105) is not more than the peak wavelength of the emission wavelength of the light emitting layer 150.

FIG. 2 is a photomicrograph illustrating the configuration of the main part of the semiconductor element according to the first embodiment of the invention.
That is, this figure is a scanning electron micrograph of the first buffer layer 110 after the first buffer layer 110 is formed on the sapphire substrate 105 in the semiconductor element 11. FIG. 4A is a photograph of the sapphire substrate 105 and the first buffer layer 110 taken from an oblique direction, and FIG. 4B shows a cross section of the sapphire substrate 105 and the first buffer layer 110 with respect to the cross section. It is a photograph taken from a nearly vertical direction.

  As shown in FIGS. 2A and 2B, a recess 105 a is formed on the surface of the sapphire substrate 105. A first buffer layer 110 is formed on the sapphire substrate 105. A bullet-shaped cavity 110a is formed on the recess 105a. The upper surface of the first buffer layer 110 is flat.

  The cavity 110 a is not exposed on the upper surface of the first buffer layer 110. That is, the cavity 110 a is closed by the surface of the first buffer layer 110 on the side opposite to the sapphire substrate 105.

  As described above, the first buffer layer 110 is provided with the cavity 110a that is disposed corresponding to the recess 105a provided on the sapphire substrate 105 and whose upper surface is closed by the first buffer layer 110. Such a cavity 110a can be formed as follows, for example.

  That is, the first layer 111 is epitaxially grown according to the first group V / group III ratio and the first temperature, and the second temperature higher than the first temperature and the first group V / III ratio are further grown thereon. Epitaxially growing the second layer 112 with a higher second group V / III ratio, on which a third temperature higher than the second temperature, and a first group V / III ratio The third layer 113 is epitaxially grown according to a third group V / group III ratio between the second group V / group III ratio. Thereby, the cavity 110a is formed on the concave portion 105a of the sapphire substrate 105, and the cavity 110a is covered with the first to third layers 111 to 113. In addition, said V group / III group ratio is ratio of ammonia supply amount / Al raw material supply amount of source gas at the time of crystal growth, for example.

  That is, the V / III ratio at the time of forming the third layer 113 is lowered between the time of the first layer 111 and the second layer 112, and the temperature is changed to the first layer 111 and the second layer 112. By further increasing the temperature, the mobility of Al atoms is increased, so that the growth in the lateral direction (direction parallel to the main surface) is accelerated. As a result, the diameter of the cavity 110a becomes smaller as the AlN layer grows, the cavity 110a is closed, and the upper surface of the first buffer layer 110 is flattened.

  In addition, since the crystal quality of AlN is enhanced by the second layer 112 (high purity first AlN buffer layer) having a high group V / group III ratio, the sapphire substrate 105 of the sapphire substrate 105 is grown even at a high temperature when the third layer 113 is grown. Denaturation is suppressed.

  As described above, the first buffer layer 110 in the semiconductor element 11 according to the present embodiment has the first temperature and the first group V / III of 1.5 to 15 on the main surface 106 of the sapphire substrate 105. A first layer 111 epitaxially grown by metalorganic vapor phase epitaxy based on the group ratio, a second temperature higher than the first temperature on the first layer 111, and a first group V / group III A second layer 112 epitaxially grown by metalorganic vapor phase epitaxy with a second V / III ratio higher than the ratio, and a third higher than the second temperature on the second layer 112 A third layer epitaxially grown by metalorganic vapor phase epitaxy with a temperature and a third group V / III ratio between the first group V / III ratio and the second group V / III ratio; Layer 113.

  As a result, the first buffer layer 110 can be formed in which the upper portion is closed by the first buffer layer 110, the shell 110 has a hollow 110a, and the upper surface is flattened.

  The inventor conducted an experiment in which single-crystal AlN was formed at a high temperature on a sapphire substrate having a depth of 0.5 μm to 2 μm, and GaN was grown thereon. This experimental result will be described as a comparative example.

(First comparative example)
In the first comparative example, a single crystal AlN layer was formed on a sapphire substrate on which a trapezoidal convex portion employed in a blue LED or the like using a low temperature growth buffer was formed.
FIG. 3 is a photomicrograph illustrating the surface state of the AlN layer of the first comparative example.
As shown in FIG. 3, in the first comparative example, AlN microcrystals 110 p having a different orientation from the reference c-axis are radially formed on the side surface of the trapezoidal convex portion 105 b on the sapphire substrate 105. It was. A complex-shaped cavity 110y was formed below the AlN layer 110x. Further, a wide gap was also formed between the crystals in the c-axis direction that spread from the protrusion 105b as a starting point, and the AlN layer 110x was in a polycrystalline state as a whole.

(Second comparative example)
In the second comparative example, the single crystal AlN layer was formed on the sapphire substrate on which the recess 105a was formed. At this time, the film formation conditions of the AlN layer are different from those in the present embodiment, and when the third layer 113 is formed, the group V / group III ratio is the same as in the first layer 111 and the second layer 112. The growth temperature is the same as that of the second layer 112 and a relatively low temperature.

FIG. 4 is a photomicrograph illustrating the surface states of the AlN layer and the GaN layer of the second comparative example.
That is, FIGS. 4A and 4B illustrate the upper surface of the AlN layer and the cross section of the AlN layer, respectively. FIGS. 3C and 3D illustrate the upper surface and cross section of the GaN layer formed on the AlN layer, respectively. In this case, the thickness of the AlN layer is 2 μm.

  As shown in FIGS. 4A and 4B, in the case of the second comparative example, the recess 110z is formed in the single crystal AlN layer 110x on the recess 105a of the sapphire substrate 105. That is, the single crystal AlN layer 110x grows from the side wall of the recess 105a of the sapphire substrate 105 as a base point. The variously oriented AlN microcrystals 110p are narrow between the c-axis oriented crystal grown from the bottom of the recess 105a and the c-axis oriented crystal grown laterally from the surface other than the recess 105a of the sapphire substrate 105. Trapped in range. However, the recess 110z is opened on the upper surface of the single crystal AlN layer 110x without being blocked.

  The crystal of the GaN layer grown on the single crystal AlN layer 110x having such a structure can grow a relatively high quality crystal without being affected by the AlN microcrystal 110p having different orientations.

  However, as shown in FIGS. 4C and 4D, the GaN layer 120x has a cavity 120y corresponding to the recess 110z of the AlN layer 110x. High-density pits 120z (holes) were observed on the surface of the GaN layer 120x. When the n-type semiconductor layer 140, the light emitting layer 150, the p-type semiconductor layer 160, the n-side electrode 140e, and the p-side electrode 160e are formed on the GaN layer 120x, the pits are formed. At 120z, for example, the electrode material diffuses, causing defects such as a short circuit and deterioration of reliability.

  The pits 120z on the surface of the GaN layer 120x largely depend on the shape of the side surface of the recess 110z of the AlN layer 110x when the AlN layer 110x is grown on the sapphire substrate 105. That is, particularly in the vicinity of the upper surface of the AlN layer 110x, when the diameter of the recess 110z is narrower than the central portion in the layer thickness direction, that is, when the side surface of the recess 110z of the AlN layer 110x is an inversely tapered side surface, It was found that size and number were suppressed.

  This is because the growth direction of the GaN crystal grown from the side surface of the recess 110z of the AlN layer 110x includes a lower component, so that the GaN layer 110x grows so as to reduce the opening of the recess 110z. This is considered to suppress the influence on the upper part of the recess 110z.

  Then, by forming the side surface of the recess 110z of the AlN layer 110x in a reverse taper shape, the generation of the pit 120z was suppressed, and the light emitting element formed thereon operated normally.

  However, although the light emission efficiency of the light emitting element is improved by about several percent with respect to a normal light emitting element, it is not greatly improved. In the case of this configuration, the wafer on which the GaN layer 120x was grown was colored brown as a whole, and this coloring was considered to hinder the improvement of the light emission efficiency. This coloring of the wafer is caused by the fact that a low-quality GaN crystal formed in the recess 110z formed in the AlN layer 110x serves as a light absorption source. This absorption is particularly problematic in the near ultraviolet region where the wavelength is less than 400 nm.

  For this reason, it was considered important that the recess 110z formed in the AlN layer 110x is not opened on the surface of the AlN layer 110x.

(Third comparative example)
In the third comparative example, the layer thickness of the AlN layer 110x is 6 μm, which is three times as thick as that of the second comparative example, and an attempt is made to cover the recess 110z of the AlN layer 110x with the AlN layer 110x. is there.
FIG. 5 is a photomicrograph illustrating the surface state of the AlN layer of the third comparative example.
That is, FIGS. 4A and 4B illustrate the upper surface of the AlN layer and the cross section of the AlN layer, respectively.

  As shown in FIGS. 5A and 5B, even when the thickness of the AlN layer 110x is increased, the recess 110z remains open on the upper surface of the AlN layer 110x, and the opening of the recess 110z is eliminated. It was difficult.

  During the growth of the AlN layer 110x, threading dislocations such as screw dislocations propagate in the growth direction, and therefore gather at the surface opening by lateral growth. For this reason, it is considered that an opening is formed as a result of strong strain concentration near the surface opening. This effect is due to the symmetry of the shape of the opening as in the concave portion 110a of the semiconductor element 11 according to the present embodiment having a circular shape (that is, a circular shape when cut in a plane perpendicular to the main surface 106). It is considered particularly strong when the is high.

  As illustrated in FIG. 5A, the shape of the opening of the recess 110z is not necessarily a circle. In particular, it was found that when the crystal orientation of the sapphire substrate 105 deviates from the c-plane, the shape of the opening of the recess 110z is complicated and the recess 110z tends to remain. This is presumably because the strain in the crystal of the AlN layer 110x becomes non-uniform and the strain concentrates locally.

  On the other hand, as illustrated in FIG. 2, in the first buffer layer 110 (AlN layer) in the semiconductor element 11 according to the present embodiment, a cavity 110 a corresponding to the recess 105 a of the sapphire substrate 105 is formed, that is, The recess 110z is covered with the first buffer layer 110 and does not open on the surface of the first buffer layer 110. Thereby, the quality of the GaN crystal (second buffer layer 120) formed on the first buffer layer 110 is improved, coloring of the wafer can be eliminated, and high luminous efficiency can be achieved.

  That is, the residual state of the opening in the surface of the AlN layer 110x of the recess 110z of the AlN layer 110x in the second and third comparative examples described above depends on the diameter of the recess 105a of the sapphire substrate 105, but the AlN layer 110x. This greatly depends on the shape of the side surface of the recess 110z. The diameter of the recess 110z (cavity 110a) from the lower side of the AlN layer 110x (side of the sapphire substrate 105) to the central portion in the layer thickness direction is substantially constant, and the upper side from the central portion (the side opposite to the sapphire substrate 105). It has been found that the opening of the recess 110z is difficult to form when the diameter of the recess 110z rapidly decreases. In other words, when the wall surface of the recess 110z (cavity 110a) is reversely tapered and the recess 110z (cavity 110a) has a shell shape, it is difficult to form an opening.

  Such a side surface shape is obtained, for example, after the first layer 111 (high carbon concentration layer) is grown by extremely reducing the V group / III group ratio in the early stage of the growth of the AlN layer, and then the growth temperature is increased. The second layer 112 can be grown by increasing the / III ratio once, and then the third layer 113 can be grown by lowering the V / III ratio while further increasing the growth temperature.

  That is, at a high group V / group III ratio, the AlN crystal grows in the vertical direction. For this reason, the reaction between the screw dislocations extending in the vertical direction is promoted, and the crystal quality rapidly increases. Further, the side surface of the AlN crystal is nearly perpendicular to the main surface 106, and stress concentration is suppressed.

  At a low group V / group III ratio, the AlN crystal tends to grow in the horizontal direction, and the vicinity of the surface of the improved AlN crystal grows preferentially in the horizontal direction. And since the crystal quality of the meeting part of the upper end of the recessed part 105a is high, and the meeting part is thin up and down, since distortion is easy to escape and does not concentrate, generation | occurrence | production of an opening is suppressed. Further, by further increasing the growth temperature while thermal damage of the sapphire substrate 105 does not become a problem, the lateral growth of the AlN crystal is further promoted, and the crystal quality is enhanced.

  As a result, in the semiconductor element 11 according to the present embodiment, the cavity 110a in the first buffer layer 110 is blocked by the upper surface of the first buffer layer 110, and the upper surface of the first buffer layer 110 is planarized. For example, a GaN crystal grown to a high quality can be made. According to the semiconductor element 11, there is provided a semiconductor element in which a single crystal AlN buffer layer grown at a high temperature is formed on an uneven sapphire substrate, and the influence of interface reflection is reduced to achieve high light extraction efficiency and high internal light emission efficiency. Can be provided.

  In the semiconductor element 11 according to the present embodiment, the crystal orientation shift in the sapphire substrate 105 to be used needs to be at least 0.3 degrees or less, and in order to make the first buffer layer 110 more uniform, 0. Within 15 degrees is desirable. That is, it is considered that the crystal orientation in the sapphire substrate 105 affects the strain distribution above the concave portion 110z formed during the growth of the first buffer layer 110. By controlling the crystal orientation shift in the sapphire substrate 105 as described above, the strain distribution above the recess 110z can be made uniform, and the diameter of the opening of the recess 110z can be efficiently reduced.

  It is indispensable to form the first layer 111 having a high carbon concentration at the initial stage of growth of the AlN crystal when forming the first buffer layer 110 in order to reduce the screw dislocation that forms the recess 110z. .

  The thickness of the first buffer layer 110 is sufficient if it is 1 μm or more in terms of crystal quality, but is 2 μm or more in order to eliminate the recess 110z and flatten the upper surface of the first buffer layer 110. It is desirable.

  In the semiconductor element 11 according to this embodiment, the cavity 110a in the first buffer layer 110 has a great effect in suppressing wafer warpage and wafer cracking. . In particular, since the cavities 110a are two-dimensionally distributed, non-uniform distortion remains less likely to occur. . In particular, since the cavities 110a are two-dimensionally distributed, non-uniform distortion remains less likely to occur.

  That is, when forming the first buffer layer 110 made of AlN on the sapphire substrate 105 when forming the semiconductor element 11, if there is no cavity, the gap between the sapphire substrate 105 and the first buffer layer 110 is Due to the stress caused by the difference in thermal expansion coefficient, the wafer (laminated body of the sapphire substrate 105 and the first buffer layer 110) may be warped or cracked. At this time, by providing the cavity 110a in the first buffer layer 110, this stress is suppressed, and the occurrence of wafer warpage and wafer cracking can be significantly suppressed. Such an effect is also effective when, for example, a GaN crystal is grown on the first buffer layer 110 and a HEMT device or the like using the GaN crystal is produced, and a semiconductor device having a high yield and its manufacture are produced. Can provide a method.

  From the viewpoint of suppressing warpage and cracking of the wafer, the thickness of the first buffer layer 110 is preferably 5 μm or less, considering the strain relaxation effect due to the cavity 110a in the first buffer layer 110, and 3 μm or less. It is more desirable to do.

  For this purpose, it is desirable that the diameter of the concave portion 105a of the sapphire substrate 105 be 6 μm or less. Considering the ease of processing when forming the recess 105a, the diameter of the recess 105a may be set to 0.5 μm to 6 μm. This is because the lateral growth rate of the AlN crystal in the recess 110z of the AlN layer 110x formed on the recess 105a is about half of the vertical direction.

  The density of the recesses 105 a provided in the sapphire substrate 105 is desirably higher for the light scattering effect in the semiconductor element 11. From this viewpoint, the interval between the recesses 105a is desirably 1.5 times or less the diameter of the recess 105a.

  In the AlN growth mechanism on the sapphire substrate 105, the microcrystals formed at the initial growth stage of the AlN crystal are united to reduce defects, and finally a structure with a period of about 0.5 μm is formed in the AlN. In order not to hinder the process of reducing defects, the interval between the recesses 105a is preferably 0.5 μm or more.

  From the above, on the sapphire substrate 105 having the c-plane of which the plane orientation deviation is within 0.15 degrees as the main surface 106, the diameter is about 1.5 μm to 5.0 μm and the mutual distance is 0.5 μm to 4.0 μm. It is desirable to form a concave portion 105a having a degree.

FIG. 6 is a schematic view illustrating the operation of the semiconductor element according to the first embodiment of the invention.
That is, this figure illustrates the light characteristics of the semiconductor element 11 according to the present embodiment.
As shown in FIG. 6, by providing a shell-shaped cavity 110 a in the first buffer layer 110, the light emitted from the light emitting layer 150 is efficient at the interface between the first buffer layer 110 and the sapphire substrate 105. And is efficiently taken out below the sapphire substrate 105 (in the direction opposite to the main surface 106).

  For example, the light L1 traveling in a direction relatively perpendicular to the main surface 106 passes through the cavity 110a, passes through the sapphire substrate 105, and is extracted outside the semiconductor element 11.

  The light L2 traveling at a relatively shallow angle with respect to the main surface is reflected by, for example, the lower surface of the first buffer layer 110 (that is, the interface between the first layer 111 and the sapphire substrate 105) and the surface of the cavity 110a. , Proceeding upward, for example, reflected by an n-side electrode 140e or p-side electrode 160e (not shown), proceeding again toward the sapphire substrate 105, and taken out.

  Then, the light L3 traveling at a relatively shallow angle with respect to the main surface is refracted in the cavity 110a, travels upward, and is reflected by the n-side electrode 140e or the p-side electrode 160e, for example, to be a sapphire substrate. The process proceeds again toward 105 and is taken out.

  That is, in the semiconductor element 11, the cavity 110 a in the first buffer layer 110 has a shape in which the upper end portion is sharp and the center portion and the lower side have a gently curved shape. The emitted light (lights L <b> 1 to L <b> 3) is effectively reflected or refracted in the direction along the normal line of the main surface 106.

  At this time, low-quality AlN crystals having different crystal orientations exist inside the cavity 110a. However, since AlN has a sufficiently wide band gap, the light absorption loss can be ignored and the light scattering effect is exhibited. Since the upper surface of the first buffer layer 110 is flattened, the crystal quality of the GaN layer that is the second buffer layer 120 provided thereon is high, is not colored, and does not substantially absorb light.

  As described above, the shape of the side surface of the AlN layer 110x in the cavity 110a of the first buffer layer 110 is inversely tapered, and the oblique incident light from the light emitting layer 150 is reflected or refracted in the vertical direction. The shape of the cavity 110 a is formed by controlling the group V / group III ratio during crystal growth of the first buffer layer 110. The cavity 110a of the first buffer layer 110 has a shape with a curvature that is less than or equal to the emission wavelength at the tip opposite to the sapphire substrate 105, and has a function of preventing reflection because the refractive index gradually changes equivalently. The light emitted from the light emitting layer 150 can be extracted efficiently.

  Thereby, high luminous efficiency can be achieved in the semiconductor element 11. That is, in the semiconductor element 11, 21 mW is obtained when the current value is 20 mA, which is 1.2 times the luminous efficiency as compared with the semiconductor element formed on the flat sapphire substrate.

  By using an element wafer manufactured using this method, a high-performance ultraviolet light emitting element having a wavelength shorter than 400 nm, for example, can be produced at a high yield and at a low cost without using a special post-process.

  As will be described later, a semiconductor device that emits white light, for example, can be manufactured by combining such a semiconductor element 11 with a phosphor. At this time, light generated by wavelength conversion with the phosphor enters the sapphire substrate 105 from the lower side of the sapphire substrate 105 of the semiconductor element 11 (the side opposite to the main surface 106). At this time, by making the bottom surface of the recess 105a of the sapphire substrate 105 practically flat, the light generated by the phosphor is reflected by the bottom surface of the recess 105a and is closer to the first buffer layer 110 than the sapphire substrate 105. Advancing and suppressing absorption by various layers on the first buffer layer 110 side. Thereby, high luminous efficiency can be realized in a semiconductor device in which the semiconductor element 11 is combined with a phosphor.

  The second buffer layer 120 (GaN lattice strain relaxation layer) provided on the first buffer layer 110 plays a role of defect reduction and strain relaxation by three-dimensional island growth on the first buffer layer 110. . In order to flatten the growth surface of the second buffer layer 120, the average thickness of the second buffer layer 120 is desirably 1 μm or more. From the viewpoint of reproducibility of crystal quality in the second buffer layer 120 and reduction of warpage, the average thickness of the second buffer layer 120 is suitably 1 to 3 μm.

  By employing the first buffer layer 110 and the second buffer layer 120 as described above, the dislocation density is 1/10 or less as compared with the conventional low-temperature growth buffer layer.

  For this reason, in the growth of various semiconductor layers provided on the second buffer layer 120, it is possible to perform crystal growth using a high growth temperature and a high V / III ratio that are usually difficult to employ due to abnormal growth. Become. For this reason, generation of point defects in the element structure portion is suppressed, and high concentration doping can be performed on AlGaN having a high Al composition and a barrier layer.

Hereinafter, an example of the method for manufacturing the semiconductor element 11 according to the present embodiment will be described.
First, for example, the sapphire substrate 105 in which the recess 105a is formed by photolithography and reactive ion etching is placed on a susceptor that also serves as a heater of a MOCVD (Metal Organic Chemical Vapor deposition) apparatus.

After introducing a gas mainly composed of high-purity hydrogen (H ₂ ) from the gas introduction pipe of the MOCVD apparatus at a flow rate of 3 × 10 ⁻² m ⁻³ per minute to replace the atmosphere in the chamber, the internal pressure Is set in the range of 10-30 kPa.

Next, the sapphire substrate 105 is heated in hydrogen (H ₂ ) gas to clean the surface of the sapphire substrate 105. Then, the substrate temperature is set to 1150 ° C. to 1200 ° C., ammonia (NH ₃ ) gas and trimethylaluminum (Al (CH ₃ ) ₃ ) are introduced into the chamber, and the first layer 111 (high carbon concentration first AlN) is introduced. The buffer layer is grown to a thickness of 3 nm to 20 nm.

  Here, in order to reduce the disorder of the crystal orientation of the first layer 111, the supply ratio (group V / group III ratio) of the group V raw material and the group III raw material to the reaction tube is appropriately controlled. That is, in the formation of the first layer 111, it is desirable that the V group / III group ratio is controlled in the range of 0.7 to 50 for the growth of the high quality film. In order to obtain well, it is more desirable that the V group / III group ratio is controlled in the range of 1.5 to 15.

  Then, the substrate temperature is raised to 1270 ° C. to 1330 ° C., AlN to be the second layer 112 and the third layer is grown to a thickness of 1 μm to 5 μm, and the surface of AlN is flattened.

  At this time, in the formation of the second layer 112, the V group / III group ratio is set to about 250 to 10,000. That is, in the growth of AlN having a thickness of 0.2 μm to 0.5 μm as the second layer 112, the V group / III ratio is set to a high V group / III ratio of about 250 to 10,000, Increase quality. Thereby, the side surface of the recess 110z of the AlN layer 110x formed on the recess 105a of the sapphire substrate 105 has a diameter that is substantially perpendicular to the main surface 106 of the sapphire substrate 105 or upward. It becomes a shape.

  It is more desirable that the V group / III group ratio in the formation of the second layer 112 is set to 1000 to 5000. Thereby, the shape of the side surface of the recess 110z of the AlN layer 110x is stabilized, and the reproducibility is improved.

  In the formation of the third layer 113, the substrate temperature is further increased by 10 ° C. to 30 ° C., and the group V / III ratio is set to 50 to 50 between the first layer 111 and the second layer 112. The AlN is grown to a thickness of 2 to 3 μm. Under this condition, in the growth of the third layer 113, the growth of AlN in the lateral direction (the direction parallel to the main surface 106 of the sapphire substrate 105) is promoted, and the opening above the recess 110z of the AlN layer 110x. Shrinks rapidly. Then, the upper portion of the recess 110z of the AlN layer 110x is closed by the AlN layer 110x, the upper surface of the AlN layer 110x is flattened, and a cavity 110a having a cross-sectional shape of a shell is formed inside the first buffer layer 110.

  Then, the substrate temperature is set to 1150 ° C. to 1250 ° C. higher than the conventional growth temperature of GaN, and the second buffer layer 120 (non-doped GaN buffer layer) is grown.

  Thereafter, the substrate temperature is lowered to 1100 ° C. to 1200 ° C., monosilane gas is added, and the Si-doped n-type GaN contact layer 141 is grown.

  In the growth of the second buffer layer 120 and the Si-doped n-type GaN contact layer 141 grown on the first buffer layer 110, it is desirable that the V group / III ratio be a high ratio of 10,000 or more.

  And after setting board | substrate temperature to 1000 to 1050 degreeC, the element structure part of the semiconductor element 11 is grown.

As the group III material, for example, trimethylaluminum (Al (CH ₃ ) ₃ ), trimethylgallium (Ga (CH ₃ ) ₃ ), and trimethylindium (In (CH ₃ ) ₃ ) can be used.

As the group V raw material, for example, ammonia (NH ₃ ) gas can be used.

As a raw material for n-type doping, for example, monosilane (SiH ₄ ) gas can be used.

Biscyclopentadienyl magnesium (Cp ₂ Mg) and bismethylcyclopentadienyl magnesium (M ₂ Cp ₂ Mg) can be used as the p-type doping raw material.

  Next, in order to form the n-side electrode 140e, the p-type semiconductor layer 160, the light emitting layer 150, and a part of the n-type semiconductor layer 140 are removed by dry etching, and the Si-doped n-type GaN contact layer of the n-type semiconductor layer 140 is removed. A part of 141 is exposed.

For example, an Al alloy that becomes a part of the n-side electrode 140e is deposited on a part of the exposed part, and a sintering process is performed in a nitrogen atmosphere at 650 ° C. to form the n-side ohmic electrode part 140o. In the remaining portion, a pad region 140p made of gold is formed through a SiO ₂ / TiO ₂ laminated film, which is a dielectric multilayer film 180 for increasing the reflectance. The n-side ohmic electrode portion 140o and the pad region 140p become the n-side electrode 140e. With this structure, it is possible to reduce the light absorption loss at the electrode portion, which is a particular problem in the flip chip structure. Note that a laminated film of Ag / Pd may be used as the n-side electrode 140e, whereby the structure can be simplified.

Next, in order to form the p-side electrode 160e, a SiO ₂ film having a thickness of 400 nm is formed on the entire surface of the n-type semiconductor layer 140 and the p-type semiconductor layer 160 using, for example, a thermal CVD apparatus. Then, a patterned resist for the registry shift-off is formed on the n-type semiconductor layer 140 and the p-type semiconductor layer 160, and the SiO ₂ film on the Mg-doped p-type GaN contact layer 162 is removed by an ammonium fluoride treatment. . Then, in a region where the SiO ₂ film has been removed, reflective Ag is formed to a thickness of 200 nm using, for example, a vacuum deposition apparatus, and a sintering process is performed in an oxygen atmosphere at 350 ° C. for 1 minute.

In this way, the p-side electrode 160e mainly composed of silver can be formed. Then, an insulating film (SiO ₂ film) that also serves as a protective film is formed around the p-side electrode 160e. Then, the surface of the p-side electrode 160e is covered with a pad layer mainly composed of gold. Thereafter, the individual LED elements are formed by cleaving or cutting with a diamond blade or the like.

Thereby, the semiconductor element 11 illustrated in FIG. 1 can be manufactured.
According to this manufacturing method, for example, on the buffer layer (for example, the AlN layer and the GaN layer) formed on the sapphire substrate 105, the element portion (the n-type semiconductor layer 140, the light emitting layer 150, and the p-type semiconductor layer 160). After forming the sapphire substrate, the sapphire substrate and the buffer layer are deleted, and it is not necessary to use the conventional special post-process that increases the light extraction efficiency by forming irregularities on the lower surface of the element part, and highly efficient ultraviolet light emission Diodes can be produced at high yield and low cost.

Note that, in the semiconductor element 11 according to the present embodiment, taking advantage of the fact that the second buffer layer 120 of low defect crystal can be formed on the first buffer layer 110 having the cavity 110a and the upper surface being planarized. In order to obtain high-efficiency light emission in the ultraviolet region, the Mg-doped p-type Al having a high Al composition and a large film thickness for preventing the overflow of electrons from the light-emitting layer 150 and increasing the efficiency of the light-emitting layer 150 itself _. Various contrivances have been made to enable the adoption of the ₂₆ Ga ₀₇₄ N clad layer 161.

That is, the barrier layers of the light emitting layer 150 (Si-doped n-type Al _0.08 Ga _0.91 In _0.01 N barrier layer 152 and Si-doped n-type Al _0.08 Ga _0.91 In _0.01 N barrier layer 153 ) Is doped with a high concentration of Si to increase the electron concentration in the well layer (GanInN well layer 151), thereby shortening the luminescence recombination lifetime and improving the efficiency of the luminescent layer 150 itself.

When the Si concentration in the barrier layer is lower than 1.2 × 10 ¹⁹ cm ⁻³ , the effect of shortening the light emission recombination lifetime is insufficient, and the Si concentration in the barrier layer is 2.1 × 10 ¹⁹ cm. ^If it is higher than ^-3 , the crystal quality is lowered.

Further, the low Si concentration Al _0.08 Ga _0.91 In _0.01 N spacer layer 155 has a Mg-doped p-type Al _0. It concentrates on the ₂₆ Ga ₀₇₄ N clad layer 161 and functions to prevent abnormal diffusion of Mg atoms due to Mg atoms drifting to the light emitting layer 150.

As a result, the resistance of the Mg-doped p-type Al _0.26 Ga ₀₇₄ N cladding layer 161 having a high Al composition can be reduced without reducing reliability and efficiency.

Further, the low Si concentration Al _0.08 Ga _0.91 In _0.01 N spacer layer 155 causes the low Si concentration Al _0.08 Ga _0.91 In _0.01 N spacer layer 155 and the Mg-doped p-type Al _{0. Since} the electron concentration in the vicinity of the interface with the ₂₆ Ga ₀₇₄ N cladding layer 161 is lowered, the electron overflow to the Mg-doped p-type Al _0.26 Ga ₀₇₄ N cladding layer 161 can be suppressed.

  Since the hole concentration in the vicinity of the interface increases, non-radiative recombination at the interface also increases, but the dislocation density is low and the barrier layer has an AlGaNInN quaternary mixed crystal (In composition of 0.3% to 2%). 0.0%), this loss can be reduced.

The Mg concentration in the Mg-doped p-type Al _0.26 Ga ₀₇₄ N cladding layer 161 is high on the light emitting layer 150 side and low on the Mg-doped p-type GaN contact layer 162 side. This cancels the piezoelectric field in the Mg-doped p-type Al _0.26 Ga ₀₇₄ N cladding layer 161 that inhibits hole injection, reduces the operating voltage, and improves the carrier confinement effect.

When the Mg concentration on the upper side of the Mg-doped p-type GaN contact layer 162 (the side opposite to the sapphire substrate 105) is higher than 1 × 10 ²⁰ cm ⁻³ , Mg diffuses into the light emitting layer 150, Efficiency and reliability are likely to deteriorate. When the Mg concentration in the Mg-doped p-type GaN contact layer 162 is lower than 5 × 10 ¹⁸ cm ⁻³ , the operating voltage increases.

FIG. 7 is a schematic cross-sectional view illustrating the configuration of another semiconductor element according to the first embodiment of the invention.
As shown in FIG. 7, in the semiconductor element 12 according to the present embodiment, the n-type semiconductor layer 140 includes the Si-doped n-type AlGaN contact layer 141 a and the Si-doped n-type Al _0.13 Ga _0.87 N clad layer. 142, and the light emitting layer 150 has a stacked structure of a Si-doped n-type Al _0.08 Ga _0.91 In _0.01 N barrier layer 152 and an AlGaInN well layer 151a. The rest is the same as the semiconductor element 11 illustrated in FIG.

  That is, the above buffer structure is applied to the semiconductor element 12 which is a light emitting element having a wavelength shorter than the forbidden width of GaN in the semiconductor element 11 illustrated in FIG. Then, Al is added to the well layer of the quantum well of the light emitting layer 150, and AlGaN having a band gap wider than the emission wavelength energy is used instead of GaN as the underlayer.

  When the emission wavelength is shorter than 280 nm, AlGaN having a high Al composition is used for the light emitting layer 150. In such an element, since light emission in the horizontal direction (direction parallel to the main surface 106) increases, the use of the first buffer layer 110 having the cavities 110a increases the efficiency. Especially effective.

FIG. 8 is a schematic cross-sectional view illustrating the configuration of another semiconductor element according to the first embodiment of the invention.
As shown in FIG. 8, another semiconductor element 30 according to this embodiment is a HEMT semiconductor element. That is, the semiconductor element 30 also has a main surface 106 made of a c-plane, a sapphire substrate 105 provided with a recess 110a on the main surface 106, and provided on the main surface 106 of the sapphire substrate 105, and has a cavity 110a. A first buffer layer 110; and a semiconductor layer 390 provided on the first buffer layer 110 and made of a nitride semiconductor.

  The semiconductor layer 390 is provided on the first buffer layer 110, and is formed on the second buffer layer 120 made of GaN or AlGaN, the GaN layer 303 provided on the second buffer layer 120, and the GaN layer 303. And an AlGaN layer 304 provided.

  A source electrode 305 and a drain electrode 306 are provided on the AlGaN layer 304, and a gate electrode 307 is provided between the source electrode 305 and the drain electrode 306. In this specific example, the gate electrode 307 is provided on the AlGaN layer 304 with the insulating film 308 interposed therebetween, but the insulating film 308 can be omitted.

  Thus, the semiconductor element 30 is a HEMT having an AlGaN / GaN hetero interface. In the semiconductor element 30, by providing the first buffer layer 110 having the cavity 110 a on the sapphire substrate 105, warpage of the sapphire substrate 105 can be suppressed and cracking can be prevented.

  Since the first buffer layer 110 has the cavity 110a and the upper surface thereof is substantially flat, the crystal quality of the semiconductor layer 190 formed thereon can be improved.

  Thus, this embodiment can be applied to various semiconductor elements using nitride semiconductors including HEMTs, in addition to semiconductor light emitting elements.

In this specification, “nitride semiconductor” refers to a composition ratio x, y in a chemical formula of In _x Al _y Ga _1-xy N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, x + y ≦ 1). And semiconductors of all compositions in which z is changed within the respective ranges. Furthermore, in the above chemical formula, those further including a group V element other than N (nitrogen) and those further including any of various dopants added for controlling the conductivity type are also referred to as “nitride semiconductors”. Shall be included.

(Second Embodiment)
FIG. 9 is a schematic cross-sectional view illustrating the configuration of a semiconductor device according to the second embodiment of the invention.
As shown in FIG. 9, the semiconductor device 201 according to the second embodiment of the present invention is a white LED in which the semiconductor element 11 according to the first embodiment and a phosphor are combined.

That is, the semiconductor device 201 according to this embodiment includes the semiconductor element 11 according to the embodiment of the present invention and a wavelength conversion unit that absorbs light emitted from the semiconductor element 11 and emits light having a wavelength different from that of the light. (Phosphor).
In the semiconductor device 201, the semiconductor element according to any of the embodiments of the present invention and a modified semiconductor element thereof can be used. However, the following description will be made assuming that the semiconductor element 11 is used.

  In the semiconductor device 201, the reflective film 23 is provided on the inner surface of the container 22 made of ceramic or the like, and the reflective film 23 is provided separately on the inner side surface and the bottom surface of the container 22. The reflective film 23 is made of, for example, aluminum. Among these, the semiconductor element 11 is installed via the submount 24 on the reflective film 23 provided on the bottom of the container 22.

  Gold bumps 25 are formed on the semiconductor element 11 by a ball bonder and fixed to the submount 24. You may fix to the submount 24 directly, without using the gold bump 25. FIG.

  For fixing the semiconductor element 11, the submount 24, and the reflective film 23, it is possible to use adhesion with an adhesive, solder, or the like.

  On the surface of the submount 24 on the semiconductor element 11 side, electrodes patterned so as to insulate the p-side electrode 160e and the n-side electrode 140e of the semiconductor element 11 are formed, and are respectively provided on the container 22 side. It is connected to an electrode (not shown) by a bonding wire 26. This connection is made at a portion between the reflective film 23 on the inner surface and the reflective film 23 on the bottom surface.

  A first phosphor layer 211 containing a red phosphor is provided so as to cover the semiconductor element 11 and the bonding wire 26, and a blue, green or yellow phosphor is placed on the first phosphor layer 211. The 2nd fluorescent substance layer 212 containing is formed. A lid portion 27 made of silicon resin is provided on the phosphor layer.

The first phosphor layer 211 includes a resin and a red phosphor dispersed in the resin.
As the red phosphor, for example, Y ₂ O ₃ , YVO ₄ , Y ₂ (P, V) O ₄ can be used as a base material, and trivalent Eu (Eu ³⁺ ) is used as an activator. Include. That is, Y ₂ O ₃ : Eu ³⁺ , YVO ₄ : Eu ^3+, etc. can be used as the red phosphor. The concentration of Eu ³⁺ can be 1% to 10% in terms of molar concentration. As a base material of the red phosphor, LaOS, Y ₂ (P, V) O ₄ or the like can be used in addition to Y ₂ O ₃ and YVO ₄ . In addition to Eu ³⁺ , Mn ⁴⁺ or the like can be used. In particular, by adding a small amount of Bi together with trivalent Eu to the YVO ₄ matrix, absorption at 380 nm is increased, so that the luminous efficiency can be further increased. Further, as the resin, silicon resin or the like can be used.

  The second phosphor layer 212 includes a resin and at least one of blue, green, and yellow phosphors dispersed in the resin. For example, a blue phosphor and a green phosphor may be used in combination, or a blue phosphor and a yellow phosphor may be used in combination, and a blue phosphor, a green phosphor and a yellow phosphor may be used. A combined phosphor may be used.

As the blue phosphor, for example, (Sr, Ca) ₁₀ (PO ₄ ) ₆ Cl ₂ : Eu ²⁺ , BaMg ₂ Al ₁₆ O ₂₇ : Eu ^2+, or the like can be used.
As the green phosphor, for example, Y ₂ SiO ₅ : Ce ³⁺ , Tb ³⁺ having trivalent Tb as the emission center can be used. In this case, energy is transferred from Ce ions to Tb ions, so that the excitation efficiency is improved. As the green phosphor, for example, Sr ₄ Al ₁₄ O ₂₅ : Eu ²⁺ can be used.
For example, Y ₃ Al ₅ : Ce ³⁺ can be used as the yellow phosphor.
Moreover, silicon resin etc. can be used as resin.
In particular, trivalent Tb exhibits sharp light emission at around 550 nm where the visibility is maximum, so that when combined with the trivalent Eu sharp red light emission, the light emission efficiency is significantly improved.

  According to the semiconductor device 201 according to the present embodiment, ultraviolet light having a wavelength of, for example, 380 nm generated from the semiconductor element 11 is emitted to the sapphire substrate 105 side of the semiconductor element 11, and the reflection on the reflective film 23 is also used. The phosphors included in each phosphor layer can be excited efficiently.

For example, the phosphor having the emission center of trivalent Eu contained in the first phosphor layer 211 is converted into light having a narrow wavelength distribution around 620 nm, and red visible light can be obtained efficiently. .
In addition, the blue, green, and yellow phosphors included in the second phosphor layer 212 are efficiently excited, and blue, green, and yellow visible light can be efficiently obtained.
As these mixed colors, it is possible to obtain white light and various other colors with high efficiency and good color rendering.

  In such a semiconductor device 201, a semiconductor capable of realizing a high light extraction efficiency and a high internal light emission efficiency by forming a high-temperature grown single crystal AlN buffer layer on an uneven sapphire substrate and reducing the influence of interface reflection. A device can be provided.

  In the semiconductor device 201, light generated by wavelength conversion by the phosphor enters the sapphire substrate 105 from the side opposite to the main surface 106 of the sapphire substrate 105 of the semiconductor element 11. At this time, by making the bottom surface of the recess 105a of the sapphire substrate 105 practically flat, the light generated by the phosphor is reflected by the bottom surface of the recess 105a and is closer to the first buffer layer 110 than the sapphire substrate 105. Advancing and suppressing absorption by various layers on the first buffer layer 110 side. Thereby, in the semiconductor device 201, higher luminous efficiency can be realized.

  As described above, in the semiconductor device using the light emission of the phosphor, it is important that the light emission of the phosphor is not reabsorbed by the element portion. In the semiconductor device 201 of this specific example, since the flat portion of the cavity 110a on the sapphire substrate 105 side reflects light emission, it is easy to obtain high-efficiency white light emission.

(Third embodiment)
FIG. 10 is a schematic cross-sectional view illustrating the configuration of a semiconductor wafer according to the third embodiment of the invention.
The semiconductor wafer 21 according to the third embodiment of the present invention includes a sapphire substrate 105 having a main surface 106 formed of a c-plane and having a recess 110 a provided on the main surface 106, and the main surface 106 of the sapphire substrate 105. And a first buffer layer 110 made of crystalline AlN. The recess 110 a is two-dimensionally arranged on the main surface 106.

  The first buffer layer 110 has a cavity 110 a provided on the recess 105 a of the sapphire substrate 105. The cavity 110a is covered with the surface of the first buffer layer 110 on the side opposite to the sapphire substrate 105. The first buffer layer 110 includes a first region 110e and a second region 110f provided between the first region 110e and the sapphire substrate 105 and having a higher carbon concentration than the first region 110e.

  The materials and configurations described in regard to the first embodiment can be applied to the sapphire substrate 105, the recess 105a, the first buffer layer 110, the cavity 110a, the first region 110e, and the second region 110f.

  In such a semiconductor wafer 21, the cavity 110 a in the first buffer layer 110 has a great effect in suppressing the warpage of the semiconductor wafer and the cracking of the semiconductor wafer. In particular, since the cavities 110a are two-dimensionally distributed, non-uniform distortion remains less likely to occur. Also, crystal defects such as dislocations in the AlN crystal layer can be reduced uniformly regardless of the orientation in the wafer plane.

  Such an effect exerts a great effect on manufacturing any semiconductor element such as a light emitting element such as an LED or a switching element such as HEMT on the semiconductor wafer 21, and it is possible to manufacture a high yield semiconductor element. A semiconductor wafer can be provided.

  Then, by forming the second buffer layer 120, the n-type semiconductor layer 140, the light emitting layer 150, and the p-type semiconductor layer 160 on the first buffer layer 110, the cavity 110a of the first buffer layer 110 is highly efficient. A semiconductor device that can reflect or refract light and realize high light extraction efficiency and high internal light emission efficiency can be manufactured.

  The semiconductor wafer 21 according to the present embodiment can further include a second buffer layer 120 provided on the first buffer layer 110 and made of GaN or AlGaN. Since the surface of the first buffer layer 110 made of AlN is relatively easy to oxidize, by forming the second buffer layer 120 made of GaN or AlGaN that is relatively hard to oxidize on the first buffer layer 110, the semiconductor wafer 21. It is easy to manage the storage and transportation of the semiconductor wafer, and an easy-to-use semiconductor wafer can be provided.

(Fourth embodiment)
FIG. 11 is a flowchart illustrating the semiconductor crystal growth method according to the fourth embodiment of the invention.
As shown in FIG. 11, in the method for growing a semiconductor crystal according to the present embodiment, on the sapphire substrate 105 having the main surface 106 made of the c-plane and having the recess 110 a on the main surface 106. The first layer 111 made of AlN is epitaxially grown by metal organic vapor phase epitaxy using a temperature of 1 and a first group V / group III ratio of 1.5 to 15 (step S110). The recess 110 a is two-dimensionally arranged on the main surface 106.

  An organometallic gas is formed on the first layer 111 by a second temperature higher than the first temperature and a second group V / group III ratio higher than the first group V / group III ratio. The second layer 112 made of AlN is epitaxially grown by the phase growth method (step S120).

  Then, on the second layer 112, a third temperature higher than the second temperature and a third V between the first group V / group III ratio and the second group V / group III ratio. A third layer made of AlN is epitaxially grown by metalorganic vapor phase epitaxy based on the group / group III ratio (step S130).

  Then, a cavity 110a is formed on the recess 105a, and the cavity 110a is covered with at least one of the first layer 111, the second layer 112, and the third layer 113.

  The materials and configurations described with respect to the first embodiment can be applied to the sapphire substrate 105, the first buffer layer 110, the first layer 111, the second layer 112, and the third layer 113. The conditions described in regard to the first embodiment can be applied. And the structure demonstrated regarding 1st Embodiment is applicable to the cavity 110a.

  According to the semiconductor crystal growth method of the present embodiment, the upper surface of the first buffer layer 110 can be planarized while forming the cavity 110a in the first buffer layer 110. This cavity 110a has a great effect in suppressing warpage of the semiconductor wafer and cracking of the semiconductor wafer, and improves the yield when manufacturing various semiconductor elements such as light emitting elements such as LEDs and switching elements such as HEMT. be able to. Then, by forming the second buffer layer 120, the n-type semiconductor layer 140, the light emitting layer 150, and the p-type semiconductor layer 160 on the first buffer layer 110, the cavity 110a of the first buffer layer 110 is highly efficient. A semiconductor device that can reflect or refract light and realize high light extraction efficiency and high internal light emission efficiency can be manufactured.

  In the semiconductor element, the semiconductor device, the semiconductor wafer and the semiconductor crystal growth method according to the embodiment of the present invention described above, the case where the light emission peak wavelength is applied to a light emitting element in the near ultraviolet region having a wavelength of 370 to 400 nm is mainly described. If the wavelength is longer than 200 nm that transmits AlN, the configuration of the embodiment of the present invention can be applied even when the wavelength is shorter than 370 to 400 nm.

  In addition to Si, Sn and Ge can be used as the n-type dopant. In particular, if Sn is doped, a high-concentration and thick n-type contact layer can be formed, and a device having a low operating voltage can be manufactured by reducing the series resistance. A silver alloy containing about 1% Ge may be used as the electrode material.

The embodiments of the present invention have been described above with reference to specific examples. However, the present invention is not limited to these specific examples. For example, a sapphire substrate, a first buffer layer, a second buffer layer, a first to a third layer, a lattice strain relaxation layer, a semiconductor layer, a contact layer, a cladding layer, a spacer layer, which constitute a semiconductor element, a semiconductor device, and a semiconductor wafer The specific configuration of each element such as a well layer, a barrier layer, an n-type semiconductor layer, a light emitting layer, a p-type semiconductor layer, an n-side electrode, and a p-side electrode should be appropriately selected by those skilled in the art from a known range. As long as the present invention can be carried out in the same manner and the same effect can be obtained, it is included in the scope of the present invention.
Moreover, what combined any two or more elements of each specific example in the technically possible range is also included in the scope of the present invention as long as the gist of the present invention is included.

  In addition, all semiconductor elements, semiconductor devices, and semiconductors that can be appropriately designed and implemented by those skilled in the art based on the semiconductor element, semiconductor device, semiconductor wafer, and semiconductor crystal growth methods described above as embodiments of the present invention. Wafer and semiconductor crystal growth methods also fall within the scope of the present invention as long as they include the gist of the present invention.

  In addition, in the category of the idea of the present invention, those skilled in the art can conceive of various changes and modifications, and it is understood that these changes and modifications also belong to the scope of the present invention. .

11, 12, 30 Semiconductor element 21 Semiconductor wafer 22 Container 23 Reflective film 24 Submount 25 Gold bump 26 Bonding wire 27 Lid 105, 305 Sapphire substrate 105a, 305a Recess 105b Protrusion 106, 306 Main surface 110 First buffer layer 110a Cavity 110e First region 110f Second region 110p Microcrystal 110s Side surface 110x AlN layer 110y Cavity 110z Recess 111 First layer 112 Second layer 113 Third layer 120 Second buffer layer 120x GaN layer 120y Cavity 120z Pit 140 N-type semiconductor layer 140e First electrode (n-side electrode)
140on side ohmic electrode part 140p pad region 141 Si-doped n-type GaN contact layer 141a Si-doped n-type AlGaN contact layer 142 Si-doped n-type Al _0.13 Ga _0.87 N cladding layer 150 Light emitting layer 151 GaInN well layer 151a AlGaInN Well layer 152 Si-doped n-type Al _0.08 Ga _0.91 In _0.01 N barrier layer 153 Si-doped n-type Al _0.08 Ga _0.91 In _0.01 N barrier layer 155 Low Si concentration Al _0.08 Ga _0.91 In _0.01 N spacer layer 160 p-type semiconductor layer 160e Second electrode (p-side electrode)
161 Mg-doped p-type Al _0.26 Ga ₀₇₄ N clad layer 162 Mg-doped p-type GaN contact layer 180 Dielectric multilayer 190 Semiconductor layer 201 Semiconductor device 211 First phosphor layer (wavelength conversion layer)
212 Second phosphor layer (wavelength conversion layer)
303 GaN layer 304 AlGaN layer 305 Source electrode 306 Drain electrode 307 Gate electrode 308 Insulating layer 390 Semiconductor layer L1-L3 Light

Claims (12)

a sapphire substrate having a main surface consisting of a c-plane and having a recess formed in the main surface;
Is provided on the front Symbol major surface, a first buffer layer made of crystalline AlN,
A semiconductor layer provided on the first buffer layer and made of a nitride semiconductor;
With
The first buffer layer has a cavity provided on the concave portion of the sapphire substrate,
The first buffer layer includes a first region, and a second region provided between the first region and the sapphire substrate and having a higher carbon concentration than the first region,
The cavity is closed in a first buffer layer, and a surface of the first buffer layer facing the semiconductor layer is flat. The carbon concentration in the second region is 3 × 10 ¹⁸ cm ⁻³ or more and 5 × 10 ²⁰ cm ⁻³ or less, and the thickness of the second region is 3 nanometers or more and 20 nanometers or less. claim 1 Symbol mounting semiconductor element and said. The cavity semiconductor device according to claim 1 or 2, characterized in that it is widened toward the side of the sapphire substrate. The first buffer layer includes:
On the main surface of the sapphire substrate, epitaxial growth is performed by metal organic vapor phase epitaxy using a first temperature and a first group V / group III ratio of 0.7 to 50. One layer,
On the first layer, an organometallic vapor phase with a second temperature higher than the first temperature and a second group V / group III ratio higher than the first group V / group III ratio. A second layer that is epitaxially grown by a growth method and is part of the first region;
On the second layer, a third temperature higher than the second temperature and a third temperature between the first group V / III ratio and the second group V / III ratio. A third layer of the other part of the first region that is epitaxially grown by metalorganic vapor phase epitaxy according to the group V / group III ratio;
Have
Said cavity, said first layer and through said second layer, said cavity semiconductor device according to any one of claims 1-3, characterized in that it is closed in the third layer . The first temperature is 1150 ° C. to 1200 ° C.,
The second temperature is 1270 ° C to 1330 ° C,
The third temperature is 10 ° C. to 30 ° C. higher than the second temperature,
The second group V / group III ratio is 250-10000,
5. The semiconductor device according to claim 4, wherein the third group V / group III ratio is 50 to 250. The semiconductor layer is
A second buffer layer provided on the first buffer layer and made of GaN or AlGaN;
An n-type semiconductor layer provided on the second buffer layer;
A light emitting layer provided on the n-type semiconductor layer;
A p-type semiconductor layer provided on the light emitting layer;
The semiconductor device according to any one of claims 1-5, characterized in that it comprises a. The curvature of the surface of the cavity opposite to the sapphire substrate is equal to or less than the peak wavelength of the emission wavelength of the light emitting layer, and the cavity is cut when the cavity is cut in a plane parallel to the main surface. width, the semiconductor device according to claim 6 wherein the sapphire substrate, wherein the direction of the opposite side is smaller than the side of the sapphire substrate. The semiconductor element according to claim 6 or 7, wherein a peak wavelength of an emission wavelength of the light emitting layer is 370 nanometers or more and less than 400 nanometers. A semiconductor element according to any one of claims 6 to 8 ,
A wavelength conversion layer that absorbs light emitted from the semiconductor element and emits light having a wavelength different from that of the light;
A semiconductor device comprising: a sapphire substrate having a main surface consisting of a c-plane and having a recess formed in the main surface;
A first buffer layer provided on the main surface and made of crystalline AlN;
A semiconductor layer provided on the first buffer layer and made of a nitride semiconductor;
A semiconductor wafer comprising:
The first buffer layer has a cavity provided on the concave portion of the sapphire substrate,
The first buffer layer includes a first region, and a second region provided between the first region and the sapphire substrate and having a higher carbon concentration than the first region,
The cavity is closed in a first buffer layer, and a surface of the first buffer layer facing the semiconductor layer is flat. On the main surface of the sapphire substrate having a main surface consisting of c-plane and having a recess formed in the main surface,
Epitaxially growing a first layer of AlN by metal organic vapor phase epitaxy using a first temperature of 1150 ° C. to 1200 ° C. and a first group V / group III ratio of 0.7 to 50;
A second layer made of AlN is formed on the first layer by metal organic vapor phase epitaxy using a second temperature of 1270 ° C. to 1330 ° C. and a second group V / III ratio of 250 to 10,000. Epitaxially grown,
On the second layer, by a metal organic vapor phase epitaxy method using a third temperature higher by 10 ° C. to 30 ° C. than the second temperature and a third group V / III ratio of 50 to 250. A method for growing a semiconductor crystal, comprising: epitaxially growing a third layer made of AlN to form a cavity on the recess, and covering the cavity with the third layer. The first group V / group III ratio is 1.5 to 15,
12. The method for growing a semiconductor crystal according to claim 11, wherein the second group V / group III ratio is 1000 to 5000.