JP5301643B2 - Abnormal lane detection circuit and method, deskew circuit and method - Google Patents

Description

  The present invention relates to an abnormal lane detection circuit and an abnormal lane detection method for detecting an abnormal lane, and a deskew circuit and a deskew method including the abnormal lane detection circuit.

A deskew method for adjusting a skew generated between lanes when data is transmitted / received using a plurality of lanes is defined (for example, see Non-Patent Document 1). Deskew method of Non-Patent Document 1, as shown in FIG. 8 (a), when transmitting the signal block _B 0 _{.about.B 19,} the signal block _B 0 _.about.B with all lanes in ₁₉ alignment markers at the same timing (Alignment Marker ) Is inserted. In FIG. 8, the signal block in which the alignment marker is inserted is shown as a black signal block. On the receiving side, the alignment marker is detected as shown in FIG. At this time, the lane of lane number # 0 in which the alignment marker is first detected is determined as the first lane. Then, as shown in FIG. 8C, the time difference between the detection time of the alignment marker in the first lane of lane number # 0 and the detection time of the alignment marker in the other lane is measured, and the alignment marker timing is adjusted. In this way, deskew is performed.

IEEE802.3

  In the deskew method of Non-Patent Document 1, as described above, the lane in which the alignment marker is first detected is determined as the first lane. However, since only the lane identifier is inserted in the alignment marker, the alignment marker inserted at different timing cannot be identified on the transmission side. For example, depending on the relationship such as clock data recovery, as shown in FIG. 9, the maximum skew value determined by the deskew method of Non-Patent Document 1 may be exceeded, and the alignment marker timing may be greatly shifted. In such a case, it is unclear whether it is an alignment marker of group N inserted at the same timing or an alignment marker of group (N + 1) inserted at a different timing, and deskew cannot be performed. Therefore, it is necessary to detect an abnormal lane in which the alignment marker timing is greatly deviated.

  An object of the present invention is to provide an abnormal lane detection circuit, an abnormal lane detection method, a deskew circuit, and a deskew method capable of detecting an abnormal lane when the timing of the alignment marker is greatly shifted.

  In order to achieve the above object, the abnormal lane detection circuit, abnormal lane detection method, deskew circuit, and deskew method of the present invention set a reference lane as a temporary head lane and are detected within a set threshold time. Count the number of alignment markers. An abnormal lane is detected by detecting a lane that is outside the threshold time when the reference lane has the largest number of alignment markers.

  Specifically, in the abnormal lane detection circuit of the present invention, a timing signal synchronized with a specific block including a predetermined identifier among signal blocks having a predetermined data amount is input to a plurality of lanes, A timing signal counting unit (41) for counting the number of timing signals of other lanes input within a threshold time set from the time point of the timing signal of one reference lane selected from the plurality of lanes; A reference lane setting unit (42) for setting one of the lanes as the reference lane, and the reference lane set by the reference lane setting unit when the threshold time in the timing signal counting unit has elapsed. A reference lane changing unit (44) that sequentially changes, and the timing signal meter when each lane is set as the reference lane. A leading lane determining unit (43) that determines the lane number of the reference lane that maximizes the number of timing signals counted by the unit as the lane number of the leading lane, and the lane number determined by the leading lane determining unit as the leading lane And an abnormal lane detection unit (45) for detecting a lane number outside the threshold time.

  Since the abnormal lane detection circuit of the present invention includes a timing signal counting unit, a reference lane setting unit, a reference lane changing unit, and a head lane determining unit, the number of alignment markers within the set threshold time is compared, A large number of lanes can be used as the first lane. Since the abnormal lane detection circuit of the present invention includes the abnormal lane detection unit, it is possible to detect a lane that is outside the threshold time when the lane having the largest number of alignment markers is set as the top lane. As a result, the abnormal lane detection circuit of the present invention can detect an abnormal lane when the timing of the alignment marker is greatly shifted.

  Specifically, the deskew circuit of the present invention includes an abnormal lane detection circuit (40) of the present invention, the signal block is input to a plurality of lanes, the timing signal is output for each lane, and the signal block A synchronization unit (31) that outputs the signal block for each lane according to the input timing, and associates the signal block of each lane output by the synchronization unit with an address corresponding to the input timing to the synchronization unit. A data storage unit (32) for storing, and the timing signal is input to a plurality of lanes, and the leading lane from the timing of the timing signal of the leading lane within a threshold time set from the timing of the timing signal of the leading lane A delay time measuring unit that measures and outputs a delay time up to the timing signal of the lane other than the lane ( It includes a 4), the address for reading the signal block from the data storage unit, an address control section for shifting (33) according to the delay time measuring of the delay time measuring unit.

  Since the deskew circuit according to the present invention includes the abnormal lane detection circuit according to the present invention, it is possible to detect an abnormal lane when the timing of the alignment marker is greatly shifted. Since the deskew circuit of the present invention includes a synchronization unit, a data storage unit, a delay time measurement unit, and an address control unit, the deskew can be performed using the first lane determined by the abnormal lane detection circuit. Therefore, the deskew circuit of the present invention can perform deskew when the timing of the alignment marker is greatly shifted.

  Specifically, the abnormal lane detection method of the present invention includes a reference lane setting procedure (S401) for setting one lane among a plurality of lanes as a reference lane, and a signal block having a predetermined amount of data. A timing signal synchronized with a specific block including a predetermined identifier is input to a plurality of lanes, and the number of timing signals input within a threshold time set from the time point of the timing signal of the reference lane is counted. The timing signal counting procedure (S402) stored together with it is determined whether or not all lanes are set as reference lanes. If there is an unset lane, the lane number of the reference lane is changed and the reference lane is changed. The reference lane changing procedure (S404 and 405) for shifting to the setting procedure, and all the lanes in the reference lane setting procedure A first lane determination procedure (S406) for determining the lane number of the reference lane that sets the maximum number of the timing signals stored in the timing signal counting procedure after setting the reference lane as the lane number of the first lane; An abnormal lane detection procedure (S407) for detecting a lane number outside the threshold time when the lane number determined in the first lane determination procedure is set as the first lane.

  Since the abnormal lane detection method of the present invention has a reference lane setting procedure, a timing signal counting procedure, a reference lane changing procedure, and a leading lane determining procedure, the number of alignment markers within the set threshold time is compared, A large number of lanes can be used as the first lane. Since the abnormal lane detection method of the present invention has an abnormal lane detection procedure, a lane that is outside the threshold time can be detected when the lane with the largest number of alignment markers is set as the first lane. Thereby, the abnormal lane detection method of the present invention can detect an abnormal lane when the timing of the alignment marker is greatly deviated.

  Specifically, the deskew method of the present invention is synchronized with the specific block before the reference lane setting procedure or between the reference lane setting procedure and the timing signal counting procedure and the abnormal lane detection method of the present invention. The timing signal is output for each lane, and after the signal block storing procedure (S301) for storing the signal block at an address corresponding to the input timing of the signal block, and the leading lane determining procedure, the timing signal is a plurality of timing signals. The delay time from the timing signal timing of the leading lane to the timing signal timing of the lane other than the leading lane is measured within the threshold time set from the timing timing timing of the leading lane. Output delay time measurement procedure (S302) and the delay time measurement procedure By shifting the address according to the delay time of each lane stored, having a signal block read procedure (S303) for reading a signal block stored in the signal blocks stored procedure.

  Since the deskew method according to the present invention executes the abnormal lane detection method according to the present invention, it is possible to detect an abnormal lane when the timing of the alignment marker is greatly shifted. Since the deskew method of the present invention executes the signal block storing procedure, the delay time measuring procedure, and the signal block reading procedure, it is possible to perform the deskew using the head lane determined in the abnormal lane detecting method. Therefore, the deskew method of the present invention can perform deskew when the timing of the alignment marker is greatly deviated.

  According to the present invention, it is possible to provide an abnormal lane detection circuit, an abnormal lane detection method, a deskew circuit, and a deskew method that can detect an abnormal lane when the timing of the alignment marker is greatly shifted.

2 shows an example of a deskew circuit according to the first embodiment. An example of a signal block input to the deskew circuit is shown. 2 shows an example of a deskew method according to the first embodiment. A storage example of each signal block of the data storage unit is shown. 4 shows an example of a deskew circuit according to a second embodiment. An example of the deskew method according to the second embodiment is shown. 6 shows an example of a deskew circuit according to a third embodiment. The deskew method of Non-Patent Document 1 is shown. An example of a signal block is shown.

  Embodiments of the present invention will be described with reference to the accompanying drawings. The embodiments described below are examples of the present invention, and the present invention is not limited to the following embodiments. In the present specification and drawings, the same reference numerals denote the same components.

(Embodiment 1)
FIG. 1 shows an example of a deskew circuit according to this embodiment. The deskew circuit 30 according to the present embodiment includes an abnormal lane detection circuit 40, a synchronization unit 31, a data storage unit 32, an address control unit 33, a delay time measurement unit 34, and a display unit 35. The abnormal lane detection circuit 40 includes a timing signal counting unit 41, a reference lane setting unit 42, a head lane determining unit 43, a reference lane changing unit 44, an abnormal lane detecting unit 45, and a threshold time setting unit 46. Prepare.

The deskew circuit 30 according to the present embodiment performs deskew of the signal blocks B _{0 to} B ₁₉ having a predetermined data amount. FIG. 2 shows an example of a signal block input to the deskew circuit. Signal blocks B ₀ (1) to B ₀ (8) are input to lane number # 0, signal blocks B ₁ (1) to B ₁ (8) are sequentially input to lane number # 1, and lane number # 2 is input. The signal blocks B ₂ (1) to B ₂ (8) are sequentially input, and the signal blocks B ₁₉ (1) to B ₁₉ (8) are sequentially input to the lane number # 19. Among the signal blocks B ₀ (1) to B ₁₉ (8), there is a specific block in which a predetermined identifier is included as an alignment marker. For example, the signal block B ₀ (2), the signal block B ₁ (4), the signal block B ₂ (3),..., The signal block B ₁₉ (4) are specific blocks. Hereinafter, a case where the signal block B ₀ (2) is input, then the signal block B ₂ (3) is input, and then the signal block B ₁ (4) and the signal block B ₁₉ (4) are input will be described.

  FIG. 3 shows an example of the deskew method according to the present embodiment. The deskew method according to this embodiment includes a signal block storage procedure S301, an abnormal lane detection method according to this embodiment, a delay time measurement procedure S302, and a signal block read procedure S303 in order. Hereinafter, the deskew method according to the present embodiment will be described with reference to FIG.

In the signal block storage procedure S301, the signal block _B 0 _{.about.B 19} is inputted into a plurality of lanes, and outputs a timing signal _T 0 _{through T 19} in which the synchronization unit 31 synchronizes to a particular block in the delay time measuring unit 34 for each lane At the same time, the signal blocks B _{0 to} B ₁₉ are output for each lane in correspondence with the input timing of the signal blocks B _{0 to} B ₁₉ . For example, the synchronization unit 31 outputs the timing signal T ₀ when an identifier included in the signal block B ₀ (2) illustrated in FIG. 2 is detected. The same applies to the signal blocks B _{1 to} B _{19 in} other lanes.

The data storage unit 32 stores the signal blocks B _{0 to} B ₁₉ of each lane output from the synchronization unit 31 in association with an address corresponding to the input timing to the synchronization unit 31. FIG. 4 shows an example of storage of each signal block in the data storage unit. 2 signal shown in block _{B 0 (1) ~B 0 (} 8) is, the signal block _B 0 (1) _~B 0 address _A 0 associated with the input timing of _{(8) (1) ~A 0} (8) Is remembered. The same applies to the signal blocks B ₁ (1) to B ₁₉ (8) in other lanes.

In the abnormal lane detection method according to the present embodiment, the abnormal lane detection circuit 40 uses the timing signals T _{0 to} T ₁₉ to detect a lane where a failure has occurred. The abnormal lane detection method according to the present embodiment includes a reference lane setting procedure S401, a timing signal counting procedure S402, reference lane changing procedures S404 and 405, a head lane determining procedure S406, and an abnormal lane detecting procedure S407. . Hereinafter, the abnormal lane detection method according to the present embodiment will be described with reference to FIG.

  Prior to the reference lane setting procedure S401, the threshold time setting unit 46 sets the threshold times of the timing signal counting unit 41 and the delay time measuring unit 34. The user of the deskew circuit 30 can arbitrarily set the threshold time.

In the reference lane setting procedure S401, the reference lane setting unit 42 sets any one lane among the plurality of lanes as the reference lane L _S. For example, when the lane number # 2 is input from the reference lane changing unit 44, the reference lane setting unit 42 sets the lane with the lane number # 2 as the reference lane of the timing signal counting unit 41.

The timing signal counting procedure S402, the timing signal _T 0 _{through T 19} are input to the plurality of lanes of the timing signal counting section 41. Timing signal counting section 41 counts the number of timing signals for other lanes that is input to the within a threshold time set from the time of the timing signal T ₂ of the reference lane, the count value N _T top lane determining unit 43 and The data is output to the reference lane changing unit 44. The first lane determining unit 43 stores the count value _NT and the reference lane L _S at that time.

In the reference lane changing procedures S404 and 405, the reference lane changing unit 44 determines whether or not all lanes have been set as reference lanes (S404). For example, the reference lane changing unit 44 obtains the reference lane L _S and the count value _NT from the timing signal counting unit 41 to determine whether or not all lanes have been set as the reference lane. If not all lanes are set as reference lanes, the reference lane changing unit 44 outputs the lane number _LN that has not been set as the reference lane to the reference lane setting unit 42. For example, the reference lane changing unit 44 changes the lane number # 2 of the reference lane to the lane with the lane number # 0 (S405). Then, the process proceeds to the reference lane setting procedure S401.

  In the reference lane setting procedure S401 again, when the lane number # 0 is input from the reference lane changing unit 44, the reference lane setting unit 42 sets the lane of the lane number # 0 as the reference lane of the timing signal counting unit 41. .

In the timing signal counting procedure S402 again, the timing signal counting unit 41 outputs the lane number # 0 and the count value _NT of the reference lane to the first lane determining unit 43. The leading lane determining unit 43 stores the lane number # 0 and the count value _NT of the reference lane from the timing signal counting unit 41.

When the timing signal T ₀ is input to the timing signal counting unit 41, the timing signal counting unit 41 counts the number of timing signals of other lanes input within the threshold time set from the time of the timing signal T _0. And the count value _NT is output to the leading lane determining unit 43 and the reference lane changing unit 44. The first lane determining unit 43 stores the count value _NT and the reference lane L _S at that time.

In the reference lane change procedures S404 and S405, the reference lane change unit 44 determines whether or not all lanes have been set as reference lanes (S404). For example, when all the lane numbers # 0 to # 19 are set as the reference lane, the process proceeds to the first lane determination procedure S406. At this time, the reference lane change unit 44 does not change the reference lane L _S.

In the first lane determination procedure S406, when the first lane determination unit 43 sets each lane as a reference lane, the lane number of the reference lane L _S that maximizes the count value _NT of the timing signal counting unit 41 is set to the first lane L. _{The H} lane number is determined. For example, a 19 count N _T is maximum when the lane of the lane numbers # 0 to the reference lane L _S, the count value N _T is 1 when the lane the lane numbers # 2 to the reference lane L _S in some cases, leading lane determination unit 43 determines the lane number # 0 at the beginning lane, and outputs the lane number # 0 of the first lane L _H to the address control unit 33 and the delay time measuring unit 34.

In the delay time measurement procedure S302, timing signals T _{0 to} T ₁₉ are input to the lanes of the delay time measurement unit 34. Delay time measuring unit 34, the top lane L _H in a threshold time set from the time of the timing signal T ₀ of the leading lane L _H of the timing signal T when the timing signals T ₁ ~ lane other than the leading lane from ₀ The delay times ΔT _{1 to} ΔT ₁₉ up to the time T ₁₉ are measured and output.

In the abnormality lane detection procedure S407, when the lane numbers # 0 determined by the top lane determination procedure S406 to top lane L _H, detects the lane number to which the outside threshold time. For example, the delay time measurement unit 34 has a function as a normal lane number detection unit, and the timing signals T _{0 to} T ₁₉ are input within the threshold time set from the time of the timing signal T ₀ of the first lane L _H. to detect the lane number _{L C} was. For example, when the lane of the lane number # 1 from # 16 and # 19 are detected to detect all of these lane number as lane numbers L _C. Then, the abnormal lane detecting unit 45 uses the lane number L _C, lane number L _C lane numbers that were not included in one of the lane number of 0 to 19, for example, the lane numbers # 17 and # 18, the threshold value It is detected as a lane number L _{U that} is out of time. Display unit 35 displays the lane number L _U as an abnormal lane.

In the signal block read procedure S303, the read address of the data storage unit 32 is shifted according to the delay times ΔT _{1 to} ΔT _{19 of} each lane stored in the delay time measurement procedure S302, and the signal block stored in the signal block storage procedure S301 is read. . For example, the address control unit 33 determines the address shift amount ΔA ₁ to ΔA ₁ to the address shift amount ΔA ₁ to ΔT ₁₉ according to the delay times ΔT _{1 to} ΔT _{19 of} each lane stored with the lane number # 0 determined by the first lane determination unit 43 as the _first lane. ΔA ₁₉ is output to the data storage unit 32. Then, the data storage unit 32 reads the signal block stored in the signal block storage procedure S301 with the address shifted according to the address shift amounts ΔA _{1 to} ΔA ₁₉ . For example, the read timing of the signal block B ₁ (4) is advanced by ΔA ₁ and the read timing of the address A ₂ (3) is advanced by ΔA ₂ . Thereby, the signal block B ₀ (2), the signal block B ₁ (4), the signal block B ₂ (3),..., The signal block B ₁₉ (4) are read at the same timing, and the signal blocks B _{0 to} B are read. ₁₉ deskews can be performed.

  The signal block storing procedure S301 is performed before the reference lane setting procedure S401, but may be performed simultaneously with the reference lane setting procedure S401 or between the reference lane setting procedure S401 and the delay time measuring procedure S302. Also good.

In addition, after the lanes are synchronized, the lane number # 0 of the reference lane and the address shift amounts ΔA _{0 to} ΔA ₁₉ of the data storage unit 32 can be fixed, so that the operation of the abnormal lane detection circuit 40 is stopped. May be.

(Embodiment 2)
FIG. 5 shows an example of a deskew circuit according to the second embodiment. FIG. 6 shows an example of the deskew method according to the present embodiment. The deskew circuit 30 according to the present embodiment differs in the operation of the abnormal lane detection unit 45 in the abnormal lane detection procedure S407. Only the configuration different from that of the first embodiment will be described below.

In the present embodiment, the timing signal counting procedure S402, the timing signal counting section 41 detects the lane number L _C from the timing signal T ₀ through T ₁₉ is input, along with the count value N _T is the number of timing signals lane and it outputs the number _{L C} at the top lane determination unit 43. Leading lane determination unit 43, the timing signal T ₀ through T ₁₉ stores lane number L _C that is input when the respective lanes based lane L _S.

In the first lane determination procedure S406, the first lane determination unit 43 determines the lane number L _C to which the timing signal T _{0 to} T ₁₉ is input when the lane number of the first lane L _H and the lane number are set to the reference lane L _S. Is output to the abnormal lane detection unit 45.

In the abnormality lane detection procedure S407, the abnormality lane detecting unit 45 uses the lane number L _C from the head lane determining unit 43, when the head lane L _H determined by the top lane decision procedure S406, and the outer threshold time to detect the lane number _{L U} made. For example, the abnormality lane detecting unit 45 detects the lane number L lane numbers that were not included in _C of the lane number of 0 to 19, as a lane number L _U as the outer threshold time.

(Embodiment 3)
FIG. 7 shows an example of a deskew circuit according to the third embodiment. The deskew circuit 30 according to the present embodiment differs in the operation of the abnormal lane detection unit 45 in the abnormal lane detection procedure S407. Only the configuration different from the first embodiment and the second embodiment will be described below.

In the present embodiment, in the timing signal counting procedure S402, the timing signal counting unit 41 detects the lane number L _U to which the timing signals T _{0 to} T ₁₉ are not input, and together with the count value _NT that is the number of timing signals. and it outputs the lane number L _U to the beginning lane determination unit 43. The first lane determination unit 43 stores the lane number L _U to which the timing signals T _{0 to} T ₁₉ are not input when each lane is set as the reference lane L _S.

In the top lane determination procedure S406, leading lane determination unit 43, the top lane L and lane number of the _H, the lane number L of timing signal T ₀ through T ₁₉ when the lane number in the reference lane L _S is not input _U is output to the abnormal lane detection unit 45.

In the abnormality lane detection procedure S407, the abnormality lane detecting unit 45 by acquiring the lane number L _U from the top lane determining unit 43, when the head lane L _H determined by the top lane decision procedure S406, threshold time The outside lane number is detected.

  In the first to third embodiments, an example in which a plurality of lanes are lane numbers # 0 to # 19 has been described. However, the lane numbers can be any number.

  The present invention can be applied to the information communication industry.

30: Deskew circuit 31: Synchronization unit 32: Data storage unit 33: Address control unit 34: Delay time measurement unit 35: Display unit 40: Abnormal lane detection circuit 41: Timing signal counting unit 42: Reference lane setting unit 43: Leading lane Determination unit 44: reference lane change unit 45: abnormal lane detection unit 46: threshold time setting unit

Claims (10)

A timing signal synchronized with a specific block including a predetermined identifier among signal blocks having a predetermined amount of data is input to a plurality of lanes, and the timing of one reference lane selected from the plurality of lanes A timing signal counting unit (41) for counting the number of timing signals of other lanes input within a threshold time set from the time of the signal;
A reference lane setting unit (42) for setting one lane of the plurality of lanes as the reference lane;
A reference lane changing unit (44) for sequentially changing the reference lane set by the reference lane setting unit when the threshold time in the timing signal counting unit has elapsed;
When each lane is set as the reference lane, the leading lane determining unit (43) determines the lane number of the reference lane that maximizes the number of timing signals counted by the timing signal counting unit as the lane number of the leading lane. When,
An abnormal lane detection unit (45) for detecting a lane number outside the threshold time when the lane number determined by the first lane determination unit is set as a first lane;
An abnormal lane detection circuit comprising: The timing signal is input to a plurality of lanes, and further includes a normal lane number detection unit that detects the lane number to which the timing signal is input within a threshold time set from the time point of the timing signal of the head lane.
The abnormal lane detection circuit according to claim 1, wherein the abnormal lane detection unit detects a lane number not detected by the normal lane number detection unit as a lane number outside the threshold time. The timing signal counting unit outputs the lane number to which the timing signal is input together with the number of the timing signals to the head lane determining unit,
The head lane determination unit stores the lane number to which the timing signal is input when each lane is set as the reference lane.
The abnormal lane detection unit uses the lane number stored in the head lane determination unit and uses the lane number determined by the head lane determination unit as the reference lane. The abnormal lane detection circuit according to claim 1, wherein a number is detected. The timing signal counting unit outputs the lane number in which the timing signal was not input together with the number of the timing signals to the head lane determining unit,
The leading lane determination unit stores a lane number in which the timing signal is not input when each lane is set as the reference lane.
The abnormal lane detection unit is a lane in which the timing signal is not input when the lane number determined by the first lane determination unit is set as the reference lane among the lane numbers stored in the first lane determination unit. The abnormal lane detection circuit according to claim 1, wherein a number is detected. An abnormal lane detection circuit (40) according to any of claims 1 to 4,
The signal block is input to a plurality of lanes, the timing signal is output for each lane, and the synchronization unit (31) outputs the signal block for each lane in correspondence with the input timing of the signal block;
A data storage unit (32) for storing the signal block of each lane output by the synchronization unit in association with an address corresponding to an input timing to the synchronization unit;
The timing signal is input to a plurality of lanes, and from the timing signal of the leading lane to the timing signal of the lane other than the leading lane within the threshold time set from the timing of the timing signal of the leading lane A delay time measuring unit (34) for measuring and outputting the delay time of
An address control unit (33) for shifting an address for reading the signal block from the data storage unit according to a delay time measured by the delay time measurement unit;
A deskew circuit comprising: A reference lane setting procedure (S401) for setting one lane among a plurality of lanes as a reference lane;
A timing signal synchronized with a specific block including a predetermined identifier among signal blocks having a predetermined amount of data is input to a plurality of lanes, and a threshold time set from the timing of the timing signal of the reference lane A timing signal counting procedure (S402) for counting and storing the number of timing signals input in
It is determined whether or not all lanes have been set as reference lanes. If there is a lane that has not been set, the lane number of the reference lane is changed and the reference lane change procedure for shifting to the reference lane setting procedure (S404 and 405),
After all the lanes are set as the reference lane in the reference lane setting procedure, the lane number of the reference lane that maximizes the number of timing signals stored in the timing signal counting procedure is determined as the lane number of the first lane. First lane determination procedure (S406),
An abnormal lane detection procedure (S407) for detecting a lane number outside the threshold time when the lane number determined in the first lane determination procedure is set as the first lane;
An abnormal lane detection method comprising:   In the abnormal lane detection procedure, the timing signal is input to a plurality of lanes, and the lane number to which the timing signal is input is detected within a threshold time set from the time of the timing signal of the head lane. The abnormal lane detection method according to claim 6. In the timing signal counting procedure, the lane number in which the timing signal is input is stored together with the number of the timing signals,
In the abnormal lane detection procedure, the lane number stored in the timing signal counting procedure is used to detect the lane number to which the timing signal is input within the threshold time set from the time point of the timing signal of the first lane. The abnormal lane detection method according to claim 6. In the timing signal counting procedure, a lane number in which the timing signal with the number of the timing signal is not input to memorize,
In the abnormal lane detection procedure, the lane number stored in the timing signal counting procedure is used to detect the lane number to which the timing signal is input within the threshold time set from the time point of the timing signal of the first lane. The abnormal lane detection method according to claim 6. The abnormal lane detection method according to any one of claims 6 to 9,
Before the reference lane setting procedure or between the reference lane setting procedure and the timing signal counting procedure, a timing signal synchronized with the specific block is output for each lane, and an address corresponding to the input timing of the signal block is set. A signal block storing procedure (S301) for storing the signal block;
After the leading lane determination procedure, the timing signal is input to a plurality of lanes, and the timing signal other than the leading lane from the timing of the timing signal of the leading lane is within the threshold time set from the timing of the timing signal of the leading lane. A delay time measurement procedure (S302) for measuring and outputting a delay time up to the time of the timing signal of the lane;
A signal block read procedure (S303) for shifting the address according to the delay time of each lane stored in the delay time measurement procedure and reading out the signal block stored in the signal block storage procedure;
A deskew method characterized by comprising:

Images