JP5292895B2 - Nitride semiconductor transistor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a normally-off type field effect transistor that is used for a power control device in which a drain current density equivalent to a high-frequency transistor in an on-state is available and a forward leakage current density of a gate electrode is suppressed when a positive voltage of 10-volt is applied to the gate electrode. <P>SOLUTION: A field effect transistor is produced. It adopts an MIS-type structure in which a gate electrode is provided on the surface of an electron supply layer consisting of a nitride semiconductor through an insulation film to suppress a forward leakage current density of the gate electrode. A drain electrode has such a structure that an ohmic contact is formed on a p-type nitride semiconductor layer formed on the surface of the electron supply layer. The field effect transistor has a function to inject holes from the drain electrode portion into a channel layer beyond the electron supply layer in an on-state during a high-voltage operation. <P>COPYRIGHT: (C)2010,JPO&amp;INPIT

Description

  The present invention relates to a field effect transistor using a nitride semiconductor. The present invention is particularly applicable to a power control device, and relates to a nitride semiconductor transistor having a structure that realizes low on-resistance and high breakdown voltage while maintaining a low gate leakage current.

Nitride-based semiconductors are characterized by a large band gap and a high electron saturation rate. Utilizing this advantage, field effect transistors using nitride-based semiconductors are actively developed for practical use not only for high-frequency devices but also for power control devices. In an application to a power control device, it is an enhancement (normally off) type field effect transistor that does not require a negative gate bias V _gs to be applied to the gate electrode in order to be turned off during the switching operation. Is required.

FIG. 6 shows an example of a normally-off field effect transistor that has been proposed for the purpose of application to a power control device (see Patent Document 1). The field effect transistor illustrated in FIG. 6 uses the following structure in order to obtain a drain current equivalent to that of a normally-on type high-frequency transistor. Conventionally, when a normally-off type field effect transistor is used, means for reducing the Al composition of the electron supply layer or reducing the thickness has been used. In the field effect transistor illustrated in FIG. A normally-off type is realized by forming a p ⁺ AlGaN layer directly under the gate electrode. In this structure, when a positive voltage is applied to the gate electrode, holes are injected from the p ⁺ AlGaN layer into the channel layer. At that time, generation of electrons is induced in the channel region immediately below the gate electrode due to the injected holes. Therefore, the concentration of electrons existing in the channel region directly under the gate electrode can be increased, and the drain current density in the ON state is remarkably increased. That is, the ON resistance calculated from the drain current-drain voltage (Ids-Vds) characteristics in the ON state is reduced. The normally-off type field effect transistor illustrated in FIG. 6 is characterized as having a high drain current density equivalent to that of a normally-on type transistor in the ON state.
JP 2007-19309 A

In the conventional MIS type normally-off type power control transistor, the switching operation is set to the gate voltage V _gs = 0 V in the “OFF state”, and the gate voltage V _gs is set to about +10 V in the “ON state”. . For applying the gate voltage V _{gs of} about +10 V for the switching operation to the “ON state”, the normally-off type field effect transistor illustrated in FIG. 6 needs to improve the following points. .

A normally-on transistor used as a high-frequency device uses a Schottky gate electrode, and its Schottky barrier Φ _B is about 1 eV. At this time, when the gate voltage V _gs reaches about +2 V, the forward current flowing through the Schottky junction increases rapidly, so the upper limit of the gate voltage V _{gs that} can be applied to the Schottky gate electrode is about +2 V. ing. On the other hand, in the normally-off type field effect transistor illustrated in FIG. 6, for example, a p ⁺ AlGaN layer is formed immediately below the gate electrode, and a stack of gate electrode / p ⁺ AlGaN layer / AlGaN electron supply layer / GaN channel layer is formed. Structure is used. Therefore, when a positive gate voltage V _gs is applied to the gate electrode, the pn junction constituted by the p ⁺ AlGaN layer / AlGaN electron supply layer / GaN channel layer is forward-biased. Forward current of the pn junction, the gate voltage V _gs is in a range not exceeding about + 6V from + 4V, although at a lower level, the gate voltage V _gs is more than + 6V, rapidly increases. Therefore, when an “ON signal” of +6 V or higher is used for the switching operation to the “ON state”, the gate voltage V _gs actually applied is, for example, converted to a voltage of about +5 V. Special consideration must be given when designing the circuit.

For example, when the part of the gate electrode / p ⁺ AlGaN layer is replaced with the MIS structure of the gate electrode / insulating film / p ⁺ AlGaN layer sandwiching the insulating film, the gate voltage V _gs is applied to the bias V applied to the MIS structure part. _{The MIS} is divided into a bias V _pn applied to a pn junction composed of a p ⁺ AlGaN layer / AlGaN electron supply layer / GaN channel layer. That is, Vgs = V _MIS + V _pn . When V _MIS > 0 V, the MIS structure of the gate electrode / insulating film / p ⁺ AlGaN layer formed on the p ⁺ type semiconductor is biased in the reverse direction. Therefore, the reverse current I _MIS-R of the MIS diode of the gate electrode / insulating film / p ⁺ AlGaN layer becomes equal to the forward current I _{pn-F of} the pn junction (I _MIS-R = I _pn-F ). Thus, the gate voltage V _gs is divided into V _MIS and V _pn .

As a result, for example, even if the gate voltage V _gs exceeds + 6V and reaches + 10V, the bias V _pn applied to the pn junction can actually be suppressed to + 5V or less. That is, in the MIS structure of the gate electrode / insulating film / p ⁺ AlGaN layer by an insulating film, the injection of holes from the gate electrode to the p ⁺ AlGaN layer, the electron emission from the p ⁺ AlGaN layer to the gate electrode is suppressed Therefore, it is possible to suppress a rapid increase in the gate current (forward leakage current). On the other hand, since the gate voltage V _gs is divided into V _MIS and V _pn , the control of the bias V _pn actually applied to the pn junction composed of the p ⁺ AlGaN layer / AlGaN electron supply layer / GaN channel layer is performed. Increases the difficulty. In the state where the gate current (forward leakage current) is suppressed by using the reverse I _MIS-R -V _MIS-R characteristic of the MIS diode of the gate electrode / insulating film / p ⁺ AlGaN layer, p ⁺ Hole injection from the AlGaN layer to the GaN channel layer is suppressed. Therefore, the generation of electrons due to hole injection into the GaN channel layer is also suppressed, and it is difficult to achieve the effect of reducing the on-resistance. That is, even when the gate voltage V _gs exceeds +6 V, the change in the positive direction of the potential of the p ⁺ AlGaN layer ΔV (forward bias V _pn applied to the pn junction) is small, and thus the ON state is reached. However, it is difficult to sufficiently achieve the effect of increasing the drain current density.

  The object of the present invention is to obtain a drain current density equivalent to that of a normally-on type high-frequency transistor in the “ON state”. For example, an “on signal” having a positive voltage of 10 V used in a power control transistor is used as a gate electrode. An object of the present invention is to provide a normally-off type transistor that can suppress a gate leakage current flowing through a gate electrode to a sufficiently low level when applied, and is suitable for application to a power control device.

The nitride semiconductor transistor of the present invention employs the following configuration in order to solve the above problems. For example, when an “on signal” with a positive voltage of 10 V is applied to the gate electrode, an insulating film is inserted between the gate electrode and the electron supply layer made of a nitride semiconductor in order to suppress the forward current flowing through the gate electrode. Thus, the MIS structure is used. In the “ON state”, in order to obtain a high drain current density, a p-type nitride semiconductor layer is inserted between the drain electrode and the electron supply layer made of a nitride semiconductor, and the p-type nitride semiconductor layer is inserted into the p-type nitride semiconductor layer. On the other hand, the drain electrode forms an ohmic contact. At this time, the p-type nitride semiconductor layer / the electron supply layer / channel layer structure composed of the nitride semiconductor has a P ⁺ In ⁻ junction or a P ⁺ n ⁻ junction, and therefore a positive drain voltage is applied. A forward bias is applied to the P ⁺ In ⁻ junction or P ⁺ n ⁻ junction. In this forward bias state, holes are injected from the drain electrode into the p-type nitride semiconductor layer, and further, as a diffusion current, holes are injected into the channel layer beyond the electron supply layer.

  That is, the nitride semiconductor transistor according to the present invention, for example, the nitride semiconductor transistor of the first embodiment has the following configuration.

In a normally-off type nitride semiconductor transistor in which electrons are carriers that run in the channel region directly under the gate electrode,
The nitride semiconductor transistor is
A field effect transistor having a MIS structure in which an insulating film is inserted between a gate electrode and a nitride semiconductor interface;
substrate,
A buffer layer formed by growth on the substrate;
Formed by epitaxial growth on the buffer layer;
A first nitride semiconductor layer on which carriers travel;
A second nitride semiconductor layer for supplying electrons;
A third nitride semiconductor layer having p-type conductivity is disposed only in the drain electrode and its peripheral region,
The drain electrode is in ohmic contact with the third nitride semiconductor layer having p-type conductivity,
The source electrode is a transistor that is in ohmic contact with the second nitride semiconductor layer that supplies electrons.

  In the nitride semiconductor transistor according to the present invention, a gate electrode is formed on an electron supply layer made of a nitride semiconductor via an insulating film to form a MIS structure. When a positive voltage is applied as a gate voltage to this MIS structure, the MIS structure is biased in the forward direction. The applied gate voltage is composed of a potential difference caused by an electric field in the insulating film layer and a nitride semiconductor. It is divided into potential differences caused by the electric field in the electron supply layer. As a result, the current density flowing to the gate electrode beyond the insulating film layer is suppressed. For example, even when a “positive voltage” of 10 V is applied to the gate electrode, the forward leakage current flowing to the gate electrode is suppressed to an allowable range when used as a power control device. In the “ON state”, a forward bias is applied to the stacked structure of the electron supply layer / channel layer made of p-type nitride semiconductor layer / nitride semiconductor, and holes are introduced from the drain electrode to the p-type nitride semiconductor layer. Further, as a diffusion current, holes are injected into the channel layer beyond the electron supply layer. As a result, in the “ON state”, due to holes injected into the channel layer, electrons are supplied from the source electrode side in the region where the holes are injected, and electrons are induced in the channel layer. Since electrons flowing through the channel region directly below the gate electrode and flowing into the drain region increase, the drain current density is increased as a whole. That is, in order to achieve a “normally OFF” state in the gate electrode region, the electron supply layer itself is supplied from the electron supply layer in the drain region and accumulated at the interface of the channel layer when a non-doped nitride semiconductor is used. The carrier (electron) density is suppressed. On the other hand, in the “ON state”, a forward bias is applied to the stacked structure of the electron supply layer / channel layer made of p-type nitride semiconductor layer / nitride semiconductor and holes are introduced from the drain electrode to the p-type nitride semiconductor layer. In order to inject and maintain “charge neutrality”, a high drain current density is achieved when the conditions for inducing electrons corresponding to the amount of injected holes are achieved by supplying electrons from the source electrode side. The The achieved drain current density is equivalent to or higher than the drain current density of the high-frequency transistor.

  Therefore, according to the present invention, a drain current density equivalent to that of a high-frequency transistor can be obtained, and even when a positive voltage of 10 V used in the power control transistor is applied to the gate electrode, a leakage current does not flow through the gate electrode. Type transistor is provided

  Hereinafter, the nitride semiconductor transistor according to the present invention will be described in more detail.

  The nitride semiconductor transistor according to the present invention is preferably a field effect transistor of the following three types.

In the first aspect of the present invention,
In a normally-off type nitride semiconductor transistor in which electrons are carriers that run in the channel region directly under the gate electrode,
The nitride semiconductor transistor is
A field effect transistor having a MIS structure in which an insulating film is inserted between a gate electrode and a nitride semiconductor interface;
substrate,
A buffer layer formed by growth on the substrate;
Formed by epitaxial growth on the buffer layer;
A first nitride semiconductor layer on which carriers travel;
A second nitride semiconductor layer for supplying electrons;
A third nitride semiconductor layer having p-type conductivity is disposed only in the drain electrode and its peripheral region,
The drain electrode is in ohmic contact with the third nitride semiconductor layer having p-type conductivity,
The source electrode is a transistor that is in ohmic contact with the second nitride semiconductor layer that supplies electrons.

In the second aspect of the present invention,
In a normally-off type nitride semiconductor transistor in which electrons are carriers that run in the channel region directly under the gate electrode,
The nitride semiconductor transistor is
A field effect transistor having a MIS structure in which an insulating film is inserted between a gate electrode and a nitride semiconductor interface;
substrate,
A buffer layer formed by growth on the substrate;
Formed by epitaxial growth on the buffer layer;
A first nitride semiconductor layer on which carriers travel;
A second nitride semiconductor layer for supplying electrons;
A third nitride semiconductor layer having p-type conductivity is disposed on the drain electrode and a part of its peripheral region;
The drain electrode is in contact with the third nitride semiconductor layer having p-type conductivity and the second nitride semiconductor layer supplying electrons,
The source electrode is a nitride semiconductor transistor that is in ohmic contact with the second nitride semiconductor layer that supplies electrons.

In the third aspect of the present invention,
In a normally-off type nitride semiconductor transistor in which electrons are carriers that run in the channel region directly under the gate electrode,
The nitride semiconductor transistor is
A field effect transistor having a MIS structure in which an insulating film is inserted between a gate electrode and a nitride semiconductor interface;
substrate,
A buffer layer formed by growth on the substrate;
Formed by epitaxial growth on the buffer layer;
A fourth nitride semiconductor layer that forms an energy barrier against electrons or holes;
A first nitride semiconductor layer on which carriers travel;
A second nitride semiconductor layer for supplying electrons;
A third nitride semiconductor layer having p-type conductivity is disposed only in the drain electrode and its peripheral region,
The drain electrode is in ohmic contact with the third nitride semiconductor layer having p-type conductivity,
The source electrode is in ohmic contact with the second nitride semiconductor layer that supplies electrons,
The nitride semiconductor transistor is characterized in that the source electrode and the conductive substrate are electrically connected.

In the nitride semiconductor transistor of the present invention,
The MIS structure with an insulating film inserted between the gate electrode and the nitride semiconductor interface is
An insulating film made of an insulating material and formed on the nitride semiconductor;
A structure including a gate electrode formed on the insulating film can be selected.

In addition, the MIS structure in which an insulating film is inserted between the gate electrode and the nitride semiconductor interface is
An insulating film made of an insulating material, formed on the second nitride semiconductor layer;
The gate electrode is formed on the insulating film,
The second nitride semiconductor layer disposed under the gate electrode has a fluorine atom-containing region to which fluorine atoms are added,
As the fluorine atom-containing region of the second nitride semiconductor layer, a structure containing about 1 × 10 ¹³ cm ⁻² of fluorine atoms can be selected as the surface density.

Furthermore, the MIS structure in which an insulating film is inserted between the gate electrode and the nitride semiconductor interface is
An undoped nitride semiconductor layer selectively grown on a portion of the second nitride semiconductor layer immediately below the gate electrode;
An insulating film formed of an insulating material so as to cover the surface of the undoped nitride semiconductor layer;
The gate electrode is formed on the insulating film,
A structure in which negative polarization charges are generated at the interface between the second nitride semiconductor layer and the undoped nitride semiconductor layer can be selected.

In the nitride semiconductor transistor of the present invention,
The third nitride semiconductor layer having p-type conductivity is formed on the surface of the second nitride semiconductor layer that supplies electrons,
The junction between the third nitride semiconductor layer having the p-type conductivity and the second nitride semiconductor layer preferably employs a structure constituting a p ⁺ n junction or a p ⁺ i junction.

that time,
The second nitride semiconductor layer that supplies electrons is formed on the surface of the first nitride semiconductor layer in which carriers travel,
The junction surface between the second nitride semiconductor layer that supplies electrons and the first nitride semiconductor layer in which carriers travel preferably employs a structure that forms a heterojunction interface.

In particular, in the nitride semiconductor transistor according to the third aspect of the present invention,
A fourth nitride semiconductor layer that forms an energy barrier against electrons or holes is formed on the surface of the buffer layer;
The first nitride semiconductor layer in which carriers travel is formed on the surface of the fourth nitride semiconductor layer,
In the stacked structure of the first nitride semiconductor layer / the fourth nitride semiconductor layer / the buffer layer,
The fourth nitride semiconductor layer is
It is possible to adopt a structure that forms an energy barrier in the injection path from the buffer layer to the first nitride semiconductor layer with respect to electrons and holes, which are carriers that determine the conductivity in the conductive substrate. preferable.

For example,
The conductive substrate is an n-type conductive substrate,
The fourth nitride semiconductor layer that forms an energy barrier against electrons or holes can employ a structure that is a nitride semiconductor layer that forms an energy barrier against electrons.

Or
The conductive substrate is a p-type conductive substrate,
The fourth nitride semiconductor layer that forms an energy barrier against electrons or holes may employ a structure that is a nitride semiconductor layer that forms an energy barrier against holes.

In the nitride semiconductor transistor according to the third aspect of the present invention, for example,
A back electrode is formed on the back surface of the conductive substrate,
A structure in which the source electrode and the back electrode of the conductive substrate are electrically connected is employed.

On the other hand, in the nitride semiconductor transistor according to the first and second embodiments of the present invention,
The substrate is preferably a high resistance substrate.

In the nitride semiconductor transistor according to the second aspect of the present invention,
The drain electrode is in ohmic contact with the third nitride semiconductor layer having p-type conductivity,
The drain electrode preferably employs a structure in which a Schottky junction is formed in contact with the second nitride semiconductor layer that supplies electrons. For example,
It is possible to select a structure in which the barrier height of the Schottky junction formed by the contact between the drain electrode and the second nitride semiconductor layer that supplies electrons is in the range of 0.8 eV to 1.1 eV. is there.

In the nitride semiconductor transistor according to the present invention, for example,
The third nitride semiconductor layer having p-type conductivity is formed on the surface of the second nitride semiconductor layer that supplies electrons,
The second nitride semiconductor layer that supplies electrons is formed on the surface of the first nitride semiconductor layer in which carriers travel,
The stacked structure of the third nitride semiconductor layer / second nitride semiconductor layer / first nitride semiconductor layer having p-type conductivity constitutes a p ⁺ n junction or a p ⁺ in junction. ,
It is preferable to use a structure in which the built-in potential formed by the p ⁺ n junction or the p ⁺ in junction is in the range of 0.7 eV to 5.0 eV.

In the nitride semiconductor transistor according to the present invention, for example,
In the heterojunction interface formed at the junction surface between the second nitride semiconductor layer that supplies electrons and the first nitride semiconductor layer in which carriers travel,
Due to the discontinuity of the conduction band edge energy between the second nitride semiconductor layer and the first nitride semiconductor layer, a potential barrier is formed in the conduction band,
A structure in which the potential barrier formed in the conduction band at the heterojunction interface is in the range of 0.13 eV to 0.77 eV can be selected.

Moreover,
In the heterojunction interface formed at the junction surface between the second nitride semiconductor layer that supplies electrons and the first nitride semiconductor layer in which carriers travel,
Due to the discontinuity of the valence band edge energy between the second nitride semiconductor layer and the first nitride semiconductor layer, a potential barrier is formed in the valence band,
A structure in which the potential barrier formed in the valence band at the heterojunction interface is in the range of 0.05 eV to 0.33 eV can be selected.

In the nitride semiconductor transistor according to the present invention,
A nitride semiconductor layer formed by epitaxial growth on a substrate is
It is preferable to produce a structure having a (0001) plane growth.

  A preferred embodiment of the above-described nitride semiconductor transistor according to the present invention will be further described.

First, in the first and second embodiments, the buffer layer, the first nitride semiconductor layer in which carriers travel, the second nitride semiconductor layer for supplying electrons, and the third having p-type conductivity. The nitride semiconductor layer includes an epitaxial growth film in which a buffer layer is grown on the substrate, and a first nitride semiconductor / second nitride semiconductor layer / third nitride semiconductor layer is sequentially stacked on the buffer layer. Can be used. For example, a first nitride semiconductor layer in which carriers travel, a second nitride semiconductor layer that supplies electrons, a third nitride semiconductor layer having p-type conductivity, a GaN channel layer, an AlGaN electron supply layer When selecting the P ⁺ -type AlGaN layer, it is preferable to select the following configuration as the buffer layer.

  In the step of forming the buffer layer by growth on the substrate, it is preferable to first grow a non-doped AlN thin film as the underlayer and use it as the nucleation layer. The thickness of the non-doped AlN thin film used as the nucleation layer is preferably selected in the range of 4 nm to 200 nm. The non-doped AlN thin film itself becomes an insulating thin film. Next, an AlGaN / GaN periodic layer is formed by epitaxial growth using the nucleation layer as a base layer.

The AlGaN / GaN periodic layer has a structure formed by laminating GaN layer having a film thickness t _b of the AlGaN layer and the thickness t _w alternately. The film thickness period (t _b + t _w ) is preferably selected in the range of 1 nm to 5 nm, and the total film thickness of the AlGaN / GaN periodic layer is preferably selected in the range of 100 nm to 500 nm. Composition of AlGaN layer having thickness t _b : Al composition (x ₀ ) in Al _x0 Ga _1-x0 N is selected in the range of 1.0 ≧ x ₀ ≧ 0.1. Thickness t _b of the AlGaN layer and the thickness t ratio of GaN layer of _w t _b: t _w is 1: 2 to 2: it is preferable to select one of the ranges.

In the AlGaN / GaN periodic layer, the difference between the conduction band edge energy Ec of the Al _x0 Ga _1-x0 N layer (Al _x0 Ga _1-x0 N) and the conduction band edge energy Ec (GaN) of the GaN layer, the band discontinuity ΔEc ( Due to (Al _x0 Ga _1-x0 N / GaN), the conduction band edge energy has a periodic structure. Further, the difference between the valence band edge energy Ev (Al _x0 Ga _{1 -x0} N) of the AlGaN layer and the valence band edge energy Ev (GaN) of the GaN layer, the band discontinuity ΔEv (Al _x0 Ga _{1 -x0} N / GaN). ), The valence band edge energy has a periodic structure. When the film thickness period (t _b + t _w ) is sufficiently thin, electrons and holes of free carriers are converted into effective conduction band edge energy Ec _-eff (Al _x0 Ga ₁₎ instead of the above periodic potential structure. _−x0 N / GaN), which is controlled by the effective valence band edge energy Ev _−eff (Al _x0 Ga _1−x0 N / GaN). The effective conduction band edge energy _{Ec -eff (Al x0 Ga 1-} x0 N / GaN) _{is, Ec (Al x0 Ga 1-} x0 N)> Ec -eff (Al x0 Ga 1-x0 N / GaN)> The effective valence band edge energy Ev _-eff (Al _x0 Ga _{1 -x0} N / GaN) located in Ec (GaN) is expressed as Ev (GaN)> Ev _-eff (Al _x0 Ga _{1 -x0} N / GaN). )> Ev (Al _x0 Ga _1-x0 N). The position depends on the film thickness ratio t _b : t _w and the film thickness cycle (t _b + t _w ). For example, even if the film thickness ratio t _b : t _w is the same, when the film thickness period (t _b + t _w ) decreases, Ec _−eff (Al _x0 Ga _1−x0 N / GaN) increases and Ev _{− eff} ( _{Alx0Ga1 -x0N} / GaN) falls.

At the heterojunction interface between the AlN nucleation layer and the AlGaN / GaN periodic layer, the conduction band edge energy Ec (AlN) of AlN and the effective conduction band edge energy Ec _-eff (Al _x0 Ga _{1 -x0} N / GaN) ), Which is equivalent to the difference from), has a band discontinuity: ΔEc (AlN / (Al _x0 Ga _1-x0 N / GaN)).

On the surface of the AlGaN / GaN periodic layer, the effective lattice constant a (AlGaN / GaN) is usually GaN lattice constant a (GaN), Al _x0 Ga1- _x0 N lattice constant a (Al _x0 Ga1- _x0). N), a (GaN) ≧ a (AlGaN / GaN)> a (Al _x0 Ga1- _x0 N). That is, the lattice relaxation proceeds by periodically laminating each AlGaN / GaN thin film layer from the lattice constant a (AlN) of AlN used as a nucleation layer, and the effective lattice constant a ( AlGaN / GaN).

The GaN channel layer, AlGaN electron supply layer, and P ⁺ -type AlGaN layer can be formed by epitaxial growth on the surface of the AlGaN / GaN periodic layer having this effective lattice constant a (AlGaN / GaN).

  In the above example, after forming an AlN layer used as a nucleation layer, lattice relaxation is performed using an AlGaN / GaN periodic layer structure, but an AlGaN layer having an average Al composition of the periodic structure is formed. Even if it is used, the same lattice relaxation effect can be obtained.

Similarly, in the third embodiment, the buffer layer, the fourth nitride semiconductor layer that forms an energy barrier against electrons or holes, the first nitride semiconductor layer in which carriers travel, the second nitride that supplies electrons The third nitride semiconductor layer having p-type conductivity is formed on the substrate, and a buffer layer is grown on the substrate, and the fourth nitride semiconductor / first nitride semiconductor layer / first nitride layer is formed on the buffer layer. An epitaxially grown film in which two nitride semiconductor layers / third nitride semiconductor layers are sequentially stacked can be used. For example, a fourth nitride semiconductor layer that forms an energy barrier against electrons or holes, a first nitride semiconductor layer that carries carriers, a second nitride semiconductor layer that supplies electrons, and p-type conductivity When the P ⁺ -type AlGaN barrier layer, the GaN channel layer, the AlGaN electron supply layer, and the P ⁺ -type AlGaN layer are selected as the third nitride semiconductor layer, the following configuration can be selected as the buffer layer: preferable.

  In the step of forming the buffer layer by epitaxial growth on the substrate, it is preferable to first grow a non-doped AlN thin film as the underlayer and use it as a nucleation layer. The thickness of the non-doped AlN thin film used as the nucleation layer is preferably selected in the range of 4 nm to 200 nm. The non-doped AlN thin film itself becomes an insulating thin film. Next, an AlGaN / GaN periodic layer is formed by epitaxial growth using the nucleation layer as a base layer.

The AlGaN / GaN periodic layer has a structure formed by laminating GaN layer having a film thickness t _b of the AlGaN layer and the thickness t _w alternately. The film thickness period: (t _b + t _w ) is preferably selected in the range of 1 nm to 5 nm, and the total film thickness of the AlGaN / GaN periodic layer is preferably selected in the range of 100 nm to 500 nm. Composition of AlGaN layer having thickness t _b : Al composition (x ₀ ) in Al _x0 Ga1- _x0 N is selected in the range of 1.0 ≧ x ₀ ≧ 0.05. The ratio of the GaN layer having a thickness t _b of the AlGaN layer and the thickness t _w, t _b: t _w is 2: 1 to 1: it is preferable to select the 2 range.

On the surface of the AlGaN / GaN periodic layer, the effective lattice constant a (AlGaN / GaN) is usually GaN lattice constant a (GaN), Al _x0 Ga1- _x0 N lattice constant a (Al _x0 Ga1- _x0). N), a (GaN)> a (AlGaN / GaN) ≧ a (Al _x0 Ga1- _x0 N). That is, the lattice relaxation proceeds by periodically laminating each AlGaN / GaN thin film layer from the lattice constant a (AlN) of AlN used as a nucleation layer, and the effective lattice constant a ( AlGaN / GaN).

  In the above example, after forming an AlN layer used as a nucleation layer, lattice relaxation is performed using an AlGaN / GaN periodic layer structure, but an AlGaN layer having an average Al composition of the periodic structure is formed. Even if it is used, the same lattice relaxation effect can be obtained.

The P ⁺ -type AlGaN barrier layer, GaN channel layer, AlGaN electron supply layer, and P ⁺ -type AlGaN layer are formed by epitaxial growth on the surface of the AlGaN / GaN periodic layer having this effective lattice constant a (AlGaN / GaN). Can do.

  The buffer layer, a fourth nitride semiconductor layer that forms an energy barrier against electrons or holes, a first nitride semiconductor layer in which carriers travel, a second nitride semiconductor layer that supplies electrons, and p-type conductivity The third nitride semiconductor layer having the property is formed of a growth film having a hexagonal crystal system (wurtzite structure) on the substrate. Table 1 shows some of the structural constants and physical constants of Group III nitride semiconductors having a hexagonal crystal system; AlN, GaN, and InN.

  In general, substrates shown in Table 2-1 are known as substrates that can be used for epitaxial growth of group III nitride semiconductors. The thermal and electrical characteristics of the substrate material are shown in Table 2-2.

  It has been reported that when an AlN layer for a nucleation layer is grown on the surface of various substrates, the relationship between the crystal orientations of both is as shown in Table 2-3 below.

In the nitride semiconductor transistor according to the present invention, the buffer layer, the fourth nitride semiconductor layer forming an energy barrier against electrons or holes, the first nitride semiconductor layer in which carriers travel, the first supplying electrons. Both the nitride semiconductor layer 2 and the third nitride semiconductor layer having p-type conductivity are preferably (0001) plane growth films. Therefore, it is preferable to use a substrate on which the AlN nucleation layer formed on the substrate is capable of C-plane ((0001) plane) growth. Therefore, as a substrate, an SiC C-plane ((0001) plane) substrate, a sapphire (α-Al ₂ O ₃ ) C-plane ((0001) plane) substrate, an Si o-plane ((111) plane) substrate, AlN , It is preferable to use a C-plane ((0001) plane) substrate of GaN. As the Si substrate and the SiC substrate, a large-diameter substrate is easily available, and is a suitable substrate for producing the multilayer epitaxial film.

In the first and second embodiments, a high resistance substrate is used as the substrate. The resistivity ρ _sub of the high resistance substrate is ρ _sub ≧ 1 × 10 ⁵ It is preferable to set to Ω · cm.

The AlN layer for the nucleation layer formed on the surface is also made of insulating AlN. If the band gap energy of AlN is Eg (AlN), the difference between the conduction band edge Ec (AlN-top) and the Fermi level E _f (Ec (AlN-top) on the surface of the AlN nucleation layer. ) −E _f ) is (Ec (AlN−top) −E _f ) ≈1 / 2 · Eg (AlN).

In the first form and the second form, it is preferable that the first nitride semiconductor layer in which carriers travel is composed of a non-doped nitride semiconductor. At that time, the film thickness t _{S1 of} the first nitride semiconductor layer and the remaining donor concentration N _D-S1 are as follows when the dielectric constant of the first nitride semiconductor layer is ε _r-S1. It is preferable to select a range that satisfies the above. For example, (N _D-S1 · t _S1 ) is (1 × 10 ¹⁶ cm ⁻³ ) · (10 ⁻⁴ cm) ≧ N _D-S1 · t _S1 ≧ (0.01 × 10 ¹⁵ cm ⁻³ ) · The range is (10 ⁻⁴ cm). At this time, the film thickness t _S1 of the first nitride semiconductor layer is GaN breakdown field strength (E _B (GaN)) 3 × 10 in order to achieve an operating voltage (drain voltage V _ds ) of 300 V to 600 V. Considering ⁶ cm ⁻¹ , it is preferable to select 1000 nm or more so as to satisfy the condition of E _B (GaN) · t _S1 ≧ 300V. On the other hand, the film thickness t _S1 of the first nitride semiconductor layer is preferably selected to be 5000 nm or less in order to reduce the warpage of the wafer to 5000 nm or less and suppress the occurrence of cracks.

When the first nitride semiconductor layer is depleted, the amount of change in potential due to the space charge is 1/2 · {q / ε _r-S1 } · N _D-S1 · (t _S1 ) ² eV.

When the interface between the first nitride semiconductor layer in which carriers travel and the buffer layer is, for example, an interface between a GaN channel layer and an AlGaN / GaN periodic layer, this interface has a barrier caused by band discontinuity. Exists. This barrier to electrons corresponds to the difference between the conduction band edge energy Ec (GaN) of GaN and the effective conduction band edge energy Ec _-eff (Al _x0 Ga _{1 -x0} N / GaN). The band _{discontinuity: ΔEc ((Al x0 Ga 1} -x0 N / GaN) / GaN) = by using a _{{Ec -eff (Al x0 Ga 1} -x0 N / GaN) -Ec (GaN)}, GaN channel Electrons are confined in the layer. The barrier against holes corresponds to the difference between the valence band edge energy Ev (GaN) of GaN and the effective conduction band edge energy Ev _-eff (Al _x0 Ga _{1 -x0} N / GaN). Using this band discontinuity: ΔEv ((Al _x0 Ga ₁ -x0 N / GaN) / GaN) = {Ev (GaN) -Ev _-eff (Al _x0 Ga _{1 -x0} N / GaN)}, a GaN channel Hole confinement in the layer.

Therefore, for temperature T (T = 300 K), ΔEc ((Al _x0 Ga _1−x0 N / GaN) / GaN)> 2 kT (k represents Boltzmann constant) and ΔEv ((Al _x0 Ga _{1− x0 N / GaN) / GaN)} > 2kT to meet, the structure of the AlGaN / GaN periodic layer, is preferably selected from the range described above.

The second nitride semiconductor layer that supplies electrons is also preferably composed of a non-doped nitride semiconductor. At this time, the film thickness t _{S2 of} the second nitride semiconductor layer and the remaining donor concentration N _{D-S2 satisfy} the following conditions when the dielectric constant of the second nitride semiconductor is ε _r-S2. It is preferable to select the range to satisfy. When the polarization charge σ _{S2 / S1} generated at the interface between the second nitride semiconductor layer and the first nitride semiconductor layer is σ _{S2 / S1} = 1 × 10 ¹³ cm ⁻² , from σ _{S2 / S1} The range is selected so that (N _D-S2 · t _S2 ) satisfies a sufficiently small condition. For example, (N _D-S2 · t _S2 ) is (5 × 10 ¹⁸ cm ⁻³ ) · (30 × 10 ⁻⁷ cm) ≧ N _D-S2 · t _S2 ≧ (1 × 10 ¹⁵ cm ⁻³ ) · The range is (30 × 10 ⁻⁷ cm).

When the second nitride semiconductor layer is depleted, the amount of change in potential due to the space charge is 1/2 · {q / ε _r-S2 } · N _D-S2 · (t _S2 ) ² eV. At that time, the gate metal and the second nitride semiconductor layer have a Schottky barrier height and can be normally turned off, for example, 1.5 eV ≧ 1/2 · {q / ε _r-S2 } · N It is preferable to select the film thickness t _S2 for the remaining donor concentration N _D-S2 so as to satisfy _D-S2 · (t _S2 ) ² eV ≧ 0 eV.

For example, an AlGaN electron supply layer is adopted as the second nitride semiconductor layer for supplying electrons, a GaN channel layer is used as the first nitride semiconductor layer in which carriers travel, and an AlGaN electron supply layer and a GaN channel layer are used. To form a heterojunction interface. Composition of AlGaN electron supply layer: The Al composition (x ₂ ) in Al _x2 Ga _1-x2 N is preferably selected as follows.

This heterojunction interface, Al _x2 Ga _1-x2 due to the difference of the conduction band edge energy _{Ec (Al x2 Ga 1-x2} N) and GaN of the conduction band edge energy Ec (GaN) of N, band discontinuity .DELTA.Ec (Al _{x2 Ga 1-x2 N / GaN)} = {Ec (Al x2 Ga 1-x2 N) -Ec (GaN)} is present. Further, the band discontinuity ΔEv (Al _x2 Ga ₁ ) due to the difference between the valence band edge energy Ev (Al _x0 Ga _{1 -x0} N) of Al _x2 Ga _{1 -x2} N and the valence band edge energy Ev (GaN) of GaN. _{-x2 N / GaN) = {Ev} (GaN) -Ev (Al x2 Ga 1-x2 N)} is present. Electrons are stored in the GaN channel layer using this band discontinuity ΔEc (Al _x2 Ga _{1 -x2} N / GaN) as a barrier against electrons. The band discontinuity ΔEv (Al _x2 Ga _{1 -x2} N / GaN) is used as a barrier against holes.

Therefore, for temperature T (T = 300K), ΔEc ((Al _x2 Ga _1−x2 N / GaN) / GaN)> 2 kT (k represents Boltzmann constant) and ΔEv ((Al _x2 Ga ₁₋ The Al composition (x ₂ ) of Al _x2 Ga _1-x2 N is preferably selected in the range of x ₂ ≧ 0.04 so as to satisfy _{x 2} N / GaN) / GaN)> 2 kT.

On the other hand, considering the critical film thickness depending on lattice mismatch when epitaxially growing on GaN, the Al composition (x ₂ ) of Al _x2 Ga _1-x2 N should be selected in the range of 0.5 ≧ x _2. Is preferred.

Therefore, when the second nitride semiconductor layer / first nitride semiconductor layer has an Al _x2 Ga _{1 -x2} N / GaN structure, the Al composition (x ₂ ) of Al _x2 Ga _{1 -x2} N is: It is desirable to select in the range of 0.5 ≧ x ₂ ≧ 0.04.

On the other hand, the source electrode forms an ohmic contact with the surface of the second nitride semiconductor layer that supplies electrons. At that time, the contact resistivity ρ _C is preferably ρ _C ≦ 1 × 10 ⁻³ Ω · cm ⁻² . Therefore, when an AlGaN electron supply layer is used as the second nitride semiconductor layer for supplying electrons, the Al composition (x ₂ ) of Al _x2 Ga _{1 -x2} N is in the range of 0.4 ≧ x ₂ ≧ 0. It is preferable to select.

Immediately below the source electrode, electrons are accumulated at the heterojunction interface between the second nitride semiconductor layer that supplies electrons and the first nitride semiconductor layer in which carriers travel, thereby forming a two-dimensional electron gas. Is preferred. Therefore, at the heterojunction interface, the difference between the conduction band edge energy Ec (S2 _−rear ) of the second nitride semiconductor layer and the Fermi level E _f (Ec (S2 _−rear ) −E _f ) is at least , (Ec (S2− _rear ) −E _f ) ≧ 2 _kT . The conduction band edge energy Ec (S2- _rear ) of the second nitride semiconductor layer and the conduction band edge energy Ec (1) of the first nitride semiconductor layer at the heterojunction interface used for forming the two-dimensional electron gas. difference _S1 -front) shall be _{{Ec (S2 -rear) -Ec (} S1 -front)}> (Ec (S2 -rear) -E f) ≧ 2kT. Preferably, it selects the range of _{0.77eV ≧ {Ec (S2 -rear)} -Ec (S1 -front)} ≧ 0.1eV.

On the other hand, at the heterojunction interface, the difference between the valence band edge energy Ev (S2 _−rear ) of the second nitride semiconductor layer and the valence band edge energy Ev (S1 _−front ) of the first nitride semiconductor layer. Also, {Ev (S1- _front ) -Ev (S2- _rear )}> _2kT . Preferably, a range of 0.33 eV ≧ {Ev (S1 _−front ) −Ev (S2 _−rear )} ≧ 0.05 eV is selected.

Of course, immediately below the source electrode, the difference between the valence band edge energy Ev (S1 _-front ) of the first nitride semiconductor layer and the Fermi level E _f (E _f -Ev (S1 _-front )) is obtained. , At least, (E _f −Ev (S1 _−front )) >> kT. A first nitride semiconductor layer of the conduction band edge energy _Ec (S1 -front), the difference between the Fermi level _{E f (E f -Ec (S1} -front)) _is, (E _f -Ec (S1 -front ))> KT.

Furthermore, the source electrode forms an ohmic contact with the surface of the second nitride semiconductor layer. That is, the second nitride semiconductor layer is configured such that electrons are injected from the metal of the source electrode in contact with the surface thereof. At that time, the barrier height barrier, Φ _{M / S2} , between the second nitride semiconductor layer and the metal of the source electrode in contact with the surface thereof is the electron affinity eχ (S2) eV of the second nitride semiconductor. This corresponds to the difference from the work function eψ (M _ohmic ) eV of the metal material _Mohmic in contact with the surface thereof, {eψ (M _ohmic ) −eχ (S2)}. In the present invention, Φ _{M / S2} is preferably selected in the range of 0.85 eV ≧ Φ _{M / S2} ≧ 0 eV.

When the drain voltage V _ds is higher than the offset voltage (V _ds > V _off-set ) and the gate voltage V _gs is V _gs > V _T , when the drain voltage I _d flows, The source electrode / second nitride semiconductor layer / first nitride semiconductor layer is biased in the reverse direction. As a result, electrons are injected from the source electrode into the second nitride semiconductor layer and further accumulated at the interface between the second nitride semiconductor layer and the first nitride semiconductor layer. At that time, a current corresponding to the drain current I _d flows through the source electrode.

When forming the source electrode, Ti, Nb, Mo, Ta, or the like can be used as the metal material _Mohmic in contact with the surface of the second nitride semiconductor. The work function eψ (M _ohmic ) eV of these metal materials _Mohmic is, for example, the work function of Ti is eψ (Ti) eV = 4.3 eV. In the formation of the source electrode, a metal having a work function eψ (M _ohmic ) eV in the range of 5.0 eV ≧ eψ (M _ohmic ) ≧ 4.0 eV is _used as the metal material M _ohmic in contact with the surface of the second nitride semiconductor. Can be used.

The drain electrode contacts the surface of the p-type conductive third nitride semiconductor layer to form an ohmic contact. The p-type conductive third nitride semiconductor layer is the same nitride semiconductor as the second nitride semiconductor layer. However, the p-type conductive third nitride semiconductor layer is doped with an acceptor at a high concentration to exhibit P ⁺ -type conductivity. A semiconductor layer is preferable. The concentration N _A-S3 of acceptor impurity atoms doped in the p-type conductive third nitride semiconductor layer is in the range of 5 × 10 ¹⁹ cm ⁻³ ≧ N _D-S1 ≧ 2 × 10 ¹⁸ cm ⁻³ . To do. The film thickness t _S3 of the p-type conductive third nitride semiconductor layer can be selected in the range of 200 nm ≧ t _S3 ≧ 20 nm.

The barrier height barrier between the third nitride semiconductor layer and the metal of the drain electrode in contact with the surface thereof, Φ _{M / S3} is the electron affinity eχ (S3) eV of the third nitride semiconductor and the surface thereof This corresponds to the difference from the work function eψ (M _drein ) eV of the metal material M _drein in contact with, {eψ (M _drain ) −eχ (S3)} When the drain electrode is formed, Ni, Pt, Au, Pd, or the like can be used as the metal material M _drain in contact with the surface of the p-type conductive third nitride semiconductor. The work function eψ (M _drain ) eV of these metal materials M _drain is, for example, the work function of Ni is eψ (Ni) eV = 5.2 eV. In the formation of the drain electrode, the work function eψ (M _drain ) eV is 6.0 eV ≧ eψ (M _drain ) ≧ 5.1 eV as the metal material M _drain in contact with the surface of the p-type conductive third nitride semiconductor. A range of metals can be utilized.

Immediately below the gate electrode, a gate electrode is formed on the surface of the second nitride semiconductor via an insulating film. At the gate electrode / insulating film interface, among the gate electrodes, the work function eψ (M _gate ) eV of the metal material M _gate in contact with the surface of the insulating film and the electron affinity eχ (I of the insulating material I _{front on} the surface of the insulating film. _front ) The barrier Φ _{M / I} corresponding to the difference from eV, (eψ (M _gate ) −eχ (I _front )) eV, is generated. At the insulating film / second nitride semiconductor layer interface, the electron affinity eχ (I _rear ) eV of the insulating material I _rear on the back surface of the insulating film and the electron affinity eχ (S2) eV of the second nitride semiconductor layer The barrier Φ _{I / S} corresponding to (eχ (S2) −eχ (I _rear )) eV is generated.

Among the gate electrodes, Ni, Pt, Au, Pd, Al, Mo, Nb, Ta, or the like can be used as the metal material M _gate in contact with the surface of the insulating film. The work function eψ (M _gate ) eV of these metal materials M _gate is, for example, eψ (Ni) eV = 5.1 eV. As the metal material M _gate in contact with the surface of the insulating film, a metal having a work function eψ (M _gate ) eV of 6.0 eV ≧ eψ (M _gate ) ≧ 4.0 eV can be used.

As the insulating film, for example, a film made of an insulator such as SiN, SiO ₂ , Al ₂ O ₃ , Hf ₂ O ₃ , MgO, or ZnO can be used. In this case, when the insulating film is a single layer, the insulating material I _front on the _front surface and the insulating material I _rear on the back surface are the same insulating material, and the electron affinity eχ (I _front ) eV and the electron affinity eχ (I _rear ) eV is equal. For example, the electron affinity of SiN is eχ (SiN) eV = 0.9 eV. As the insulating film, an insulating material having an electron affinity eχ (I) in a range of eχ (I) ≧ eψ (M _gate ) can be used. The insulating film may be composed of a plurality of layers, for example, SiO ₂ / SiN, Hf ₂ O ₃ / Al ₂ O ₃ or the like.

In addition, immediately under the gate electrode, the structure of the gate electrode / insulating film / second nitride semiconductor layer is inserted, and an undoped thin nitride semiconductor film is inserted at the interface between the insulating film and the second nitride semiconductor layer. It can be changed to a structure. The thickness t _{spacer of the} undoped thin nitride semiconductor film to be inserted and the remaining donor concentration N _D-spacer are, for example, (N _D-spacer · t _spacerS2 ), (1 × 10 ¹⁷ cm ⁻³ ) (10 × 10 ⁻⁷ cm) ≧ N _D-spacerS2 · t _spacerS2 ≧ (1 × 10 ¹⁵ cm ⁻³ ) · (10 × 10 ⁻⁷ cm)

In the nitride semiconductor transistor according to the present invention, when the drain voltage V _ds is set to V _ds = 0V and the gate voltage V _gs is set to V _gs = 0V, the nitride semiconductor transistor is in the “OFF state”. In that case, immediately below the gate electrode, the second nitride semiconductor layer / first nitride semiconductor layer in the stacked structure of the gate electrode / insulating film / second nitride semiconductor layer / first nitride semiconductor layer. In the interface, no carriers (electrons) exist. Therefore, at the interface between the second nitride semiconductor layer and the first nitride semiconductor layer, the difference between the conduction band edge energy Ec (S1 _-front ) of the first nitride semiconductor layer and the Fermi level E _f ( _Ec (S1 -front) -E _f) has become a _{(Ec (S1 -front) -E f} )> kT. On the other hand, considering the difference in conduction band edge energy between the second nitride semiconductor and the first nitride semiconductor, the band discontinuity {Ec (S2) −Ec (S1)} = ΔEc (S2 / S1) at the interface, and the second nitride semiconductor layer of the conduction band edge energy _Ec (S2 -rear), the difference between the Fermi level _{E f (Ec (S2 -rear)} -E f) _is, (Ec (S2 -rear ) −E _f )> ΔEc (S2 / S1) + kT. Furthermore, in the channel region, the difference between the conduction band edge energy Ec (S2 _-front ) of the second nitride semiconductor layer and the Fermi level E _{f at} the interface between the insulating film and the second nitride semiconductor layer ( _Ec (S2 -front) -E _f) has a _{(Ec (S2 -front) -E f} )> (Ec (S2 -rear) -E f)> ΔEc (S2 / S1) + kT. Therefore, at least in the channel region directly below the gate electrode, the undoped thin nitride semiconductor film / second nitride semiconductor layer portion is depleted.

  In the third embodiment, a conductive substrate is used as the substrate.

  When an n-type conductive substrate is used as the conductive substrate, a fourth nitride semiconductor layer that forms an energy barrier against electrons between the buffer layer and the first nitride semiconductor layer in which carriers travel. Is provided.

For example, a P ⁺ conductive nitride semiconductor layer can be used as the fourth nitride semiconductor layer that forms an energy barrier against electrons. The film thickness t _{S4: P +} of the P ⁺ conductive nitride semiconductor layer and the acceptor impurity concentration N _A-S4 are, for example, (N _A-S4 · t _{S4: P +} ), (5 × 10 ¹⁹ cm ^{− 3} ) ・ (30 × 10 ⁻⁷ cm) ≧ (NA _−S4 · t _{S4: P +} ) ≧ (5 × 10 ¹⁸ cm ⁻³ ) · (30 × 10 ⁻⁷ cm) is there. The junction surface between the first nitride semiconductor layer and the P ⁺ conductive nitride semiconductor layer is an nP ⁺ type junction. The energy barrier for electrons corresponds to the _built-in potential of the nP ⁺ type junction, eV _built-in (S1 / S4).

Alternatively, the fourth nitride semiconductor layer that forms an energy barrier against electrons is insulative and has a difference in conduction band edge energy Ec with respect to the conductive substrate, that is, the conduction band edge energy Ec (Sub of the substrate). ) And the difference between the conduction band edge energies Ec (S3) of the fourth nitride semiconductor layer, ΔEc (Sub / S3) can be selected. As the fourth nitride semiconductor layer, for example, an insulating nitride semiconductor layer that satisfies the condition of 0.77 eV> ΔEc (Sub / S3)> 3 kT eV can be used. In this case, the structure of the substrate / buffer layer / fourth nitride semiconductor layer / first nitride semiconductor layer exhibits N ⁺ / n / i / n conductivity, for example. That is, an n-i-n type tunnel diode structure is formed, and the fourth nitride semiconductor layer functions as an energy barrier against electrons.

Further, a back electrode is provided on the back surface of the n-type conductive substrate, and the back electrode is kept at the same potential as the source electrode. In this case, the nP ⁺ type junction is biased in the reverse direction, and the inflow of electrons from the n type conductive substrate to the first nitride semiconductor layer beyond the nP ⁺ type junction is performed. It is suppressed. Also, when an n-i-n heterojunction is used as an energy barrier against electrons, the inflow of electrons from the n-type conductive substrate to the first nitride semiconductor layer is suppressed.

  When a p-type conductive substrate is used as the conductive substrate, a fourth nitride semiconductor that forms an energy barrier against holes between the buffer layer and the first nitride semiconductor layer in which carriers travel. A layer is provided.

  For example, the fourth nitride semiconductor layer that forms an energy barrier against holes is insulative and has a difference in valence band edge energy Ev with respect to the first nitride semiconductor, that is, a band discontinuity {Ev (S1) -Ev (S3)} = It is preferable to select one having a large ΔEv (S1 / S3). For example, a range of 0.3 eV> ΔEv (S1 / S3)> 3 kT eV can be selected.

  In addition, a back electrode is provided on the back surface of the p-type conductive substrate, and the back electrode is kept at the same potential as the source electrode. At that time, the first nitride semiconductor layer / fourth nitride semiconductor layer / buffer layer / p-type conductive substrate is biased in the reverse direction, and the fourth nitride semiconductor layer The flow of holes from the pn-type conductive substrate to the first nitride semiconductor layer is suppressed.

  The operating characteristics of the “ON state” of the nitride semiconductor transistor according to the present invention will be described below.

In the structure shown in FIG. 1, for example, in an AlGaN / GaN heterojunction transistor having a MIS structure in which an insulating film is inserted between the gate electrode and the nitride semiconductor interface, a p ⁺ AlGaN layer is formed immediately below the drain electrode, and the drain electrode is p ⁺ Has ohmic contact with the AlGaN layer.

The second nitride semiconductor layer / first nitride semiconductor layer forms, for example, an AlGaN / GaN heterojunction. In the “ON state”, a current of a two-dimensional electron gas generated at this interface in the channel region. The transistor operates by transport. A gate electrode is formed immediately below the gate electrode on an electron supply layer made of AlGaN with an insulating film interposed therebetween. At that time, when the gate voltage V _gs = 0 V applied to the gate electrode, the second nitride semiconductor layer / first nitride semiconductor layer is depleted in the channel region so that the second nitride semiconductor layer / first nitride semiconductor layer is depleted. The nitride semiconductor layer / first nitride semiconductor layer thickness, residual donor concentration, and barrier height at the gate electrode are selected. On the other hand, when the gate voltage V _gs is positive, the two-dimensional electron gas accumulates at the interface between the second nitride semiconductor layer / first nitride semiconductor layer and becomes “ON state”. That is, it is a “normally OFF” type nitride semiconductor transistor in which the threshold voltage V _T is a positive value.

When a positive voltage is applied to the drain electrode and a gate voltage V _gs higher than the threshold voltage V _T is applied to the gate electrode to make the “ON state”, a forward bias is applied to the gate, but the MIS structure is Since it is selected, the gate leakage current is suppressed. Specifically, even when the gate voltage V _gs is applied and V _gs = 10 V is applied, the forward leakage current is kept at a low level.

Immediately below the drain electrode, a stacked structure of a P-type third nitride semiconductor layer / second nitride semiconductor layer / first nitride semiconductor layer, for example, an electron supply layer made of p ⁺ AlGaN layer / AlGaN / A P ⁺ In ⁻ junction or a P ⁺ n ⁻ junction is formed by a laminated structure of channel layers made of GaN. At that time, the drain electrode forms an ohmic junction with a P-type third nitride semiconductor layer, for example, a p ⁺ AlGaN layer.

When the gate voltage V _gs applied to the gate electrode is lower than the threshold voltage V _T (V _gs <V _T ), the drain current does not flow even when a positive voltage is applied to the drain electrode. " At this time, for example, the P ⁺ In ⁻ junction or the P ⁺ n ⁻ junction of the p ⁺ AlGaN layer / the electron supply layer made of AlGaN / the channel layer made of GaN is in a forward biased state. Holes are injected from the drain electrode. When holes are injected into the channel layer made of GaN, electrons corresponding to the injected holes are induced in the channel layer between the gate and the drain.

  In a power control device, a large gate-drain distance is taken in order to achieve a high breakdown voltage. In the “ON state”, holes are injected into the channel layer between the gate and the drain. An amount of electrons corresponding to the amount of holes injected into the channel layer is supplied from the source electrode side, and electrons are induced in the injection region. At this time, in the region between the drain electrode-gate-source, electrons in the channel layer are accumulated at the heterojunction interface of the second nitride semiconductor layer / first nitride semiconductor layer. When the amount of injected holes is increased, an amount of electrons equivalent to the amount of injected holes can be induced up to the maximum electron concentration that can be accumulated at the interface. In that situation, a drain current density equal to or higher than that of the high frequency device can be obtained. Therefore, in order to obtain a gate breakdown voltage, the on-resistance can be reduced even when the gate-drain distance is longer than that of the high-frequency device.

If the gate voltage V _gs applied to the gate electrode is lower than the threshold voltage V _T (V _gs <V _T ), even if a positive voltage is applied to the drain electrode, the electrons will flow through the channel region immediately below the gate electrode. Not flowing. At that time, holes injected from the drain electrode travel to the drain side end of the gate electrode by an electric field between the gate and the drain. As described in Applied Physics Letter Vol. 86 No. 05 2105 (2005) (Appl. Phys. Lett. Vol. 86, 05 2105 (2005)), the hole diffusion length is 10 ⁶ cm ^−2. Even if it is reduced to 0.2, it is as small as 0.2 μm. Therefore, in the range where the gate voltage V _gs is lower than the threshold voltage V _T (V _gs <V _T ), holes do not diffuse between the gate electrode and the source electrode beyond the channel region immediately below the drain electrode. . Therefore, drain current does not flow due to induction of electrons corresponding to the amount of holes injected into the channel layer.

  That is, in the nitride semiconductor transistor according to the present invention, the drain current density equal to or higher than that of the high frequency transistor is obtained, the on-resistance is low, and the gate voltage can be increased even when the positive voltage 10V used in the power control transistor is applied to the gate electrode. The gate leakage current in the forward direction flowing through the electrode is at a low level, and a normally-off type transistor for power control having a high breakdown voltage can be obtained.

  Hereinafter, the semiconductor device of the present invention will be described in more detail with reference to specific examples. The specific examples shown here are examples of the best mode of the present invention, but the present invention is not limited to the forms exemplified in these specific examples.

  The specific example illustrated below is an example in which the semiconductor device of the present invention is configured in the form of a field effect transistor.

(First form)
The structure of the field effect transistor according to the first embodiment of the present invention and the operating principle thereof will be described below.

  FIG. 1 is a cross-sectional view schematically showing an example of the structure of the field effect transistor according to the first embodiment of the present invention.

On the substrate 1, buffer layer 2 having a thickness t _2, as the channel layer, the first nitride semiconductor layer 3 having a thickness of t _3, as an electron supply layer, a second nitride film thickness t ₄ the semiconductor layer 4 In addition, the third nitride semiconductor layer 5 having the thickness t ₅ and having P-type conductivity is grown sequentially. Except for the drain region, the third nitride semiconductor layer 5 is removed by etching, and the surface of the second nitride semiconductor layer 4 is exposed.

  A source electrode 6 is formed on the surface of the second nitride semiconductor layer 4 of the electron supply layer, and a drain electrode 7 is formed on the surface of the third nitride semiconductor layer 5 having P-type conductivity. . The source electrode 6 forms an ohmic junction with the second nitride semiconductor layer 4, and the drain electrode 7 forms an ohmic junction with the third nitride semiconductor layer 5. A gate electrode 8 is provided in a region sandwiched between the source electrode 6 and the drain electrode 7.

A recess for forming the gate electrode 8 is formed on the surface of the second nitride semiconductor layer 4 of the electron supply layer. The surface of the second nitride semiconductor layer 4 on which the recess is formed is covered with an insulating film 9, and the recess is formed in a shape in which the gate electrode 8 is embedded via the insulating film 9. Yes. The gate electrode 8 has a gate length L _gate-8, and a MIS structure is formed immediately below the gate electrode 8 / insulating film 9 / second nitride semiconductor layer 4. The thickness is the film thickness t ₉ at the surface of the second nitride semiconductor layer 4 and the bottom portion of the recess portion, and the film thickness t _9-well at the portion covering the sidewall of the recess portion.

The depth d _Recess of the recessed portion can be than the thickness t ₉ of the insulating film 9 is selected to be greater. Further, the thickness t ₉ of the insulating film 9 may be chosen thicker than the depth d _Recess of the recessed portion.

The width W _Recess of the recessed portion, and the thickness t _9-well of the insulating film side wall surface of the recessed portion, the gate length L _Gate-8 of the gate electrode _{8, W recess = L gate-} 8 + 2 × It is set so as to satisfy the condition of _t9-well .

In the channel region immediately below the recess portion, the thickness of the second nitride semiconductor layer 4 is etched and thinned along with the formation of the recess portion. Thickness t _4-Recess of the second nitride semiconductor layer 4 immediately below the recess portion in accordance with the depth d _Recess of the recessed portion, and it is _{t 4-recess = t 4 -d} recess.

The channel region immediately below the gate electrode 8 has a stacked structure of the gate electrode 8 / insulating film 9 / second nitride semiconductor layer 4 / first nitride semiconductor layer 3 having a film thickness t _{4 -recess} . When the gate voltage V _gs applied to the gate electrode 8 is set to V _gs = 0V, no carriers (electrons) exist in this channel region. That is, the threshold voltage V _T is V _T > 0V.

At the interface between the gate electrode 8 and the insulating film 9, the work function eψ (M _gate ) eV of the metal material M _gate in contact with the surface of the insulating film 9 in the gate electrode 8 and the insulating material I _{front on} the surface of the insulating film 9. A barrier Φ _{M / I} corresponding to the difference from the electron affinity eχ (I _front ) eV, (eψ (M _gate ) −eχ (I _front )) eV, is generated. At the interface between the insulating film 9 and the second nitride semiconductor layer 4, the electron affinity eχ (I _rear ) eV of the insulating material I _rear on the back surface of the insulating film 9 and the electron affinity eχ ( S2) A barrier Φ _{I / S} corresponding to the difference from eV, (eχ (S2) −eχ (I _rear )) eV is generated.

  Further, at the interface between the second nitride semiconductor layer 4 and the first nitride semiconductor layer 3, the band discontinuity ΔEc (S2 / S2) due to the conduction band energy difference between the second nitride semiconductor and the first nitride semiconductor. S1) exists. There is also a band discontinuity ΔEv (S2 / S1) due to the valence band energy difference.

  In the “ON state”, an energy barrier corresponding to the band discontinuity ΔEc (S2 / S1) is used at the interface between the second nitride semiconductor layer 4 and the first nitride semiconductor layer 3. , Carriers (electrons) are accumulated. At that time, the material of the second nitride semiconductor layer 4 / the first nitride semiconductor layer is preferably selected so that the band discontinuity ΔEc (S2 / S1)> 2 kT.

When V _gs = 0V, there is no carrier (electron) in this channel region, so the second nitride semiconductor layer 4 having a film thickness t _4-recess immediately below the gate electrode 8 and the first The surface side of one nitride semiconductor layer 3 is depleted. Further, carriers (electrons) are not accumulated at the heterojunction interface between the second nitride semiconductor layer 4 and the first nitride semiconductor layer 3. In that case, the film thickness t _3g-sc of the depleted region on the surface side of the first nitride semiconductor layer 3 is t ₃ ≧ t _3g-sc .

The second nitride semiconductor layer 4 is undoped or doped with an n-type impurity (donor), and is depleted when the concentration of the included n-type impurity (donor) is N _D (S2) cm ⁻³ . At this time, the surface density of the space charge due to the ionized n-type impurity (donor) is N _D (S2) · t _4−recess cm ⁻² . The first nitride semiconductor layer 3 is undoped, and when the residual n-type impurity (donor) concentration contained is N _D (S1) cm ⁻³ , ionization occurs when the film thickness t _3g-sc is depleted. The surface density of the space charge resulting from the n-type impurity (donor) is N _D (S1) · t _3g-sc cm ⁻² .

When V _gs = 0V, depleted portions in the second nitride semiconductor layer 4 and the first nitride semiconductor layer 3 exhibit band bends (bends) due to space charge. As a result, in the second nitride semiconductor layer 4 having the film thickness t _4-recess , the energy level difference at the conduction band edge, ΔEc (S2: N _D (S2) · t _4-recess ), and the second There is an energy level difference ΔEcp (S1: Polarization) derived from the polarization electric field generated between the nitride semiconductor layer 4 and the first nitride semiconductor layer 3. In the depletion region of the film thickness t _3g-sc of the first nitride semiconductor layer 3, an energy level difference ΔEc (S1: N _D (S1) · t _3g-sc ) is generated. .

Considering the band diagram in the channel region immediately below the gate electrode 8 when V _gs = 0 V, Φ _{M / I} ≧ Φ _{I / S} + ΔEc (S2: N _D (S2) · t _4-recess ) + ΔEcp ( It is necessary to satisfy the relationship of (S1: Polarization) + ΔEc (S2 / S1) + ΔEc (S1: N _D (S1) · t _3g-sc ) when configuring a normally-off transistor. For example, a combination of nitride semiconductor materials of the second nitride semiconductor layer 4 and the first nitride semiconductor layer 3 so as to achieve the above condition, a combination of (N _D (S2), t _4-recess ), A combination of (N _D (S1), t _3g-sc ) is appropriately selected.

In order to enter the “ON state”, it is necessary to apply to the gate electrode 8 a positive gate voltage V _gs that can eliminate the depletion region present in the first nitride semiconductor layer 3. Therefore, the threshold voltage V _T to be shifted from the “OFF state” to the “ON state” is at least V _T > ΔEc (S1: N _D (S1) · t _3g-sc ) / q> 0 V (where q Represents the charge amount (unit charge) of electrons.

  Immediately below the drain electrode 7, a stacked structure of the drain electrode 7 / the third nitride semiconductor layer 5 / the second nitride semiconductor layer 4 / the first nitride semiconductor layer 3 having P-type conductivity is formed. ing.

The third nitride semiconductor layer 5 having P-type conductivity is doped with a p-type impurity (acceptor) at a high concentration and functions as a p ⁺ layer. Ohmic contact is achieved between the drain electrode 7 / P-type third nitride semiconductor layer 5 having conductivity. At this interface, of the drain electrode 7, the work function eψ (M _ohmic ) eV of the metal material M _ohmic that is in contact with the third nitride semiconductor layer 5 and the electron affinity eχ (S 3) of the third nitride semiconductor layer 5. A barrier Φ _{M / S3} corresponding to the difference from eV, (eψ (M _ohmic ) −eχ (S3)) eV, is generated. Due to this barrier Φ _{M / S3} , the thickness of the depletion region formed at the interface of the p ⁺ layer is extremely thin. Therefore, the depletion region is tunneled, and electrons are quickly emitted from the p ⁺ layer to the drain electrode 7, and apparently the third nitride semiconductor layer 5 having P-type conductivity from the drain electrode 7. Holes are injected into.

On the other hand, the portion of the third nitride semiconductor layer 5 / second nitride semiconductor layer 4 / first nitride semiconductor layer 3 having P-type conductivity is a P ⁺ In ⁻ junction or a P ⁺ n ⁻ junction. Configure. At that time, in the P ⁺ In ⁻ junction or the P ⁺ n ⁻ junction, the difference between the conduction band edge energy Ec (P ⁺ ) and the Fermi level energy L _{f in} the P ⁺ layer (Ec (P ⁺ ) −E _f ). And the difference between the conduction band edge energy Ec (n ⁻ ) and the Fermi level energy L _{f in} the n ⁻ layer (Ec (n ⁻ ) −E _f ). Accordingly, P ⁺ an In ^- the bonding, ^- bonding or ^{P + n {(Ec (P} +) -E f) - (Ec (n -) -E f)} corresponds to the built-in potential eV _{Built- in} is generated. Therefore, the n-type impurity (donor) contained in the second nitride semiconductor layer 4 is ionized. That is, the second nitride semiconductor layer 4 is depleted. In addition, since the band discontinuity ΔEc (S2 / S1) exists at the interface between the second nitride semiconductor layer 4 and the first nitride semiconductor layer 3, when carriers (electrons) are generated. Accumulated at this interface.

When the drain voltage V _ds applied to the drain electrode 7 is a positive voltage, the energy band immediately below the drain electrode 7 is shown in FIG. At that time, the P ⁺ In ⁻ junction (P ⁺ n ⁻ junction) is forward-biased, and hole diffusion and electron diffusion occur in the second nitride semiconductor layer 4. That is, from the third nitride semiconductor layer 5 having P-type conductivity, which is a P ⁺ layer, toward the second nitride semiconductor layer 4 / first nitride semiconductor layer 3 which is an In ⁻ region. , Holes diffuse. At the same time, the band discontinuity ΔEc (S2 / S1) at the interface of the second nitride semiconductor layer 4 / first nitride semiconductor layer 3 is further generated from the first nitride semiconductor layer 3 to the interface of the second nitride semiconductor layer 4 / first nitride semiconductor layer 3. Beyond that, electrons diffuse into the second nitride semiconductor layer 4.

  As the diffusion current, holes injected from the third nitride semiconductor layer 5 over the second nitride semiconductor layer 4 to the first nitride semiconductor layer 3 are transferred to the first nitride semiconductor. It is distributed according to the band bend (bending) of the valence band in the layer 3.

When V _gs = 0 V, the state is “OFF state”, and even if the drain voltage V _ds is a positive voltage, no drain current flows. Therefore, the hole concentration distribution and the electron concentration distribution formed in the first nitride semiconductor layer 3 are in an equilibrium state. FIG. 3 shows the first nitride semiconductor layer of the field effect transistor of the first embodiment of the present invention illustrated in FIG. 1 when the drain voltage V _ds is a positive voltage and is in the “OFF state”. The hole density | concentration currently formed in 3 is shown typically.

In the portion from the channel region immediately below the gate electrode 8 to the source electrode 6, the hole concentration is “0”. Holes are distributed from the end of the channel region immediately below the gate electrode 8 on the drain electrode 7 side to the drain electrode 7. At that time, the hole concentration is high in the region immediately below the drain electrode 7, and the hole concentration decreases toward the drain electrode 7 side end of the channel region directly below the gate electrode 8. In the “OFF state”, in the channel region immediately below the gate electrode 8, the first nitride semiconductor layer 3 is depleted, but the holes present on the drain electrode 7 side are slightly diffused. The region where the holes are slightly diffused corresponds to the _hole diffusion length L _hole in the first nitride semiconductor layer 3. In addition, when a positive drain voltage V _ds is applied to the drain electrode 7, there is a potential difference due to the concentration of holes formed in the first nitride semiconductor layer 3. That is, the potential is high in the region immediately below the drain electrode 7, and the potential is low in the portion from the channel region immediately below the gate electrode 8 to the source electrode 6. In the meantime, a potential gradient is formed in the portion from the drain electrode 7 side end of the channel region immediately below the gate electrode 8 to the drain electrode 7.

Note that the hole diffusion length L _hole in the first nitride semiconductor layer 3 depends on the composition of the first nitride semiconductor and the dislocation density. For example, in the case of GaN, even if the dislocation density is reduced to 10 ⁶ cm ⁻² , the hole diffusion length L _hole is 0.2 μm. Applied Physics Letter Vol. 86 No. 05 2105 (2005 ) (Appl. Phys. Lett. Vol. 86, 05 2105 (2005)).

When V _gs = 0V, the positive drain voltage V _ds applied to the drain electrode 7 increases, and the channel region immediately below the gate electrode 8 exists in the portion from the end on the drain electrode 7 side to the drain electrode 7. The hole concentration also increases. Also in this case, the region where the holes are slightly diffused on the drain electrode 7 side of the channel region directly under the gate electrode 8 is the hole diffusion length L _hole ≈0.2 μm. Therefore, if the gate length L _gate-8 is made significantly longer than the _hole diffusion length L _hole (L _gate-8 >> L _hole ), the gate electrode 8 and the source beyond the channel region immediately below the gate electrode 8 are obtained. Holes do not reach the region between the electrodes 6 by diffusion. That is, the occurrence of a recombination current due to recombination of holes and electrons that diffuse beyond the channel region immediately below the gate electrode 8 is avoided. Therefore, a high off breakdown voltage can be obtained.

On the other hand, when V _gs > V _T > 0 V and the “ON state” is established, carriers (electrons) are also present at the interface between the second nitride semiconductor layer 4 and the first nitride semiconductor layer 3 even in the channel region immediately below the gate electrode 8. ) Is accumulated. Therefore, the electrons flowing from the source electrode 6 side and the holes injected from the drain electrode 7 are the interface between the second nitride semiconductor layer 4 / first nitride semiconductor layer 3 in the channel region immediately below the gate electrode 8. When recombining in the vicinity, a recombination current is generated.

  This situation, which is achieved when entering the “ON state”, is similar to the “ON state” situation in the p + gate, normally-off, field effect transistor illustrated in FIG. Give density. Therefore, compared with the MIS structure, normally-off, and field effect transistor illustrated in FIG. 7, the field effect transistor according to the first embodiment of the present invention illustrated in FIG. 1 achieves a significantly higher drain current density. Is done.

  Next, the structure of the field effect transistor according to the first embodiment of the present invention will be described using a specific example.

(First embodiment)
FIG. 4 is a cross-sectional view schematically showing the device structure of the field effect transistor of the first embodiment. The field effect transistor according to the first embodiment has a structure described below.

  As the substrate 1, a high resistance Si substrate is used. For example, the buffer layer 2, the first nitride semiconductor layer 3, the second nitride semiconductor layer 4, and the third nitride semiconductor layer 5, which are grown on the (111) plane Si substrate, are grown in order. It is formed by epitaxial growth.

On the (111) plane Si substrate, for example, an AlN buffer layer having a film thickness of 4 nm is formed as a nucleation layer, and then an AlGaN / GaN periodic layer is formed to 1000 nm. The AlN buffer layer and the AlGaN / GaN periodic layer are formed as a buffer layer. Use as 2. On the AlGaN / GaN periodic layer, a film made of Al _0.20 Ga _0.80 N (Al composition 0.20) as the first nitride semiconductor layer 3 as a GaN layer with a thickness of 1000 nm and as the second nitride semiconductor layer 4 An AlGaN layer having a thickness of 30 nm is formed. Further, as the third nitride semiconductor layer 5, a p ⁺ -AlGaN layer having a thickness of 30 nm made of Zn-doped Al _0.20 Ga _0.80 N (Al composition 0.20) is formed. The Zn concentration added to this p ⁺ -AlGaN layer is selected to be 10 ¹⁹ cm ⁻³ .

The drain electrode region is covered with a resist, and the third nitride semiconductor layer 5 in other regions is removed by etching. For the selective etching of the p ⁺ -AlGaN layer, ICP plasma mainly composed of boron trichloride (BCl ₃ ) gas is used.

As the source electrode 6 formed on the surface of the exposed AlGaN layer, Ti and Al metal are formed by vapor deposition and a lift-off process. As the drain electrode 7 formed on the surface of the p ⁺ -AlGaN layer, Ni and Au metals are formed by vapor deposition and a lift-off process. An ohmic contact is formed by heat treatment at 650 ° C. in a nitrogen atmosphere.

Element isolation is performed by nitrogen ion implantation. As the nitrogen ion implantation conditions, acceleration voltage: 100 kV and implantation density: 2 × 10 ¹⁴ cm ⁻² are selected using a resist film having a thickness of 1 μm as a mask. After element isolation, a 200 nm SiN film is formed by plasma CVD. An opening for forming a recess is formed in the SiN film. The SiN film in the recess portion is removed using ICP plasma whose opening width is 2.0 μm and whose main component is sulfur hexafluoride (SF ₆ ) gas. The AlGaN layer exposed in the opening of the SiN film is etched away by 20 nm using ICP plasma mainly composed of boron trichloride (BCl ₃ ) gas to form a recess. Therefore, immediately below the recess portion, the thickness of the AlGaN layer is 10 nm.

  Thereafter, as the gate insulating film, a SiN film is formed to a thickness of 20 nm, for example, by plasma CVD. The thickness of the SiN film covering the side wall of the recess is 20 nm. Since the depth of the recess portion is 20 nm and the thickness of the SiN film is 20 nm, the surface of the SiN film covering the bottom surface of the recess portion and the surface of the AlGaN layer other than the recess portion are located at the same level. .

  The gate electrode 8 is formed by evaporating and lifting off, for example, Ni 20 nm and Au 200 nm. At that time, the gate electrode 8 formed so as to be embedded in the recess portion through the gate insulating film has a gate length corresponding to (2.0 μm−2 × 20 nm).

  The width of the electrode formed by lift-off is wider than the width of the recess portion, and on the drain electrode 7 side, the surface of the AlGaN layer other than the recess portion, which is covered with the SiN film having the total thickness (200 nm + 20 nm), is integrated. The part is covered. A portion covering the surface of the AlGaN layer other than the recess portion via the SiN film functions as a field plate electrode. The field plate electrode portion extends 5 μm from the recess portion to the drain electrode 7 side.

  The width from the end of the recess portion on the drain electrode 7 side to the end of the third nitride semiconductor layer 5 on the gate electrode side is selected to be 12 μm. The width of the third nitride semiconductor layer 5 itself is selected to be 100 μm.

  On the bottom surface of the recess portion, the ratio of the thickness of the AlGaN layer immediately below the gate electrode 8 to the gate length is (2.0 μm−2 × 20 nm) / 10 nm.

For comparison, a conventional structure MIS type normally-off transistor illustrated in FIG. 5 and a conventional structure P ⁺ gate normally-off transistor illustrated in FIG. 6 are manufactured by the following procedure.

  The MIS type normally-off transistor having a conventional structure illustrated in FIG. 5 has a structure in which the following points are changed with respect to the field effect transistor of the first embodiment. The drain electrode portion is used as the drain electrode 7 by forming an ohmic electrode having the same configuration as the source electrode 6 on the surface of the AlGaN layer of the second nitride semiconductor layer 4.

Specifically, the step of forming a 30 nm thick p ⁺ -AlGaN layer made of Zn-doped Al _0.20 Ga _0.80 N (Al composition 0.20) is omitted. Further, in the step of forming the source electrode 6, the drain electrode 7 is also formed. At this time, the width from the end of the recess portion on the drain electrode 7 side to the end of the drain electrode 7 on the gate electrode 8 side is selected to be 12 μm.

The conventional P ⁺ gate normally-off transistor illustrated in FIG. 6 has a structure in which the following points are changed with respect to the field-effect transistor of the first embodiment. The drain electrode portion is used as the drain electrode 7 by forming an ohmic electrode having the same configuration as the source electrode 6 on the surface of the AlGaN layer of the second nitride semiconductor layer 4. On the other hand, the structure of the gate portion uses a 30 nm thick AlGaN layer made of Al _0.20 Ga _0.80 N (Al composition 0.20) as the second nitride semiconductor layer 4, and has a P ⁺ gate structure on the surface thereof. I am making it.

Specifically, a p ⁺ -AlGaN layer having a thickness of 30 nm made of Zn-doped Al _0.20 Ga _0.80 N (Al composition 0.20) is formed on the second nitride semiconductor layer 4. This p ⁺ -AlGaN layer is etched to form a P ⁺ gate portion having a width of 2.0 μm at a position corresponding to the recess portion. That is, using a resist mask having a width of 2.0 μm, the p ⁺ -AlGaN layer in other regions is removed by etching. For the selective etching of the p ⁺ -AlGaN layer, ICP plasma mainly composed of boron trichloride (BCl ₃ ) gas is used.

  As the source electrode 6 and the drain electrode 7 formed on the surface of the exposed AlGaN layer, Ti and Al metal are formed by vapor deposition and lift-off process. An ohmic contact is formed by heat treatment at 650 ° C. in a nitrogen atmosphere.

As the gate electrode 8 to be formed on the surface of the P ⁺ gate portion (p ⁺ -AlGaN layer) having a width of 2.0 μm, Ni and Au metals are formed by vapor deposition and a lift-off process. The gate electrode 8 is also heat-treated at 650 ° C. in a nitrogen atmosphere to form an ohmic contact.

  Thereafter, a 200 nm SiN film is formed by plasma CVD in a region sandwiched between the source electrode 6 and the drain electrode 7. This 200 nm thick SiN film functions as a protective insulating film that covers the exposed surface of the AlGaN layer.

At this time, the width from the end of the P ⁺ gate portion on the drain electrode 7 side to the end of the drain electrode 7 on the gate electrode 8 side is selected to be 12 μm.

The ratio of the thickness of the AlGaN layer immediately below the gate electrode 8 to the gate length of the P ⁺ gate portion is (2.0 μm) / 30 nm.

A positive drain voltage V _ds = 20 V is applied to the drain electrode 7, and a positive gate voltage V _gs = V _T +5 V is applied to the gate electrode 8. Distributions of electrons and holes existing in the second nitride semiconductor layer 4 and the first nitride semiconductor layer 3 are schematically shown in FIGS. 4, 5, and 6.

  In the case of the MIS normally-off transistor having the conventional structure shown in FIG. 5, electrons are accumulated at the interface between the second nitride semiconductor layer 4 and the first nitride semiconductor layer 3 in the “ON state”. .

In the field effect transistor of the first embodiment shown in FIG. 4, electrons are accumulated at the interface between the second nitride semiconductor layer 4 and the first nitride semiconductor layer 3 in the “ON state”. In addition, holes are injected by diffusion from the third nitride semiconductor layer 5 (p ⁺ AlGaN layer) on the drain electrode 7 side to the second nitride semiconductor layer 4. Further, the holes diffused into the first nitride semiconductor layer 3 beyond the second nitride semiconductor layer 4 are caused by the interface between the second nitride semiconductor layer 4 and the first nitride semiconductor layer 3. Distributed in a region in the first nitride semiconductor layer 3 adjacent to the first nitride semiconductor layer 3. In the distribution of the hole concentration in the first nitride semiconductor layer 3, the hole concentration is 0 in the channel region immediately below the gate electrode 8 and the source electrode 6 side. Holes are distributed in the region from the end of the gate electrode 8 on the drain electrode 7 side to the region immediately below the third nitride semiconductor layer 5 (p ⁺ AlGaN layer) on the drain electrode 7 side.

  Compared to the MIS type normally-off transistor having the conventional structure shown in FIG. 5, in the field effect transistor of the first embodiment, electrons are injected by diffusion so as to correspond to the injected holes. As a result, the amount of electrons accumulated at the interface between the second nitride semiconductor layer 4 and the first nitride semiconductor layer 3 is increased.

In the case of the P ⁺ gate normally-off transistor having the conventional structure shown in FIG. 6, in the “ON state”, P ⁺ In ⁻ made of p ⁺ AlGaN layer / AlGaN layer / GaN layer is directly under the P ⁺ gate portion. The junction or P ⁺ n ⁻ junction is forward biased. As a result, holes diffused from the p ⁺ AlGaN layer (P ⁺ gate portion) to the GaN layer (first nitride semiconductor layer 3) beyond the AlGaN layer (second nitride semiconductor layer 4). Are distributed in a region in the first nitride semiconductor layer 3 close to the interface between the second nitride semiconductor layer 4 and the first nitride semiconductor layer 3. The distribution of the hole concentration in the first nitride semiconductor layer 3 is concentrated on the channel region immediately below the gate electrode 8 and on the source electrode 6 side. On the other hand, in the region from the end of the gate electrode 8 on the drain electrode 7 side to immediately below the drain electrode 7, the hole concentration is 0.

Compared with the MIS type normally-off transistor having the conventional structure shown in FIG. 5, the P ⁺ gate normally-off transistor having the conventional structure shown in FIG. 6 corresponds to the injected holes by diffusion. In addition, as a result of the electron injection by diffusion, the amount of electrons accumulated at the interface between the second nitride semiconductor layer 4 and the first nitride semiconductor layer 3 is increased.

FIG. 7 shows drain current-gate voltage measured under the condition that a positive drain voltage V _ds = 20 V is applied to the drain electrode 7 for the three types of normally-off transistors shown in FIGS. The (I _d −V _gs ) characteristics are shown in comparison.

The field effect transistor of the first embodiment shown in FIG. 4 and the conventional MIS type normally-off transistor shown in FIG. 5 both employ a MIS structure gate electrode, and the threshold voltage V _T is In both cases, V _T ≈3V. On the other hand, since the P ⁺ gate normally-off transistor having the conventional structure shown in FIG. 6 employs a P ⁺ gate, the threshold voltage V _T is V _T ≈1.8V.

Both the field effect transistor of the first embodiment shown in FIG. 4 and the MIS type normally-off transistor of the conventional structure shown in FIG. 5 can operate under the condition of the gate voltage V _gs = 10V. The densities I _d / W _gate are I _d / W _gate ≈0.40 A / mm and I _d / W _gate ≈0.20 A / mm, respectively. On the other hand, the P ⁺ gate normally-off transistor of the conventional structure shown in FIG. 6, for the increase of the gate leakage current, only in the range of the gate voltage V _gs = 7V, no good operation. At that time, the drain current density I _d / W _{gate at} the gate voltage V _gs = 7 V is I _d / W _gate ≈0.29 A / mm.

In the field effect transistor of the first embodiment shown in FIG. 4 and the P ⁺ gate normally-off transistor of the conventional structure shown in FIG. 6, in the “ON state”, from the p ⁺ AlGaN layer / AlGaN layer / GaN layer. By adopting a structure in which a forward bias is applied to the P ⁺ In ⁻ junction or P ⁺ n ⁻ junction, holes are injected into the GaN layer of the channel layer, and a drain current is generated by the injected holes. Contributing electrons are induced, and the drain current density is increased. The drain current density is comparable to the drain current density of normally-on conventional high-frequency devices.

  On the other hand, in the MIS type normally-off transistor having the conventional structure shown in FIG. 5, the hole current is not injected into the GaN layer of the channel layer, so that the drain current density is relatively low. Its drain current density is low compared to the drain current density of normally-on conventional high frequency devices.

FIG. 8 shows the gate current-gate voltage measured under the condition that a positive drain voltage V _ds = 20 V is applied to the drain electrode 7 for the three types of normally-off transistors shown in FIGS. The (I _g -V _gs ) characteristics are shown in comparison.

The field effect transistor of the first embodiment shown in FIG. 4 and the conventional MIS type normally-off transistor shown in FIG. 5 both employ a MIS structure gate electrode, and have a gate voltage V _gs = 10V. In the following range, the gate current density I ₈ / W _gate is in the range of I ₈ / W _gate <10 ⁻⁹ A / mm. On the other hand, since the P ⁺ gate normally-off transistor having the conventional structure shown in FIG. 6 employs a P ⁺ gate, a P ⁺ In ⁻ junction composed of p ⁺ AlGaN layer / AlGaN layer / GaN layer or P ⁺ When a forward bias is applied to the n ⁻ junction and the gate voltage V _gs exceeds its threshold voltage V _T , the gate current density I ₈ / W _gate increases. When the gate voltage V _gs is around 8 V, the gate current density I ₈ / W _gate level of 10 ⁻³ A / mm, which is a standard for device stable operation, is reached.

The structure of the field effect transistor of the first embodiment shown in FIG. 4 has two requirements for a power control device: a high drain current density and a low gate current density when a positive gate voltage V _gs = 10 V is applied. It is judged that both are satisfied.

  In the field effect transistor according to the first embodiment, a high-resistance (111) Si substrate is used as a substrate, and a (0001) -plane grown III-nitride epitaxial film is used on the device. Is making. If a (0001) -plane-grown III-nitride epitaxial film can be formed on the surface and the substrate is a high-resistance substrate, a sapphire substrate, SiC substrate, ZnO substrate can be used instead of the high-resistance (111) -plane Si substrate. Etc. can be used.

  Further, as a nucleation layer grown on the substrate, an AlN buffer layer having a thickness of 4 nm and subsequently an AlGaN / GaN periodic layer of 1000 nm are formed, and this AlN buffer layer and the AlGaN / GaN periodic layer are used as the buffer layer 2. ing. Instead, an AlN buffer layer having a thickness of 4 nm is formed as a nucleation layer, and then an AlGaN single layer having an Al composition equal to the average Al composition of the AlGaN / GaN periodic layer is formed to 1000 nm, and the AlN buffer layer and the AlGaN single layer are formed. The buffer layer 2 can also be used.

(Second Embodiment)
FIG. 9 is a cross-sectional view schematically showing the device structure of the field effect transistor of the second embodiment. The field effect transistor of the second embodiment has a structure described below.

  As the substrate 1, a high resistance Si substrate is used. For example, the buffer layer 2, the first nitride semiconductor layer 3, the second nitride semiconductor layer 4, and the third nitride semiconductor layer 5, which are grown on the (111) plane Si substrate, are grown in order. It is formed by epitaxial growth.

On the (111) plane Si substrate, for example, an AlN buffer layer having a film thickness of 4 nm is formed as a nucleation layer, and then an AlGaN / GaN periodic layer is formed to 1000 nm. The AlN buffer layer and the AlGaN / GaN periodic layer are formed as a buffer layer. Use as 2. On the AlGaN / GaN periodic layer, a film made of Al _0.20 Ga _0.80 N (Al composition 0.20) as the first nitride semiconductor layer 3 as a GaN layer with a thickness of 1000 nm and as the second nitride semiconductor layer 4 An AlGaN layer having a thickness of 30 nm is formed. Further, as the third nitride semiconductor layer 5, a p ⁺ -AlGaN layer having a thickness of 30 nm made of Zn-doped Al _0.20 Ga _0.80 N (Al composition 0.20) is formed. The Zn concentration added to this p ⁺ -AlGaN layer is selected to be 10 ¹⁹ cm ⁻³ .

The drain electrode region is covered with a resist, and the third nitride semiconductor layer 5 in other regions is removed by etching. For the selective etching of the p ⁺ -AlGaN layer, ICP plasma mainly composed of boron trichloride (BCl ₃ ) gas is used.

As the source electrode 6 formed on the surface of the exposed AlGaN layer, Ti and Al metal are formed by vapor deposition and a lift-off process. As the drain electrode 7 formed on the surface of the p ⁺ -AlGaN layer, Ni and Au metals are formed by vapor deposition and a lift-off process. An ohmic contact is formed by heat treatment at 650 ° C. in a nitrogen atmosphere.

Element isolation is performed by nitrogen ion implantation. As the nitrogen ion implantation conditions, acceleration voltage: 100 kV and implantation density: 2 × 10 ¹⁴ cm ⁻² are selected using a resist film having a thickness of 1 μm as a mask. After element isolation, a 200 nm SiN film is formed by plasma CVD. Openings are formed in this SiN film. The SiN film is removed using ICP plasma whose opening width is 2.0 μm and whose main component is sulfur hexafluoride (SF ₆ ) gas. In the second embodiment, fluorine (F) is diffused from the surface of the AlGaN layer exposed in the opening of the SiN film to form a fluorine diffusion region.

For example, carbon tetrafluoride (CF ₄ ) The AlGaN layer exposed in the opening is exposed to plasma using gas for 2 minutes and 30 seconds. By this treatment, diffusion of fluorine atoms proceeds from the surface of the AlGaN layer exposed in the opening to a range of a diffusion depth of 60 nm. The concentration of fluorine atoms introduced from the surface corresponds to a surface concentration of 5 × 10 ¹⁹ cm ^−3, and the surface density of fluorine atoms introduced into the entire region is selected to be 1 × 10 ¹⁵ cm ^−2. ing. Therefore, in the fluorine diffusion region, the positive polarization charge generated at the interface between the first nitride semiconductor layer and the second nitride semiconductor layer is canceled by the introduced fluorine atoms.

  Thereafter, as the gate insulating film, a SiN film is formed to a thickness of 20 nm, for example, by plasma CVD. The thickness of the SiN film covering the surface of the AlGaN layer exposed to the opening and the opening side wall of the SiN film is 20 nm.

  The gate electrode 8 is formed by evaporating and lifting off, for example, Ni 20 nm and Au 200 nm. At that time, the gate electrode 8 formed so as to be embedded in the opening via a gate insulating film has a gate length corresponding to (2.0 μm−2 × 20 nm).

  Note that the width of the electrode formed by lift-off is wider than the width of the opening, and on the drain electrode 7 side, the surface of the AlGaN layer other than the opening, which is covered with the SiN film having the total thickness (200 nm + 20 nm), is integrated. The part is covered. A portion covering the surface of the AlGaN layer other than the opening via the SiN film functions as a field plate electrode. The field plate electrode portion extends 5 μm from the opening to the drain electrode 7 side.

  The width from the end of the opening on the drain electrode 7 side to the end of the third nitride semiconductor layer 5 on the gate electrode side is selected to be 12 μm. The width of the third nitride semiconductor layer 5 itself is selected to be 100 μm.

  On the bottom surface of the recess portion, the ratio of the thickness of the AlGaN layer immediately below the gate electrode 8 to the gate length is (2.0 μm−2 × 20 nm) / 10 nm.

Immediately below the gate electrode 8, a laminated structure of gate electrode / insulating film / i-type AlGaN region / AlGaN layer / GaN layer is formed. As a result, when the gate voltage V _gs = 0 V is applied to the gate electrode 8, the gate electrode 8 is “OFF state”. The gate portion has a MIS structure.

Also in the field effect transistor according to the second embodiment, the measured gate current-gate voltage (I _g -V _gs ) characteristic is as follows when a positive drain voltage V _ds = 20 V is applied to the drain electrode 7. This is substantially the same as the field effect transistor of the first embodiment. Further, regarding the drain current-gate voltage (I _d -V _gs ) characteristics measured under the condition that a positive drain voltage V _ds = 20 V is applied to the drain electrode 7, the field effect transistor of the second embodiment is also used. The performance is substantially the same as the performance of the field effect transistor of the first embodiment.

Similar to the structure of the field effect transistor of the first embodiment shown in FIG. 4, the structure of the field effect transistor of the second embodiment shown in FIG. 9 also has a high drain current density required for the power control device, It is judged that both of the two requirements of the low gate current density when the positive gate voltage V _gs = 10 V is applied are satisfied.

  In the field effect transistor of the second embodiment, a high-resistance (111) Si substrate is used as a substrate, and a (0001) -plane grown Group III nitride epitaxial film is used on the device. Is making. If a (0001) -plane-grown III-nitride epitaxial film can be formed on the surface and the substrate is a high-resistance substrate, a sapphire substrate, SiC substrate, ZnO substrate can be used instead of the high-resistance (111) -plane Si substrate. Etc. can be used.

(Third embodiment)
FIG. 10 is a cross-sectional view schematically showing the device structure of the field effect transistor of the third embodiment. The field effect transistor of the third embodiment has a structure described below.

  As the substrate 1, a high resistance SiC substrate is used. For example, the buffer layer 2, the first nitride semiconductor layer 3, the second nitride semiconductor layer 4, and the third nitride semiconductor layer 5 that are grown on the (0001) plane on the (0001) plane SiC substrate are sequentially formed. It is formed by epitaxial growth.

On a (001) plane SiC substrate, for example, an AlN buffer layer having a film thickness of 4 nm is formed as a nucleation layer, and then an AlGaN / GaN periodic layer having a thickness of 1000 nm is formed. The AlN buffer layer and the AlGaN / GaN periodic layer are buffered. Used as layer 2. On the AlGaN / GaN periodic layer, a film made of Al _0.20 Ga _0.80 N (Al composition 0.20) as the first nitride semiconductor layer 3 as a GaN layer with a thickness of 1000 nm and as the second nitride semiconductor layer 4 An AlGaN layer having a thickness of 30 nm is formed. Further, as the third nitride semiconductor layer 5, a p ⁺ -AlGaN layer having a thickness of 30 nm made of Zn-doped Al _0.20 Ga _0.80 N (Al composition 0.20) is formed. The Zn concentration added to this p ⁺ -AlGaN layer is selected to be 10 ¹⁹ cm ⁻³ .

The drain electrode region is covered with a resist, and the third nitride semiconductor layer 5 in other regions is removed by etching. For the selective etching of the p ⁺ -AlGaN layer, ICP plasma mainly composed of boron trichloride (BCl ₃ ) gas is used.

Element isolation is performed by nitrogen ion implantation. As the nitrogen ion implantation conditions, acceleration voltage: 100 kV and implantation density: 5 × 10 ¹⁴ cm ⁻² are selected using a resist film having a thickness of 1 μm as a mask. After element isolation, a 200 nm SiN film is formed by plasma CVD. Openings are formed in this SiN film. The SiN film is removed using ICP plasma whose opening width is 2.0 μm and whose main component is sulfur hexafluoride (SF ₆ ) gas.

  In the third embodiment, undoped GaN is grown to 10 nm by selective growth on the surface of the AlGaN layer exposed in the opening of the SiN film. Therefore, a laminated structure of undoped GaN layer / AlGaN layer / GaN layer is formed in this opening.

Further, the SiN film used as the selective growth mask is removed by BHF treatment. As the source electrode 6 formed on the surface of the exposed AlGaN layer, Ti and Al metal are formed by vapor deposition and a lift-off process. As the drain electrode 7 formed on the surface of the p ⁺ -AlGaN layer, Ni and Au metals are formed by vapor deposition and a lift-off process. An ohmic contact is formed by heat treatment at 650 ° C. in a nitrogen atmosphere.

  Thereafter, as the gate insulating film, a SiN film is formed to a thickness of 20 nm, for example, by plasma CVD.

  The gate electrode 8 is formed by evaporating and lifting off, for example, Ni 20 nm and Au 200 nm.

  Note that the width of the gate electrode 8 formed by lift-off is wider than that of the selectively grown undoped GaN layer, and partially covers the surface of the AlGaN layer adjacent to the undoped GaN layer. A portion covering the surface of the AlGaN layer other than the undoped GaN layer via the SiN film functions as a field plate electrode. The field plate electrode portion extends 5 μm from the opening to the drain electrode 7 side.

  The width from the end of the opening on the drain electrode 7 side to the end of the third nitride semiconductor layer 5 on the gate electrode side is selected to be 12 μm. The width of the third nitride semiconductor layer 5 itself is selected to be 100 μm.

A laminated structure of gate electrode / insulating film / GaN layer / AlGaN layer / GaN layer is formed immediately below the gate electrode 8. At that time, the interface charges of σ _p (GaN / AlGaN) and σ _p (AGaN / GaN) are caused at the GaN layer / AlGaN layer interface and the AlGaN layer / GaN layer interface, respectively, due to the polarization effect. Produces. When the thickness of the AlGaN layer is selected to be 30 nm, tensile strain exists only in the AlGaN layer due to lattice mismatch. As a result, the sum of the interface charges, {σ _p (GaN / AlGaN) + σ _p (AGaN / GaN)}, is substantially {σ _p (GaN / AlGaN) + σ _p (AGaN / GaN)} ≈0. ing. As a result, the field effect transistor of the third embodiment is also in the “OFF state” when the gate voltage V _gs = 0 V is applied to the gate electrode 8. The gate portion has a MIS structure.

Also in the field effect transistor of the third embodiment, the measured gate current-gate voltage (I _g -V _gs ) characteristic is as follows when a positive drain voltage V _ds = 20 V is applied to the drain electrode 7. This is substantially the same as the field effect transistor of the first embodiment. Further, regarding the measured drain current-gate voltage (I _d -V _gs ) characteristics under the condition that a positive drain voltage V _ds = 20 V is applied to the drain electrode 7, the field effect transistor of the third embodiment is also used. The performance is substantially the same as the performance of the field effect transistor of the first embodiment.

Similar to the structure of the field effect transistor of the first embodiment shown in FIG. 4, the structure of the field effect transistor of the third embodiment shown in FIG. 10 also has a high drain current density required for the power control device, It is judged that both the two requirements of the low gate current density when the positive gate voltage V _gs = 10 V is applied are satisfied.

  In the field effect transistor of the third embodiment, a high-resistance (0001) plane SiC substrate is used as a substrate, and a (0001) plane grown III-nitride epitaxial film is used on the device. Is making. If a (0001) -plane-grown III-nitride epitaxial film can be formed on the surface, and a high-resistance substrate, a sapphire substrate, Si substrate, or ZnO substrate can be used instead of the high-resistance (001) plane SiC substrate. Etc. can be used.

(Second form)
The structure of the field effect transistor according to the second embodiment of the present invention and its operating principle will be described below.

  FIG. 11A is a plan view schematically showing an example of the structure of the field effect transistor according to the second embodiment of the present invention, and FIG. 11B shows the drain electrode portion with a broken line. It is sectional drawing which shows typically the structure observed when cut | disconnecting in the site | part shown and observing from the cut surface side.

On the substrate 1, buffer layer 2 having a thickness t _2, as the channel layer, the first nitride semiconductor layer 3 having a thickness of t _3, as an electron supply layer, a second nitride film thickness t ₄ the semiconductor layer 4 In addition, the third nitride semiconductor layer 5 having the thickness t ₅ and having P-type conductivity is grown sequentially. Except for the drain region, the third nitride semiconductor layer 5 is removed by etching, and the surface of the second nitride semiconductor layer 4 is exposed. In the drain region, the third nitride semiconductor layer 5 is etched into a stripe shape, and the surface of the second nitride semiconductor layer 4 is exposed between the stripe-shaped third nitride semiconductor layers 5. There is a part that is.

  A source electrode 6 is formed on the surface of the second nitride semiconductor layer 4 of the electron supply layer. On the other hand, in the drain region, the drain electrode 7 is formed on the surface of the striped third nitride semiconductor layer 5 and on the surface of the second nitride semiconductor layer 4 exposed therebetween. The source electrode 6 forms an ohmic junction with the second nitride semiconductor layer 4. On the other hand, the drain electrode 7 forms an ohmic junction with the striped third nitride semiconductor layer 5. Further, the drain electrode 7 forms a Schottky junction with respect to the second nitride semiconductor layer 4 exposed in the meantime. A gate electrode 8 is provided in a region sandwiched between the source electrode 6 and the drain electrode 7.

A recess for forming the gate electrode 8 is formed on the surface of the second nitride semiconductor layer 4 of the electron supply layer. The surface of the second nitride semiconductor layer 4 on which the recess is formed is covered with an insulating film 9, and the recess is formed in a shape in which the gate electrode 8 is embedded via the insulating film 9. Yes. The gate electrode 8 has a gate length L _gate-8, and a MIS structure is formed immediately below the gate electrode 8 / insulating film 9 / second nitride semiconductor layer 4. The thickness is the film thickness t ₉ at the surface of the second nitride semiconductor layer 4 and the bottom portion of the recess portion, and the film thickness t _9-well at the portion covering the sidewall of the recess portion.

The depth d _Recess of the recessed portion can be than the thickness t ₉ of the insulating film 9 is selected to be greater. Further, the thickness t ₉ of the insulating film 9 may be chosen thicker than the depth d _Recess of the recessed portion.

The width W _Recess of the recessed portion, and the thickness t _9-well of the insulating film side wall surface of the recessed portion, the gate length L _Gate-8 of the gate electrode _{8, W recess = L gate-} 8 + 2 × It is set so as to satisfy the condition of _t9-well .

In the channel region immediately below the recess portion, the thickness of the second nitride semiconductor layer 4 is etched and thinned along with the formation of the recess portion. Thickness t _4-Recess of the second nitride semiconductor layer 4 immediately below the recess portion in accordance with the depth d _Recess of the recessed portion, and it is _{t 4-recess = t 4 -d} recess.

The channel region immediately below the gate electrode 8 has a stacked structure of the gate electrode 8 / insulating film 9 / second nitride semiconductor layer 4 / first nitride semiconductor layer 3 having a film thickness t _{4 -recess} . When the gate voltage V _gs applied to the gate electrode 8 is set to V _gs = 0V, no carriers (electrons) exist in this channel region. That is, the threshold voltage V _T is V _T > 0V.

At the interface between the gate electrode 8 and the insulating film 9, the work function eψ (M _gate ) eV of the metal material M _gate in contact with the surface of the insulating film 9 in the gate electrode 8 and the insulating material I _{front on} the surface of the insulating film 9. A barrier Φ _{M / I} corresponding to the difference from the electron affinity eχ (I _front ) eV, (eψ (M _gate )) eV, is generated. At the interface between the insulating film 9 and the second nitride semiconductor layer 4, the electron affinity eχ (I _rear ) eV of the insulating material I _rear on the back surface of the insulating film 9 and the electron affinity eχ ( A barrier Φ _{I / S} ) corresponding to (eχ (S2) −eχ (I _rear )) eV is generated.

  Further, at the interface between the second nitride semiconductor layer 4 and the first nitride semiconductor layer 3, the band discontinuity ΔEc (S2 / S2) due to the conduction band energy difference between the second nitride semiconductor and the first nitride semiconductor. S1) exists. There is also a band discontinuity ΔEv (S2 / S1) due to the valence band energy difference.

  In the “ON state”, an energy barrier corresponding to the band discontinuity ΔEc (S2 / S1) is used at the interface between the second nitride semiconductor layer 4 and the first nitride semiconductor layer 3. , Carriers (electrons) are accumulated. At that time, the material of the second nitride semiconductor layer 4 / the first nitride semiconductor layer is preferably selected so that the band discontinuity ΔEc (S2 / S1)> 2 kT.

When V _gs = 0V, there is no carrier (electron) in this channel region, so the second nitride semiconductor layer 4 having a film thickness t _4-recess immediately below the gate electrode 8 and the first The surface side of one nitride semiconductor layer 3 is depleted. Further, carriers (electrons) are not accumulated at the heterojunction interface between the second nitride semiconductor layer 4 and the first nitride semiconductor layer 3. In that case, the film thickness t _3g-sc of the depleted region on the surface side of the first nitride semiconductor layer 3 is t ₃ ≧ t _3g-sc .

The second nitride semiconductor layer 4 is undoped or doped with an n-type impurity (donor), and is depleted when the concentration of the included n-type impurity (donor) is N _D (S2) cm ⁻³ . At this time, the surface density of the space charge due to the ionized n-type impurity (donor) is N _D (S2) · t _4−recess cm ⁻² . The first nitride semiconductor layer 3 is undoped, and when the residual n-type impurity (donor) concentration contained is N _D (S1) cm ⁻³ , ionization occurs when the film thickness t _3g-sc is depleted. The surface density of the space charge resulting from the n-type impurity (donor) is N _D (S1) · t _3g-sc cm ⁻² .

When V _gs = 0V, depleted portions in the second nitride semiconductor layer 4 and the first nitride semiconductor layer 3 exhibit band bends (bends) due to space charge. As a result, in the second nitride semiconductor layer 4 having the film thickness t _4-recess , the energy level difference at the conduction band edge, ΔEc (S2: N _D (S2) · t _4-recess ), and the second There is an energy level difference ΔEcp (S1: Polarization) derived from the polarization electric field generated between the nitride semiconductor layer 4 and the first nitride semiconductor layer 3. In the depletion region of the film thickness t _3g-sc of the first nitride semiconductor layer 3, an energy level difference ΔEc (S1: N _D (S1) · t _3g-sc ) is generated. .

Considering the band diagram in the channel region immediately below the gate electrode 8 when V _gs = 0 V, Φ _{M / I} ≧ Φ _{I / S} + ΔEc (S2: N _D (S2) · t _4-recess ) + ΔEcp ( It is necessary to satisfy the relationship of (S1: Polarization) + ΔEc (S2 / S1) + ΔEc (S1: N _D (S1) · t _3g-sc ) when configuring a normally-off transistor. For example, a combination of the second nitride semiconductor layer 4 and the nitride semiconductor material constituting the first nitride semiconductor layer, a combination of (N _D (S2), t _4-recess ) so as to achieve the above condition , (N _D (S1), t _3g-sc ) is appropriately selected.

In order to enter the “ON state”, it is necessary to apply to the gate electrode 8 a positive gate voltage V _gs that can eliminate the depletion region present in the first nitride semiconductor layer 3. Therefore, the threshold voltage V _T to be shifted from the “OFF state” to the “ON state” is at least V _T > ΔEc (S1: N _D (S1) · t _3g-sc ) / q> 0 V (where q Represents the charge amount (unit charge) of electrons.

  Immediately below the drain electrode 7, in the region where the striped third nitride semiconductor layer 5 is present, the drain electrode 7 / third nitride semiconductor layer 5 having P-type conductivity / second nitride semiconductor. A layered structure of layer 4 / first nitride semiconductor layer 3 is formed. On the other hand, in the region where the surface of the second semiconductor layer 4 is exposed, a stacked structure of the drain electrode 7 / the second nitride semiconductor layer 4 / the first nitride semiconductor layer 3 is formed.

  FIG. 12A schematically shows a band diagram of a region where the striped third nitride semiconductor layer 5 is present immediately below the drain electrode 7. FIG. 12B schematically shows a band diagram of a region where the surface of the second semiconductor layer 4 is exposed immediately below the drain electrode 7.

The third nitride semiconductor layer 5 having P-type conductivity is doped with a p-type impurity (acceptor) at a high concentration and functions as a p ⁺ layer. Ohmic contact is achieved between the drain electrode 7 / P-type third nitride semiconductor layer 5 having conductivity. At this interface, of the drain electrode 7, the work function eψ (M _ohmic ) eV of the metal material M _ohmic that is in contact with the third nitride semiconductor layer 5 and the electron affinity eχ (S 3) of the third nitride semiconductor layer 5. A barrier Φ _{M / S3} corresponding to the difference from eV, (eψ (M _ohmic ) −eχ (S3)) eV, is generated. Due to this barrier Φ _{M / S3} , the thickness of the depletion region formed at the interface of the p ⁺ layer is extremely thin. Therefore, the depletion region is tunneled, and electrons are quickly emitted from the p ⁺ layer to the drain electrode 7, and apparently the third nitride semiconductor layer 5 having P-type conductivity from the drain electrode 7. Holes are injected into.

The stacked structure portion of the third nitride semiconductor layer 5 / second nitride semiconductor layer 4 / first nitride semiconductor layer 3 having P-type conductivity is a P ⁺ In ⁻ junction or a P ⁺ n ⁻ junction. Configure. At that time, in the P ⁺ In ⁻ junction or the P ⁺ n ⁻ junction, the difference between the conduction band edge energy Ec (P ⁺ ) and the Fermi level energy L _{f in} the P ⁺ layer (Ec (P ⁺ ) −E _f ). And the difference between the conduction band edge energy Ec (n ⁻ ) and the Fermi level energy L _{f in} the n ⁻ layer (Ec (n ⁻ ) −E _f ). Accordingly, P ⁺ an In ^- the bonding, ^- bonding or ^{P + n {(Ec (P} +) -E f) - (Ec (n -) -E f)} corresponds to the built-in potential eV _{Built- in} is generated. Therefore, the n-type impurity (donor) contained in the second nitride semiconductor layer 4 is ionized. That is, the second nitride semiconductor layer 4 is depleted. At this time, since the band discontinuity ΔEc (S2 / S1) exists at the interface between the second nitride semiconductor layer 4 and the first nitride semiconductor layer 3, when carriers (electrons) are generated. Will accumulate electrons at this interface.

When the drain voltage V _ds applied to the drain electrode 7 is a positive voltage, the P ⁺ In ⁻ junction (P ⁺ n ⁻ junction) is in a forward-biased state, and the second nitride semiconductor layer 4, hole diffusion and electron diffusion occur. That is, from the third nitride semiconductor layer 5 having P-type conductivity, which is a P ⁺ layer, toward the second nitride semiconductor layer 4 / first nitride semiconductor layer 3 which is an In ⁻ region. , Holes diffuse. At the same time, the band discontinuity ΔEc (S2 / S1) at the interface of the second nitride semiconductor layer 4 / first nitride semiconductor layer 3 is further generated from the first nitride semiconductor layer 3 to the interface of the second nitride semiconductor layer 4 / first nitride semiconductor layer 3. Beyond that, electrons diffuse into the second nitride semiconductor layer 4.

A forward bias is applied to the P ⁺ In ⁻ junction (P ⁺ n ⁻ junction), and the conduction band edge Ec (S3) of the third nitride semiconductor layer 5 and the conduction band of the first nitride semiconductor layer 3 are applied. When the energy difference from the end Ec (S1) reaches kT, a large forward current flows through the P ⁺ In ⁻ junction (P ⁺ n ⁻ junction). That is, the _forward bias applied to the P ⁺ In ⁻ junction (P ⁺ n ⁻ junction), V _PIN-forward , with respect to the band gap energy Eg (S 3) of the third nitride semiconductor layer 5, When the condition of Eg (S3) −q · V _PIN-forward ≦ kT is satisfied, a large forward current flows. In other words, P ⁺ an In ^- bonded ^- to supply a large forward current (P ⁺ n junction) is, P ⁺ an In ^- bonding ^- forward bias applied to the (P ⁺ n junction), V _PIN-forward Q · V _PIN-forward ≧ (Eg (S3) −kT). The _forward bias V _PIN-forward applied to the P ⁺ In ⁻ junction (P ⁺ n ⁻ junction) with respect to the drain voltage V _{ds satisfies} V _ds > V _PIN-forward . Therefore, in order to allow a large forward current to flow through the P ⁺ In ⁻ junction (P ⁺ n ⁻ junction), the drain voltage V _ds needs to be q · V _ds > (Eg (S3) −kT). is there.

On the other hand, the second nitride semiconductor layer 4 is undoped or doped with an n-type impurity (donor) and functions as an i layer or an n ⁻ layer. Therefore, ohmic contact is not achieved between the drain electrode 7 / the second nitride semiconductor layer 4, and a Schottky junction is formed. At this interface, of the drain electrode 7, the work function eψ (M _ohmic ) eV of the metal material M _ohmic in contact with the third nitride semiconductor layer 5 and the electron affinity eχ (S 2) of the second nitride semiconductor layer 4. A barrier Φ _{M / S2} corresponding to the difference from eV, (eψ (M _ohmic ) −eχ (S2)) eV, is generated.

When the drain voltage V _ds applied to the drain electrode 7 is a positive voltage, a Schottky junction having a stacked structure of the drain electrode 7 / second nitride semiconductor layer 4 / first nitride semiconductor layer 3 is used. Is forward biased. The forward bias V _MES (M _ohmic / S3) applied to this Schottky junction is {Φ _{M / S2} −q · V _MES (M _ohmic / S3)} ≦ kT with respect to the barrier Φ _{M / S2} . When the condition is satisfied, a large forward current flows. The forward bias V _MES (M _ohmic / S3) applied to the Schottky junction with respect to the drain voltage V _ds is V _ds > V _MES (M _ohmic / S3). Therefore, if the drain voltage V _ds is q · V _ds > q · V _MES (M _ohmic / S3) ≧ (Φ _{M /} S ₂ −kT), a large forward current can flow through this Schottky junction. It is.

Of course, with respect to the band gap energy Eg (S2) of the second nitride semiconductor layer 4, the barrier Φ _{M / S4} satisfies Eg (S2)> Φ _{M / S2} . Therefore, for example, when the band gap energy Eg (S2) of the second nitride semiconductor layer 4 and the band gap energy Eg (S3) of the third nitride semiconductor layer 5 are equal, Eg (S3) = Eg (S2)> Φ _{M / S2} .

Therefore, in the field effect transistor according to the second embodiment of the present invention, when the gate voltage V _gs applied to the gate electrode 8 is made higher than the positive threshold voltage V _T (V _gs > V _T > 0 V), “ In the range where the drain voltage V _ds does not satisfy the condition of q · V _ds > (Φ _{M / S2} −kT), the drain current I _d is at a low level. On the other hand, when the drain voltage V _ds satisfies the condition of q · V _ds > (Φ _{M / S2} −kT), the drain current I _d increases as the drain voltage V _ds increases. In other words, in the field effect transistor according to the second embodiment of the present invention, the offset voltage V _off-set is (Φ _{M / S2} −kT) / q V.

In this case, when the drain voltage V _ds is “ON” in the range of (Eg (S3) −kT)> q · V _ds > (Φ _{M / S2} −kT), the drain electrode mainly A drain current I _d flows through a region where the surface of the second semiconductor layer 4 is exposed immediately below 7. When the drain voltage V _ds reaches the range of q · V _ds > (Eg (S3) −kT)> (Φ _{M / S2} −kT), when the drain voltage V _ds is in the “ON state”, In addition to the region where the surface of the second semiconductor layer 4 is exposed, the drain current I _{d is} also passed through the region where the striped third nitride semiconductor layer 5 exists immediately below the drain electrode 7. Will be in a state of flowing.

In the field effect transistor of the first embodiment of the present invention described above, when the gate voltage V _gs applied to the gate electrode 8 is made higher than the positive threshold voltage V _T (V _gs > V _T > 0 V). However, the drain current I _d is at a low level within a range where the drain voltage V _ds does not satisfy the condition of q · V _ds > (Eg (S3) −kT). In other words, in the field effect transistor according to the first aspect of the present invention, the offset voltage V _off-set is a value corresponding to (Eg (S3) −kT) / qV.

In the field effect transistor according to the second aspect of the present invention, the region where the striped third nitride semiconductor layer 5 exists immediately below the drain electrode 7 and the second semiconductor layer directly below the drain electrode 7. The following effects are achieved by using together with the region where the surface of 4 is exposed. That is, by having a region where the striped third nitride semiconductor layer 5 exists immediately below the drain electrode 7, the field effect transistor according to the second aspect of the present invention also has the first aspect of the present invention described above. A high drain current density can be obtained as in the case of the field effect transistor of the form. In addition, by using a region where the surface of the second semiconductor layer 4 is exposed immediately below the drain electrode 7, the offset voltage V _off-set (( [Phi] _{M / S2-} kT) / q V) is significantly lower than the offset voltage _Voff-set ((Eg (S3) -kT) / q V) of the field effect transistor according to the first embodiment of the present invention. Is done.

For example, the barrier Φ _{M / S2} (contact potential difference) of the Schottky junction between the drain electrode 7 and the second nitride semiconductor layer 4 is about 1 eV, but the band gap of the third nitride semiconductor layer 5 When the energy Eg (S3) is about 4 eV, the difference in the offset voltage V _off-set associated therewith becomes significant.

In order to fully exhibit these two effects, the total area S _total (S3) of the stripe-shaped third nitride semiconductor layer 5 and the second semiconductor layer 4 directly below the drain electrode 7 are provided. The ratio of the _total area S _total (M _ohmic / S2) of the area where the surface is exposed is at least in the range of 50/50 ≧ S _total (M _ohmic / S2) / S _total (S3) ≧ _10/70 It is preferable to select.

  Next, the structure of the field effect transistor according to the second embodiment of the present invention will be described using a specific example.

(Fourth embodiment)
FIG. 13 is a cross-sectional view schematically showing the device structure of the field effect transistor of the fourth embodiment. The field effect transistor of the fourth embodiment has a structure described below.

  As the substrate 1, a high resistance SiC substrate is used. For example, the buffer layer 2, the first nitride semiconductor layer 3, the second nitride semiconductor layer 4, and the third nitride semiconductor layer 5 that are grown on the (0001) plane on the (0001) plane SiC substrate are sequentially formed. It is formed by epitaxial growth.

On a (001) plane SiC substrate, for example, an AlN buffer layer having a film thickness of 4 nm is formed as a nucleation layer, and then an AlGaN / GaN periodic layer having a thickness of 1000 nm is formed. The AlN buffer layer and the AlGaN / GaN periodic layer are buffered. Used as layer 2. On the AlGaN / GaN periodic layer, a film made of Al _0.20 Ga _0.80 N (Al composition 0.20) as the first nitride semiconductor layer 3 as a GaN layer with a thickness of 1000 nm and as the second nitride semiconductor layer 4 An AlGaN layer having a thickness of 30 nm is formed. Further, as the third nitride semiconductor layer 5, a p ⁺ -AlGaN layer having a thickness of 30 nm made of Zn-doped Al _0.20 Ga _0.80 N (Al composition 0.20) is formed. The Zn concentration added to this p ⁺ -AlGaN layer is selected to be 10 ¹⁹ cm ⁻³ .

The drain electrode region is covered with a striped resist, and the third nitride semiconductor layer 5 in other regions is removed by etching. For the selective etching of the p ⁺ -AlGaN layer, ICP plasma mainly composed of boron trichloride (BCl ₃ ) gas is used. The striped resist used for the etching mask has a stripe width of 20 μm, a stripe length of 100 μm, and a gap between stripes of 5 μm. Further, the gap from the end of the striped resist to the end of the recess used for forming the gate electrode 8 on the drain electrode 7 side is set to 12 μm.

As the source electrode 6 formed on the surface of the exposed AlGaN layer, Ti and Al metal are formed by vapor deposition and a lift-off process. In the drain electrode region where the striped p ⁺ -AlGaN layer is formed, Ni and Au metals are formed as a drain electrode 7 by vapor deposition and a lift-off process. The drain electrode 7 is in contact with the striped p ⁺ -AlGaN layer and the surface of the AlGaN layer exposed therebetween. The ratio of the sum S _total (S3) of the area of the striped p ⁺ -AlGaN layer and the sum S _total (M _ohmic / S2) of the surface area of the AlGaN layer in contact with the drain electrode 7 is S _total (M _ohmic / S2) are selected _{/ S total (S3) = 5} /20. The surface of the AlGaN layer and the source electrode 6, and the surface of the striped p ⁺ -AlGaN layer and the drain electrode 7 are subjected to heat treatment at 650 ° C. in a nitrogen atmosphere to form ohmic contacts.

Element isolation is performed by nitrogen ion implantation. As the nitrogen ion implantation conditions, an acceleration voltage of 100 kV and an implantation density of 4 × 10 ¹⁴ cm ⁻² are selected using a resist film having a thickness of 1 μm as a mask. After element isolation, a 200 nm SiN film is formed by plasma CVD. An opening for forming a recess is formed in the SiN film. The SiN film in the recess portion is removed using ICP plasma whose opening width is 2.0 μm and whose main component is sulfur hexafluoride (SF ₆ ) gas. The AlGaN layer exposed in the opening of the SiN film is etched away by 20 nm using ICP plasma mainly composed of boron trichloride (BCl ₃ ) gas to form a recess. Therefore, immediately below the recess portion, the thickness of the AlGaN layer is 10 nm.

  Thereafter, as the gate insulating film, a SiN film is formed to a thickness of 20 nm, for example, by plasma CVD. The thickness of the SiN film covering the side wall of the recess is 20 nm. Since the depth of the recess portion is 20 nm and the thickness of the SiN film is 20 nm, the surface of the SiN film covering the bottom surface of the recess portion and the surface of the AlGaN layer other than the recess portion are located at the same level. .

  The gate electrode 8 is formed by evaporating and lifting off, for example, Ni 20 nm and Au 200 nm. At that time, the gate electrode 8 formed so as to be embedded in the recess portion through the gate insulating film has a gate length corresponding to (2.0 μm−2 × 20 nm).

  The width of the electrode formed by lift-off is selected to be 2.0 μm. Therefore, the surface of the AlGaN layer other than the recess is not covered with this electrode. That is, no structure corresponding to the field plate electrode is provided on the drain electrode 7 side of the recess.

  The width from the end of the recess portion on the drain electrode 7 side to the end of the third nitride semiconductor layer 5 on the gate electrode side is selected to be 12 μm. The width of the third nitride semiconductor layer 5 itself corresponds to the stripe length of 100 μm.

  On the bottom surface of the recess portion, the ratio of the thickness of the AlGaN layer immediately below the gate electrode 8 to the gate length is (2.0 μm−2 × 20 nm) / 10 nm.

Therefore, when the structure of the field effect transistor of the fourth embodiment is viewed from above, it corresponds to the structure illustrated in FIG. The structure shown in the cross-sectional view of FIG. 13 schematically shows the cross-sectional structure of the region where the striped p ⁺ -AlGaN layer exists. In addition, when the drain electrode part is cut | disconnected in the site | part shown with a broken line in (a) of FIG. 11, and it observes from the cut surface side, the structure observed is illustrated in (b) of FIG. It corresponds to the structure.

  For comparison, the field effect transistor according to the first embodiment of the present invention having the structure illustrated in FIG. 1 is manufactured by the following procedure.

The field effect transistor according to the first embodiment of the present invention having the structure illustrated in FIG. 1 has a structure in which the following points are changed with respect to the field effect transistor according to the fourth embodiment. Instead of the striped p ⁺ -AlGaN layer, there is no region where the AlGaN layer is exposed between the stripes, and the entire structure has a rectangular p ⁺ -AlGaN layer in the drain electrode region. The gap between the end of the rectangular p ⁺ -AlGaN layer on the gate electrode 8 side and the end of the recess used for forming the gate electrode 8 on the drain electrode 7 side is 12 μm.

Further, the area S _full (S3) of the p ⁺ -AlGaN layer in the field effect transistor according to the first embodiment of the present invention having the structure illustrated in FIG. 1 and the stripe in the field effect transistor according to the fourth embodiment. The ratio of the _total S _total (S3) of the area of the p ⁺ -AlGaN layer is S _total (S3) / S _full (S3) = 20/25.

When the gate voltage V _gs = 8 V is set, the drain current measured for the field effect transistor of the fourth embodiment shown in FIG. 13 and the field effect transistor of the first embodiment of the present invention having the structure shown in FIG. -Drain voltage (I _d -V _ds ) characteristics are shown in comparison with FIG.

The band gap energy of Al _0.20 Ga _0.80 N used for p ⁺ -AlGaN / n ⁻ -AlGaN / GaN P ⁺ In ⁻ junction (or P ⁺ n ⁻ junction) is Eg (Al _0.20 Ga _0.80 N). It is about 3.8 eV. At that time, in the field effect transistor according to the first embodiment of the present invention shown in FIG. 1, the drain electrode portion is a p ⁺ -AlGaN / n ⁻ -AlGaN / GaN P ⁺ In ⁻ junction (or P ⁺ n ⁻ junction). ), The offset voltage V _off-set is about 4V.

On the other hand, the barrier Φ _{M / S2} of the Schottky junction composed of Au / Ni / n ⁻ -Al _0.20 Ga _0.80 N is about Φ _{M / S2} ≈1.1 eV. At that time, in the field effect transistor of the fourth embodiment, the portion where the Ni / Au electrode is formed on the surface of the AlGaN layer of the second nitride semiconductor layer 4 is present in the drain electrode portion. _{The off-set} is about 1V. When the drain voltage V _ds becomes V _ds > 4 V, the p ⁺ -AlGaN / n ⁻ -AlGaN / GaN P ⁺ In ⁻ junction (or P ⁺ n ⁻ junction) existing in the drain electrode portion is in the forward direction. Biased. At that time, holes are injected from the third nitride semiconductor layer 5 (p ⁺ -AlGaN layer) into the first nitride semiconductor layer 3 (GaN layer) of the channel layer, and as a result, carriers (electrons) are injected. Is induced and accumulated at the n ⁻ -AlGaN / GaN interface. As a result, when the drain voltage V _ds becomes V _ds > 5 V, the drain current density reaches a level of 0.40 A / mm.

The field effect transistor of the fourth embodiment shown in FIG. 13 satisfies two conditions, which are required for a power control device, a high drain current density and a low gate current density when a positive gate voltage of 10 V is applied. Further, in the “ON state”, the offset voltage V _off-set of the drain voltage V _ds indicating the rising of the drain current I _d is greatly reduced.

  In the field effect transistor of the fourth embodiment, a high-resistance (0001) plane SiC substrate is used as a substrate, and a (0001) plane grown III-nitride epitaxial film is used on the device. Is making. If a (0001) -plane-grown III-nitride epitaxial film can be formed on the surface, and a high-resistance substrate, a sapphire substrate, Si substrate, or ZnO substrate can be used instead of the high-resistance (001) plane SiC substrate. Etc. can be used.

(Third form)
The structure of the field effect transistor according to the third embodiment of the present invention and its operating principle will be described below.

  FIG. 15 is a cross-sectional view schematically showing an example of the structure of the field effect transistor according to the third embodiment of the present invention.

As a barrier layer serving as an energy barrier against carriers (electrons or holes) in the conductive substrate 1 on the conductive substrate 1, the buffer layer 2 having a thickness t _2, a fourth nitride having a thickness t ₁₂ is used. semiconductor layer 12, as a channel layer, having a first nitride semiconductor layer 3 having a thickness of t _3, as an electron supply layer, the second nitride semiconductor layer 4 having a thickness t _4, as well, a P-type conductivity The third nitride semiconductor layer 5 having a film thickness t ₅ is sequentially grown. Except for the drain region, the third nitride semiconductor layer 5 is removed by etching, and the surface of the second nitride semiconductor layer 4 is exposed.

  A source electrode 6 is formed on the surface of the second nitride semiconductor layer 4 of the electron supply layer, and a drain electrode 7 is formed on the surface of the third nitride semiconductor layer 5 having P-type conductivity. . The source electrode 6 forms an ohmic junction with the second nitride semiconductor layer 4, and the drain electrode 7 forms an ohmic junction with the third nitride semiconductor layer 5. A gate electrode 8 is provided in a region sandwiched between the source electrode 6 and the drain electrode 7.

A recess for forming the gate electrode 8 is formed on the surface of the second nitride semiconductor layer 4 of the electron supply layer. The surface of the second nitride semiconductor layer 4 on which the recess is formed is covered with an insulating film 9, and the recess is formed in a shape in which the gate electrode 8 is embedded via the insulating film 9. Yes. The gate electrode 8 has a gate length L _gate-8, and a MIS structure is formed immediately below the gate electrode 8 / insulating film 9 / second nitride semiconductor layer 4. The thickness is the film thickness t ₉ at the surface of the second nitride semiconductor layer 4 and the bottom portion of the recess portion, and the film thickness t _9-well at the portion covering the sidewall of the recess portion.

The depth d _Recess of the recessed portion can be than the thickness t ₉ of the insulating film 9 is selected to be greater. Further, the thickness t ₉ of the insulating film 9 may be chosen thicker than the depth d _Recess of the recessed portion.

The width W _Recess of the recessed portion, and the thickness t _9-well of the insulating film side wall surface of the recessed portion, the gate length L _Gate-8 of the gate electrode _{8, W recess = L gate-} 8 + 2 × It is set so as to satisfy the condition of _t9-well .

In the channel region immediately below the recess portion, the thickness of the second nitride semiconductor layer 4 is etched and thinned along with the formation of the recess portion. Thickness t _4-Recess of the second nitride semiconductor layer 4 immediately below the recess portion in accordance with the depth d _Recess of the recessed portion, and it is _{t 4-recess = t 4 -d} recess.

The channel region immediately below the gate electrode 8 has a stacked structure of the gate electrode 8 / insulating film 9 / second nitride semiconductor layer 4 / first nitride semiconductor layer 3 having a film thickness t _{4 -recess} . When the gate voltage V _gs applied to the gate electrode 8 is set to V _gs = 0V, no carriers (electrons) exist in this channel region. That is, the threshold voltage V _T is V _T > 0V.

At the interface between the gate electrode 8 and the insulating film 9, the work function eψ (M _gate ) eV of the metal material M _gate in contact with the surface of the insulating film 9 in the gate electrode 8 and the insulating material I _{front on} the surface of the insulating film 9. A barrier Φ _{M / I} corresponding to the difference from the electron affinity eχ (I _front ) eV, (eψ (M _gate ) −eχ (I _front )) eV, is generated. At the interface between the insulating film 9 and the second nitride semiconductor layer 4, the electron affinity eχ (I _rear ) eV of the insulating material I _rear on the back surface of the insulating film 9 and the electron affinity eχ ( S2) A barrier Φ _{I / S} corresponding to the difference from eV, (eχ (S2) −eχ (I _rear )) eV is generated.

  Further, at the interface between the second nitride semiconductor layer 4 and the first nitride semiconductor layer 3, the band discontinuity ΔEc (S2 / S2) due to the conduction band energy difference between the second nitride semiconductor and the first nitride semiconductor. S1) exists. There is also a band discontinuity ΔEv (S2 / S1) due to the valence band energy difference.

  In the “ON state”, an energy barrier corresponding to the band discontinuity ΔEc (S2 / S1) is used at the interface between the second nitride semiconductor layer 4 and the first nitride semiconductor layer 3. , Carriers (electrons) are accumulated. At that time, the material of the second nitride semiconductor layer 4 / the first nitride semiconductor layer is preferably selected so that the band discontinuity ΔEc (S2 / S1)> 2 kT.

When V _gs = 0V, there is no carrier (electron) in this channel region, so the second nitride semiconductor layer 4 having a film thickness t _4-recess immediately below the gate electrode 8 and the first The surface side of one nitride semiconductor layer 3 is depleted. Further, carriers (electrons) are not accumulated at the heterojunction interface between the second nitride semiconductor layer 4 and the first nitride semiconductor layer 3. In that case, the film thickness t _3g-sc of the depleted region on the surface side of the first nitride semiconductor layer 3 is t ₃ ≧ t _3g-sc .

The second nitride semiconductor layer 4 is undoped or doped with an n-type impurity (donor), and is depleted when the concentration of the included n-type impurity (donor) is N _D (S2) cm ⁻³ . At this time, the surface density of the space charge due to the ionized n-type impurity (donor) is N _D (S2) · t _4−recess cm ⁻² . The first nitride semiconductor layer 3 is undoped, and when the residual n-type impurity (donor) concentration contained is N _D (S1) cm ⁻³ , ionization occurs when the film thickness t _3g-sc is depleted. The surface density of the space charge resulting from the n-type impurity (donor) is N _D (S1) · t _3g-sc cm ⁻² .

When V _gs = 0V, depleted portions in the second nitride semiconductor layer 4 and the first nitride semiconductor layer 3 exhibit band bends (bends) due to space charge. As a result, in the second nitride semiconductor layer 4 having the film thickness t _4-recess , the energy level difference at the conduction band edge, ΔEc (S2: N _D (S2) · t _4-recess ), and the second There is an energy level difference ΔEcp (S1: Polarization) derived from the polarization electric field generated between the nitride semiconductor layer 4 and the first nitride semiconductor layer 3. In the depletion region of the film thickness t _3g-sc of the first nitride semiconductor layer 3, an energy level difference ΔEc (S1: N _D (S1) · t _3g-sc ) is generated. .

Considering the band diagram in the channel region immediately below the gate electrode 8 when V _gs = 0 V, Φ _{M / I} ≧ Φ _{I / S} + ΔEc (S2: N _D (S2) · t _4-recess ) + ΔEcp ( It is necessary to satisfy the relationship of (S1: Polarization) + ΔEc (S2 / S1) + ΔEc (S1: N _D (S1) · t _3g-sc ) when configuring a normally-off transistor. For example, a combination of nitride semiconductor materials constituting the second nitride semiconductor layer 4 and the first nitride semiconductor layer 3 so as to achieve the above condition, (N _D (S2), t _4-recess ) A combination and a combination of (N _D (S1), t _3g-sc ) are appropriately selected.

In order to enter the “ON state”, it is necessary to apply to the gate electrode 8 a positive gate voltage V _gs that can eliminate the depletion region present in the first nitride semiconductor layer 3. Therefore, the threshold voltage V _T to be shifted from the “OFF state” to the “ON state” is at least V _T > ΔEc (S1: N _D (S1) · t _3g-sc ) / q> 0 V (where q Represents the charge amount (unit charge) of electrons.

On the other hand, a back electrode in ohmic contact with the conductive substrate 1 is formed on the back surface of the conductive substrate 1. This back electrode is electrically connected to the source electrode 6 and has the same potential. Therefore, a bias corresponding to the drain voltage V _ds is also applied between the conductive substrate 1 and the drain electrode 7.

  When the conductive substrate 1 is an n-type conductive substrate, the fourth nitride semiconductor layer 12 functions as a barrier layer that serves as an energy barrier against carriers (electrons) in the conductive substrate 1. .

When the buffer layer 2 and the first nitride semiconductor layer 3 of the channel layer are layers made of an n ⁻ type nitride semiconductor, when a positive drain voltage V _ds is applied to the drain electrode 7, the channel layer A positive bias is applied between the first nitride semiconductor layer 3 and the source electrode 6. Therefore, a positive bias is also applied between the first nitride semiconductor layer 3 of the channel layer and the n-type conductive electrode 1. The fourth nitride semiconductor layer 12, which is a barrier layer functioning as an energy barrier against electrons, includes, for example, a layer made of a nitride semiconductor exhibiting p-type conductivity doped with p-type impurities at a high concentration. adopt. At this time, the first nitride semiconductor layer 3 / the fourth nitride semiconductor layer 12 / the first nitride semiconductor layer 3 / the substrate have a structure of n ⁻ layer / p ⁺ layer / n ⁻ layer / n ⁺ substrate. Therefore, injection of electrons from the n-type conductive substrate 1 to the first nitride semiconductor layer 3 is prevented.

That is, in the p ⁺ n ⁻ junction of the p ⁺ layer / n ⁻ layer / n ⁺ substrate, the difference between the conduction band edge energy Ec (p ⁺ ) and the Fermi level energy E _{f in} the p ⁺ layer (Ec (p ⁺ ) and -E _f), n ^- in the layer, the conduction band edge energy Ec (n ^- is difference between) -E _f) -) and difference in Fermi level Enrugi E _f ^(Ec (n. Therefore, the p ⁺ n ⁻ junction has a _built-in potential eV _built-in (p ⁺ / n) corresponding to {(Ec (p ⁺ ) −E _f ) − (Ec (n ⁻ ) −E _f )}. ^- ) Has been generated. Further, even in an n ⁻ p ⁺ junction of the n ⁻ layer / p ⁺ layer, a built-in potential eV _built corresponding to {(Ec (p ⁺ ) −E _f ) − (Ec (n ⁻ ) −E _f )}) _-in ⁽ⁿ - / p ⁺⁾ is generated. n ^- layer / p ⁺ layer / n ^- the layer / n ⁺ structure of the substrate, when a positive voltage is applied, p ⁺ layer / n ^- layer / n ⁺ substrate portion p ⁺ n ^- The junction forward bias On the other hand, a reverse bias is applied to the n ⁻ p ⁺ junction of the n ⁻ layer / p ⁺ layer portion. Since the reverse current flowing through the n ⁻ p ⁺ junction of the n ⁻ layer / p ⁺ layer portion is limited, injection of electrons from the n-type conductive substrate 1 to the first nitride semiconductor layer 3 is prevented. Is done.

Alternatively, the fourth nitride semiconductor layer that forms an energy barrier against electrons is insulative and has a difference in conduction band edge energy Ec with respect to the conductive substrate, that is, the conduction band edge energy Ec (Sub of the substrate). ) And the difference between the conduction band edge energies Ec (S3) of the fourth nitride semiconductor layer, ΔEc (Sub / S3) can be selected. As the fourth nitride semiconductor layer, for example, an insulating nitride semiconductor layer that satisfies the condition of 0.77 eV> ΔEc (Sub / S3)> 3 kT eV can be used. In this case, the structure of the substrate / buffer layer / fourth nitride semiconductor layer / first nitride semiconductor layer exhibits N ⁺ / n / i / n conductivity, for example. That is, an n-i-n type tunnel diode structure is formed, and the fourth nitride semiconductor layer functions as an energy barrier against electrons.

  In addition, when the conductive substrate 1 is a p-type conductive substrate, the fourth nitride semiconductor layer 12 is a barrier layer that serves as an energy barrier against carriers (holes) in the conductive substrate 1. Function as.

When the buffer layer 2 and the first nitride semiconductor layer 3 of the channel layer are layers made of an n ⁻ type nitride semiconductor, when a positive drain voltage V _ds is applied to the drain electrode 7, the channel layer A positive bias is applied between the first nitride semiconductor layer 3 and the source electrode 6. Therefore, a positive bias is also applied between the first nitride semiconductor layer 3 of the channel layer and the p-type conductive electrode 1.

The fourth nitride semiconductor layer 12, which is a barrier layer functioning as an energy barrier against holes, is, for example, insulative, and energy caused by band discontinuity ΔEv of the conduction band at the interface with the buffer layer 2. A layer made of a nitride semiconductor having a large band gap energy Eg is used to form a barrier. At that time, the first nitride semiconductor layer 3 / the fourth nitride semiconductor layer 12 / first nitride semiconductor layer 3 / substrate, n ^- layer / p ⁺ structure of the substrate ^- layer / I layer / n Therefore, the injection of holes from the p-type conductive substrate 1 to the first nitride semiconductor layer 3 is prevented.

Therefore, in the field effect transistor of the third embodiment of the present invention having the structure shown in FIG. 15, when a high drain voltage V _ds is applied to the drain electrode 7, the conductive substrate 1 _conducts in the “OFF state”. Injection of carriers (electrons or holes) beyond the fourth nitride semiconductor layer 12, which is a barrier layer serving as an energy barrier against carriers (electrons or holes) in the conductive substrate 1, is prevented.

For example, in the n ⁻ p ⁺ junction of the n ⁻ layer / p ⁺ substrate, the difference (Ec (p ⁺ ) −E _f ) between the conduction band edge energy Ec (p ⁺ ) and the Fermi level energy L _{f in} the p ⁺ substrate. ) And the difference between the conduction band edge energy Ec (n ⁻ ) and the Fermi level energy L _f (Ec (n ⁻ ) −E _f ) in the n ⁻ layer. Therefore, the n ⁻ p ⁺ junction has a _built-in potential eV _built-in (n ⁻ / p corresponding to {(Ec (p ⁺ ) −E _f ) − (Ec (n ⁻ ) −E _f )}). ⁺ ) Has been generated. Further, the n ⁻ layer / I layer / n ⁻ layer portion constitutes a structure corresponding to a tunnel diode. When a positive voltage is applied to the structure of the n ⁻ layer / I layer / n ⁻ layer / p ⁺ substrate, a forward bias is applied to the n ⁻ p ⁺ junction of the n ⁻ layer / p ⁺ substrate, and the remaining voltage Is applied to the n ⁻ layer / I layer / n ⁻ layer portion. Since the reverse current flowing through the n ⁻ p ⁺ junction of the n ⁻ layer / p ⁺ layer portion is limited, the injection of holes from the p-type conductive substrate 1 to the first nitride semiconductor layer 3 is Is prevented.

In the field effect transistor according to the third embodiment of the present invention having the structure shown in FIG. 15, the conductive substrate 1 is set to the same potential as the source electrode 6, so that a high drain voltage V _ds is applied to the drain electrode 7. The electric fields formed in the second nitride semiconductor layer 4 and the first nitride semiconductor layer 3 are distributed not only in the horizontal direction in which the gate electrode 8 is located but also in the vertical direction. As a result, an effect of reducing the concentration of the electric field near the drain end of the gate electrode 8 can be obtained.

  When a lateral field effect transistor using a high-resistance substrate is operated at a high voltage, the potential of the channel layer varies due to the trapping of electrons in the deep level existing in the channel layer, and An increase in on-resistance is often observed due to the accompanying channel constriction. On the other hand, in the field effect transistor of the third embodiment of the present invention having the structure shown in FIG. 15, the potential of the conductive substrate is equal to the potential of the source electrode, and further, an energy barrier against carriers (electrons or holes). Therefore, even if electrons or holes are trapped in deep levels existing in the channel layer, the potential of the channel layer itself does not vary greatly. Accordingly, in the field effect transistor according to the third embodiment of the present invention having the structure shown in FIG. 15, an increase in on-resistance due to a change in the potential of the channel layer and the accompanying channel constriction can be avoided.

(Fifth embodiment)
FIG. 15 is a cross-sectional view schematically showing the device structure of the field effect transistor of the fifth embodiment. The field effect transistor of the fifth embodiment has a structure described below.

  As the substrate 1, an n-type conductive Si substrate is used. For example, the buffer layer 2, the fourth nitride semiconductor layer 12, the first nitride semiconductor layer 3, and the second nitride semiconductor layer 4 grown on the (111) plane n-type Si substrate and grown on the (0001) plane. The third nitride semiconductor layer 5 is sequentially formed by epitaxial growth.

On the (111) plane n-type Si substrate, for example, as a nucleation layer, an AlN buffer layer having a film thickness of 4 nm and subsequently an AlGaN / GaN periodic layer of 1000 nm are formed, and this AlN buffer layer and an AlGaN / GaN periodic layer are formed, Used as the buffer layer 2. On the AlGaN / GaN periodic layer, a p ⁺ -AlGaN layer having a thickness of 40 nm made of Zn-doped Al _0.20 Ga _0.80 N (Al composition 0.20) is formed as the fourth nitride semiconductor layer 12. The Zn concentration added to the p ⁺ -AlGaN layer used for this barrier layer is selected to be 10 ¹⁹ cm ⁻³ . A GaN layer having a thickness of 1000 nm is formed as the first nitride semiconductor layer 3, and an AlGaN layer having a thickness of 30 nm made of Al _0.20 Ga _0.80 N (Al composition 0.20) is formed as the second nitride semiconductor layer 4. . Further, as the third nitride semiconductor layer 5, a p ⁺ -AlGaN layer having a thickness of 30 nm made of Zn-doped Al _0.20 Ga _0.80 N (Al composition 0.20) is formed. The Zn concentration added to this p ⁺ -AlGaN layer is also selected to be 10 ¹⁹ cm ⁻³ .

The drain electrode region is covered with a resist, and the third nitride semiconductor layer 5 in other regions is removed by etching. For the selective etching of the p ⁺ -AlGaN layer, ICP plasma mainly composed of boron trichloride (BCl ₃ ) gas is used.

As the source electrode 6 formed on the surface of the exposed AlGaN layer, Ti and Al metal are formed by vapor deposition and a lift-off process. As the drain electrode 7 formed on the surface of the p ⁺ -AlGaN layer, Ni and Au metals are formed by vapor deposition and a lift-off process. An ohmic contact is formed by heat treatment at 650 ° C. in a nitrogen atmosphere.

Element isolation is performed by nitrogen ion implantation. As the nitrogen ion implantation conditions, an acceleration voltage of 100 kV and an implantation density of 4 × 10 ¹⁴ cm ⁻² are selected using a resist film having a thickness of 1 μm as a mask. After element isolation, a 200 nm SiN film is formed by plasma CVD. An opening for forming a recess is formed in the SiN film. The SiN film in the recess portion is removed using ICP plasma whose opening width is 2.0 μm and whose main component is sulfur hexafluoride (SF ₆ ) gas. The AlGaN layer exposed in the opening of the SiN film is etched away by 20 nm using ICP plasma mainly composed of boron trichloride (BCl ₃ ) gas to form a recess. Therefore, immediately below the recess portion, the thickness of the AlGaN layer is 10 nm.

  Thereafter, as the gate insulating film, a SiN film is formed to a thickness of 20 nm, for example, by plasma CVD. The thickness of the SiN film covering the side wall of the recess is 20 nm. Since the depth of the recess portion is 20 nm and the thickness of the SiN film is 20 nm, the surface of the SiN film covering the bottom surface of the recess portion and the surface of the AlGaN layer other than the recess portion are located at the same level. .

  The gate electrode 8 is formed by evaporating and lifting off, for example, Ni 20 nm and Au 200 nm. At that time, the gate electrode 8 formed so as to be embedded in the recess portion through the gate insulating film has a gate length corresponding to (2.0 μm−2 × 20 nm).

  The width of the electrode formed by lift-off is selected to be 2.0 μm. Therefore, the surface of the AlGaN layer other than the recess is not covered with this electrode. That is, no structure corresponding to the field plate electrode is provided on the drain electrode 7 side of the recess.

  The width from the end of the recess portion on the drain electrode 7 side to the end of the third nitride semiconductor layer 5 on the gate electrode side is selected to be 10 μm. The width of the third nitride semiconductor layer 5 itself is selected to be 100 μm. The width from the end of the recess portion on the drain electrode 7 side to the end of the drain electrode 7 on the gate electrode side is selected to be 15 μm. On the other hand, the width from the end of the recess portion on the source electrode 6 side to the end of the source electrode 6 on the gate electrode side is selected to be 1 μm.

  On the bottom surface of the recess portion, the ratio of the thickness of the AlGaN layer immediately below the gate electrode 8 to the gate length is (2.0 μm−2 × 20 nm) / 10 nm.

Further, the following via-hole connection is used for the connection between the n-type conductive Si substrate 1 and the source electrode 6. An ICP plasma mainly composed of sulfur hexafluoride (SF ₆ ) gas is formed from the back surface of the n-type Si substrate 1 toward the source electrode 6 through a through hole having a diameter of 80 μm. Via holes are connected to the through holes having a diameter of 80 μm and a depth of 200 μm by plating with Au.

  On the back surface of the n-type Si substrate 1, an ohmic back electrode made of Ti / Al is formed. Further, the substrate 1, the buffer layer 2, the fourth nitride semiconductor layer 12, the first nitride semiconductor layer 3, the second nitride semiconductor layer 4, and the third nitride semiconductor are formed on the side wall surface of the through hole. The side end surface of the layer 5 is exposed. Au plating film, substrate 1, buffer layer 2, fourth nitride semiconductor layer 12, first nitride semiconductor layer 3, second nitride semiconductor layer 4, third nitride semiconductor layer 5 side In order to prevent the end surface from being in direct electrical contact, a structure in which the side wall surface of the through hole is covered with a Ti / Pt / Au film formed by a sputtering method is employed.

  For comparison, the field effect transistor according to the first embodiment of the present invention having the structure illustrated in FIG. 1 is manufactured by the following procedure.

The field effect transistor according to the first embodiment of the present invention having the structure illustrated in FIG. 1 has a structure in which the following points are changed with respect to the field effect transistor according to the fifth embodiment. As the substrate 1, a (111) plane high-resistance Si substrate is used instead of the (111) plane n-type Si substrate. Further, the p ⁺ -AlGaN layer made of Zn-doped Al _0.20 Ga _0.80 N (Al composition 0.20) and having a thickness of 40 nm is not used as the fourth nitride semiconductor layer 12. Therefore, the first nitride semiconductor layer 3 is formed on the surface of the substrate 1 via the buffer layer 2.

  Note that the back surface of the high-resistance Si substrate and the source electrode 6 are via-hole connected in the same manner as the field effect transistor of the fifth embodiment. That is, a back electrode is provided on the back surface of the high-resistance Si substrate and is electrically connected to the source electrode 6 so as to have the same potential.

  Contrast the drain-stress voltage dependence of on-resistance measured for the field-effect transistor of the fifth embodiment and the field-effect transistor of the first embodiment of the present invention having the structure of FIG. As shown in FIG.

This drain resistance stress voltage measurement of on-resistance is carried out under the following conditions. In the “OFF state” where the gate voltage V _gs = 0 V, a pulse-like drain stress voltage having a pulse width (stress time) of 20 msec is applied as the drain voltage V _ds to the drain electrode 7 with a repetition period of 100 msec for a total of 1 sec. Apply. Thereafter, the on-resistance, the "ON state" of the gate voltage V _gs = 8V, the drain voltage V _ds = 10V, from the measured value of the drain current density I _d (A / mm), as [Delta] V _ds / [Delta] I _d, is calculated To do.

  The field effect transistor according to the first embodiment of the present invention having the structure shown in FIG. 1 is turned on when the drain stress voltage exceeds 80 V under the above-described measurement condition of the drain stress voltage dependency of the on resistance. It shows a rapid increase in resistance. On the other hand, the field effect transistor of the fifth embodiment exhibits a rapid increase in on-resistance when the drain-stress voltage is in a range of 200 V or less under the above-described measurement condition of the drain-stress voltage dependence of on-resistance. Not shown.

The field effect transistor according to the fifth embodiment shown in FIG. 15 satisfies the two conditions required for the power control device: a high drain current density and a low gate current density when a positive gate voltage of 10 V is applied. Further, in the “OFF state” where the gate voltage V _gs = 0V, even when a high drain stress voltage of 200 V is applied, the ON resistance in the “ON state” is kept low. Therefore, even when a high voltage operation is performed using a high drain voltage V _ds , it can be used as a power control device capable of low loss operation.

  In the field effect transistor of the fifth embodiment, an n-type conductive (111) plane Si substrate is used as a substrate, and a (0001) plane grown III-nitride epitaxial film is used thereon. , Making devices. A (0001) -plane-grown III nitride epitaxial film can be formed on the surface, and if it is an n-type conductive substrate, an SiC n-type conductive substrate instead of the (111) -plane n-type Si substrate ZrB n-type conductive substrate or the like can be used.

Further, when a p-type conductive substrate is used instead of the n-type conductive substrate, the fourth nitride semiconductor layer 12 is made of Zn-doped Al _0.20 Ga _0.80 N (Al composition 0.20). By using an Al _0.30 Ga _0.70 N (Al composition 0.30) layer having a thickness of 40 nm instead of the p ⁺ -AlGaN layer having a thickness of 40 nm, equivalent characteristics can be achieved. At that time, a (0001) plane-grown group III nitride epitaxial film can be formed on the surface, and a p-type Si substrate, a p-type conductive substrate of SiC, if it is a low-resistance p-type conductive substrate, A ZrB p-type conductive substrate or the like can also be used.

  The present invention can be used to manufacture a normally-off type field effect transistor applicable to a power control device.

It is sectional drawing which shows typically the structure of the field effect transistor of the 1st form of this invention. In the field effect transistor of the 1st form of this invention, it is a figure which shows typically the energy band figure of the drain electrode vicinity. In the field effect transistor according to the first aspect of the present invention, when a gate voltage V _gs = 0 V and a drain voltage V _ds = 100 V are applied, a lateral potential distribution, an electron / hole distribution formed inside the transistor, and It is sectional drawing which shows hole concentration distribution typically. It is sectional drawing which shows typically the structure of the field effect transistor of 1st Embodiment concerning this invention. It is sectional drawing which shows typically the structure of the conventional MIS type | mold normally-off and a field effect transistor. It is sectional drawing which shows typically the structure of the conventional p ^<+> gate * normally * off * field effect transistor. Dependence of drain current on gate voltage (I _d − in the field effect transistor according to the first embodiment of the present invention, the conventional MIS type normally-off field-effect transistor, and the p ⁺ gate, normally-off, field-effect transistor ₎ It is a figure which compares and shows ( _Vgs characteristic). In the field effect transistor according to the first embodiment of the present invention, the conventional MIS type normally-off / field-effect transistor, and p ⁺ gate / normally-off / field-effect transistor, the dependence of the gate current on the gate voltage (gate FIG. 6 is a diagram showing a comparison of leakage current characteristics). It is sectional drawing which shows typically the structure of the field effect transistor of 2nd Embodiment concerning this invention. It is sectional drawing which shows typically the structure of the field effect transistor of 3rd Embodiment concerning this invention. It is the top view and sectional drawing which show typically the characteristic structure of the field effect transistor of the 2nd form of this invention. In the field effect transistor of the 2nd form of this invention, it is a figure which shows typically the energy band figure of the drain electrode vicinity of the characteristic structure. It is sectional drawing which shows typically the structure of the field effect transistor of 4th Embodiment concerning this invention. Drain current-drain voltage characteristics (I _d -V _ds characteristics) in the field effect transistor according to the first embodiment of the present invention and the field effect transistor according to the fourth embodiment having the structure shown in FIG. It is a figure which compares and shows. It is sectional drawing which shows typically the structure of the field effect transistor of the 3rd form of this invention. Deterioration characteristics of on-resistance due to application of drain stress voltage in the field effect transistor of the first embodiment according to the present invention and the field effect transistor of the fifth embodiment according to the present invention having the structure shown in FIG. It is a figure which compares and shows.

Explanation of symbols

1 ... Substrate (SiC, sapphire, Si, etc.)
2 ... buffer layer 3 ... first nitride semiconductor layer 4 ... second nitride semiconductor layer 5 ... third nitride semiconductor layer 6 ... source electrode 7 ... drain electrode 8 ... gate electrode 9 ... insulating film 10 ... positive Hole 11 ... Electron 12 ... Fourth nitride semiconductor layer

Claims (19)

In a normally-off type nitride semiconductor transistor in which electrons are carriers that run in the channel region directly under the gate electrode,
The nitride semiconductor transistor is
A field effect transistor having a MIS structure in which an insulating film is inserted at an interface between a gate electrode and a nitride semiconductor;
substrate,
A buffer layer formed by growth on the substrate;
Formed by epitaxial growth on the buffer layer;
A first nitride semiconductor layer on which carriers travel;
A second nitride semiconductor layer for supplying electrons;
A third nitride semiconductor layer having p-type conductivity is disposed only in the drain electrode and its peripheral region,
The drain electrode is in ohmic contact with the third nitride semiconductor layer having p-type conductivity,
The transistor is characterized in that the source electrode is in ohmic contact with the second nitride semiconductor layer that supplies electrons. In a normally-off type nitride semiconductor transistor in which electrons are carriers that run in the channel region directly under the gate electrode,
The nitride semiconductor transistor is
A field effect transistor having a MIS structure in which an insulating film is inserted at an interface between a gate electrode and a nitride semiconductor;
substrate,
A buffer layer formed by growth on the substrate;
Formed by epitaxial growth on the buffer layer;
A first nitride semiconductor layer on which carriers travel;
A second nitride semiconductor layer for supplying electrons;
A third nitride semiconductor layer having p-type conductivity is disposed on the drain electrode and a part of its peripheral region;
The drain electrode is in contact with the third nitride semiconductor layer having p-type conductivity and the second nitride semiconductor layer supplying electrons,
The nitride semiconductor transistor, wherein the source electrode is in ohmic contact with the second nitride semiconductor layer that supplies electrons. In a normally-off type nitride semiconductor transistor in which electrons are carriers that run in the channel region directly under the gate electrode,
The nitride semiconductor transistor is
A field effect transistor having a MIS structure in which an insulating film is inserted at an interface between a gate electrode and a nitride semiconductor;
Conductive substrate,
A buffer layer formed by growth on the conductive substrate;
Formed by epitaxial growth on the buffer layer;
A fourth nitride semiconductor layer that forms an energy barrier against electrons or holes;
A first nitride semiconductor layer on which carriers travel;
A second nitride semiconductor layer for supplying electrons;
A third nitride semiconductor layer having p-type conductivity is disposed only in the drain electrode and its peripheral region,
The drain electrode is in ohmic contact with the third nitride semiconductor layer having p-type conductivity,
The source electrode is in ohmic contact with the second nitride semiconductor layer that supplies electrons,
A nitride semiconductor transistor, wherein a source electrode and a conductive substrate are electrically connected. The MIS structure in which an insulating film is inserted at the interface between the gate electrode and the nitride semiconductor is
An insulating film made of an insulating material and formed on the nitride semiconductor;
The nitride semiconductor transistor according to claim 1, comprising a gate electrode formed on the insulating film. The MIS structure in which an insulating film is inserted at the interface between the gate electrode and the nitride semiconductor is
An insulating film made of an insulating material, formed on the second nitride semiconductor layer;
The gate electrode is formed on the insulating film,
The second nitride semiconductor layer disposed under the gate electrode has a fluorine atom-containing region to which fluorine atoms are added,
4. The fluorine atom-containing region of the second nitride semiconductor layer includes a fluorine atom having a surface density of about 1 × 10 ¹³ cm ⁻² . 5. Nitride semiconductor transistor. The MIS structure in which an insulating film is inserted at the interface between the gate electrode and the nitride semiconductor is
An undoped nitride semiconductor layer selectively grown on a portion of the second nitride semiconductor layer immediately below the gate electrode;
An insulating film formed of an insulating material so as to cover the surface of the undoped nitride semiconductor layer;
The gate electrode is formed on the insulating film,
4. The nitride semiconductor according to claim 1, wherein negative polarization charges are generated at an interface between the second nitride semiconductor layer and the undoped nitride semiconductor layer. 5. Transistor. The third nitride semiconductor layer having p-type conductivity is formed on the surface of the second nitride semiconductor layer that supplies electrons,
The junction between the third nitride semiconductor layer having the p-type conductivity and the second nitride semiconductor layer constitutes a p ⁺ n junction or a p ⁺ i junction. The nitride semiconductor transistor as described in any one of -6. The second nitride semiconductor layer that supplies electrons is formed on the surface of the first nitride semiconductor layer in which carriers travel,
8. The junction surface between the second nitride semiconductor layer that supplies electrons and the first nitride semiconductor layer in which carriers travel forms a heterojunction interface. The nitride semiconductor transistor according to one item. A fourth nitride semiconductor layer that forms an energy barrier against electrons or holes is formed on the surface of the buffer layer;
The first nitride semiconductor layer in which carriers travel is formed on the surface of the fourth nitride semiconductor layer,
In the stacked structure of the first nitride semiconductor layer / the fourth nitride semiconductor layer / the buffer layer,
The fourth nitride semiconductor layer is
An energy barrier is formed in an injection path from the buffer layer to the first nitride semiconductor layer for electrons and holes, which are carriers that determine conductivity in the conductive substrate. Item 4. The nitride semiconductor transistor according to Item 3. The conductive substrate is an n-type conductive substrate,
The nitride semiconductor transistor according to claim 3 or 9, wherein the fourth nitride semiconductor layer forming an energy barrier against electrons or holes is a nitride semiconductor layer forming an energy barrier against electrons. The conductive substrate is a p-type conductive substrate,
The nitride semiconductor transistor according to claim 3 or 9, wherein the fourth nitride semiconductor layer forming an energy barrier against electrons or holes is a nitride semiconductor layer forming an energy barrier against holes. . A back electrode is formed on the back surface of the conductive substrate,
11. The nitride semiconductor transistor according to claim 3, wherein the source electrode is electrically connected to the back electrode of the conductive substrate. The nitride semiconductor transistor according to claim 1, wherein the substrate is a high resistance substrate. The drain electrode is in ohmic contact with the third nitride semiconductor layer having p-type conductivity,
3. The nitride semiconductor transistor according to claim 2, wherein the drain electrode is in contact with the second nitride semiconductor layer that supplies electrons to form a Schottky junction. The third nitride semiconductor layer having p-type conductivity is formed on the surface of the second nitride semiconductor layer that supplies electrons,
The second nitride semiconductor layer that supplies electrons is formed on the surface of the first nitride semiconductor layer in which carriers travel,
The stacked structure of the third nitride semiconductor layer / second nitride semiconductor layer / first nitride semiconductor layer having p-type conductivity constitutes a p ⁺ n junction or a p ⁺ in junction. ,
8. The nitride semiconductor transistor according to claim 7, wherein the built-in potential formed by the p ⁺ n junction or the p ⁺ in junction is in the range of 1.76 eV to 5.0 eV. The barrier height of the Schottky junction formed by the contact between the drain electrode and the second nitride semiconductor layer for supplying electrons is in the range of 0.3 eV to 1.5 eV. The nitride semiconductor transistor described in 1. In the heterojunction interface formed at the junction surface between the second nitride semiconductor layer that supplies electrons and the first nitride semiconductor layer in which carriers travel,
Due to the discontinuity of the conduction band edge energy between the second nitride semiconductor layer and the first nitride semiconductor layer, a potential barrier is formed in the conduction band,
9. The nitride semiconductor transistor according to claim 8, wherein a potential barrier formed in the conduction band at the heterojunction interface is in a range of 0.13 eV to 0.77 eV. In the heterojunction interface formed at the junction surface between the second nitride semiconductor layer that supplies electrons and the first nitride semiconductor layer in which carriers travel,
Due to the discontinuity of the valence band edge energy between the second nitride semiconductor layer and the first nitride semiconductor layer, a potential barrier is formed in the valence band,
The nitride semiconductor transistor according to claim 8, wherein a potential barrier formed in a valence band at the heterojunction interface is in a range of 0.05 eV to 0.33 eV. A nitride semiconductor layer formed by epitaxial growth on a substrate is
The nitride semiconductor transistor according to claim 1, wherein the nitride semiconductor transistor is grown in (0001) plane.