JP5287111B2 - Display device, driving method thereof, and electronic apparatus - Google Patents

Display device, driving method thereof, and electronic apparatus Download PDF

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JP5287111B2
JP5287111B2 JP2008259166A JP2008259166A JP5287111B2 JP 5287111 B2 JP5287111 B2 JP 5287111B2 JP 2008259166 A JP2008259166 A JP 2008259166A JP 2008259166 A JP2008259166 A JP 2008259166A JP 5287111 B2 JP5287111 B2 JP 5287111B2
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signal
potential
power supply
scanning
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JP2009139928A5 (en
JP2009139928A (en
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哲郎 山本
勝秀 内野
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ソニー株式会社
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  The present invention relates to an active matrix display device using a light emitting element for a pixel and a driving method thereof. Further, the present invention relates to an electronic device provided with such a display device.

  In recent years, development of flat self-luminous display devices using organic EL devices as light-emitting elements has become active. An organic EL device is a device that utilizes the phenomenon of light emission when an electric field is applied to an organic thin film. Since the organic EL device is driven at an applied voltage of 10 V or less, it has low power consumption. In addition, since the organic EL device is a self-luminous element that emits light, it does not require an illumination member and can be easily reduced in weight and thickness. Furthermore, since the response speed of the organic EL device is as high as several μs, an afterimage does not occur when displaying a moving image.

Among planar self-luminous display devices that use organic EL devices as pixels, active matrix display devices in which thin film transistors are integrated and formed as driving elements in each pixel are particularly active. Active matrix type flat self-luminous display devices are described in, for example, Patent Documents 1 to 5 below.
JP 2003-255856 A JP 2003-271095 A JP 2004-133240 A JP 2004-029791 A JP 2004-093682 A

  FIG. 23 is a schematic circuit diagram showing an example of a conventional active matrix display device. The display device includes a pixel array unit 1 and peripheral driving units. The drive unit includes a horizontal selector 3 and a write scanner 4. The pixel array unit 1 includes columnar signal lines SL and row-shaped scanning lines WS. Pixels 2 are arranged at the intersections between the signal lines SL and the scanning lines WS. In the figure, only one pixel 2 is shown for easy understanding. The write scanner 4 includes a shift register, operates in response to an externally supplied clock signal ck, and sequentially transfers start pulses sp supplied from the outside, thereby sequentially outputting control signals to the scanning lines WS. . The horizontal selector 3 supplies a video signal to the signal line SL in accordance with the line sequential scanning on the write scanner 4 side.

  The pixel 2 includes a sampling transistor T1, a driving transistor T2, a storage capacitor C1, and a light emitting element EL. The driving transistor T2 is a P-channel type, and the source which is one current end thereof is connected to the power supply line, and the drain which is the other current end is connected to the light emitting element EL. The gate which is the control end of the driving transistor T2 is connected to the signal line SL via the sampling transistor T1. The sampling transistor T1 is turned on in response to the control signal supplied from the write scanner 4, samples the video signal supplied from the signal line SL, and writes it to the holding capacitor C1. The driving transistor T2 receives the video signal written in the storage capacitor C1 as the gate voltage Vgs at the gate thereof, and causes the drain current Ids to flow through the light emitting element EL. As a result, the light emitting element EL emits light with a luminance corresponding to the video signal. The gate voltage Vgs represents the gate potential with reference to the source.

The driving transistor T2 operates in the saturation region, and the relationship between the gate voltage Vgs and the drain current Ids is expressed by the following characteristic equation (1).
Ids = (1/2) μ (W / L) Cox (Vgs−Vth) 2 (1 )
Here, μ is the mobility of the driving transistor, W is the channel width of the driving transistor, L is the channel length, Cox is the gate insulating film capacitance per unit area, and Vth is the threshold voltage. As is apparent from this characteristic equation, when the driving transistor T2 operates in the saturation region, it functions as a constant current source that supplies the drain current Ids according to the gate voltage Vgs.

  FIG. 24 is a graph showing voltage / current characteristics of the light emitting element EL. The horizontal axis represents the anode voltage V, and the vertical axis represents the drive current Ids. The anode voltage of the light emitting element EL is the drain voltage of the driving transistor T2. In the light emitting element EL, the current / voltage characteristics change with time, and the characteristic curve tends to fall with time. For this reason, the anode voltage (drain voltage) V changes even if the drive current Ids is constant. In that respect, the pixel circuit 2 shown in FIG. 23 operates in the saturation region of the driving transistor T2, and can drive the driving current Ids according to the voltage Vgs at the gate regardless of the fluctuation of the drain voltage. It is possible to keep the light emission luminance constant regardless of the change in the characteristics over time.

  FIG. 25 is a circuit diagram showing another example of a conventional pixel circuit. A difference from the pixel circuit shown in FIG. 23 is that the driving transistor T2 is changed from the P-channel type to the N-channel type. In the circuit manufacturing process, it is often advantageous to make all the transistors constituting the pixel N-channel type.

  The display panel has been increased in definition and size, and the number of scanning lines has exceeded 1,000. A light scanner that scans a large number of scanning lines line-sequentially has also been increased in size. In recent years, so-called block driving has been developed along with the increase in the size of the display panel and the driving unit. In this case, the drive unit of the display device divides the scanning lines into blocks for each predetermined number, blocks sequential driving for sequentially driving the matrix pixels in units of blocks, and scans the scanning lines within each block. Line sequential driving for sequentially driving the pixels in units of rows is performed, and an image is displayed on the panel.

  In the conventional block drive, there is a problem that a luminance difference occurs due to a difference in operating conditions between pixel rows located at the boundary between adjacent blocks, and the uniformity of the screen is impaired. In the pair of blocks, the last pixel row of the preceding block is scanned line-sequentially at that block. On the other hand, the first pixel row of the succeeding block is first line-sequentially scanned. Although the last row pixel of the preceding block and the first pixel row of the succeeding block are adjacent to each other, when viewed from the driving conditions, the order of line sequential scanning is the last and first, and the temporal driving conditions are This is extremely different, and this appears as a subtle difference in luminance between the two pixel rows, which causes a reduction in the uniformity of the screen.

  In view of the above-described problems of the conventional technology, an object of the present invention is to improve screen uniformity in a block drive type display device. In order to achieve this purpose, the following measures were taken. That is, the present invention relates to a pixel array including scanning lines arranged in rows, signal lines arranged in columns, and matrix-like pixels arranged in a portion where each scanning line and each signal line intersect. And a drive unit that drives each pixel via the scan line and the signal line, the drive unit divides the scan line into blocks for each predetermined number, and blocks matrix pixels Block sequential driving for sequentially driving in units and line sequential driving for scanning each scanning line and sequentially driving pixels in units of rows in each block are performed. As a feature, control is performed so that the scanning directions of the line-sequential driving are reversed between adjacent blocks.

  In one aspect, the driving unit includes a signal selector that supplies a video signal having a signal potential corresponding to a gradation and a predetermined reference potential to a columnar signal line, and a light that sequentially supplies a control signal to the row scanning line. A scanner and a drive scanner for supplying a power supply voltage that switches between a high potential and a low potential to a power supply line arranged in parallel with each scanning line, and the pixel has one current terminal connected to a signal line and controlled A sampling transistor whose end is connected to the scanning line, a driving transistor whose drain-side current terminal is connected to the power supply line and whose gate is the control terminal is connected to the other current terminal of the sampling transistor, and the driving transistor A light emitting element connected to a current end on a source side of the transistor and a storage capacitor connected between a source and a gate of the driving transistor; A predetermined number of lines are grouped into blocks, the phase is shifted sequentially in block units, and the high potential and low potential are switched to perform block sequential driving, and the potential of a predetermined number of power supply lines is switched in the same phase within the block, The write scanner performs line-sequential driving for sequentially supplying a control signal to each scanning line for each horizontal period within each block, and controls the scanning direction of the line-sequential driving to be opposite to each other between adjacent blocks. . Preferably, in the block sequential driving, the power supply scanner simultaneously switches each power supply line from a high potential to a low potential to lower the source voltage of the driving transistor, and then simultaneously changes each power supply line from a low potential to a high potential. On the other hand, the write scanner supplies a control signal to each scanning line to turn on the sampling transistor and turn on the source of the driving transistor when the signal line is at the reference potential in line sequential driving. The voltage is increased, and a correction operation is performed to discharge the storage capacitor so that the voltage between the gate and the source of the driving transistor is directed to the threshold voltage. In the line-sequential drive, when the signal line is at a signal potential, the write scanner performs a writing operation of supplying a control signal to each scanning line, turning on the sampling transistor, and writing the signal potential to the storage capacitor. The signal selector reverses the order of signal potentials supplied to each signal line between adjacent blocks. The power scanner includes a plurality of gate drivers divided corresponding to each block.

  In another aspect, each pixel includes at least a sampling transistor, a driving transistor, a storage capacitor, and a light emitting element, and the sampling transistor has a control end connected to the scanning line, A current end is connected between the signal line and a control end of the driving transistor, and the driving transistor has one of a pair of current ends connected to the light emitting element, the other connected to a power source, and the holding The capacitor is connected between the control terminal and the current terminal of the driving transistor, and the driving unit supplies at least a write scanner for supplying a control signal to each scanning line, and a signal potential and a reference potential for each signal line. A switching signal to be supplied, and the sampling transistor performs a threshold voltage correction operation according to a control signal supplied to the scanning line when the signal line is at a reference potential, A voltage corresponding to the threshold voltage of the driving transistor is written to the storage capacitor, and when the signal line is at the signal potential, a signal potential writing operation is performed in accordance with a control signal supplied to the scanning line, and the signal line The signal potential is sampled and written to the storage capacitor, and the driving transistor supplies the light emitting element with a driving current corresponding to the signal potential written to the storage capacitor to emit light. The scanning line is divided into blocks for each number, and the scanning period assigned to each of the predetermined number of scanning lines is combined into one combined period divided into a first period and a second period. In addition, each block is sequentially selected for each synthesis period to drive the pixel array block sequentially, and in the first period of each synthesis period, one block is assigned to a predetermined number of scanning lines belonging to one block. , A threshold voltage correction operation is executed for each block, and in the second period, a control signal is sequentially output to a predetermined number of scanning lines belonging to one block to perform line sequential driving. Then, the signal potential writing operation is sequentially executed for each row of pixels, and in the adjacent blocks, the control directions are sequentially output to the respective scanning lines to reverse the scanning directions in which the line sequential driving is performed. Preferably, the write scanner includes a plurality of gate drivers divided corresponding to each block. In addition, pixels belonging to adjacent rows between adjacent blocks have the same time from the completion of the threshold voltage correction operation to the start of the signal potential writing operation.

  According to the present invention, control is performed so that the scanning directions of line sequential driving are opposite to each other between adjacent blocks. This minimizes the difference in operating conditions between pixel rows located at the boundary between adjacent blocks and does not cause a difference in luminance, so that the uniformity of the screen can be improved. In the pair of blocks, the last pixel row of the preceding block is scanned line-sequentially at that block. On the other hand, the first pixel row of the succeeding block is also scanned line-sequentially. This is because control is performed so that the scanning directions of line-sequential driving are opposite to each other between adjacent blocks. The last row pixel of the preceding block and the first pixel row of the succeeding block that are adjacent to each other are both row-sequentially scanned, and the temporal driving conditions are the same, and the difference in luminance between the two pixel rows is It does not occur and the uniformity of the screen can be improved.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing the overall configuration of the first embodiment of the display device of the present invention. As shown in the figure, the display device includes a pixel array section 1 and driving sections (3, 4, 5) for driving the pixel array section 1. The pixel array unit 1 includes a row-like scanning line WS, a column-like signal line SL, a matrix-like pixel 2 arranged at a portion where both intersect, and a power source arranged corresponding to each row of each pixel 2 And a feeder line DS which is a line. The drive unit (3, 4, 5) supplies a control signal to each scanning line WS sequentially to scan the pixels 2 line-sequentially in units of rows, and a control scanner (write scanner) 4 in accordance with this line-sequential scanning. A power supply scanner (drive scanner) 5 that supplies a power supply voltage to be switched between a high potential and a low potential to each power supply line DS, and a signal potential and a reference potential that become video signals on the column-shaped signal lines SL in accordance with the line sequential scanning. And a signal selector (horizontal selector) 3 for supplying. The write scanner 4 operates in response to a clock signal WSck supplied from the outside, and sequentially transfers start pulses WSsp supplied from the outside, thereby outputting a control signal to each scanning line WS. The drive scanner 5 operates in response to a clock signal DSck supplied from outside, and sequentially transfers start pulses DSsp supplied from the outside, thereby switching the potential of the power supply line DS line-sequentially.

  In the first embodiment, the drive scanner 5 collectively blocks a predetermined number of row power supply lines DS, switches the phase between the blocks in order, and switches between the high potential Vcc and the low potential Vss. Then, the potentials of a predetermined number of feeder lines DS are switched at the same phase. In the example shown in the figure, the drive scanner 5 collects two row power supply lines DS into blocks, switches the phase sequentially in units of blocks, and switches between a high potential and a low potential, and 2 at the same phase in the block. The potential of the power supply line DS is switched. However, in the present invention, the number of blocks to be blocked is not limited to two. In general, the drive timing of the power supply line (power supply line) DS is shared by a plurality of rows (a plurality of stages).

  The drive scanner 5 basically includes a shift register and an output buffer connected to each stage. The shift register operates in response to a clock signal DSck supplied from the outside, and sequentially outputs a start signal DSsp also supplied from the outside, thereby outputting a control signal that is a source of power source switching for each stage. . The output buffer switches the power supply line between a high potential and a low potential according to this control signal, and supplies the power supply line DS. In the present invention, the output buffer is shared among the plurality of power supply lines by sharing the control timing of the plurality of power supply lines. Thereby, the number of output buffers can be reduced. Since the output buffer supplies power to the power supply line DS, a large current driving capability is required, and the device size is large. By reducing the number of output buffers having a large device size, the circuit size of the peripheral driver can be reduced, the cost can be reduced, and the yield can be increased. For example, as in the example of FIG. 1, if one output buffer is shared by two power supply lines DS, the number of output buffers as a whole can be halved compared to the first embodiment. Further, if the control timings of the ten power supply lines DS are made common, the number of output buffers can be reduced to 1/10 of that of the first embodiment.

  FIG. 2 is a circuit diagram showing a specific configuration of the pixel 2 included in the display device shown in FIG. As shown in the figure, the pixel circuit 2 includes a two-terminal (diode type) light emitting element EL represented by an organic EL device, an N-channel sampling transistor T1, and an N-channel driving transistor T2. And a thin film type storage capacitor C1. The sampling transistor T1 has a gate that is a control end connected to the scanning line WS, a source and a drain that are a pair of current ends connected to the signal line SL, and the other connected to the gate G of the driving transistor T2. doing. One of the source and the drain of the driving transistor T2 is connected to the light emitting element EL, and the other is connected to the power supply line DS. In this embodiment, the driving transistor T2 is an N-channel type, and the drain side which is one current end thereof is connected to the power supply line DS, and the source S side which is the other current end is connected to the anode side of the light emitting element EL. Yes. The cathode of the light emitting element EL is fixed at a predetermined cathode potential Vcat. The storage capacitor C1 is connected between the source S that is the current end of the driving transistor T2 and the gate G that is the control end. For the pixel 2 having such a configuration, the control scanner (write scanner) 4 sequentially outputs a control signal by switching the scanning line WS between a low potential and a high potential, and the pixels 2 are line-sequentially in units of rows. Scan. A power supply scanner (drive scanner) 5 supplies a power supply voltage that is switched between a high potential Vcc and a low potential Vss to each power supply line DS in accordance with line sequential scanning. The signal selector (horizontal selector 3) supplies a signal potential Vsig and a reference potential Vofs that are video signals to the column-shaped signal lines SL in accordance with line sequential scanning.

  In such a configuration, when the power supply line DS is at the high potential Vcc and the signal line SL is Vofs, the light-emitting element EL is switched from the light-on state to the light-off state by turning on the sampling transistor T1 according to the control signal. I do. Subsequently, the feed line DS is switched from the high potential Vcc to the low potential Vss, and while the feed line DS is at the low potential Vss, the sampling transistor T1 is not turned on, the source voltage of the drive transistor T2 is lowered, and the gate G A preparatory operation for setting the source-to-source voltage Vgs to a voltage exceeding the threshold voltage Vth of the driving transistor T2 is performed. Thereafter, when the power supply line DS is returned from the low potential Vss to the high potential Vcc and the signal line SL is at the reference potential Vofs, the sampling transistor T1 is turned on according to the control signal to increase the source voltage of the driving transistor T2, and the gate A correction operation for discharging the storage capacitor C1 is performed so that the G-source S voltage Vgs is directed toward the threshold voltage Vth.

  According to the present invention, first, when the power supply line DS is at the high potential Vcc and the signal line SL is at the reference potential Vofs, the light-emitting element EL is switched off from the on state to the off state. Subsequently, the power supply line DS is switched to the low potential Vss, and the gate-source voltage Vgs of the driving transistor T2 is set to the threshold voltage Vth without turning on the sampling transistor T1 while the power supply line DS is at the low potential Vss. A preparatory operation for setting a large voltage is performed. Thereafter, when the power supply line DS is returned from the low potential Vss to the high potential Vcc and the signal line SL is at the reference potential Vofs, the sampling transistor T1 is turned on, and the gate-source voltage Vgs of the driving transistor T2 becomes the threshold voltage. A correction operation is performed to discharge the storage capacitor C1 toward Vth. In this manner, by performing the turn-off operation, the preparation operation, and the correction operation in order, the malfunction can be prevented and the threshold voltage of the driving transistor T2 can be corrected reliably and stably. In particular, in the preparatory operation, the source voltage of the driving transistor T2 is lowered without turning on the sampling transistor T1, thereby preventing malfunction of the pixel 2 and stabilizing the correction operation.

  FIG. 3A is a timing chart for explaining the operation of the first embodiment shown in FIG. In this timing chart, the power lines for three stages are controlled at a common timing. In the timing chart of FIG. 3A, the video signal (input signal) supplied to the signal line, the potential change of the power supply line (power supply line) blocked by three lines, and the scanning line of each row (each stage) are applied. Represents a control signal (control pulse). First, in the input signal, the signal potential Vsig and the reference potential Vofs are alternately switched within one horizontal period (1H). In the power supply line, the potential changes in the first to third stages are shared, and the first to third stages are simultaneously switched from the high potential to the low potential and then returned to the high potential. On the other hand, when the input signal is Vofs and the power supply line is at the high potential Vcc, the first-stage scanning line outputs the first control pulse, and the pixels in the corresponding row are switched from the lit state to the unlit state. Thereafter, the second to fourth control pulses are continuously generated, and the threshold voltage correcting operation is repeated three times. Finally, a fifth control pulse is generated, and writing of the signal potential Vsig and mobility correction are performed.

  For the second-stage scanning line, the phase is shifted by 1H from the first stage, and the first to fifth control pulses are sequentially output, and the turn-off operation, threshold voltage correction operation, and A signal potential write operation is performed. Similarly, in the third stage, the 1H phase is shifted from the second stage, and five control pulses are sequentially output, and the light-off operation, the time division correction operation, and the signal writing operation are performed.

  When the operation sequence proceeds to the fourth to sixth stages, the drive scanner temporarily switches the power line shared by the fourth to sixth stages from the high potential Vcc to the low potential Vss, and then returns to Vcc. In this way, the drive scanner switches the potentials of the power lines of the fourth to sixth stages while shifting the phase from the first to third stages. Correspondingly, five consecutive control pulses are sequentially applied to the fourth to sixth scanning lines, and the same operation as in the first to third stages is repeated.

  As is clear from the above description, in this embodiment, the potential of the power supply lines for three stages is controlled at a common timing. By doing so, the number of outputs of the drive scanner can be reduced (in this embodiment, 1/3), and the cost can be reduced.

  In the present embodiment, after the power line is returned from Vss to Vcc, the time until the first threshold voltage correction operation is started is different in the first stage, the second stage, and the third stage. . As described above, when the power supply line is returned from Vcc to Vss, if the current flowing through the driving transistor is small (Vgs of the driving transistor is small), the gate voltage and the source voltage hardly increase, and any stage However, the threshold voltage correction operation can be normally performed.

  FIG. 3B is another timing chart for explaining the operation of the pixel shown in FIG. This timing chart shows a change in the potential of the scanning line WS, a change in the potential of the power supply line (power supply line) DS, and a change in the potential of the signal line SL with a common time axis. The potential change of the scanning line WS represents a control signal, and the opening / closing control of the sampling transistor T1 is performed. The change in the potential of the power supply line DS represents switching between the power supply voltages Vcc and Vss. Further, the potential change of the signal line SL represents switching between the signal potential Vsig of the input signal and the reference potential Vofs. In parallel with these potential changes, the potential changes of the gate G and the source S of the driving transistor T2 are also shown. As described above, the potential difference between the gate G and the source S is Vgs.

  In this timing chart, the periods are divided as shown in (1) to (11) for convenience in accordance with the operation sequence of the pixels. In the lighting period (1), the pixel is in a light emitting state. In the extinguishing period (2), the pixel switches from the light emitting state to the non-light emitting state. Subsequently, in the preparation periods (3) to (5), the pixel performs a preparatory operation for correcting the threshold voltage of the driving transistor. Thereafter, an actual threshold voltage correction operation is performed in the correction period (6). Normally, this correction period (6) is repeated a plurality of times with the standby period (8) in between, and the threshold voltage correction operation is completed. Thereafter, in the writing period (9), the signal potential is written into the holding capacitor C1, and the mobility of the driving transistor T1 is corrected. Finally, in the light emission period (11), the pixel is switched from the non-light emitting state to the light emitting state. In the figure, for simplification of description, the correction operation is performed in one threshold voltage correction period (6).

  Thereafter, the process proceeds to the writing period / mobility correction period (9). Here, the signal potential Vsig of the video signal is written into the storage capacitor C1 in a form added to Vth, and the mobility correction voltage ΔV is subtracted from the voltage held in the storage capacitor C1. In the writing period / mobility correction period (9), the sampling transistor T1 needs to be turned on in a time zone in which the signal line SL is at the signal potential Vsig. Thereafter, the process proceeds to the light emission period (11), and the light emitting element emits light with a luminance corresponding to the signal potential Vsig. At that time, since the signal potential Vsig is adjusted by a voltage corresponding to the threshold voltage Vth and the mobility correction voltage ΔV, the light emission luminance of the light emitting element EL varies in the threshold voltage Vth and mobility μ of the driving transistor T2. Will not be affected. Note that the bootstrap operation is performed at the beginning of the light emission period (11), and the gate potential and the source potential of the driving transistor T2 rise while the gate G / source S voltage Vgs of the driving transistor T2 is kept constant.

  The operation of the pixel circuit shown in FIG. 2 will be described in detail with reference to FIGS. First, in the light emission period (1) of the light emitting element EL, the power source is Vcc as shown in FIG. 4A and the sampling transistor T1 is turned off. At this time, since the driving transistor T2 is set to operate in the saturation region, the current Ids flowing through the light emitting element EL takes a value represented by the characteristic formula 1 according to the gate-source voltage Vgs of the driving transistor T2. .

  Next, in the extinguishing period (2), when the signal line potential is Vofs, the sampling transistor T1 is turned on and Vofs is input to the gate of the driving transistor T2 (FIG. 4-2). As a result, the gate-source voltage of the driving transistor T2 becomes equal to or lower than the threshold voltage, and no current flows through the light emitting element EL, so that the light emitting element EL is turned off. At that time, since the voltage applied to the light emitting element EL becomes the threshold voltage of the light emitting element EL, the anode voltage of the light emitting element EL becomes the sum of the threshold voltage and the cathode voltage of the light emitting element EL, that is, Vcat + Vthel.

  Further, after a predetermined time has elapsed, the power supply voltage is changed from Vcc to Vss in the preparation period (3). At this time, the power source side becomes the source of the driving transistor T2, and a current flows from the anode of the light emitting element EL to the power source as shown in FIG. 4-3. Thereby, the voltage of the anode of the light emitting element EL decreases with time. At this time, since the sampling transistor T1 is off, the gate of the driving transistor T2 also decreases with the anode voltage of the light emitting element EL. That is, the gate-source voltage of the driving transistor T2 (the potential between the gate of the driving transistor T2 and the power source) decreases with time.

  At this time, if the driving transistor T2 operates in the saturation region, that is, if Vgs−Vthd ≦ Vds, the gate of the driving transistor T2 becomes Vss + Vthd as shown in FIG. Here, Vthd is a threshold voltage between the gate power supplies of the driving transistor T2.

  In the period (5), the power supply voltage is again set to Vcc (FIG. 4-5). At this time, the coupling amount input to the gate of the driving transistor T2 is ΔV, and the anode voltage of the light emitting element EL is Vx. By setting the power supply to Vcc, the source of the driving transistor T2 becomes the anode of the light emitting element EL, and a current flows from the power supply to the anode of the light emitting element EL by the gate-source voltage Vgs of the driving transistor T2. If the gate-source voltage is smaller than the threshold voltage, the gate and source due to current hardly rise.

In the threshold correction period (6), the sampling transistor T1 is turned on when the signal voltage is Vofs (FIG. 4-6). As a result, the gate voltage of the driving transistor T2 becomes Vofs, and the amount of change in the gate voltage is input to the source at a constant ratio by the holding capacitor C1, the parasitic capacitance Cgs between the gate and the source, and the parasitic capacitance Cel of the light emitting element EL. The input ratio at this time is represented by g. g is a value represented by the following Equation 2.
g = (C1 + Cgs) / (C1 + Cgs + Cel) (2)

  In this state, if the gate-source voltage Vgs of the driving transistor T2 is larger than the threshold voltage Vth, a current flows from the power supply as shown in FIG. In other words, it is necessary to set the values of Vofs and Vss so that Vgs at this time is larger than the threshold voltage of the driving transistor T2. As described above, since the equivalent circuit of the light emitting element EL is represented by a diode and a capacitor, as long as Vel ≦ Vcat + Vthel (the leakage current of the light emitting element EL is considerably smaller than the current flowing through the driving transistor T2), the driving transistor T2 Current is used to charge C1 and Cel. At this time, Vel rises with time as shown in FIG. 4-7.

  In the next standby period (8), the sampling transistor T1 is turned off before the signal voltage changes from Vofs to Vsig. At this time, since the gate-source voltage of the driving transistor T2 is larger than Vth, a current flows as shown in FIG. 4-8, and the gate and source voltages of the driving transistor T2 rise. At this time, since the reverse bias is applied to the light emitting element EL, the light emitting element EL does not emit light.

  After completion of the threshold cancel operation, the sampling transistor T1 is turned off. Subsequently, when the signal line potential becomes Vsig in the writing period (9), the sampling transistor T1 is turned on again (FIG. 4-9). Vsig is a voltage corresponding to the gradation. The gate potential of the driving transistor T2 becomes Vsig because the sampling transistor T1 is turned on, but since the current flows from the power supply, the source potential increases with time. At this time, if the source voltage of the driving transistor T2 does not exceed the sum of the threshold voltage Vthel and the cathode voltage Vcat of the light emitting element EL (if the leakage current of the light emitting element EL is much smaller than the current flowing through the driving transistor T2), The current in transistor T2 is used to charge C1 and Cel. At this time, since the threshold value correcting operation of the driving transistor T2 is completed, the current flowing through the driving transistor T2 reflects the mobility μ. Specifically, those with high mobility have a large current amount at this time, and the source rises quickly. On the other hand, when the mobility is low, the amount of current is small and the source rises slowly (FIG. 4-10). As a result, the gate-source voltage of the driving transistor T2 is reduced to reflect the mobility, and becomes Vgs for completely correcting the mobility after a predetermined time has elapsed.

  Finally, when the sampling transistor T1 is turned off and writing is completed and the light emission period (11) is reached, the light emitting element EL is caused to emit light. Since the gate-source voltage of the driving transistor T2 is constant, the driving transistor T2 passes a constant current Ids ′ to the light emitting element EL, and Vel rises to a voltage at which a current of Ids ′ flows through the light emitting element EL. Emits light (Figure 4-11)

  In this circuit as well, the IV characteristic of the light emitting element EL changes as the light emission time becomes longer. Therefore, the potential at point B in the figure also changes. However, since the gate-source voltage of the driving transistor T2 is kept constant, the current flowing through the light emitting element EL does not change. Therefore, even if the IV characteristic of the light emitting element EL deteriorates, the constant current Ids always flows, and the luminance of the light emitting element EL does not change.

 Here, driving of the pixel circuit is considered. As described above, the main drive takes the drive timing shown in FIG. 3A. However, after the power supply line is changed from Vss to Vcc, the time until the threshold correction operation is performed is between the lines having the same power supply line timing. It is different. Specifically, the time for which the power supply line is at the potential Vcc is longer before the threshold correction is performed in the (N + 1) th stage than in the Nth stage. Accordingly, the source voltage of the driving transistor is higher in the (N + 1) th stage than in the Nth stage due to the leakage current of the driving transistor and the leakage current of the light emitting element.

  Basically, even if the source voltage of the driving transistor is different before the threshold correction operation, the threshold correction operation can be normally performed if the gate-source voltage Vgs of the driving transistor is larger than the threshold voltage Vth in the threshold correction operation. . However, the light emission luminance depends on the source voltage of the driving transistor before the threshold correction operation. For this reason, in this driving, the source voltage of the driving transistor at the time of threshold correction at the last stage and the next stage (the third stage and the fourth stage in FIG. (From the first stage to the third stage changes slowly).

  For this reason, streaks such as streaks occur on the screen of the display device at the cycle of a plurality of lines (hereinafter referred to as blocks) sharing the power supply timing as shown in FIG. In the figure, the unevenness is exaggerated from the actual value.

  The present invention proposes to reverse the scanning direction of the sampling transistor in the block between adjacent blocks in order to solve the above-mentioned problems. FIG. 6 shows the timing when the present invention is applied as an example. This timing chart is basically the same as FIG. In the present invention, the difference from the case of FIG. 3A is that the time from when the power supply voltage is changed from Vss to Vcc until the threshold correction operation is performed is the same in adjacent lines between adjacent blocks, and input to the pixels. The output order of the signal voltage is reversed between adjacent blocks.

  By using the present invention, the time from when the power supply line is set to Vcc to the threshold correction operation between adjacent lines between adjacent blocks can be made the same, depending on the leakage current of the driving transistor and the light emitting element EL, etc. The amount of increase in the source voltage of the driving transistor can be made the same. As a result, it is possible to replace the uneven stripe between the blocks visually recognized as shown in FIG. 5 with unevenness such as shading as shown in FIG. 5 and 7, the shading unevenness is exaggerated from the actual value. Generally, unevenness such as streaks that change suddenly between adjacent blocks is visually recognized with a luminance difference of about 1%, but unevenness that changes slowly like shading cannot be visually recognized with a luminance difference of about 1%. By using the present invention, uniform image quality in which unevenness is not visually recognized can be obtained. In addition, even if the number of lines constituting the block is increased by using the present invention, unevenness is not visually recognized, so that the number of lines constituting the block can be increased compared to the conventional case, that is, the number of blocks of the panel can be reduced. Cost reduction is possible. In addition, since the present invention adopts a method in which the scanning direction of the sampling transistor is inverted for each adjacent block, in the case of a panel without a built-in gate driver, the unit is preferably a gate driver unit.

  FIG. 8A is a block diagram showing the overall configuration of the second embodiment of the display device according to the present invention. As shown in the figure, the display device includes a pixel array unit 1 and driving units (3, 4, 5) for driving the pixel array unit 1. The pixel array unit 1 includes a row-like scanning line WS, a column-like signal line SL, a matrix-like pixel 2 arranged at a portion where both intersect, and a power source arranged corresponding to each row of each pixel 2 And a feeder line DS which is a line. The drive unit (3, 4, 5) supplies a control signal to each scanning line WS sequentially to scan the pixels 2 line-sequentially in units of rows, and a control scanner (write scanner) 4 in accordance with this line-sequential scanning. A power supply scanner (drive scanner) 5 for supplying a power supply voltage to be switched between the first potential and the second potential to each power supply line DS, and a signal potential that becomes a video signal on the column-shaped signal line SL in accordance with the line sequential scanning. And a signal driver (horizontal selector) 3 for supplying a reference potential. The write scanner 4 operates in response to a clock signal WSck supplied from the outside, and sequentially transfers start pulses WSsp supplied from the outside, thereby outputting a control signal to each scanning line WS. The drive scanner 5 operates in response to a clock signal DSck supplied from outside, and sequentially transfers start pulses DSsp supplied from the outside, thereby switching the potential of the power supply line DS line-sequentially. The difference from the first embodiment shown in FIG. 1 is that the feeder line DS is not shared in units of blocks.

  FIG. 8B is a circuit diagram illustrating a specific configuration of the pixel 2 included in the display device illustrated in FIG. As shown in the figure, the pixel circuit 2 includes a two-terminal (diode type) light emitting element EL represented by an organic EL device, an N-channel sampling transistor T1, and an N-channel driving transistor T2. And a thin film type storage capacitor C1. The sampling transistor T1 has a gate that is a control end connected to the scanning line WS, a source and a drain that are a pair of current ends connected to the signal line SL, and the other connected to the gate G of the driving transistor T2. doing. One of the source and the drain of the driving transistor T2 is connected to the light emitting element EL, and the other is connected to the power supply line DS. In this embodiment, the driving transistor T2 is an N-channel type, and the drain side which is one current end thereof is connected to the power supply line DS, and the source S side which is the other current end is connected to the anode side of the light emitting element EL. Yes. The cathode of the light emitting element EL is fixed at a predetermined cathode potential Vcat. The storage capacitor C1 is connected between the source S that is the current end of the driving transistor T2 and the gate G that is the control end. For the pixel 2 having such a configuration, the control scanner (write scanner) 4 sequentially outputs a control signal by switching the scanning line WS between a low potential and a high potential, and the pixels 2 are line-sequentially in units of rows. Scan. The power supply scanner (drive scanner) 5 supplies a power supply voltage to be switched between the first potential Vcc and the second potential Vss to each power supply line DS in accordance with line sequential scanning. The signal driver (horizontal selector 3) supplies a signal potential Vsig and a reference potential Vofs, which are video signals, to the column-shaped signal lines SL in accordance with line sequential scanning.

  In such a configuration, the sampling transistor T1 has a first timing when the video signal rises from the reference potential Vofs to the signal potential Vsig, and then a second timing when the control signal rises to a third timing when the control signal falls and turns off. During the sampling period (between the second timing and the third timing), the signal potential Vsig is sampled and written to the storage capacitor C1. At the same time, the current flowing in the driving transistor T2 is negatively fed back to the holding capacitor C1, and the correction for the mobility μ of the driving transistor T2 is applied to the signal potential written in the holding capacitor C1. That is, the sampling period from the second timing to the third timing is also a mobility correction period in which the current flowing through the driving transistor T2 is negatively fed back to the storage capacitor C1.

  The pixel circuit shown in FIG. 8-2 has a threshold voltage correction function in addition to the mobility correction function described above. That is, the power supply scanner (drive scanner) 5 switches the power supply line DS from the first potential Vcc to the second potential Vss at the first timing before the sampling transistor T1 samples the signal potential Vsig. Similarly, before the sampling transistor T1 samples the signal potential Vsig, the control scanner (write scanner) 4 conducts the sampling transistor T1 at the second timing to supply the reference potential Vofs from the signal line SL to the driving transistor T2. While being applied to the gate G, the source S of the driving transistor T2 is set to the second potential Vss. The power supply scanner (drive scanner) 5 switches the power supply line DS from the second potential Vss to the first potential Vcc at a third timing after the second timing, and sets a voltage corresponding to the threshold voltage Vth of the driving transistor T2. It is held in the holding capacitor C1. With this threshold voltage correction function, the display device can cancel the influence of the threshold voltage Vth of the driving transistor T2 that varies from pixel to pixel. Note that the timing before and after the first timing and the second timing does not matter.

  The pixel circuit 2 shown in FIG. 8-2 further has a bootstrap function. That is, when the signal potential Vsig is held in the holding capacitor C1, the write scanner 4 turns off the sampling transistor T1 to electrically disconnect the gate G of the driving transistor T2 from the signal line SL. The gate potential is interlocked with the change in the source potential of the driving transistor T2, and the voltage Vgs between the gate G and the source S is maintained constant. Even if the current / voltage characteristics of the light emitting element EL change with time, the gate voltage Vgs can be kept constant, and the luminance does not change.

  FIG. 9 is a timing chart for explaining the operation of the pixel shown in FIG. This timing chart shows a change in the potential of the scanning line WS, a change in the potential of the power supply line (power supply line) DS, and a change in the potential of the signal line SL with a common time axis. The potential change of the scanning line WS represents a control signal, and the opening / closing control of the sampling transistor T1 is performed. The change in the potential of the power supply line DS represents switching between the power supply voltages Vcc and Vss. Further, the potential change of the signal line SL represents switching between the signal potential Vsig of the input signal and the reference potential Vofs. In parallel with these potential changes, the potential changes of the gate G and the source S of the driving transistor T2 are also shown. As described above, the potential difference between the gate G and the source S is Vgs.

  In this timing chart, the periods are divided for convenience as (1) to (7) in accordance with the transition of the operation of the pixel. In the period (1) immediately before entering the field, the light emitting element EL is in a light emitting state. After that, a new field of line sequential scanning is entered, and in the first period (2), the feeder line DS is switched from the first potential Vcc to the second potential Vss. In the next period (3), the input signal is switched from Vsig to Vofs. Further, the sampling transistor T1 is turned on in the next period (4). During this period (2) to (4), the gate voltage and the source voltage of the driving transistor T2 are initialized. Periods (2) to (4) are preparation periods for threshold voltage correction. The gate G of the driving transistor T2 is initialized to Vofs, while the source S is initialized to Vss. Subsequently, a threshold voltage correction operation is actually performed in the threshold correction period (5), and a voltage corresponding to the threshold voltage Vth is held between the gate G and the source S of the driving transistor T2. Actually, a voltage corresponding to Vth is written in the holding capacitor C1 connected between the gate G and the source S of the driving transistor T2.

  In the embodiment shown in FIG. 9, the threshold correction period (5) is divided into three times, and the threshold voltage correction operation is performed in a time division manner. A standby period (5a) is inserted between each threshold voltage correction period (5). In this way, by dividing the threshold voltage correction period (5) and repeating the threshold voltage correction operation a plurality of times, a voltage corresponding to Vth is written to the storage capacitor C1. However, the present invention is not limited to this, and the correction operation can be performed in one threshold voltage correction period (5).

  Thereafter, the process proceeds to the writing operation period / mobility correction period (6). Here, the signal potential Vsig of the video signal is written into the storage capacitor C1 in a form added to Vth, and the mobility correction voltage ΔV is subtracted from the voltage held in the storage capacitor C1. In the writing period / mobility correction period (6), the sampling transistor T1 needs to be turned on in a time zone in which the signal line SL is at the signal potential Vsig. Thereafter, the process proceeds to the light emission period (7), and the light emitting element emits light with a luminance corresponding to the signal potential Vsig. At that time, since the signal potential Vsig is adjusted by a voltage corresponding to the threshold voltage Vth and the mobility correction voltage ΔV, the light emission luminance of the light emitting element EL varies in the threshold voltage Vth and mobility μ of the driving transistor T2. Will not be affected. Note that a bootstrap operation is performed at the beginning of the light emission period (7), and the gate potential and the source potential of the driving transistor T2 rise while the gate G / source S voltage Vgs of the driving transistor T2 is kept constant.

  The operation of the pixel circuit shown in FIG. 8-2 will be described in detail with reference to FIGS. First, as shown in FIG. 10A, in the light emission period (1), the power supply potential is set to Vcc, and the sampling transistor T1 is turned off. At this time, since the driving transistor T2 is set so as to operate in the saturation region, the driving current Ids flowing through the light emitting element EL depends on the voltage Vgs applied between the gate G and the source S of the driving transistor T2. The value shown by the transistor characteristic equation described above is taken.

  Subsequently, as shown in FIG. 10-2, when the preparation periods (2) and (3) are entered, the potential of the power supply line (power supply line) is set to Vss. At this time, Vss is set to be smaller than the sum of the threshold voltage Vthel and the cathode voltage Vcat of the light emitting element EL. That is, since Vss <Vthel + Vcat, the light emitting element EL is turned off, and the power supply line side becomes the source of the driving transistor T2. At this time, the anode of the light emitting element EL is charged to Vss.

  Further, as shown in FIG. 10-3, in the next preparation period (4), the potential of the signal line SL becomes Vofs, while the sampling transistor T1 is turned on, and the gate potential of the driving transistor T2 is set to Vofs. . In this way, the source S and the gate G of the driving transistor T2 at the time of light emission are initialized, and the gate-source voltage Vgs at this time becomes a value of Vofs−Vss. Vgs = Vofs−Vss is set to be larger than the threshold voltage Vth of the driving transistor T2. In this way, by initializing the drive transistor T2 so that Vgs> Vth, preparation for the next threshold voltage correction operation is completed.

  Subsequently, as shown in FIG. 10-4, when the threshold voltage correction period (5) is entered, the potential of the feeder line DS (power supply line) returns to Vcc. By setting the power supply voltage to Vcc, the anode of the light emitting element EL becomes the source S of the driving transistor T2, and a current flows as shown in the figure. At this time, an equivalent circuit of the light emitting element EL is represented by a parallel connection of a diode Tel and a capacitor Cel as shown in the figure. Since the anode potential (that is, the source potential Vss) is lower than Vcat + Vthel, the diode Tel is in the off state, and the leak current flowing therethrough is considerably smaller than the current flowing through the driving transistor T2. Therefore, most of the current flowing through the driving transistor T2 is used to charge the holding capacitor C1 and the equivalent capacitor Cel.

  FIG. 10-5 represents the time change of the source voltage of the driving transistor T2 in the threshold voltage correction period (5) shown in FIG. 10-4. As shown in the figure, the source voltage of the driving transistor T2 (that is, the anode voltage of the light emitting element EL) rises from Vss with time. When the threshold voltage correction period (5) elapses, the driving transistor T2 is cut off, and the voltage Vgs between the source S and the gate G becomes Vth. At this time, the source potential is given by Vofs−Vth. If this value Vofs−Vth is still lower than Vcat + Vthel, the light emitting element EL is in a cut-off state.

  As shown in the graph of FIG. 10-5, the source voltage of the driving transistor T2 increases with time. However, in this example, since the first threshold voltage correction period (5) ends before the source voltage of the driving transistor T2 reaches Vofs−Vth, the sampling transistor T1 is turned off and the standby period (5a) is entered. FIG. 11A shows the state of the pixel circuit in the standby period (5a). In the first standby period (5a), the gate G / source S voltage Vgs of the driving transistor T2 is still larger than Vth, so that the current flows from the power source Vcc through the driving transistor T2 to the holding capacitor C1 as shown in the figure. Flows. As a result, the source voltage of the driving transistor T2 rises. However, since the sampling transistor T1 is off and the gate G is in a high impedance state, the potential of the gate G also rises as the potential of the source S increases. That is, in the first standby period (5a), the source potential and the gate potential of the driving transistor T2 both rise in the bootstrap operation. At this time, since the light emitting element EL is continuously reverse-biased, the light emitting element EL does not emit light.

  Thereafter, when 1H elapses and the potential of the signal line SL becomes Vofs again, the sampling transistor T1 is turned on to start the second threshold voltage correcting operation. Thereafter, when the second threshold voltage correction period (5) elapses, the process proceeds to the second standby period (5a). Thus, by repeating the threshold voltage correction period (5) and the standby period (5a), the voltage between the gate G and the source S of the driving transistor T2 finally reaches a voltage corresponding to Vth. At this time, the source potential of the driving transistor T2 is Vofs−Vth, which is smaller than Vcat + Vthel.

  Next, as shown in FIG. 11B, when the signal writing period / mobility correction period (6) starts, the sampling transistor T1 is turned on after the potential of the signal line SL is switched from Vofs to Vsig. At this time, the signal potential Vsig is a voltage corresponding to the gradation. The gate potential of the driving transistor T2 is Vsig because the sampling transistor T1 is turned on. On the other hand, the source potential rises with time because current flows from the power supply Vcc. Even at this time, if the source potential of the driving transistor T2 does not exceed the sum of the threshold voltage Vthel and the cathode voltage Vcat of the light emitting element EL, the current flowing from the driving transistor T2 is exclusively used for charging the equivalent capacitor Cel and the holding capacitor C1. Is called. At this time, since the threshold voltage correction operation of the driving transistor T2 has already been completed, the current flowing through the driving transistor T2 reflects the mobility μ. Specifically, the driving transistor T2 having a high mobility μ has a large amount of current at this time, and the source potential increase ΔV is also large. On the contrary, when the mobility μ is small, the current amount of the driving transistor T2 is small, and the increase ΔV of the source is small. With this operation, the gate voltage Vgs of the driving transistor T2 is compressed by ΔV reflecting the mobility μ, and Vgs with the mobility μ completely corrected is obtained when the mobility correction period (6) is completed.

  FIG. 11C is a graph showing temporal changes in the source voltage of the driving transistor T2 during the mobility correction period (6) described above. As shown in the figure, when the mobility of the driving transistor T2 is large, the source voltage rises quickly, and Vgs is compressed accordingly. That is, when the mobility μ is large, Vgs is compressed so as to cancel the influence, and the drive current can be suppressed. On the other hand, when the mobility μ is small, the source voltage of the driving transistor T2 does not rise so fast, so that Vgs is not strongly compressed. Therefore, when the mobility μ is small, Vgs of the driving transistor is not compressed so as to compensate for the small driving capability.

  FIG. 12 shows an operation state in the light emission period (7). In this light emission period (7), the sampling transistor T1 is turned off to cause the light emitting element EL to emit light. The gate-source voltage Vgs of the driving transistor T2 is kept constant, and the driving transistor T2 supplies a constant current Ids ′ to the light emitting element EL according to the above-described characteristic equation. The anode voltage of the light emitting element EL (that is, the source voltage of the driving transistor T2) flows to the light emitting element EL, so that the current Ids ′ rises to Vx, and the light emitting element EL emits light when this exceeds Vcat + Vthel. The light emitting element EL changes its current / voltage characteristics as the light emission time becomes longer. For this reason, the potential of the source S shown in FIG. However, since the gate-source voltage Vgs of the driving transistor T2 is maintained at a constant value by the bootstrap operation, the current Ids ′ flowing through the light emitting element EL does not change. Therefore, even if the current / voltage characteristics of the light emitting element EL deteriorate, a constant drive current Ids ′ always flows, and the luminance of the light emitting element EL does not change.

  By the way, as the display device becomes higher in definition and speeded up, the 1H period becomes shorter. Even in this case, it is necessary to complete the threshold voltage correction operation and the signal potential writing operation within the last 1H. At that time, in consideration of the transient of the input signal and the control signal, the input of Vofs to the signal line, the threshold voltage correction operation, the off operation of the sampling transistor T1, the input of the signal potential Vsig to the signal line SL, and the signal potential writing operation The sampling transistor T1 must be turned off within 1H. However, in practice, when the display device is further refined and speeded up, 1H is considerably shortened, and it is difficult to complete the threshold voltage correction operation and the signal potential writing operation within 1H.

  In order to cope with the above-described problems, the present invention combines a plurality of horizontal periods and performs a threshold voltage correction operation in common for a part of the combined period. Thereafter, the signal potential writing operation is sequentially performed in the remaining part of the synthesis period. FIG. 13 is a timing chart schematically showing an operation sequence when two horizontal periods (2H) are combined as an example. For comparison, the operation sequence of the reference example described above is shown in the upper part of this timing chart, and the operation sequence of the present invention is shown in the lower part. In the operation sequence of the reference example, the input signal switches between Vofs and Vsig in units of 1H. A control signal including three pulses P0, P1, and P2 is sequentially applied to the sampling transistor T1 (N) on the Nth line. The sampling transistor T1 (N) is turned on in response to the pulses P0, P1, and P2. The control signal including the pulses P0, P1, P2 is applied to the sampling transistor T1 (N + 1) on the (N + 1) th line with the phase shifted 1H backward. In the first 1H period, when the input signal is Vofs, the sampling transistor T1 (N) is turned on according to the control pulse P1, and the threshold voltage correcting operation is performed. Thereafter, when the input signal becomes the signal potential Vsig1 in the same 1H period, the sampling transistor T1 (N) is turned on according to the control pulse P2, and the signal potential writing operation is performed. In this way, the sampling transistor T1 (N) on the Nth line completes the threshold voltage correcting operation and the signal potential writing operation in the first horizontal period. At this time, the sampling transistor T1 (N + 1) in the next line is turned on in response to the control pulse P0, and the first threshold voltage correction operation is performed.

  In the second horizontal period, when the input signal is Vofs, the sampling transistor T1 (N + 1) on the (N + 1) th line is turned on in response to the control pulse P1, and the second threshold voltage correcting operation is performed. Subsequently, when the input signal is switched from Vofs to Vsig2, the sampling transistor T1 (N + 1) is turned on in response to the control pulse P2, and the signal potential writing operation is performed. In this way, the sampling transistors in each line perform the threshold voltage correcting operation and the signal potential writing operation within 1H. In this reference example, the correction is not completed by a single threshold voltage correction operation, so the threshold voltage correction operation is repeatedly performed in two steps.

  On the other hand, in the operation sequence according to the present invention, the write scanner includes the first period and the second period in combination with the scanning period (1H) assigned to each of the plurality of scanning lines (two lines in this embodiment). The synthesis period. In other words, this combined scanning period corresponds to 2H. In the first period, the control signal P1 is output simultaneously to the two scanning lines (N line and N + 1 line), and the threshold voltage correction operation is executed simultaneously. Subsequently, the control signal P2 is sequentially output to the two scanning lines (line N and line N + 1) in the second period, and the signal potential writing operation is sequentially performed. In the illustrated example, the input signal is Vofs in the first period corresponding to the first half of the composite scanning period 2H, and sequentially changes from Vsig1 to Vsig2 in the second half of the second half. At this time, the sampling transistor T1 (N) on the Nth line is turned on in response to the control signal pulse P2, and samples Vsig1. Subsequently, the sampling transistor T1 (N + 1) on the (N + 1) th line is turned on in response to the control signal pulse P2, and samples Vsig2.

  FIG. 14 is a timing chart showing the overall configuration of the operation sequence of the present invention including the change in potential of the power supply line. As shown in the figure, the control signal waveforms applied to the sampling transistors T1 (N) and T1 (N + 1) in the correction preparation period and the threshold voltage correction period in the Nth line and the N + 1th line are common. On the other hand, the difference between the signal writing time for the pixel on the N-th line and the signal writing time for the pixel on the N + 1-th line is 1H or less. Further, the difference between the Nth line and the (N + 1) th line is less than 1H in the time when the power line DS becomes Vss (non-light emission period start timing). At the time of non-light emission, the gate of the driving transistor is set to Vofs and the source is set to Vss, and then the power supply line is switched from Vss to Vcc to perform the division threshold voltage correction operation. Thereafter, the signal potentials Vsig1 and Vsig2 are written to the holding capacitors of the respective lines while performing mobility correction, and the light emitting element EL is caused to emit light. As described above, in this operation sequence, the control signals are sequentially output to the scanning lines WS (N, N + 1) with a phase difference smaller than one scanning period (1H) in the second period. The power supply scanner simultaneously supplies the low potential Vss to the plurality of power supply lines DS corresponding to the plurality of scanning lines WS (N, N + 1) in order to execute the threshold voltage correction operation in the first period, and then simultaneously increases the high potential. It is switched to Vcc. At this time, the low potential Vss is sequentially supplied to the plurality of power supply lines DS (N, N + 1) with a phase difference smaller than one scanning period (1H) in the first period, and then simultaneously switched to the high potential Vcc.

  As described above, according to the present invention, the scanning lines are divided into blocks every predetermined number, and the scanning lines assigned to each of the predetermined number of scanning lines are combined to be divided into the first period and the second period. The synthesis period. In the timing chart shown in FIG. 14, for easy understanding, the scanning lines are divided into blocks every two lines, and one horizontal period (1H) assigned to each of the two scanning lines is synthesized. One synthesis period (2H) divided into a first period and a second period is used. The timing chart of FIG. 14 represents an operation sequence for one block including the Nth scanning line and the (N + 1) th scanning line.

  FIG. 15A is a waveform diagram showing changes in the gate potential and the source potential of the driving transistor T2 included in the pixel on the Nth line. Corresponding to the potential waveforms of the gate G and the source S, changes in the power supply line DS, changes in the control signal of the sampling transistor T1, and changes in the potential of the input signal supplied to the signal line SL are also shown. The pixel on the N-th line has a correction preparation period (4), a threshold correction period (5), a signal writing period (6), etc., according to the potential change of the power supply line DS and the control signal and input signal of the sampling transistor T1. Perform a predetermined operation.

  In the preparation period (4), the gate G of the driving transistor T2 is set to Vofs, and the source S is set to Vss. After that, after the first threshold voltage correction period (5) and standby period (5a), the voltage Vgs between the gate G and the source S is fixed at a voltage corresponding to Vth in the second threshold voltage correction period (5). Is done.

  Subsequently, after the transition period (5b), the signal writing period (6) is entered, and the signal potential Vsig1 is written. In the pixel on the Nth line, the transition period (5b) from the end of the second threshold voltage correction period (5) to the start of the signal potential writing period (6) is very short. In the transition period (5b), the potential of the gate G and the source S varies because there is a slight current leakage of the driving transistor T2. However, since the transition period (5b) is very short in the pixel on the N-th line, the influence of the current leakage of the driving transistor T2 is hardly observed, and the potential variation of the source S is hardly observed.

  FIG. 15B is a waveform diagram showing potential changes of the gate G and the source S of the driving transistor T2 belonging to the pixel on the (N + 1) th line. As described above, the line N and the line N + 1 belong to the same block, and the threshold voltage correction operation is collectively performed in units of blocks, but the signal potential writing operation is sequentially performed in the block. Therefore, in the signal writing period (6), the pixel on the (N + 1) th line shifts backward compared to the pixel on the Nth line. Therefore, as shown in the timing chart of FIG. 15B, the transition period (5b) interposed between the second threshold voltage correction period (5) and the signal potential writing period (6) is N + 1-th line compared to the N-th line pixel. The pixels are longer. Therefore, the potential of the gate G and the source S of the driving transistor T2 rises so as to be strongly affected by the current leakage of the driving transistor T2 and surrounded by the dotted circle. In particular, the gate potential G rises due to the potential rise of the source S. As a result, the dynamic range of the signal potential written to the storage capacitor C1 is reduced, and the pixel of the (N + 1) th line cannot obtain a desired luminance, and the luminance is lower than that of the pixel of the Nth line.

  When the operation of the block composed of the N line and the N + 1 line is finished and the operation proceeds to the next block, the operations for the N + 2 line and the N + 3 line are repeated in the same manner as the operations of the N line and the N + 1 line. That is, the transition period of the N + 2 line pixels is short, and the transition period between the threshold voltage correction period and the signal writing period is long in the N + 3 line pixels. N + 1 lines adjacent to each other between adjacent blocks have a long transition period, and N + 2 lines have a short transition period. Therefore, the transition period is greatly different at the block boundaries, and uneven brightness appears clearly.

  In the present invention, in order to cope with the above-described problems, the control signals are sequentially output to the respective scanning lines in the adjacent blocks to reverse the directions in which the line sequential scanning is performed. As a result, the pixels belonging to the adjacent lines between the adjacent blocks have the same transition time from the completion of the threshold voltage correction operation to the start of the signal potential write operation. As a result, a difference in luminance does not appear between a pair of adjacent lines at the boundary between adjacent blocks, and a non-conspicuous display is obtained.

  FIG. 15C is a timing chart showing the operation sequence of the present invention. In the present embodiment, as an example, two scanning lines are set as one block, and two horizontal periods (2H) are set as one synthesis period. In the example of FIG. 15C, the N line and the N + 1 line are set as one block, and the N + 2 line and the N + 3 line are set as the next block. Therefore, the boundary between adjacent blocks is between the N + 1 line and the N + 2 line. As shown in the timing chart, the signal writing order, the power supply line potential switching order, and the signal input order are reversed between adjacent blocks.

  By reversing the direction of line sequential scanning performed at the time of signal writing in adjacent blocks in this way, the transition time from the end of the threshold correction operation to the start of the signal writing operation is the same for the N + 1 line and the N + 2 line. It has become. Since the N + 1 line and the N + 2 line belong to different blocks, the switching timing of the power supply line (N) and the power supply line (N + 2) has a phase difference of 2H. The phase difference between the control signal pulses applied to the sampling transistors T1 (N + 1) and T1 (N + 2) is also 2H, which is one synthesis period. In accordance with this, the input signal changes in the order of Vsig (N), Vsig (N + 1), Vsig (N + 3), and Vsig (N + 2). That is, Vsig (N + 3) and Vsig (N + 2) are switched in accordance with the inversion of the line sequential scanning between the blocks.

  By setting the transition time from the end of the threshold voltage correction operation to the start of the signal potential writing operation as shown in the timing chart of FIG. 15C, the pixels on the N + 1 line and the pixels on the N + 2 line belonging to different blocks The current leakage amount of the driving transistors can be made substantially the same between the pixels of the N + 1 line and the pixels of the N + 2 line, which were visually recognized in the reference example, and the luminance difference becomes inconspicuous. Thereby, uniform image quality without periodic unevenness can be obtained. In order to realize such a writing operation, the signal output needs to be reversed in the adjacent synthesis period.

  FIG. 15D is a schematic plan view showing the state of the screen displayed on the pixel array unit 1. This reference example is an example in which 400 scanning lines (400 lines) are formed in the pixel array section 1, and these are bundled into 100 blocks and divided into four blocks B1, B2, B3, and B4. As described above, the threshold voltage correction operation is performed for each block in a block sequential manner. On the other hand, the signal potential writing operation is performed line-sequentially within each block. In this reference example, each of the blocks B1 to B4 has a line sequential scanning direction from top to bottom. In other words, the line sequential scanning direction is not reversed between adjacent blocks.

  First, the threshold voltage correction operation is collectively performed in the block B1, and then line sequential scanning for signal writing is performed from the top to the bottom. As it goes down, the transition time from the end of the threshold voltage correction operation to the start of the signal writing operation becomes longer, so that the amount of current leakage increases and the luminance decreases accordingly. In the screen shown in the figure, the luminance decreases slightly from top to bottom in the block B1. This is because current leakage increases and the luminance decreases as the transition time increases. Hereinafter, in the present specification, the transition time is redefined as the leak time for convenience of explanation.

  In the next block B2, the threshold voltage correction operation is again performed collectively, and then the signal writing operation is performed by line sequential scanning. The direction of line sequential scanning is from the top to the bottom of the screen in block B2 as well as in block B1. Therefore, the luminance gradually decreases from top to bottom in the block B2.

  Here, focusing on the boundary between the block B1 and the block B2, the leak time of the last line of the block B1 is the longest. The first line of the block B2 adjacent to this has the shortest leak time. Therefore, the leak times of the lines adjacent to each other at the boundary between the block B1 and the block B2 are the largest, and the greatest difference in luminance occurs along this boundary. Therefore, when the screen of the pixel array unit 1 is viewed as a whole, strip-shaped unevenness is visually recognized in units of blocks B1, B2, B3, and B4 as shown in the figure, and the uniformity of the screen is deteriorated.

  FIG. 15E is a schematic plan view showing the state of the screen displayed on the pixel array unit 1 in accordance with the operation sequence of the present invention. Similarly to FIG. 15D, 400 scanning lines (400 lines) included in the pixel array unit 1 are divided into four blocks B1, B2, B3, and B4. The direction of the line sequential scanning of the block B1 and the line sequential scanning of the block B2 are reversed. Similarly, in the blocks B2 and B3, the direction of line sequential scanning is reversed. Further, the direction of line sequential scanning is also reversed between B3 and B4. Focusing on the first block B1, line sequential scanning for signal writing proceeds from top to bottom. Therefore, the leak time of the last line of block B1 is the longest. Subsequently, in the block B2, on the contrary, the line sequential scanning is performed from the bottom to the top. Therefore, the leak time is the longest in the line located at the head of the block B2. Paying attention to the boundary between the block B1 and the block B2, the lines adjacent to each other have the longest leakage time, and there is no luminance difference between the two. In other words, no luminance difference appears at the boundary between the block B1 and the block B2.

  Subsequently, when focusing on the boundary of B3 of block B2, the leak time of the last line on the block B2 side is the shortest. Since the block B3 performs line sequential scanning from the top to the bottom as opposed to the block B2, the leak time of the first line of B3 is the shortest. Therefore, the lines adjacent to each other at the boundary between the block B2 and the block B3 have the shortest leak time and no luminance difference. Therefore, there is no noticeable luminance unevenness between the block B2 and the block B3, and a uniform luminance distribution is obtained.

  The display device according to the present invention has a thin film device configuration as shown in FIG. This figure shows a schematic cross-sectional structure of a pixel formed on an insulating substrate. As shown in the figure, the pixel includes a transistor part (a single TFT is illustrated in the figure) including a plurality of thin film transistors, a capacitor part such as a storage capacitor, and a light emitting part such as an organic EL element. A transistor portion and a capacitor portion are formed on a substrate by a TFT process, and a light emitting portion such as an organic EL element is laminated thereon. A transparent counter substrate is pasted thereon via an adhesive to form a flat panel.

  The display device according to the present invention includes a flat module-shaped display as shown in FIG. For example, a pixel array unit in which pixels made up of organic EL elements, thin film transistors, thin film capacitors and the like are integrated in a matrix is provided on an insulating substrate, and an adhesive is disposed so as to surround the pixel array unit (pixel matrix unit). Then, a counter substrate such as glass is attached to form a display module. If necessary, this transparent counter substrate may be provided with a color filter, a protective film, a light shielding film, and the like. For example, an FPC (flexible printed circuit) may be provided in the display module as a connector for inputting / outputting a signal to / from the pixel array unit from the outside.

  The display device according to the present invention described above has a flat panel shape and is input to an electronic device such as a digital camera, a notebook personal computer, a mobile phone, or a video camera, or an electronic device. It is possible to apply to the display of the electronic device of all fields which display the image signal produced | generated in the inside as an image or an image | video. Examples of electronic devices to which such a display device is applied are shown below.

  FIG. 18 shows a television to which the present invention is applied, which includes a video display screen 11 including a front panel 12, a filter glass 13, and the like, and is manufactured by using the display device of the present invention for the video display screen 11. .

  FIG. 19 shows a digital camera to which the present invention is applied, in which the top is a front view and the bottom is a back view. This digital camera includes an imaging lens, a light emitting unit 15 for flash, a display unit 16, a control switch, a menu switch, a shutter 19, and the like, and is manufactured by using the display device of the present invention for the display unit 16.

  FIG. 20 shows a notebook personal computer to which the present invention is applied. The main body 20 includes a keyboard 21 operated when inputting characters and the like, and the main body cover includes a display unit 22 for displaying an image. This display device is used for the display portion 22.

  FIG. 21 shows a mobile terminal device to which the present invention is applied. The left side shows an open state and the right side shows a closed state. The portable terminal device includes an upper housing 23, a lower housing 24, a connecting portion (here, a hinge portion) 25, a display 26, a sub-display 27, a picture light 28, a camera 29, and the like, and includes the display device of the present invention. The display 26 and the sub-display 27 are used.

  FIG. 22 shows a video camera to which the present invention is applied. The video camera includes a main body 30, a lens 34 for photographing a subject, a start / stop switch 35 at the time of photographing, a monitor 36, etc. on the side facing forward. It is manufactured by using the device for its monitor 36.

1 is an overall block diagram showing a first embodiment of a display device according to the present invention. It is a circuit diagram which shows the circuit structure of 1st Embodiment. It is a reference timing chart with which operation | movement description of 1st Embodiment is provided. It is another reference timing chart with which operation | movement description of 1st Embodiment is provided. It is a schematic diagram with which operation | movement description of 1st Embodiment is provided. It is a schematic diagram for explaining the operation of the first embodiment. It is a schematic diagram with which operation | movement description of 1st Embodiment is provided. It is a schematic diagram with which operation | movement description of 1st Embodiment is provided. It is a schematic diagram with which operation | movement description of 1st Embodiment is provided. It is a schematic diagram with which operation | movement description of 1st Embodiment is provided. It is a graph with which it uses for operation | movement description of 1st Embodiment. It is a schematic diagram with which operation | movement description of 1st Embodiment is provided. It is a schematic diagram with which operation | movement description of 1st Embodiment is provided. It is a graph with which it uses for operation | movement description of 1st Embodiment. It is a schematic diagram with which operation | movement description of 1st Embodiment is provided. It is a typical top view which shows the display state of the reference example of a display apparatus. It is a timing chart with which it uses for operation | movement description of 1st Embodiment. It is a typical top view which shows the display state of the display apparatus concerning 1st Embodiment. It is a block diagram which shows the whole structure of 2nd Embodiment of the display apparatus concerning this invention. It is a circuit diagram which shows an example of the pixel formed in the display apparatus shown to FIGS. It is a timing chart which shows operation | movement of the pixel shown to FIGS. 8-2. It is a schematic diagram with which it uses for operation | movement description of the pixel shown to FIGS. 8-2. It is a schematic diagram for explaining the operation in the same manner. It is a schematic diagram for explaining the operation in the same manner. It is a schematic diagram for explaining the operation in the same manner. It is a graph similarly provided for operation | movement description. It is a schematic diagram for explaining the operation in the same manner. It is a schematic diagram for explaining the operation in the same manner. It is a graph similarly provided for operation | movement description. It is a schematic diagram for explaining the operation in the same manner. It is a timing chart with which it uses for operation | movement description of the pixel shown to FIGS. 8-2. It is a timing chart which shows the drive method of the display apparatus shown to FIGS. It is a wave form diagram with which it uses for operation | movement description of a display apparatus similarly. It is a wave form diagram with which it uses for operation | movement description of a display apparatus similarly. It is a timing chart which shows the drive method of the display apparatus concerning 2nd Embodiment of this invention. It is a schematic diagram which shows the screen of the display apparatus concerning a reference example. It is a schematic diagram which shows the screen of the display apparatus concerning this invention. It is sectional drawing which shows the device structure of the display apparatus concerning this invention. It is a top view which shows the module structure of the display apparatus concerning this invention. It is a perspective view which shows the television set provided with the display apparatus concerning this invention. It is a perspective view which shows the digital still camera provided with the display apparatus concerning this invention. 1 is a perspective view illustrating a notebook personal computer including a display device according to the present invention. It is a schematic diagram which shows the portable terminal device provided with the display apparatus concerning this invention. It is a perspective view which shows the video camera provided with the display apparatus concerning this invention. It is a circuit diagram which shows an example of the conventional display apparatus. It is a graph showing the problem of the conventional display apparatus. It is a circuit diagram which shows another example of the conventional display apparatus.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Pixel array, 2 ... Pixel, 3 ... Horizontal selector (signal driver), 4 ... Control scanner, 5 ... Power supply scanner, T1 ... Sampling transistor, T2. -Driving transistor, C1 ... holding capacitor, EL ... light emitting element, WS ... scanning line, DS ... power feed line, SL ... signal line

Claims (5)

  1. A plurality of scan lines disposed in rows, a plurality of signal lines arranged in columns, and a pixel array section in which each scanning line and each signal line is provided with a matrix of picture element disposed at the intersection And
    Block sequential driving is performed to sequentially drive matrix pixels in units of pixel blocks corresponding to scanning line groups divided by a predetermined number, and the scanning direction of line sequential driving is reversed between adjacent blocks. A drive unit that performs line-sequential driving for scanning each scanning line in each block and sequentially driving pixels in units of rows ,
    With
    The drive unit
    A signal selector that supplies a video signal to a signal line that switches between a signal potential corresponding to a gradation and a predetermined reference potential;
    A write scanner that supplies a control signal to the scanning lines to drive the pixels line-sequentially so that the scanning directions of the line-sequential driving are opposite to each other between adjacent blocks; and
    A drive scanner that supplies a power supply voltage that switches between a high potential and a low potential to a power supply line assembled for each block;
    Have
    Pixel is
    A sampling transistor having one current end connected to a signal line and a control end connected to a scanning line;
    A driving transistor having a drain connected to the power supply line and a gate connected to the other current end of the sampling transistor;
    A light emitting device connected to the source of the driving transistor, and
    A storage capacitor connected between the source and gate of the driving transistor,
    Have
    Depending on the drive unit,
    When the reference potential is supplied to the signal line, a turn-off operation is performed in which the light-emitting elements that are turned on are turned off by sequentially scanning the pixels in the block so that the sampling transistor is turned on.
    The power supply voltage of the power supply line corresponding to the block is switched from a high potential to a low potential to lower the voltage of the source of the pixel drive transistor, and then a correction preparation operation is performed in which the power supply voltage of the power supply line is returned to the high potential Then
    When the signal line is at the reference potential, the pixels in the block are sequentially scanned so that the sampling transistor is turned on, and the storage capacitor is set so that the voltage between the gate and source of the driving transistor is directed to the threshold voltage of the driving transistor. Corrective action is taken to discharge the
    Display device.
  2. The signal selector supplies a video signal to each signal line so that the order of signal potentials supplied to each signal line is reversed between adjacent blocks,
    After the correction operation, the drive unit sequentially scans the pixels in the block so that the sampling transistor is turned on when the signal line is at the signal potential, and performs a writing operation to write the signal potential to the storage capacitor. Item 4. The display device according to Item 1.
  3. Drive scanner display device according to claim 1 or claim 2 comprising a plurality of gate drivers divided corresponding to each block.
  4. A plurality of scan lines disposed in rows, a plurality of signal lines arranged in columns, and a pixel array section in which each scanning line and each signal line is provided with a matrix of picture element disposed at the intersection And
    Block sequential driving is performed to sequentially drive matrix pixels in units of pixel blocks corresponding to scanning line groups divided by a predetermined number, and the scanning direction of line sequential driving is reversed between adjacent blocks. A drive unit that performs line-sequential driving for scanning each scanning line in each block and sequentially driving pixels in units of rows ,
    With
    The drive unit
    A signal selector that supplies a video signal to a signal line that switches between a signal potential corresponding to a gradation and a predetermined reference potential;
    A write scanner that supplies a control signal to the scanning lines to drive the pixels line-sequentially so that the scanning directions of the line-sequential driving are opposite to each other between adjacent blocks; and
    A drive scanner that supplies a power supply voltage that switches between a high potential and a low potential to a power supply line assembled for each block;
    Have
    Pixel is
    A sampling transistor having one current end connected to a signal line and a control end connected to a scanning line;
    A driving transistor having a drain connected to the power supply line and a gate connected to the other current end of the sampling transistor;
    A light emitting device connected to the source of the driving transistor, and
    A storage capacitor connected between the source and gate of the driving transistor,
    A driving method of a display device having
    The drive unit
    Performing a light-off operation to switch a light-emitting element in a light-on state to a light-off state by sequentially scanning the pixels in the block so that the sampling transistor is turned on when a reference potential is supplied to the signal line,
    By switching the power supply voltage of the power supply line corresponding to the block from a high potential to a low potential, the voltage of the source of the drive transistor of the pixel is lowered, and then a correction preparation operation is performed to return the power supply voltage of the power supply line to a high potential,
    The pixels in the block are sequentially scanned so that the sampling transistor is turned on when the signal line is at the reference potential, and the storage capacitor is set so that the voltage between the gate and source of the driving transistor is directed to the threshold voltage of the driving transistor. Corrective action to discharge
    A driving method of a display device.
  5. Consists of a Main body portion, a display unit for displaying the information outputted from the information or the main body is input to the main body portion,
    The display section
    A plurality of scan lines disposed in rows, a plurality of signal lines arranged in columns, and a pixel array section in which each scanning line and each signal line is provided with a matrix of picture element disposed at the intersection And
    Block sequential driving is performed to sequentially drive matrix pixels in units of pixel blocks corresponding to scanning line groups divided by a predetermined number, and the scanning direction of line sequential driving is reversed between adjacent blocks. A drive unit that performs line-sequential driving for scanning each scanning line in each block and sequentially driving pixels in units of rows ,
    With
    The drive unit
    A signal selector that supplies a video signal to a signal line that switches between a signal potential corresponding to a gradation and a predetermined reference potential;
    A write scanner that supplies a control signal to the scanning lines to drive the pixels line-sequentially so that the scanning directions of the line-sequential driving are opposite to each other between adjacent blocks; and
    A drive scanner that supplies a power supply voltage that switches between a high potential and a low potential to a power supply line assembled for each block;
    Have
    Pixel is
    A sampling transistor having one current end connected to a signal line and a control end connected to a scanning line;
    A driving transistor having a drain connected to the power supply line and a gate connected to the other current end of the sampling transistor;
    A light emitting device connected to the source of the driving transistor, and
    A storage capacitor connected between the source and gate of the driving transistor,
    Have
    Depending on the drive unit,
    When the reference potential is supplied to the signal line, a turn-off operation is performed in which the light-emitting elements that are turned on are turned off by sequentially scanning the pixels in the block so that the sampling transistor is turned on.
    The power supply voltage of the power supply line corresponding to the block is switched from a high potential to a low potential to lower the voltage of the source of the pixel drive transistor, and then a correction preparation operation is performed in which the power supply voltage of the power supply line is returned to the high potential. Then
    When the signal line is at the reference potential, the pixels in the block are sequentially scanned so that the sampling transistor is turned on, and the storage capacitor is set so that the voltage between the gate and source of the driving transistor is directed to the threshold voltage of the driving transistor. Corrective action is taken to discharge the
    Electronics.
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KR20080111475A KR101517110B1 (en) 2007-11-14 2008-11-11 Display device, method of driving the same,
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