JP5284044B2 - Nonvolatile semiconductor memory device - Google Patents

Nonvolatile semiconductor memory device Download PDF

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JP5284044B2
JP5284044B2 JP2008287881A JP2008287881A JP5284044B2 JP 5284044 B2 JP5284044 B2 JP 5284044B2 JP 2008287881 A JP2008287881 A JP 2008287881A JP 2008287881 A JP2008287881 A JP 2008287881A JP 5284044 B2 JP5284044 B2 JP 5284044B2
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layer
columnar
formed
embodiment
semiconductor memory
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JP2010114376A (en
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啓安 田中
英明 青地
竜太 勝又
大 木藤
傑 鬼頭
嘉晃 福住
陽介 小森
恵 石月
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株式会社東芝
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    • H01L27/112Read-only memory structures [ROM] and multistep manufacturing processes therefor
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    • H01L27/1021Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including bipolar components including diodes only
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    • H01L27/2409Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including solid state components for rectifying, amplifying or switching without a potential-jump barrier or surface barrier, e.g. resistance switching non-volatile memory structures comprising two-terminal selection components, e.g. diodes
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    • H01L27/2436Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including solid state components for rectifying, amplifying or switching without a potential-jump barrier or surface barrier, e.g. resistance switching non-volatile memory structures comprising multi-terminal selection components, e.g. transistors
    • H01L27/2454Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including solid state components for rectifying, amplifying or switching without a potential-jump barrier or surface barrier, e.g. resistance switching non-volatile memory structures comprising multi-terminal selection components, e.g. transistors of the vertical channel field-effect transistor type
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    • H01L27/2463Arrangements comprising multiple bistable or multistable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays, details of the horizontal layout
    • H01L27/2481Arrangements comprising multiple bistable or multistable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays, details of the horizontal layout arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays, details of the vertical layout
    • H01L27/249Arrangements comprising multiple bistable or multistable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays, details of the horizontal layout arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays, details of the vertical layout the switching components being connected to a common vertical conductor
    • GPHYSICS
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    • G11C2213/30Resistive cell, memory material aspects
    • G11C2213/33Material including silicon
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    • G11C2213/00Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/30Resistive cell, memory material aspects
    • G11C2213/34Material includes an oxide or a nitride
    • GPHYSICS
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    • G11C2213/72Array wherein the access device being a diode
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C2213/00Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70Resistive array aspects
    • G11C2213/78Array wherein the memory cells of a group share an access device, all the memory cells of the group having a common electrode and the access device being not part of a word line or a bit line driver
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    • H01L45/04Bistable or multistable switching devices, e.g. for resistance switching non-volatile memory
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    • H01L45/04Bistable or multistable switching devices, e.g. for resistance switching non-volatile memory
    • H01L45/12Details
    • H01L45/122Device geometry
    • H01L45/1226Device geometry adapted for essentially horizontal current flow, e.g. bridge type devices
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    • H01L45/04Bistable or multistable switching devices, e.g. for resistance switching non-volatile memory
    • H01L45/14Selection of switching materials
    • H01L45/145Oxides or nitrides

Abstract

A non-volatile semiconductor storage device includes a plurality of memory element groups, each of the memory element groups having a plurality of memory elements, each of the memory elements having a resistance-change element and a Schottky diode connected in series. Each of the memory element groups includes: a first columnar layer extending in a lamination direction; a first insulation layer formed on a side surface of the first columnar layer and functioning as the resistance-change element; and a first conductive layer formed to surround the first columnar layer via the first insulation layer. The first conductive layer is formed of metal. The first columnar layer is formed of a semiconductor having such a impurity concentration that the first conductive layer and the semiconductor configure the Schottky diode.

Description

  The present invention relates to a nonvolatile semiconductor memory device capable of electrically rewriting data.

  In order to increase the integration and capacity of a semiconductor memory device, it is necessary to reduce the design rule. In order to reduce the design rule, further fine processing such as a wiring pattern is required. In order to realize further fine processing of wiring patterns and the like, a very advanced processing technique is required, so that it is difficult to reduce the design rule.

  Therefore, in recent years, a semiconductor memory device in which memory elements are three-dimensionally arranged has been proposed in order to increase the degree of memory integration (see Patent Document 1). In Patent Document 1, the memory element has a configuration in which a pn diode and a resistance change element are connected in series.

However, the semiconductor memory device having the pn diode has a problem in wiring resistance and the like. For this reason, the signal from the memory cell cannot be increased, and its operation is not sufficiently reliable.
JP 2008-181978 A

  The present invention provides a nonvolatile semiconductor memory device that can increase a signal from a memory cell and improve reliability.

The nonvolatile semiconductor memory device according to one embodiment of the present invention includes a plurality of memory element group including a plurality of memory elements, said memory element group includes a first columnar layer extending in the stacking direction, the side surface of the first columnar layer And a first insulating layer that functions as a resistance change element and is destroyed when a predetermined voltage is applied, and a first insulating layer that surrounds the first columnar layer via the first insulating layer. The first conductive layer is made of metal, and the first columnar layer is in contact with the first conductive layer through the destroyed first insulating layer. The semiconductor device functions as a Schottky diode and is made of a semiconductor having an impurity concentration for forming the Schottky diode .

The nonvolatile semiconductor memory device according to one embodiment of the present invention includes a plurality of memory element group including a plurality of memory elements, said memory element group includes a first columnar layer extending in the stacking direction, the first columnar layer And a first insulating layer that functions as a resistance change element and is destroyed by applying a predetermined voltage, and is formed so as to surround the first columnar layer via the first insulating layer. A first conductive layer, the first columnar layer is made of metal, and the first conductive layer is in contact with the first columnar layer through the destroyed first insulating layer . The semiconductor device functions as a Schottky diode together with the columnar layer and is made of a semiconductor having an impurity concentration for constituting the Schottky diode .

  The present invention can provide a nonvolatile semiconductor memory device in which a signal from a memory cell can be increased, thereby improving reliability.

  Hereinafter, an embodiment of a nonvolatile semiconductor memory device according to the present invention will be described with reference to the drawings.

[First Embodiment]
(Schematic configuration of the nonvolatile semiconductor memory device 100 according to the first embodiment)
First, a schematic configuration of the nonvolatile semiconductor memory device 100 according to the first embodiment will be described with reference to FIGS. 1 and 2. FIG. 1 is a schematic configuration diagram of a nonvolatile semiconductor memory device 100 according to the first embodiment of the present invention. FIG. 2 is a circuit diagram showing a memory element region 1 to be described later.

  As shown in FIG. 1, the nonvolatile semiconductor memory device 100 includes a memory element region 1, a bit line driving circuit 2, a word line driving circuit 3, a source line driving circuit 4, a sense amplifier (not shown), and the like.

  The memory element region 1 is formed by arranging a large number of memory elements, and is configured so that data can be written to or read from each memory element. Although not shown in FIG. 1, the memory element region 1 has a plurality of stacked conductive layers, a columnar layer formed so as to penetrate these conductive layers, and an insulation formed between the columnar layer and the conductive layer. It is composed of layers. Note that the configurations of the conductive layer, the columnar layer, and the insulating layer will be described in detail later.

  As shown in FIGS. 1 and 2, the memory element region 1 includes a memory string MS, a plurality of selection transistors STr, a plurality of source lines SL, a plurality of word lines WL, and a plurality of bit lines BL. Have.

  1 and 2, the memory strings MS (MS (1, 1) to MS (20, 10) are provided in 20 rows and 10 columns. Similarly, the selection transistors STr (STr (1, 1) are provided. ) To STr (20, 10)) are provided in 20 rows and 10 columns, and four source lines (SL1 to SL4) are provided in the stacking direction, and word lines WL (WL1 to WL20). ) Are provided along the column direction perpendicular to the stacking direction, and 10 bit lines BL (BL1 to BL10) are provided along the row direction perpendicular to the stacking direction and the column direction. Yes.

  As shown in FIG. 2, the memory strings MS are formed in a matrix in the row direction and the column direction. The memory string MS is composed of four memory elements MC1 to MC4. Each of the memory elements MC1 to MC4 includes a resistance change element R and a Schottky diode SBD.

  The resistance change element R is composed of an insulating layer such as a silicon oxide layer. The resistance change element R changes its resistance value by being applied with a predetermined voltage and being destroyed. Note that the nonvolatile semiconductor memory device 100 according to the present invention stores information based on whether or not the resistance change element R is destroyed. The detailed configuration of the resistance change element R will be described later.

  Schottky diode SBD is composed of a metal layer and an n-type semiconductor layer provided so as to sandwich an insulating layer (resistance change element R). The metal layer and the n-type semiconductor layer function as a Schottky diode SBD when the insulating layer (resistance change element R) is destroyed and brought into contact with each other. The detailed configuration of the Schottky diode SBD will be described later.

  The variable resistance element R and the Schottky diode SBD are connected in series. One end of the resistance element R is connected to the anode of the Schottky diode SBD. In the same memory string MS, the other ends of the four resistance change elements R are commonly connected to each other. Between different memory strings MS (MS (1, 1) to MS (20, 10)), the cathode of the Schottky diode SBD of the memory element MC1 is commonly connected to the source line SL1. Similarly, the cathode of the Schottky diode SBD of the memory element MC2 is commonly connected to the source line SL2 between different memory strings MS. Similarly, between different memory strings MS, the cathode of the Schottky diode SBD of the memory element MC3 is commonly connected to the source line SL3. Similarly, between the different memory strings MS, the cathode of the Schottky diode SBD of the memory element MC4 is commonly connected to the source line SL4.

  As shown in FIG. 2, one end of the selection transistor STr is connected to the other end of the memory string MS (resistance change element R). The other end of the selection transistor STr is connected to the bit line BL. The control gate of the selection transistor STr is connected to the word line WL. The selection transistor STr controls conduction to the memory string MS.

  The source line SL is formed so as to spread two-dimensionally in the row direction and the column direction. The bit lines BL are formed to extend in the column direction with a predetermined pitch in the row direction. The word lines WL are formed to extend in the row direction with a predetermined pitch in the column direction.

  The bit line drive circuit 2 drives a plurality of bit lines BL. The word line driving circuit 3 drives a plurality of word lines WL. The source line drive circuit 4 drives a plurality of source lines SL. The sense amplifier reads data from the plurality of source lines SL.

(Specific Configuration of Nonvolatile Semiconductor Memory Device 100 According to First Embodiment)
Next, a specific configuration of the nonvolatile semiconductor memory device 100 according to the first embodiment will be described with reference to FIGS. 3 and 4A to 4C. FIG. 3 is a schematic perspective view of the memory element region 1. 4A is a top view of FIG. 3, FIG. 4B is an AA ′ sectional view of FIG. 4A, and FIG. 4C is a BB ′ sectional view of FIG. 4A. Note that FIG. 3 does not show an interlayer insulating layer formed between layers functioning as the source line SL (bit line BL, word line WL). The right side of FIG. 4A shows the upper surface of a part of the wiring layer 10 and the select transistor 20 described later. Further, the left side of FIG. 4B shows the upper surface of the memory unit 30 described later.

  As illustrated in FIGS. 3, 4B, and 4C, the memory element region 1 includes a wiring layer 10, a selection transistor layer 20, and a memory layer 30 that are sequentially stacked on the substrate Ba. The selection transistor layer 20 functions as a selection transistor STr. The memory layer 30 functions as the memory string MS.

  As shown in FIGS. 3, 4B, and 4C, the wiring layer 10 includes a first insulating layer 11 and a bit line conductive layer 12 that are sequentially stacked.

  The first insulating layer 11 is formed to extend in the column direction with a predetermined pitch in the row direction. The bit line conductive layer 12 is formed on the first insulating layer 11 and extends in the column direction with a predetermined pitch in the row direction. An interlayer insulating layer 13 is formed between the side walls of the first insulating layer 11 and the bit line conductive layer 12.

The first insulating layer 11 and the interlayer insulating layer 13 are made of silicon oxide (SiO 2 ). The bit line conductive layer 12 is made of tungsten (W).

  The bit line conductive layer 12 functions as the bit line BL described above.

  The select transistor layer 20 includes a first protective layer 21, a second insulating layer 22, a word line conductive layer 23, and a third insulating layer 24 that are sequentially stacked.

  The first protective layer 21 is formed so as to spread two-dimensionally in a predetermined region configured in the row direction and the column direction. The second insulating layer 22, the word line conductive layer 23, and the third insulating layer 24 are formed to extend in the row direction with a predetermined pitch in the column direction. An interlayer insulating layer 25 is formed on the side walls of the second insulating layer 22, the word line conductive layer 23, and the third insulating layer 24.

The first protective layer 21 is made of silicon nitride (SiN). The second insulating layer 22 and the third insulating layer 24 are composed of silicon oxide (SiO 2 ). The word line conductive layer 23 is composed of polysilicon (p-Si) (n + type semiconductor) doped with n + type impurity ions.

  The select transistor layer 20 has a transistor hole 26.

  The transistor hole 26 is formed so as to penetrate the first protective layer 21, the second insulating layer 22, the word line conductive layer 23, and the third insulating layer 24. The transistor hole 26 is formed at a position aligned with the bit line conductive layer 12. The transistor holes 26 are formed in a matrix as viewed from above.

  The selection transistor layer 20 includes a selection gate insulating layer 27 and a columnar layer 28.

  The select gate insulating layer 27 is formed on the side wall facing the transistor hole 26 with a predetermined thickness. The columnar layer 28 is formed in a column shape so as to extend in the stacking direction. The columnar layer 28 is formed so as to contact the select gate insulating layer 27 and fill the transistor hole 26.

The selection gate insulating layer 27 is composed of silicon oxide (SiO 2 ). The columnar layer 28 is made of polysilicon (p-Si) (p + type semiconductor) doped with p + type impurities.

  In the configuration of the select transistor layer 20 as described above, the word line conductive layer 23 functions as the word line WL. Further, the word line conductive layer 23, the select gate insulating layer 27, and the columnar layer 28 function as a select transistor STr. Further, the end portion of the word line conductive layer 23 functions as a control gate of the selection transistor STr.

  The memory layer 30 includes a second protective layer 31, fourth to eighth insulating layers 32a to 32e, and source line conductive layers 33a to 33d.

  The second protective layer 31, the fourth to eighth insulating layers 32a to 32e, and the first to fourth source line conductive layers 33a to 33d spread two-dimensionally in a predetermined region configured in the row direction and the column direction. It is formed as follows. The fourth to eighth insulating layers 32 a to 32 e are formed in the upper layer of the second protective layer 31. The first to fourth source line conductive layers 33a to 33d are formed between the fourth to eighth insulating layers 32a to 32e.

The second protective layer 31 is composed of silicon nitride (SiN). The fourth to eighth insulating layers 32a to 32e are made of silicon oxide (SiO 2 ). The first to fourth source line conductive layers 33a to 33d are composed of metal layers. The first to fourth source line conductive layers 33a to 33d are made of, for example, any one of TiB, TaB, HfSix, TiN, and Ta.

  Further, the memory layer 30 has a memory hole 34.

  The memory hole 34 is formed so as to penetrate the second protective layer 31, the fourth to eighth insulating layers 32a to 32e, and the first to fourth source line conductive layers 33a to 33d. The memory hole 34 is formed at a position aligned with the transistor hole 26. The memory holes 34 are formed in a matrix when viewed from above.

  The memory layer 30 includes a memory gate insulating layer 35 and a columnar layer 36.

  The memory gate insulating layer 35 is formed on the side wall facing the memory hole 34 with a predetermined thickness. The columnar layer 36 is formed in a column shape extending in the stacking direction. The columnar layer 36 is formed so as to contact the memory gate insulating layer 35 and fill the memory hole 34.

The memory gate insulating layer 35 is made of, for example, silicon oxide (SiO 2 ). The memory gate insulating layer 35 is configured to change its resistance value when a predetermined voltage is applied and destroyed. That is, the resistance is changed in accordance with the applied voltage. The columnar layer 36 is composed of polysilicon (p-Si) (p-type semiconductor) doped with p-type impurity ions. The columnar layer 36 is composed of a semiconductor having an impurity concentration that constitutes the Schottky diode SBD together with the first to fourth source line conductive layers 33a to 33d.

  In the configuration of the memory layer 30 as described above, the first to fourth source line conductive layers 33a to 33d function as source lines SL (SL1 to SL4). The first to fourth source line conductive layers 33a to 33d, the memory gate insulating layer 35, and the columnar layer 36 function as memory strings MS (memory elements MC1 to MC4). The memory gate insulating layer 35 functions as the resistance change element R. The first to fourth source line conductive layers 33a to 33d and the columnar layer 36 function as a Schottky diode SBD.

(Method for Manufacturing Nonvolatile Semiconductor Memory Device 100 According to First Embodiment)
Next, with reference to FIG. 5A (FIGS. 5B and 5C) to FIG. 16A (FIGS. 16B and 16C), a method for manufacturing the nonvolatile semiconductor memory device 100 according to the first embodiment will be described. FIG. 5A to FIG. 16A are top views showing manufacturing processes of the nonvolatile semiconductor memory device 100 according to the first embodiment. 5B to 16B are cross-sectional views taken along line AA ′ of FIGS. 5A to 16A, and FIGS. 5C to 16C are cross-sectional views taken along line BB ′ of FIGS. 5A to 16A.

First, as shown in FIGS. 5A to 5C, silicon oxide (SiO 2 ) and tungsten (W) are deposited on the substrate Ba to form a layer 11a and a layer 12a.

  Next, as shown in FIGS. 6A to 6C, a groove 41 is formed so as to penetrate the layer 11a and the layer 12a. The grooves 41 are formed to extend in the column direction with a predetermined pitch in the row direction. Through this step, the layer 11 a becomes the first insulating layer 11. Further, the layer 12 a becomes the bit line conductive layer 12.

Subsequently, as shown in FIGS. 7A to 7C, silicon oxide (SiO 2 ) is deposited so as to fill the groove 41. Thereafter, planarization is performed by CMP (chemical mechanical polishing) or the like to form an interlayer insulating layer 13.

Next, as shown in FIGS. 8A to 8C, on the upper surface of the bit line conductive layer 12 (interlayer insulating layer 13), silicon nitride (SiN) (for example, 15 nm), silicon oxide (SiO 2 ) (for example, 20 nm), n + type polysilicon (p-Si) (for example, 200 nm), and silicon oxide (SiO 2 ) (for example, 20 nm) are deposited. By this step, the first protective layer 21, the layer 22a, the layer 23a, and the layer 24a are formed on the upper surface of the bit line conductive layer 12 (interlayer insulating layer 13).

  Subsequently, as illustrated in FIGS. 9A to 9C, a transistor hole 26 is formed so as to penetrate the first protective layer 21, the layer 22a, the layer 23a, and the layer 24a. The transistor hole 26 is formed at a position aligned with the bit line conductive layer 12. The transistor holes 26 are formed so as to be arranged in a matrix as viewed from above.

Next, as shown in FIGS. 10A to 10C, silicon oxide (SiO 2 ) ( 2 to 3 nm) is deposited by CVD (chemical vapor deposition) so as to cover the surface facing the transistor hole 26 and the upper surface of the layer 24a. Layer 27a is formed.

  Subsequently, as shown in FIGS. 11A to 11C, the surface facing the transistor hole 26 and the layer 27a on the upper surface of the layer 24a are selectively etched and removed. By this step, the select gate insulating layer 27 is formed.

  Next, as shown in FIGS. 12A to 12C, p + type polysilicon (p-Si) is deposited so as to fill the transistor hole 26, and then etch back is performed. By this step, the columnar layer 28 is formed.

  Subsequently, as shown in FIGS. 13A to 13C, a groove 42 is formed so as to penetrate the layers 22a to 24a. The grooves 42 are formed to extend in the row direction with a predetermined pitch in the column direction. By this step, the layer 22 a becomes the second insulating layer 22. The layer 23 a becomes the word line conductive layer 23. The layer 24 a becomes the third insulating layer 24.

Next, as shown in FIGS. 14A to 14C, silicon oxide (SiO 2 ) is deposited so as to fill the groove 42. Thereafter, planarization is performed by CMP or the like to form an interlayer insulating layer 25.

Subsequently, as shown in FIGS. 15A to 15C, silicon nitride (SiN) is deposited by CVD to form the second protective layer 31. Then, a silicon oxide (SiO 2 ) and a metal layer (any of TiB, TaB, HfSix, TiN, Ta) are sequentially stacked on the second protective layer 31 by CVD, and the fourth to eighth insulating layers 32a to 32a 32e and first to fourth source line conductive layers 33a to 33d are formed.

Next, as shown in FIGS. 16A to 16C, the memory hole is formed so as to penetrate the second protective layer 31, the fourth to eighth insulating layers 32a to 32e, and the first to fourth source line conductive layers 33a to 33d. 34 is formed. The memory hole 34 is formed at a position aligned with the transistor hole 26. The memory holes 34 are formed so as to be positioned in a matrix as viewed from above. Further, silicon oxide (SiO 2 ) is deposited on the side wall facing the memory hole 34 to form a memory gate insulating layer 35.

  Subsequently, p-type polysilicon (p-Si) is deposited so as to fill the memory hole 34 to form a columnar layer 36. Through the above manufacturing process, the nonvolatile semiconductor memory device 100 according to the first embodiment shown in FIGS. 3 and 4A to 4C is formed.

(Effect of Nonvolatile Semiconductor Memory Device 100 According to First Embodiment)
The effects of the nonvolatile semiconductor memory device 100 according to the first embodiment will be described. The nonvolatile semiconductor memory device 100 according to the first embodiment can be highly integrated as shown in the stacked structure.

  Further, as described in the manufacturing process, the nonvolatile semiconductor memory device 100 can manufacture each layer functioning as the memory string MS and the selection transistor STr with a predetermined number of lithography processes regardless of the number of stacked layers. That is, the nonvolatile semiconductor memory device 100 can be manufactured at a low cost.

  Further, in the nonvolatile semiconductor memory device 100, the first to fourth source line conductive layers 33a to 33d are composed of metal layers. Therefore, the nonvolatile semiconductor memory device 100 according to the first embodiment can reduce the wiring resistance, increase the signal from the memory cell, and increase the operation reliability.

  Next, effects of the nonvolatile semiconductor memory device 100 according to the first embodiment D2 will be described with reference to FIGS. 17A and 17B while comparing with the comparative example (conventional example) D1. FIG. 17A is a diagram illustrating a comparative example D1 during the read operation, and FIG. 17B is a diagram illustrating the first embodiment D2 during the read operation. Here, the comparative example D1 includes the first to fourth source line conductive layers 33Ba to 33Bd configured by n + type semiconductor layers and the columnar layer 36B configured by p− type semiconductor layers. Other configurations in the comparative example are the same as those in the first embodiment.

  17A and 17B, it is assumed that the memory gate insulating layer 35 (35B) of the memory elements MC2 to MC4 is destroyed. On the other hand, the memory gate insulating layer 35 (35B) of the memory element MC1 is not destroyed. Further, in FIGS. 17A and 17B, data is read from the memory element MC3. Here, a forward bias is applied to the memory element MC3 to be read, and a reverse bias is applied to the memory elements MC1, MC2, and MC4 that are not to be read.

  The impurity concentration of the columnar layer 36B of the comparative example D1 is lower than that of the first embodiment D2. Therefore, as shown in FIG. 17A, in the comparative example D1, the depletion layer E1 spreads over a wide range in the columnar layer 36B at the time of reading. Therefore, in Comparative Example D1, there is a possibility that the voltage is not transmitted to the memory element MC3 to be read.

  On the other hand, the impurity concentration of the columnar layer 36 of the first embodiment D2 is higher than that of the comparative example D1. Therefore, as shown in FIG. 17B, in the first embodiment D2, the range in which the depletion layer E2 is formed during reading is suppressed more than in the comparative example D1. Therefore, the nonvolatile semiconductor memory device 100 according to the first embodiment D2 can solve the problem as in the comparative example D1.

  In Comparative Example D1, the first to fourth source line conductive layers 33Ba to 33Bd (n + type semiconductor layer) and the columnar layer 36B (p − type semiconductor layer) constitute a pn diode. On the other hand, in the first embodiment D2, the first to fourth source line conductive layers 33a to 33d (metal layer) and the columnar layer 36 (p-type semiconductor layer) constitute a Schottky diode SBD. Here, the Schottky diode SBD has a lower voltage drop in the forward direction than the pn diode and has a fast switching speed. That is, the first embodiment D2 has switching characteristics superior to those of the comparative example D1. In addition, since the voltage drop is low, the first embodiment D2 can increase the signal from the memory cell, thereby improving the operation reliability.

[Second Embodiment]
(Schematic configuration of nonvolatile semiconductor memory according to the second embodiment)
Next, a schematic configuration of the nonvolatile semiconductor memory device according to the second embodiment will be described with reference to FIG. FIG. 18 is a circuit diagram showing a memory element region 1A of the nonvolatile semiconductor memory device according to the second embodiment. Note that in the second embodiment, identical symbols are assigned to configurations similar to those in the first embodiment and descriptions thereof are omitted.

  As shown in FIG. 18, the memory element region 1A according to the second embodiment includes memory strings MSa (MSa (1, 1) to MS (10, 20)) different from the first embodiment. The memory string MSa is composed of memory elements MCa1 to MCa4 different from the first embodiment.

  Similarly to the first embodiment, the memory elements MCa1 to MCa4 include a resistance change element R and a Schottky diode SBD.

  In the memory elements MCa1 to MCa4, the variable resistance element R and the Schottky diode SBD are connected in series as in the first embodiment. On the other hand, in the second embodiment, unlike the first embodiment, one end of the resistance element R is connected to the cathode of the Schottky diode SBD. In the second embodiment, the other ends of the four resistance change elements R are commonly connected to each other in the same memory string MSa. Between the different memory strings MSa (MSa (1, 1) to MSa (20, 10)), the anode of the Schottky diode SBD of the memory element MCa1 is commonly connected to the source line SL1. Similarly, between the different memory strings MSa, the anodes of the Schottky diodes SBD of the memory elements MCa2 are commonly connected to the source line SL2. Similarly, between the different memory strings MSa, the anodes of the Schottky diodes SBD of the memory elements MC3a are commonly connected to the source line SL3. Similarly, the anode of the Schottky diode SBD of the memory element MC4a is commonly connected to the source line SL4 between the different memory strings MSa.

(Specific Configuration of Nonvolatile Semiconductor Memory According to Second Embodiment)
Next, a specific configuration of the nonvolatile semiconductor memory device according to the second embodiment will be described. In the second embodiment, the first to fourth source line conductive layers 33a to 33d are made of, for example, any one of Pt, WC, WB, TaC, W, Pt, TiN, CoSi, and Co. The columnar layer 36 is composed of polysilicon (p-Si) (n-type semiconductor) doped with n-type impurities. The columnar layer 36 is composed of a semiconductor having an impurity concentration that constitutes the Schottky diode SBD together with the first to fourth source line conductive layers 33a to 33d.

(Effects of Nonvolatile Semiconductor Memory According to Second Embodiment)
The effect of the nonvolatile semiconductor memory according to the second embodiment will be described. The nonvolatile semiconductor memory device according to the second embodiment has substantially the same configuration as that of the first embodiment, and has the same effects as those of the first embodiment.

[Third embodiment]
(Specific Configuration of Nonvolatile Semiconductor Memory According to Third Embodiment)
Next, a specific configuration of the nonvolatile semiconductor memory device according to the third embodiment will be described with reference to FIGS. 19A to 19C. FIG. 19A is a top view of the memory element region 1B according to the third embodiment. 19B is a cross-sectional view taken along line AA ′ of FIG. 19A, and FIG. 19C is a cross-sectional view taken along line BB ′ of FIG. 19A. The right side of FIG. 19A shows the upper surface of the wiring layer 10 and some layers of the select transistor 20. Further, the left side of FIG. 19B shows an upper surface of a memory unit 30A described later. Note that in the third embodiment, identical symbols are assigned to configurations similar to those in the first and second embodiments and descriptions thereof are omitted.

  As shown in FIGS. 19B and 19C, the memory element region 1B has a memory layer 30A different from the first and second embodiments. The memory layer 30A includes first to fourth source line conductive layers 33Aa to 33Ad and a columnar layer 36A different from the first embodiment.

  The first to fourth source line conductive layers 33Aa to 33Ad are composed of polysilicon (p-Si) (n-type semiconductor) doped with n-type impurities. The first to fourth source line conductive layers 33Aa to 33Ad are made of a semiconductor having an impurity concentration that constitutes the Schottky diode SBD together with the columnar layer 36A.

  The columnar layer 36A is composed of a metal layer. The columnar layer 36A is made of, for example, any one of Pt, WC, WB, TaC, W, Pt, TiN, CoSi, and Co.

  In the configuration of the memory layer 30A, the first to fourth source line conductive layers 33Aa to 33Ad and the columnar layer 36A function as a Schottky diode SBD.

(Effects of Nonvolatile Semiconductor Memory According to Third Embodiment)
Next, the effect of the nonvolatile semiconductor memory according to the third embodiment will be described. As in the first embodiment, the nonvolatile semiconductor memory device according to the third embodiment can be highly integrated and can be manufactured at low cost.

  Furthermore, in the nonvolatile semiconductor memory device according to the third embodiment, the columnar layer 36A is configured by a metal layer. Therefore, the nonvolatile semiconductor memory device according to the third embodiment, its wiring resistance can be reduced, and the operation reliability can be increased.

[Fourth embodiment]
(Specific Configuration of Nonvolatile Semiconductor Memory According to Fourth Embodiment)
Next, a specific configuration of the nonvolatile semiconductor memory device according to the fourth embodiment will be described with reference to FIG. FIG. 20 is a cross-sectional view of the memory element region 1C according to the fourth embodiment. Note that in the fourth embodiment, identical symbols are assigned to configurations similar to those in the first through third embodiments and descriptions thereof are omitted.

  In the memory element region 1C, as shown in FIG. 20, the select transistor layer 20 is located in an upper layer of the memory layer 30 unlike the first embodiment. The wiring layer 10 is located above the selection transistor layer 20.

(Effects of Nonvolatile Semiconductor Memory According to Fourth Embodiment)
Next, effects of the nonvolatile semiconductor memory according to the fourth embodiment will be described. The nonvolatile semiconductor memory device according to the fourth embodiment has substantially the same configuration as that of the first embodiment, and has the same effects as those of the first embodiment.

  Further, in the nonvolatile semiconductor memory device according to the fourth embodiment, the wiring layer 10 and the select transistor layer 20 are provided in the upper layer of the memory layer 30. Therefore, the nonvolatile semiconductor memory device according to the fourth embodiment can increase the degree of freedom of wiring of the bit line BL and the word line WL.

[Fifth Embodiment]
(Specific Configuration of Nonvolatile Semiconductor Memory According to Fifth Embodiment)
Next, a specific configuration of the nonvolatile semiconductor memory device according to the fifth embodiment will be described with reference to FIG. FIG. 21 is a cross-sectional view of the memory element region 1D according to the fifth embodiment. Note that in the fifth embodiment, identical symbols are assigned to configurations similar to those in the first through fourth embodiments and descriptions thereof are omitted.

  The memory element region 1D includes a wiring layer 10, a select transistor layer 20, and a memory layer 30 as in the first embodiment. The memory element region 1D further includes a control circuit layer 50 between the substrate Ba and the wiring layer 10. The control circuit layer 50 functions as a control circuit (for example, a sense amplifier or a row decoder) that controls the memory string MS and the selection transistor STr.

  The substrate Ba has a base region Ba1 and a pair of source / drain regions Ba2 and Ba3 on its surface. For example, the base region Ba1 is made of a p-type semiconductor, and the source / drain regions Ba2 and Ba3 are made of an n-type semiconductor. Further, the base region Ba1 may be composed of an n-type semiconductor, and the source / drain regions Ba2 and Ba3 may be composed of a p-type semiconductor.

  The control circuit layer 50 includes a gate insulating layer 51 formed on the upper surface of the substrate Ba and straddling the source / drain regions Ba2 and Ba3, and a gate conductive layer 52 formed on the gate insulating layer 51.

  The control circuit layer 50 includes first contact layers 53a, 53b, and 53c, and first wiring layers 54a, 54b, and 54c. The first contact layers 53a, 53b, and 53c are provided in contact with the upper surfaces of the source / drain regions Ba2 and Ba3 and the gate conductive layer 52, and are formed to extend in the stacking direction. The first wiring layers 54a, 54b, 54c are connected to the first contact layers 53a, 53b, 53c, respectively.

  The control circuit layer 50 includes second contact layers 55a and 55b and second wiring layers 56a and 56b. The second contact layers 55a and 55b are provided in contact with the upper surfaces of the first wiring layers 54a and 54b and are formed to extend in the stacking direction. The second wiring layers 56a and 56b are connected to the second contact layers 55a and 55b, respectively.

  In the configuration of the control circuit layer 50, the source / drain regions Ba2, Ba3, the gate insulating layer 51, and the gate conductive layer 52 function as a transistor Tr.

(Effects of Nonvolatile Semiconductor Memory According to Fifth Embodiment)
Next, effects of the nonvolatile semiconductor memory according to the fifth embodiment will be described. The nonvolatile semiconductor memory device according to the fifth embodiment has substantially the same configuration as that of the first embodiment, and has the same effects as those of the first embodiment.

  Furthermore, the nonvolatile semiconductor memory device according to the fifth embodiment includes a control circuit layer 50 between the substrate Ba and the wiring layer 10. Therefore, the non-volatile semiconductor memory device according to the fifth embodiment can reduce the occupied area as compared with the first embodiment.

[Other embodiments]
Although one embodiment of the nonvolatile semiconductor memory device has been described above, the present invention is not limited to the above-described embodiment, and various modifications, additions, substitutions, and the like can be made without departing from the spirit of the invention. Is possible.

1 is a schematic configuration diagram of a nonvolatile semiconductor memory device 100 according to a first embodiment of the present invention. 2 is a circuit diagram showing a memory element region 1. FIG. 2 is a schematic perspective view of a memory element region 1. FIG. FIG. 4 is a top view of FIG. 3. It is A-A 'sectional drawing of FIG. 4A. It is B-B 'sectional drawing of FIG. 4A. FIG. 6 is a top view showing a manufacturing process of the nonvolatile semiconductor memory device 100 in accordance with the first embodiment. It is A-A 'sectional drawing of FIG. 5A. It is B-B 'sectional drawing of FIG. 5A. FIG. 6 is a top view showing a manufacturing process of the nonvolatile semiconductor memory device 100 in accordance with the first embodiment. It is A-A 'sectional drawing of FIG. 6A. It is B-B 'sectional drawing of FIG. 6A. FIG. 6 is a top view showing a manufacturing process of the nonvolatile semiconductor memory device 100 in accordance with the first embodiment. It is A-A 'sectional drawing of FIG. 7A. It is B-B 'sectional drawing of FIG. 7A. FIG. 6 is a top view showing a manufacturing process of the nonvolatile semiconductor memory device 100 in accordance with the first embodiment. It is A-A 'sectional drawing of FIG. 8A. It is B-B 'sectional drawing of FIG. 8A. FIG. 6 is a top view showing a manufacturing process of the nonvolatile semiconductor memory device 100 in accordance with the first embodiment. It is A-A 'sectional drawing of FIG. 9A. It is B-B 'sectional drawing of FIG. 9A. FIG. 6 is a top view showing a manufacturing process of the nonvolatile semiconductor memory device 100 in accordance with the first embodiment. It is A-A 'sectional drawing of FIG. 10A. It is B-B 'sectional drawing of FIG. 10A. FIG. 6 is a top view showing a manufacturing process of the nonvolatile semiconductor memory device 100 in accordance with the first embodiment. It is A-A 'sectional drawing of FIG. 11A. It is B-B 'sectional drawing of FIG. 11A. FIG. 6 is a top view showing a manufacturing process of the nonvolatile semiconductor memory device 100 in accordance with the first embodiment. It is A-A 'sectional drawing of FIG. 12A. It is B-B 'sectional drawing of FIG. 12A. FIG. 6 is a top view showing a manufacturing process of the nonvolatile semiconductor memory device 100 in accordance with the first embodiment. It is A-A 'sectional drawing of FIG. 13A. It is B-B 'sectional drawing of FIG. 13A. FIG. 6 is a top view showing a manufacturing process of the nonvolatile semiconductor memory device 100 in accordance with the first embodiment. It is A-A 'sectional drawing of FIG. 14A. It is B-B 'sectional drawing of FIG. 14A. FIG. 6 is a top view showing a manufacturing process of the nonvolatile semiconductor memory device 100 in accordance with the first embodiment. It is A-A 'sectional drawing of FIG. 15A. It is B-B 'sectional drawing of FIG. 15A. FIG. 6 is a top view showing a manufacturing process of the nonvolatile semiconductor memory device 100 in accordance with the first embodiment. It is A-A 'sectional drawing of FIG. 16A. It is B-B 'sectional drawing of FIG. 16A. It is a figure which shows the comparative example D1 at the time of read-out operation | movement. It is a figure which shows 1st Embodiment D2 at the time of read-out operation | movement. FIG. 6 is a circuit diagram showing a memory element region 1A of a nonvolatile semiconductor memory device according to a second embodiment of the present invention. FIG. 6 is a top view of a memory element region 1B according to a third embodiment of the present invention. It is A-A 'sectional drawing of FIG. 19A. It is B-B 'sectional drawing of FIG. 19A. It is sectional drawing of 1 C of memory element area | regions concerning 4th Embodiment of this invention. It is sectional drawing of memory element area | region 1D based on 5th Embodiment of this invention.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1, 1A-1D ... Memory element area | region, 2 ... Bit line drive circuit, 3 ... Word line drive circuit, 4 ... Source line drive circuit, 10 ... Wiring layer, 20 ... Selection transistor layer, 30, 30A ... Memory layer, 50 ... Control circuit layer, Ba ... Substrate, MS, MSa ... Memory string, MC1 to MC4, MCa1 to MCa4 ... Memory element, SBD ... Schottky diode, R ... Variable resistance element, 100 ... Nonvolatile semiconductor memory device.

Claims (5)

  1. A plurality of memory element group including a plurality of memory devices,
    The memory element group includes:
    A first columnar layer extending in the stacking direction;
    A first insulating layer that is formed on a side surface of the first columnar layer and functions as a resistance change element, and is destroyed by applying a predetermined voltage ;
    A first conductive layer formed so as to surround the first columnar layer via the first insulating layer,
    The first conductive layer is made of metal,
    The first columnar layer functions as a Schottky diode together with the first conductive layer by contacting the first conductive layer via the destroyed first insulating layer, and an impurity concentration for configuring the Schottky diode A non-volatile semiconductor memory device, comprising:
  2. A control circuit for controlling the memory element group;
    The nonvolatile semiconductor memory device according to claim 1, wherein the control circuit is formed in a lower layer of the memory element group.
  3. A selection transistor connected to one end of the memory element group and controlling conduction to the memory element group;
    The selection transistor is:
    A second columnar layer extending in the stacking direction from the upper surface or the lower surface of the first columnar layer;
    A second insulating layer formed on a side surface of the second columnar layer;
    3. The nonvolatile semiconductor memory device according to claim 1, further comprising: a second conductive layer formed so as to surround the second columnar layer with the second insulating layer interposed therebetween.
  4. A plurality of memory element group including a plurality of memory devices,
    The memory element group includes:
    A first columnar layer extending in the stacking direction;
    A first insulating layer that is formed on a side surface of the first columnar layer and functions as a resistance change element, and is destroyed by applying a predetermined voltage ;
    A first conductive layer formed so as to surround the first columnar layer via the first insulating layer,
    The first columnar layer is made of metal,
    The first conductive layer functions as a Schottky diode together with the first columnar layer by contacting the first columnar layer via the destroyed first insulating layer, and an impurity concentration for configuring the Schottky diode A non-volatile semiconductor memory device, comprising:
  5. A control circuit for controlling the memory element group;
    The nonvolatile semiconductor memory device according to claim 4, wherein the control circuit is formed in a lower layer of the memory element group.
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US8461566B2 (en) * 2009-11-02 2013-06-11 Micron Technology, Inc. Methods, structures and devices for increasing memory density
KR101738533B1 (en) * 2010-05-24 2017-05-23 삼성전자 주식회사 Stacked memory devices and method of manufacturing the same
KR101811308B1 (en) 2010-11-10 2017-12-27 삼성전자주식회사 Non-volatile memory device having resistance changeable element and method of forming the same
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US8891277B2 (en) * 2011-12-07 2014-11-18 Kabushiki Kaisha Toshiba Memory device
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US8971092B2 (en) * 2013-02-28 2015-03-03 Kabushiki Kaisha Toshiba Semiconductor memory device
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