JP5268962B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP5268962B2 JP5268962B2 JP2010026686A JP2010026686A JP5268962B2 JP 5268962 B2 JP5268962 B2 JP 5268962B2 JP 2010026686 A JP2010026686 A JP 2010026686A JP 2010026686 A JP2010026686 A JP 2010026686A JP 5268962 B2 JP5268962 B2 JP 5268962B2
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- insulating film
- gate insulating
- semiconductor device
- gate
- film
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- 229910004143 HfON Inorganic materials 0.000 description 1
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- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
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- 238000011835 investigation Methods 0.000 description 1
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- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
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- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
以下に、本発明の第1の実施形態に係る半導体装置の構成について、図3及び図4(a) 〜(d) を参照しながら説明する。図3は、本発明の第1の実施形態に係る半導体装置の構成を示す平面図である。図4(a) は、本発明の第1の実施形態に係る半導体装置の構成を示すゲート幅方向の断面図である。図4(b) 〜(d) は、本発明の第1の実施形態に係る半導体装置の構成を示すゲート長方向の断面図である。具体的には、図4(a) 〜(d) は、それぞれ、図3に示すIVa-IVa線、IVb-IVb線、IVc-IVc線及びIVd-IVd線のそれぞれにおける断面図である。図3及び図4(a) において、左側にNMIS領域を示し、右側にPMIS領域を示す。「NMIS領域」とは、n型の第1のMISトランジスタが形成される領域をいう。「PMIS領域」とは、p型の第2のMISトランジスタが形成される領域をいう。
d1<0.5s
の関係式が成り立っている。
d1≦0.5(s−h)
の関係式が成り立っている。
d1<d2
の関係式が成り立っている。
d3≦d1
の関係式が成り立っている。
d4≦d2
の関係式が成り立っている。
d1<0.5s
の関係式が成り立っている。
d1≦0.5(s−h)
の関係式が成り立っている。
d1<d2
の関係式が成り立っている。
d3≦d1
の関係式が成り立っている。
d4≦d2
の関係式が成り立っている。
以下に、本発明の第2の実施形態に係る半導体装置の製造方法について、図19及び図20(a) 〜(d) 、図21及び図22(a) 〜(d) 、図23及び図24(a) 〜(d) 並びに図25及び図26(a) 〜(d) を参照しながら説明する。図19、図21、図23及び図25は、本発明の第2の実施形態に係る半導体装置の製造方法を工程順に示す平面図である。図20(a) 、図22(a) 、図24(a) 及び図26(a) は、本発明の第2の実施形態に係る半導体装置の製造方法を工程順に示すゲート幅方向の断面図である。図20(b) 〜(d) 、図22(b) 〜(d) 、図24(b) 〜(d) 及び図26(b) 〜(d) は、本発明の第2の実施形態に係る半導体装置の製造方法を工程順に示すゲート長方向の断面図である。具体的には、図20(a) 、図22(a) 、図24(a) 、図26(a) は、それぞれ、図19に示すXXa-XXa線、図21に示すXXIIa-XXIIa線、図23に示すXXIVa-XXIVa線、図25に示すXXVIa-XXVIa線のそれぞれにおける断面図である。図20(b) 、図22(b) 、図24(b) 、図26(b) は、それぞれ、図19に示すXXb-XXb線、図21に示すXXIIb-XXIIb線、図23に示すXXIVb-XXIVb線、図25に示すXXVIb-XXVIb線のそれぞれにおける断面図である。図20(c) 、図22(c) 、図24(c) 、図26(c) は、それぞれ、図19に示すXXc-XXc線、図21に示すXXIIc-XXIIc線、図23に示すXXIVc-XXIVc線、図25に示すXXVIc-XXVIc線のそれぞれにおける断面図である。図20(d) 、図22(d) 、図24(d) 、図26(d) は、それぞれ、図19に示すXXd-XXd線、図21に示すXXIId-XXIId線、図23に示すXXIVd-XXIVd線、図25に示すXXVId-XXVId線のそれぞれにおける断面図である。図19〜図26(d) において、第1の実施形態における構成要素と同一の構成要素には、図5〜図18(d) における符号と同一の符号を付す。従って、本実施形態では、第1の実施形態と同様の説明を適宜省略する。
d1<0.5s
の関係式が成り立っている。
d1≦0.5(s−h)
の関係式が成り立っている。
d1<d2
の関係式が成り立っている。
d3≦d1
の関係式が成り立っている。
d4≦d2
の関係式が成り立っている。
以下に、本発明の第2の実施形態の変形例に係る半導体装置の製造方法について、図27及び図28(a) 〜(d) 並びに図29及び図30(a) 〜(d) を参照しながら説明する。図27及び図29は、本発明の第2の実施形態の変形例に係る半導体装置の製造方法を工程順に示す平面図である。図28(a) 及び図30(a) は、本発明の第2の実施形態の変形例に係る半導体装置の製造方法を工程順に示すゲート幅方向の断面図である。図28(b) 〜(d) 及び図30(b) 〜(d) は、本発明の第2の実施形態の変形例に係る半導体装置の製造方法を工程順に示すゲート長方向の断面図である。具体的には、図28(a) 及び図30(a) は、それぞれ、図27に示すXXVIIIa-XXVIIIa線及び図29に示すXXXa-XXXa線のそれぞれにおける断面図である。図28(b) 及び図30(b) は、それぞれ、図27に示すXXVIIIb-XXVIIIb線及び図29に示すXXXb-XXXb線のそれぞれにおける断面図である。図28(c) 及び図30(c) は、それぞれ、図27に示すXXVIIIc-XXVIIIc線及び図29に示すXXXc-XXXc線のそれぞれにおける断面図である。図28(d) 及び図30(d) は、それぞれ、図27に示すXXVIIId-XXVIIId線及び図29に示すXXXd-XXXd線のそれぞれにおける断面図である。図27〜図30(d) において、第2の実施形態における構成要素と同一の構成要素には、図19〜図26(d) に示す符号と同一の符号を付す。従って、本変形例では、第2の実施形態と同様の説明を適宜省略する。
11 素子分離領域
11L 第1の素子分離領域
11M 第2の素子分離領域
11N 第3の素子分離領域
12a p型ウェル領域
12b n型ウェル領域
13 高誘電率膜
13x 第1の高誘電率膜
13y 第2の高誘電率膜
14 第2の調整用金属膜
13X 第1のゲート絶縁膜用膜
14Y 第2のゲート絶縁膜用膜
13a 第1の高誘電率膜
13b 第2の高誘電率膜
14b 第2の調整用金属膜
13A 第1のゲート絶縁膜
14B 第2のゲート絶縁膜
15 保護膜
16 第1の調整用金属膜
17 金属膜
18 シリコン膜
18Z ゲート電極用膜
17a 第1の金属膜
17b 第2の金属膜
18a 第1のシリコン膜
18b 第2のシリコン膜
18A 第1のゲート電極
18B 第2のゲート電極
19a n型エクステンション注入領域
19b p型エクステンション注入領域
20a 第1の内側サイドウォール
20b 第2の内側サイドウォール
20c 内側サイドウォール
21a 第1の外側サイドウォール
21b 第2の外側サイドウォール
21c 外側サイドウォール
21A 第1のサイドウォール
21B 第2のサイドウォール
21C サイドウォール
22a n型ソースドレイン注入領域
22b p型ソースドレイン注入領域
23a n型エクステンション領域
23b p型エクステンション領域
24a n型ソースドレイン領域
24b p型ソースドレイン領域
25a 第1のシリサイド膜
25b 第2のシリサイド膜
26a 第3のシリサイド膜
26b 第4のシリサイド膜
27 層間絶縁膜
28 コンタクトホール
29 コンタクトプラグ
30 応力絶縁膜
50 半導体基板
50x 活性領域
51 素子分離領域
52a,52b Laを含む高誘電率膜
52A,52B ゲート絶縁膜
53a,53b 金属膜
54a,54b シリコン膜
54A,54B ゲート電極
Re レジストパターン
Re1 第1のレジストパターン
Re2 第2のレジストパターン
d1〜d4,d1x〜d4x 突き出し量
s 距離
h,hx 距離
D1〜D4 距離
Claims (12)
- 第1導電型の第1のMISトランジスタと第2導電型の第2のMISトランジスタとを備えた半導体装置において、
前記第1のMISトランジスタは、
半導体基板における素子分離領域に囲まれた第1の活性領域上に形成され、第1の高誘電率膜を有する第1のゲート絶縁膜と、
前記第1のゲート絶縁膜上に形成された第1のゲート電極と、
前記第1のゲート電極におけるゲート長方向の側面上に形成された第1のサイドウォールとを備え、
前記第2のMISトランジスタは、
前記半導体基板における前記素子分離領域に囲まれた第2の活性領域上に形成され、第2の高誘電率膜を有する第2のゲート絶縁膜と、
前記第2のゲート絶縁膜上に形成された第2のゲート電極と、
前記第2のゲート電極におけるゲート長方向の側面上に形成された第2のサイドウォールとを備え、
前記第1のゲート絶縁膜と前記第2のゲート絶縁膜とは、前記第1の活性領域と前記第2の活性領域との間に位置する前記素子分離領域における第1の素子分離領域上において分離されており、
前記第2の活性領域は、前記第1の活性領域から見てゲート幅方向に前記第1の素子分離領域を挟んで配置されており、
前記第1のゲート電極におけるゲート幅方向の側面上には前記第1のサイドウォールが形成されておらず、
前記第2のゲート電極におけるゲート幅方向の側面上には前記第2のサイドウォールが形成されておらず、
前記第1の素子分離領域を挟んで対向する前記第1の活性領域の一端と前記第2の活性領域の一端との距離をsとし、前記第1の活性領域の一端から前記第1の素子分離領域上に位置する前記第1のゲート絶縁膜の一端までの突き出し量をd1としたとき、
d1<0.5s
の関係式が成り立っていることを特徴とする半導体装置。 - 請求項1に記載の半導体装置において、
前記第1のゲート絶縁膜の一端と前記第1の素子分離領域上に位置する前記第2のゲート絶縁膜の一端との距離をhとしたとき、
d1≦0.5(s−h)
の関係式が成り立っていることを特徴とする半導体装置。 - 請求項1又は2に記載の半導体装置において、
前記第2の活性領域の一端から前記第1の素子分離領域上に位置する前記第2のゲート絶縁膜の一端までの突き出し量をd2としたとき、
d1<d2
の関係式が成り立っていることを特徴とする半導体装置。 - 請求項1〜3のうちいずれか1項に記載の半導体装置において、
前記第1の活性領域の他端から前記素子分離領域における第2の素子分離領域上に位置する前記第1のゲート絶縁膜の他端までの突き出し量をd3としたとき、
d3≦d1
の関係式が成り立っていることを特徴とする半導体装置。 - 請求項1〜4のうちいずれか1項に記載の半導体装置において、
前記第2の活性領域の一端から前記第1の素子分離領域上に位置する前記第2のゲート絶縁膜の一端までの突き出し量をd2とし、前記第2の活性領域の他端から前記素子分離領域における第3の素子分離領域上に位置する前記第2のゲート絶縁膜の他端までの突き出し量をd4としたとき、
d4≦d2
の関係式が成り立っていることを特徴とする半導体装置。 - 請求項1〜5のうちいずれか1項に記載の半導体装置において、
前記第1のゲート電極と前記第2のゲート電極とは、前記第1の素子分離領域上において分離されており、
前記第1の素子分離領域上に、前記第1のゲート電極の端部と前記第2のゲート電極の端部とに跨って形成されたコンタクトプラグをさらに備えていることを特徴とする半導体装置。 - 請求項1〜6のうちいずれか1項に記載の半導体装置において、
前記第1のMISトランジスタは、n型MISトランジスタであり、
前記第2のMISトランジスタは、p型MISトランジスタであることを特徴とする半導体装置。 - 請求項1〜7のうちいずれか1項に記載の半導体装置において、
前記第1のゲート絶縁膜は第1の調整用金属を含み、
前記第2のゲート絶縁膜は前記第1の調整用金属を含まないことを特徴とする半導体装置。 - 請求項8に記載の半導体装置において、
前記第1の調整用金属はLaであることを特徴とする半導体装置。 - 請求項1〜9のうちいずれか1項に記載の半導体装置において、
前記第2のゲート絶縁膜は第2の調整用金属を含み、
前記第1のゲート絶縁膜は前記第2の調整用金属を含まないことを特徴とする半導体装置。 - 請求項10に記載の半導体装置において、
前記第2の調整用金属はAlであることを特徴とする半導体装置。 - 請求項1〜11のうちいずれか1項に記載の半導体装置において、
前記第1のゲート電極は、前記第1のゲート絶縁膜上に形成された第1の金属膜と、前記第1の金属膜上に形成された第1のシリコン膜とを有し、
前記第2のゲート電極は、前記第2のゲート絶縁膜上に形成された第2の金属膜と、前記第2の金属膜上に形成された第2のシリコン膜とを有することを特徴とする半導体装置。
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US20120280328A1 (en) | 2012-11-08 |
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