JP5245989B2 - Method for manufacturing power module substrate and method for manufacturing power module substrate with heat sink - Google Patents

Method for manufacturing power module substrate and method for manufacturing power module substrate with heat sink Download PDF

Info

Publication number
JP5245989B2
JP5245989B2 JP2009085645A JP2009085645A JP5245989B2 JP 5245989 B2 JP5245989 B2 JP 5245989B2 JP 2009085645 A JP2009085645 A JP 2009085645A JP 2009085645 A JP2009085645 A JP 2009085645A JP 5245989 B2 JP5245989 B2 JP 5245989B2
Authority
JP
Japan
Prior art keywords
film
power module
aluminum
sio
module substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2009085645A
Other languages
Japanese (ja)
Other versions
JP2010238932A (en
Inventor
宗太郎 大井
Original Assignee
三菱マテリアル株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 三菱マテリアル株式会社 filed Critical 三菱マテリアル株式会社
Priority to JP2009085645A priority Critical patent/JP5245989B2/en
Publication of JP2010238932A publication Critical patent/JP2010238932A/en
Application granted granted Critical
Publication of JP5245989B2 publication Critical patent/JP5245989B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation

Description

The present invention relates to a method for manufacturing a power module substrate used in a semiconductor device that controls a large current and a high voltage , and a method for manufacturing a power module substrate with a heat sink .

A power module for supplying power among semiconductor elements has a relatively high calorific value. For example, an Al (aluminum) metal plate is formed on a ceramic substrate made of AlN (aluminum nitride). A power module substrate bonded via a Si-based brazing material is used.
This metal plate is used as a circuit layer, and a semiconductor element as a power element is mounted on the circuit layer via a solder material. It has been proposed that a metal plate made of Al or the like is bonded to the lower surface of the ceramic substrate to form a metal layer for heat dissipation, and a heat sink is bonded via the metal layer.

Here, in the circuit layer made of aluminum, since an aluminum oxide film (passive film) is formed on the surface, it may not be possible to satisfactorily join the solder material.
Therefore, conventionally, as disclosed in, for example, Patent Document 1, a Ni plating film is formed on the surface of a circuit layer by electroless plating or the like, and a solder material is disposed on the Ni plating film to provide a semiconductor element. It was joined.
Patent Document 2 proposes a technique for joining semiconductor elements using Ag nanopaste without using a solder material.

JP 2006-216659 A JP 2006-202938 A

  By the way, as described in Patent Document 1, when a Ni plating film is formed on the surface of the circuit layer, the Ni plating film deteriorates if brazing or the like is performed after the Ni plating film is formed. After the module substrate and the heat sink were brazed to form the power module substrate with the heat sink, the entire power module substrate with the heat sink was immersed in the plating bath. For this reason, the Ni plating film is also formed on portions other than the circuit layer. Here, when the heat sink is made of aluminum and an aluminum alloy, there is a possibility that electrolytic corrosion may proceed between the heat exchanger made of aluminum and the Ni plating film, so a Ni plating film is formed on the heat sink portion. It was necessary to perform a masking process so as not to occur. As described above, since the plating process is performed after the masking process is performed, a great amount of labor is required to form the Ni plating film on the circuit layer portion.

  On the other hand, as disclosed in Patent Document 2, when joining semiconductor elements using Ag nano paste without using a solder material, it is not necessary to form a Ni plating film. However, when the Ag nanopaste is used, the organic solvent contained in the Ag nanopaste remains, resulting in a bubble defect after bonding, and a decrease in strength at the junction between the circuit layer and the semiconductor element. There was a risk of degradation of the thermal and thermal characteristics. Further, in the case of Ag nano paste, since the thickness is formed thinner than that of the solder material, the stress at the time of thermal cycle load tends to act on the semiconductor element, and the semiconductor element itself may be damaged.

The present invention has been made in view of the above-described circumstances, and manufacture of a power module substrate for manufacturing a power module substrate capable of easily and reliably joining a semiconductor element on a circuit layer. It is an object of the present invention to provide a method and a method for manufacturing a power module substrate with a heat sink .

In order to solve the above-described problems and achieve the above-described object, in the method for manufacturing a power module substrate of the present invention, a circuit layer made of aluminum or an aluminum alloy is disposed on one surface of the ceramic substrate. A method for manufacturing a power module substrate , comprising: a plating step of forming a metal plating film on a surface of an aluminum plate or an aluminum alloy plate serving as a circuit layer; and a SiO 2 coating for forming a SiO 2 coating on the metal plating film The aluminum plate or the aluminum alloy plate on which the metal plating film and the SiO 2 film are formed is laminated on the ceramic substrate through a brazing material, and cooled after pressurization / heating, thereby forming the aluminum plate or the A step of joining the aluminum alloy plate and the ceramic substrate, and before being formed on the metal plating film It is characterized in that it comprises a SiO 2 film removal step of removing the SiO 2 film, a.

According to the method for manufacturing a power module substrate having this configuration, since the metal plating film and the SiO 2 film are formed on one surface of the circuit layer, the power module substrate When brazing to a heat sink, the deterioration of the metal plating film is prevented by the SiO 2 film . Moreover, since the metal plating film is exposed by removing the SiO 2 film , the semiconductor element can be reliably bonded by disposing a solder material on the metal plating film . In addition, since the solder material is used, it is possible to increase the thickness of the solder material, to suppress the stress acting on the semiconductor element during thermal cycle load, and to prevent damage to the semiconductor element itself Can do.

Here, the metal plating film is preferably a Ni plating film or a Cu plating film.
In this case, since the circuit layer is previously subjected to the Ni plating process or the Cu plating process, it is not necessary to perform the Ni plating process or the Cu plating process after brazing the heat sink. Also, Ni or Cu has good bondability with, for example, Sn-Ag, Sn-In, or Sn-Ag-Cu solder materials, and semiconductor elements can be reliably bonded using these solder materials. can do.

In addition, since the SiO 2 film is excellent in heat resistance, it is possible to reliably prevent deterioration of the metal plating film even if a process involving heat treatment such as brazing is performed. Further, the SiO 2 film can be easily removed by, for example, irradiation with a semiconductor laser or blasting, and the semiconductor element can be reliably bonded with a solder material by exposing the metal plating film .

Here, before the plating step, between the surface of the aluminum plate or aluminum alloy plate to be the circuit layer and the metal plating film, there is conductivity, and aluminum and the metal constituting the metal plating film It is preferable to provide a diffusion preventing film forming step of forming a diffusion preventing film for preventing diffusion of the above .
When the aluminum constituting the circuit layer and the metal element constituting the metal plating film are likely to diffuse, these metal elements may be interdiffused and alloyed by heat treatment such as brazing. For this reason, it is preferable to provide a diffusion prevention film between the circuit layer surface and the metal plating film to prevent alloying. When the metal plating film is made of Ni, it is preferable to form a Ti film or a Pt film as the diffusion preventing film .

A method for manufacturing a power module substrate with a heat sink according to the present invention is a method for manufacturing a power module substrate with a heat sink using the power module substrate manufactured by the method for manufacturing a power module substrate described above. A heat sink joining step for joining a heat sink to the other surface side of the ceramic substrate of the power module substrate is provided before the two- film removal step .
In this case, in the heat sink joining process for joining the heat sink, the deterioration of the metal plating film formed on the circuit layer by the SiO 2 film is prevented, and the semiconductor element is placed on the circuit layer by the subsequent protective film removing process and the solder joining process. Can be reliably bonded.
In addition, according to the method for manufacturing a power module substrate with a heat sink having this configuration, a metal film having good bonding property to the solder material and a protective film for protecting the metal film are formed on the circuit layer in advance. By simply removing the protective film, the semiconductor element can be joined via the solder material.
Note that the heat sink does not need to be directly bonded to the other surface of the ceramic substrate, but via a metal layer made of aluminum or aluminum alloy, or a buffer layer made of aluminum, an aluminum alloy, or a composite material containing aluminum (for example, AlSiC). The other surface of the ceramic substrate may be bonded.

ADVANTAGE OF THE INVENTION According to this invention, the manufacturing method of the board | substrate for power modules which manufactures the board | substrate for power modules which can join a semiconductor element on a circuit layer easily and reliably, and the manufacturing method of the board | substrate for power modules with a heat sink Can be provided.

It is a schematic explanatory drawing of the power module using the board | substrate for power modules which is embodiment of this invention. It is explanatory drawing which shows the board | substrate for power modules which is embodiment of this invention. FIG. 3 is an enlarged explanatory diagram of a circuit layer surface in the power module substrate of FIG. 2. It is a flowchart which shows the manufacturing method of the board | substrate for power modules of FIG. It is a flowchart which shows the manufacturing method of the power module which is embodiment of this invention.

Embodiments of the present invention will be described below with reference to the accompanying drawings. FIG. 1 shows a power module according to an embodiment of the present invention.
The power module 1 includes a power module substrate 10 on which a circuit layer 12 is disposed, a semiconductor chip 3 bonded to the surface of the circuit layer 12 via a solder material 2, and a heat sink 4.

The power module substrate 10 has a ceramic substrate 11, a circuit layer 12 disposed on one surface (the upper surface in FIG. 1) of the ceramic substrate 11, and the other surface (lower surface in FIG. 1) of the ceramic substrate 11. And a disposed metal layer 13.
The ceramic substrate 11 prevents electrical connection between the circuit layer 12 and the metal layer 13, and is made of highly insulating AlN (aluminum nitride). In addition, the thickness of the ceramic substrate 11 is set within a range of 0.2 to 1.5 mm, and in this embodiment is set to 0.635 mm. In the present embodiment, as shown in FIG. 1, the width of the ceramic substrate 11 is set wider than the widths of the circuit layer 12 and the metal layer 13.

  The circuit layer 12 is formed by bonding a conductive metal plate 22 to one surface of the ceramic substrate 11. In the present embodiment, the circuit layer 12 is formed by joining a metal plate 22 made of a rolled plate of aluminum (so-called 4N aluminum) having a purity of 99.99% or more to the ceramic substrate 11.

  The metal layer 13 is formed by bonding a metal plate 23 to the other surface of the ceramic substrate 11. In the present embodiment, the metal layer 13 is formed by joining a metal plate 23 made of a rolled plate of aluminum (so-called 4N aluminum) having a purity of 99.99% or more, like the circuit layer 12, to the ceramic substrate 11. Is formed.

The heat sink 4 is for cooling the power module substrate 10 described above. The heat sink 4 is joined to the power module substrate 10, and the heat dissipated downward from the top plate 5. The fin 6 and the flow path 7 for distribute | circulating a cooling medium (for example, cooling water) are provided. The heat sink 4 (top plate portion 5) is preferably made of a material having good thermal conductivity, and in this embodiment, is made of A6063 (aluminum alloy).
In the present embodiment, a buffer layer 15 made of aluminum, an aluminum alloy, or a composite material containing aluminum (for example, AlSiC) is provided between the top plate portion 5 of the heat sink 4 and the metal layer 13. .

In the power module 1 shown in FIG. 1, a Ni plating film 32 is formed on the surface of the circuit layer 12 (upper surface in FIG. 1). And the solder material 2 is arrange | positioned on the surface of this Ni plating film 32, and the semiconductor chip 3 is joined. Here, as a solder material, the joining property with Ni is favorable, for example, Sn-Ag system, Sn-In system, or Sn-Ag-Cu system is mentioned.
In the present embodiment, as shown in FIG. 1, the Ni plating film 32 is formed only on the surface of the circuit layer 12, and the Ni plating film is formed on the other portions of the power module substrate 10 and the heat sink 4. Is not formed.

2 and 3 show the power module substrate 10 before the semiconductor chip 3 is joined by the solder material 2.
In this power module substrate 10, a diffusion prevention film 31 is formed on the surface of the circuit layer 12 (upper surface in FIGS. 2 and 3), a Ni plating film 32 is formed on the diffusion prevention film 31, and A SiO 2 film 33 is formed on the Ni plating film 32 as a protective film.

  The diffusion prevention film 32 is provided to prevent Al constituting the circuit layer 12 and Ni of the Ni plating film 32 from diffusing with each other. Has been. In the present embodiment, the thickness td of the diffusion preventing film 31 is set to 0.5 μm ≦ td ≦ 5 μm.

The Ni plating film 32 is formed by an electrolytic plating method or an electroless plating method, and the thickness tm thereof is set to 3 μm ≦ tm ≦ 10 μm.
The SiO 2 film 33 is formed to cover and protect the Ni plating film 32, and its thickness tp is set to 10 nm ≦ tp ≦ 300 nm.

Next, a method for manufacturing the power module substrate will be described with reference to a flowchart shown in FIG.
First, an aluminum plate to be the circuit layer 12 is prepared, and a diffusion prevention film 31 made of Ti is formed on the surface of the aluminum plate ( diffusion prevention film forming step S1 ). The diffusion prevention film 31 can be formed by, for example, vapor deposition or sputtering.

Next, a Ni plating film 32 is formed on the diffusion prevention film 31 by an electrolytic plating method or an electroless plating method (Ni plating film forming step S2).
Further, a SiO 2 film 33 is formed as a protective film on the Ni plating film 32 (SiO 2 film forming step S3). Here, the SiO 2 film 33 can be formed at a processing temperature of 450 ° C. or lower by low-temperature sputtering.

Then, the aluminum plate on which the diffusion preventing film 31 , the Ni plating film 32, and the SiO 2 film 33 are formed is laminated on the ceramic substrate 11 through a brazing material, and is cooled after being pressurized and heated, thereby cooling the aluminum plate The ceramic substrate 11 is joined (joining process S4).
As a result, as shown in FIG. 2, the power module substrate 10 including the circuit layer 12 is produced.

Below, the manufacturing method of the power module 1 using the board | substrate 10 for power modules shown in FIG. 2 is demonstrated with reference to the flowchart shown in FIG.
The power module substrate 10 on which the diffusion prevention film 31, the Ni plating film 32, and the SiO 2 film 33 are formed on the surface of the circuit layer 12 is joined to the top plate portion 5 of the heat sink 4, and the power module substrate with a heat sink is attached. It forms (heat sink joining process S11). At this time, the bonding temperature is 580 ° C. or higher and 650 ° C. or lower.

Next, the SiO 2 film 33 formed on the outermost layer of the circuit layer 12 is removed (SiO 2 film removal step S12). Examples of the method for removing the SiO 2 film 33 include semiconductor laser irradiation, etching with a fluorine-containing solution or gas, and the like. In the present embodiment, the SiO 2 coating 33 is removed by a water jet guide laser processing method in which a water jet is collided and laser light is advanced in the water column of the water jet.

Next, the surface of the Ni plating film 32 exposed to the outside after the SiO 2 film 33 is removed is cleaned (cleaning step S13). In this embodiment, as described above, since the SiO 2 film 33 is removed by the water jet / guide laser processing method, the surface of the Ni plating film 32 is cleaned by this water jet. . That is, in the present embodiment, the SiO 2 film removal step S12 and the cleaning step S13 are performed in the same step.

Then, the semiconductor chip 3 is placed on the surface of the Ni plating film 32 exposed to the outside via the solder material 2 and soldered in a reduction furnace (solder joining step S14).
Thereby, as shown in FIG. 1, the power module 1 in which the semiconductor chip 3 is bonded onto the circuit layer 12 is produced.

In the power module substrate 10 and the power module 1 according to the present embodiment configured as described above, the Ni plating film 32 having a good bondability with the solder material 2 is formed on the surface of the circuit layer 12, Since the SiO 2 film 33 is formed on the Ni plating film 32 as a protective film for covering and protecting the Ni plating film 32, the power module substrate 10 is placed on the top plate portion 5 of the heat sink 4 at 580. Even when brazing is performed at a temperature of not lower than 650 ° C. and not higher than 650 ° C., the Ni plating film 32 can be prevented from being deteriorated by the SiO 2 film 33 having high heat resistance.

Therefore, by removing the SiO 2 film 33 after brazing the heat sink 4, the Ni plating film 32 having good bonding properties with the solder material 2 is exposed without deterioration, and the solder material 2 causes the semiconductor to be exposed. The chip 3 can be reliably bonded.
In particular, in the present embodiment, since the solder material 2 having good bondability with the Sn-Ag-based, Sn-In-based, or Sn-Ag-Cu-based Ni plating film 32 is used, the semiconductor chip 3 is firmly formed. Can be joined.
Furthermore, since the semiconductor chip 3 is joined using the solder material 2, it becomes possible to form the solder material 2 thick, and it is possible to suppress the stress during the heat cycle load from acting on the semiconductor chip 3, Damage to the semiconductor chip 3 can be prevented.

  Further, in this embodiment, since the diffusion prevention film 31 is formed between the circuit layer 12 and the Ni plating film 32, even if the power module substrate 10 is heated by brazing or the like, the circuit layer 12 and the Ni plating film 32 are prevented from diffusing and the Ni plating film 32 can be prevented from deteriorating.

In the power module manufacturing method according to the present embodiment, the power module substrate 10, the heat sink 4, and the heat module 4 are formed with the diffusion prevention film 31, the Ni plating film 32, and the SiO 2 film 33 formed on the circuit layer 12. Therefore, the Ni plating film 32 is prevented from being deteriorated by the SiO 2 film 33 having high heat resistance.
When the semiconductor chip 3 is bonded, the SiO 2 film 33 is removed by a water jet / guide laser processing method to expose the Ni plating film 32 and the surface of the Ni plating film 32 is washed. By arranging the material 2 on the Ni plating film 32 and bonding the semiconductor chip 3, the semiconductor chip 3 can be firmly bonded. Therefore, the high quality power module 1 can be manufactured easily.

As mentioned above, although embodiment of this invention was described, this invention is not limited to this, It can change suitably in the range which does not deviate from the technical idea of the invention.
For example, the metal plate constituting the circuit layer and the metal layer has been described as a rolled plate of pure aluminum having a purity of 99.99%, but is not limited to this, and aluminum having a purity of 99% (2N aluminum) It may be.

As the protective film, has been described as forming the SiO 2 film is not limited thereto and may be formed DLC film or the Cr film.
In the case of a DLC film, it can be formed by, for example, a CVD method. Further, it can be removed by a semiconductor laser or the like.
In the case of a Cr film, it can be formed by, for example, a plating method. It can also be removed by spraying with weak hydrochloric acid.

Further, the SiO 2 film is described as being removed by the water jet / guide laser processing method, but the present invention is not limited to this, and other means such as a blast method may be used.
Furthermore, after forming a diffusion prevention film, a Ni plating film, and a SiO 2 film on the surface of the aluminum plate to be the circuit layer, the aluminum plate and the ceramic substrate are joined to produce a power module substrate. However, the present invention is not limited to this, and after producing a power module substrate, a diffusion prevention film, a Ni plating film, and a SiO 2 film may be formed on the surface of the circuit layer.

Moreover, although it demonstrated by what formed Ni plating film as a metal film which consists of a metal with favorable joining property with a solder material, it is not limited to this and the joining property with the used solder material is good A metal film made of metal may be formed.
Furthermore, although it demonstrated as what formed Ti film | membrane as a diffusion prevention film | membrane, it is not limited to this. In the case where a Ni plating film is formed on the circuit layer, the Pt film can be formed as a diffusion preventing film.

Moreover, although demonstrated as what provided the buffer layer which consists of aluminum, the aluminum alloy, or the composite material containing aluminum (for example, AlSiC etc.) between the top-plate part of a heat sink and a metal layer, even if this buffer layer is not provided Good.
Furthermore, although the heat sink has been described as being made of aluminum, it may be made of an aluminum alloy or a composite material containing aluminum. Furthermore, although the heat sink has been described as having heat radiation fins and cooling medium flow paths, the structure of the heat sink is not particularly limited.

1 Power Module 2 Solder Material 3 Semiconductor Chip (Semiconductor Element)
4 heat sink 5 top plate 10 power module substrate 11 ceramic substrate 12 circuit layer 13 metal layer 31 diffusion prevention film 32 Ni plating film (metal film)
33 SiO 2 film (protective film)

Claims (3)

  1. A method for manufacturing a power module substrate in which a circuit layer made of aluminum or an aluminum alloy is disposed on one surface of a ceramic substrate,
    A plating step of forming a metal plating film on the surface of an aluminum plate or aluminum alloy plate to be a circuit layer;
    And SiO 2 film forming step of forming a SiO 2 film on the metal plating layer,
    The aluminum plate or aluminum alloy plate on which the metal plating film and the SiO 2 film are formed is laminated on the ceramic substrate via a brazing material, and is cooled after being pressurized and heated, thereby cooling the aluminum plate or the aluminum alloy plate. Bonding the ceramic substrate;
    And SiO 2 film removal step of removing the SiO 2 film formed on the metal plating layer,
    The manufacturing method of the board | substrate for power modules characterized by comprising.
  2. Prior to the plating step, between the surface of the aluminum plate or aluminum alloy plate to be the circuit layer and the metal plating film, there is conductivity, and diffusion of aluminum and the metal constituting the metal plating film is performed. The method for manufacturing a power module substrate according to claim 1, further comprising a diffusion prevention film forming step of forming a diffusion prevention film to be prevented.
  3. A method for producing a power module substrate with a heat sink using the power module substrate produced by the method for producing a power module substrate according to claim 1 or 2,
    SiO 2 A method for manufacturing a substrate for a power module with a heat sink, comprising a heat sink joining step for joining a heat sink to the other surface side of the ceramic substrate of the power module substrate before the film removing step.
JP2009085645A 2009-03-31 2009-03-31 Method for manufacturing power module substrate and method for manufacturing power module substrate with heat sink Active JP5245989B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2009085645A JP5245989B2 (en) 2009-03-31 2009-03-31 Method for manufacturing power module substrate and method for manufacturing power module substrate with heat sink

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2009085645A JP5245989B2 (en) 2009-03-31 2009-03-31 Method for manufacturing power module substrate and method for manufacturing power module substrate with heat sink

Publications (2)

Publication Number Publication Date
JP2010238932A JP2010238932A (en) 2010-10-21
JP5245989B2 true JP5245989B2 (en) 2013-07-24

Family

ID=43092998

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2009085645A Active JP5245989B2 (en) 2009-03-31 2009-03-31 Method for manufacturing power module substrate and method for manufacturing power module substrate with heat sink

Country Status (1)

Country Link
JP (1) JP5245989B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
USRE38087E1 (en) 1993-09-10 2003-04-22 Tokai Rubber Industries, Ltd. Fuel hose and method of its production

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5869781B2 (en) * 2011-05-27 2016-02-24 昭和電工株式会社 Method for manufacturing laminated material for insulating substrate
JP5614423B2 (en) * 2012-03-29 2014-10-29 三菱マテリアル株式会社 Power module substrate and manufacturing method thereof
JP2014112732A (en) * 2012-03-30 2014-06-19 Mitsubishi Materials Corp Substrate for power module with heat sink and power module
JP6152626B2 (en) * 2012-03-30 2017-06-28 三菱マテリアル株式会社 Power module substrate manufacturing method
JP2013229579A (en) 2012-03-30 2013-11-07 Mitsubishi Materials Corp Substrate for power module, substrate for power module having heat sink, and power module
JP6008544B2 (en) * 2012-04-06 2016-10-19 昭和電工株式会社 Insulating substrate manufacturing method
JP5917992B2 (en) * 2012-04-19 2016-05-18 昭和電工株式会社 Insulating substrate manufacturing method
JP5918008B2 (en) * 2012-05-08 2016-05-18 昭和電工株式会社 Manufacturing method of cooler
JP2014072314A (en) 2012-09-28 2014-04-21 Toyota Industries Corp Semiconductor device and semiconductor device manufacturing method

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3025560B2 (en) * 1991-09-18 2000-03-27 日本特殊陶業株式会社 Ceramic wiring board and method of manufacturing the same
JPH07297557A (en) * 1994-04-27 1995-11-10 Hitachi Ltd Manufacture of thick film-thin film hybrid substrate
JPH08250858A (en) * 1995-03-07 1996-09-27 Ngk Spark Plug Co Ltd Circuit board
JPH08255973A (en) * 1995-03-17 1996-10-01 Toshiba Corp Ceramic circuit board
JP5131205B2 (en) * 2009-01-13 2013-01-30 三菱マテリアル株式会社 Power module substrate manufacturing method
JP5131204B2 (en) * 2009-01-13 2013-01-30 三菱マテリアル株式会社 Power module substrate manufacturing method
JP5141566B2 (en) * 2009-01-14 2013-02-13 三菱マテリアル株式会社 Insulated circuit board manufacturing method, insulated circuit board, and power module substrate

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
USRE38087E1 (en) 1993-09-10 2003-04-22 Tokai Rubber Industries, Ltd. Fuel hose and method of its production

Also Published As

Publication number Publication date
JP2010238932A (en) 2010-10-21

Similar Documents

Publication Publication Date Title
JP5614485B2 (en) Power module substrate with heat sink, power module with heat sink, and method for manufacturing power module substrate with heat sink
TWI622138B (en) Power module substrate, power module substrate having heatsink, power module having heatsink
JP4609296B2 (en) High temperature solder, high temperature solder paste material, and power semiconductor device using the same
KR101971756B1 (en) Substrate for power module, substrate for power module with heat sink, power module, and method for manufacturing substrate for power module
KR100758760B1 (en) Circuit device and manufacturing method of the same
US9560755B2 (en) Bonding body, power module substrate, and heat-sink-attached power module substrate
JP4015023B2 (en) Electronic circuit member, its manufacturing method, and electronic component
TWI462236B (en) Sub-mounting sheet and manufacturing method thereof
US9833855B2 (en) Method for manufacturing power module substrate
JP5440721B2 (en) Power module substrate with heat sink and method for manufacturing the same, power module with heat sink, and substrate for power module
US8559475B2 (en) Heat sink and assembly or module unit
DE102006011232B4 (en) Substrate for mounting an electronic component and electronic component
US8486766B2 (en) Method for thermally contacting opposing electrical connections of a semiconductor component arrangement
JP5160201B2 (en) Solder material and manufacturing method thereof, joined body and manufacturing method thereof, power semiconductor module and manufacturing method thereof
JP5128951B2 (en) Heat sink module and manufacturing method thereof
JP5515947B2 (en) Cooling system
JP4904767B2 (en) Semiconductor device
US9480144B2 (en) Power module substrate, power module substrate with heat sink, and power module
US9076755B2 (en) Method for producing substrate for power module with heat sink, substrate for power module with heat sink, and power module
JP5918008B2 (en) Manufacturing method of cooler
JP3922538B2 (en) Manufacturing method of ceramic circuit board
CN102917835B (en) Junction material, manufacturing method thereof, and manufacturing method of junction structure
JP4998404B2 (en) Power module substrate, manufacturing method thereof, and power module
KR20120098575A (en) Electronic device
EP2750173B1 (en) Power semiconductor device with a power semiconductor element bonded to a substrate by a Sn-Sb-Cu solder and with a terminal bonded to the substrate by a Sn-Ag-based or Sn-Ag-Cu-based solder

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20110928

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20121122

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20121127

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20130125

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20130312

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20130325

R150 Certificate of patent or registration of utility model

Ref document number: 5245989

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20160419

Year of fee payment: 3