JP5182783B2 - Soi基板を形成するための方法 - Google Patents
Soi基板を形成するための方法 Download PDFInfo
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- 239000000758 substrate Substances 0.000 title claims description 104
- 238000000034 method Methods 0.000 title claims description 45
- -1 oxygen ions Chemical class 0.000 claims description 139
- 238000005468 ion implantation Methods 0.000 claims description 118
- 239000012212 insulator Substances 0.000 claims description 94
- 229910052757 nitrogen Inorganic materials 0.000 claims description 72
- 239000001301 oxygen Substances 0.000 claims description 72
- 229910052760 oxygen Inorganic materials 0.000 claims description 72
- IJGRMHOSHXDMSA-UHFFFAOYSA-N nitrogen Substances N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 71
- 125000006850 spacer group Chemical group 0.000 claims description 68
- 239000004065 semiconductor Substances 0.000 claims description 48
- 150000002500 ions Chemical class 0.000 claims description 33
- 238000000137 annealing Methods 0.000 claims description 14
- 238000002513 implantation Methods 0.000 description 30
- 239000007943 implant Substances 0.000 description 29
- 239000004020 conductor Substances 0.000 description 23
- 239000000463 material Substances 0.000 description 15
- 230000008569 process Effects 0.000 description 14
- 230000000873 masking effect Effects 0.000 description 11
- 238000005137 deposition process Methods 0.000 description 10
- 239000003989 dielectric material Substances 0.000 description 9
- 238000002955 isolation Methods 0.000 description 9
- 150000004767 nitrides Chemical class 0.000 description 9
- 230000015572 biosynthetic process Effects 0.000 description 8
- 238000005229 chemical vapour deposition Methods 0.000 description 8
- 239000011248 coating agent Substances 0.000 description 7
- 238000000576 coating method Methods 0.000 description 7
- 238000005530 etching Methods 0.000 description 7
- 230000000694 effects Effects 0.000 description 6
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 4
- 238000001020 plasma etching Methods 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000000231 atomic layer deposition Methods 0.000 description 3
- 238000000224 chemical solution deposition Methods 0.000 description 3
- 230000007547 defect Effects 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 230000005669 field effect Effects 0.000 description 3
- 239000011261 inert gas Substances 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 238000001704 evaporation Methods 0.000 description 2
- 230000008020 evaporation Effects 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 2
- 238000005546 reactive sputtering Methods 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000927 Ge alloy Inorganic materials 0.000 description 1
- 229910000673 Indium arsenide Inorganic materials 0.000 description 1
- 229910003811 SiGeC Inorganic materials 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000000280 densification Methods 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000011049 filling Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 229910003465 moissanite Inorganic materials 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 230000000153 supplemental effect Effects 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
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- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
- H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
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- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
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- H01L21/76243—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using silicon implanted buried insulating layers, e.g. oxide layers, i.e. SIMOX techniques
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
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- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
- H01L21/76283—Lateral isolation by refilling of trenches with dielectric material
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- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
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- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823878—Complementary field-effect transistors, e.g. CMOS isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
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- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
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Description
所定の第1、第2、および第3の領域を備える実質的に平坦な上面を有する半導体基板を形成するステップと、
酸素イオンまたは窒素イオンあるいはそれら両方を、半導体基板の第1の領域内ではなく、第2の領域および第3の領域内に選択的に注入するために、1つ以上のイオン注入ステップを実施するステップと、
注入された酸素イオンまたは窒素イオンあるいはそれら両方を埋込み絶縁体に変換するために1つ以上のアニーリング・ステップを実施するステップとを含み、
半導体基板の第1の領域は、いかなる埋込み絶縁体も含まず、半導体基板の第2の領域は、パターン形成された埋込み絶縁体層の第1の部分を実質的に平坦な上面から第1の深さに含み、半導体基板の第3の領域は、パターン形成された埋込み絶縁体層の第2の部分を実質的に平坦な上面から第2の深さに含み、第1の深さは、第2の深さより大きい。
パターン形成された埋込み絶縁体層が内部に設置された実質的に平坦な上面を有するセミコンダクタ・オン・インシュレータ(SOI)基板を形成するステップであって、SOI基板は、どのような埋込み絶縁体も含まない第1の領域と、パターン形成された埋込み絶縁体層の第1の部分を実質的に平坦な上面から第1の深さに含む第2の領域と、パターン形成された埋込み絶縁体層の第2の部分を実質的に平坦な上面から第2の深さに含む第3の領域とを含み、第1の深さは、第2の深さより大きい、ステップと、
1つ以上の電界効果トランジスタ(FET)を形成するステップであって、FETは、
(1)SOI基板の第1の領域中に設置された1つ以上のチャネル領域と、(2)SOI基板の第2の領域中に設置されたソース領域およびドレイン領域と、(3)SOI基板の第3の領域中に設置されたソース拡張領域およびドレイン拡張領域とを含む、ステップとを含む。
11 上面
12 埋込み絶縁体層
20 FET
22A S/D(ソース/ドレイン)領域
22B S/D(ソース/ドレイン)領域
23 チャネル領域
24A S/D(ソース/ドレイン)拡張領域
24B S/D(ソース/ドレイン)拡張領域
26 ゲート導体
28 ゲート電極
30 分離領域
40 FET
42A S/D(ソース/ドレイン)領域
42B S/D(ソース/ドレイン)領域
43 チャネル領域
44A S/D(ソース/ドレイン)拡張領域
44B S/D(ソース/ドレイン)拡張領域
46 ゲート導体
48 ゲート電極
102 薄い誘電体層
104 ブランケット誘導体マスク層
106 誘電体マスク
108 誘電体マスク
110 選択的エッチング可能層
112 誘電体スペーサ
114 誘電体スペーサ
116 酸素イオンまたは窒素イオンあるいはその両方
118 注入イオン層
120 ブランケット・ゲート導体層
122 ブランケット誘電体キャップ層
128 誘電体マスク
130 誘電体マスク
132 選択的エッチング可能層
134 誘電体スペーサ
136 誘電体スペーサ
138 酸素イオンまたは窒素イオンあるいはその両方
140 イオン注入層
150 酸化物層
152 犠牲スペーサ
154 犠牲スペーサ
156 HDP酸化物層
158 HDP酸化物層
160 酸素イオンまたは窒素イオンあるいはその両方
162 イオン注入層
164 誘電体スペーサ
166 誘電体スペーサ
167 酸素イオンまたは窒素イオンあるいはその両方
168 第1の部分
170 レジスト被覆
172 トレンチ
174 酸素イオンまたは窒素イオンあるいはその両方
176 第2の部分
178 酸素イオンまたは窒素イオンあるいはその両方
180 第1の部分
182 酸素イオンまたは窒素イオンあるいはその両方
184 第2の部分
D1 第1の深さ
D2 第2の深さ
T1 第1の厚さ
T2 第2の厚さ
T+ 第2の厚さ
Claims (11)
- セミコンダクタ・オン・インシュレータ(SOI)基板を形成するための方法であって、
実質的に平坦な表面を有する半導体基板を形成するステップと、
前記半導体基板の第1の領域の上にゲート構造を形成するステップと、
前記ゲート構造の側壁を覆う誘電体スペーサを形成し、これにより、前記誘電体スペーサの直下の前記半導体基板の第2の領域と、前記誘電体スペーサの外側の前記半導体基板の第3の領域とが画定される、ステップと、
前記誘電体スペーサが形成された後に、酸素イオンまたは窒素イオンあるいはそれら両方を前記半導体基板の第3の領域にのみ選択的にイオン注入する第1のイオン注入ステップと、
前記半導体基板の第2の領域を露出させるマスクを形成するステップであって、前記誘電体スペーサの部分を除く前記半導体基板の表面を覆うマスク層を形成することと、前記誘電体スペーサを除去して前記第2の領域を露出させることとを含む、ステップと、
酸素イオンまたは窒素イオンあるいはそれら両方を前記半導体基板の前記露出された第2の領域にのみ選択的にイオン注入する第2のイオン注入ステップと、
前記注入された酸素イオンまたは窒素イオンあるいはそれら両方を埋込み絶縁体に変換するために1つ以上のアニーリング・ステップを実施するステップと、を含み、
前記半導体基板の前記第1の領域は、いかなる埋込み絶縁体も含まず、前記半導体基板の前記第2の領域は、パターン形成された埋込み絶縁体層の第1の部分を前記実質的に平坦な上面から第1の深さに含み、前記半導体基板の前記第3の領域は、前記パターン形成された埋込み絶縁体層の第2の部分を前記実質的に平坦な上面から第2の深さに含み、前記第2の深さは、前記第1の深さより大きい、方法。 - 前記マスク層は、レジスト層であり、前記誘電体スペーサは、前記レジスト層に対して選択的に除去される、請求項1に記載の方法。
- 前記第1のイオン注入ステップにおいて、前記半導体基板の前記第3の領域は、酸素イオンまたは窒素イオンあるいはその両方が前記第3の領域中の前記第2の深さに注入され、
前記第2のイオン注入ステップにおいて、前記半導体基板の前記第2の領域は、酸素イオンまたは窒素イオンあるいはその両方が前記第2の領域中の前記第1の深さに注入される、請求項1に記載の方法。 - 前記誘電体スペーサは、100nm〜2000nmの範囲の厚さを有する、請求項1に記載の方法。
- 前記第1のイオン注入ステップにおいて、酸素イオンまたは窒素イオンあるいはその両方が前記半導体基板のソースおよびドレイン領域に注入される、請求項1に記載の方法。
- 前記第2の深さは、20nm〜200nmの範囲である、請求項5に記載の方法。
- 前記第1の深さは、10nm〜100nmの範囲である、請求項5に記載の方法。
- 前記パターン形成された埋込み絶縁体層の前記第1および第2の部分は、10nm〜200nmの範囲の平均厚さを有する、請求項1に記載の方法。
- 前記パターン形成された埋込み絶縁体層の前記第1の部分は、10nm〜200nmの範囲の平均厚さを有し、前記パターン形成された埋込み絶縁体層の前記第2の部分は、20nm〜400nmの範囲の平均厚さを有する、請求項1に記載の方法。
- 前記第1のイオン注入ステップおよび前記第2のイオン注入ステップは、60KeV〜200KeVのエネルギー・レベルを有するエネルギー・ビームおよび5.0×1016/cm2〜5.0×1018/cm2のドーズ量を用いておこなわれる、請求項5に記載の方法。
- 前記アニーリング・ステップは、1250℃以上の温度でおこなわれる、請求項5に記載の方法。
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