JP5165215B2 - ページバッファとそれを含む不揮発性メモリ装置 - Google Patents
ページバッファとそれを含む不揮発性メモリ装置 Download PDFInfo
- Publication number
- JP5165215B2 JP5165215B2 JP2006177272A JP2006177272A JP5165215B2 JP 5165215 B2 JP5165215 B2 JP 5165215B2 JP 2006177272 A JP2006177272 A JP 2006177272A JP 2006177272 A JP2006177272 A JP 2006177272A JP 5165215 B2 JP5165215 B2 JP 5165215B2
- Authority
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- Japan
- Prior art keywords
- memory device
- latch circuit
- page buffer
- circuit
- bit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- 230000015654 memory Effects 0.000 claims description 69
- 238000012795 verification Methods 0.000 claims description 18
- 230000004044 response Effects 0.000 claims description 14
- 230000008569 process Effects 0.000 claims description 9
- 238000010586 diagram Methods 0.000 description 40
- 238000009826 distribution Methods 0.000 description 18
- 238000000034 method Methods 0.000 description 9
- 239000000758 substrate Substances 0.000 description 8
- 230000005540 biological transmission Effects 0.000 description 5
- 230000000903 blocking effect Effects 0.000 description 4
- 238000011084 recovery Methods 0.000 description 4
- 230000004913 activation Effects 0.000 description 3
- 230000006870 function Effects 0.000 description 3
- 230000005641 tunneling Effects 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 230000009471 action Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000010924 continuous production Methods 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 229920001690 polydopamine Polymers 0.000 description 1
- 230000002250 progressing effect Effects 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
- G11C11/5628—Programming or writing circuits; Data input circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/26—Sensing or reading circuits; Data output circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
- G11C2211/564—Miscellaneous aspects
- G11C2211/5642—Multilevel memory with buffers, latches, registers at input or output
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2216/00—Indexing scheme relating to G11C16/00 and subgroups, for features not directly covered by these groups
- G11C2216/12—Reading and writing aspects of erasable programmable read-only memories
- G11C2216/14—Circuits or methods to write a page or sector of information simultaneously into a nonvolatile memory, typically a complete row or word line in flash memory
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Read Only Memory (AREA)
Description
200 メインラッチ
300 キャッチラッチ
400 バイアス及び選択回路
500 スィッチ回路
600 行デコーダ
700 感知部
800 プリチャージ
900 出力駆動部
1000 デコーダ
Claims (10)
- メインラッチ回路と、
キャッシュラッチ回路と、
感知ノード及び前記キャッシュラッチ回路の電圧に回答して前記メインラッチ回路を参照電位に選択的に連結する共有感知回路と、
初期感知制御信号に応答して、前記メインラッチ回路を前記キャッシュラッチ回路に選択的に連結するスイッチ回路と、を含む
ことを特徴とする不揮発性メモリ装置のページバッファ。 - 前記メモリ装置は単一レベルセルSLCモードとマルチレベルセルMLCモードの両方で動作する
ことを特徴とする請求項1に記載の不揮発性メモリ装置のページバッファ。 - 前記SLCモードはプログラムデータが前記キャッシュラッチ回路にあらかじめローディング(事前ロード)されるSLCプログラム過程を含む
ことを特徴とする請求項2に記載の不揮発性メモリ装置のページバッファ。 - 前記MLCモードはLSBプログラム過程と後に従うMSBプログラム過程を含むMLCプログラム動作を含む
ことを特徴とする請求項2に記載の不揮発性メモリ装置のページバッファ。 - 前記MSBプログラム過程は初期読み出し動作を含み、
前記初期読み出し動作は、前記スイッチ回路が制御信号に回答して前記キャッシュラッチ回路を前記メインラッチ回路に連結し、前記共有感知回路が前記感知ノードの電圧に回答して前記メインラッチ回路を前記参照電位に選択的に連結する
ことを特徴とする請求項4に記載の不揮発性メモリ装置のページバッファ。 - 前記MSBプログラム過程は前記初期の読み出し動作以後に、メモリセルがプログラムされるMSBプログラム動作及び前記プログラムされたメモリセルを検証する少なくとも一度のMSB検証動作をさらに含む
ことを特徴とする請求項5に記載の不揮発性メモリ装置のページバッファ。 - 前記MLCモードで、前記不揮発性メモリセルは第1、第2、第3、第4閾値電圧の状態の中で少なくとも一つの状態で選択的にプログラムされ、
前記第1、第2、第3、第4閾値電圧状態はデータ値“11”、“10”、“00”、そして“01”をそれぞれ規定する
ことを特徴とする請求項6に記載の不揮発性メモリ装置のページバッファ。 - 前記少なくとも一度のMSB検証動作は“00”検証動作を含み、
前記“00”検証動作は前記スイッチ回路が制御信号に回答して前記キャッシュラッチ回路と前記メインラッチ回路を遮断し、前記共有感知回路が前記感知ノード及び前記キャッシュラッチ回路の電圧に回答して前記メインラッチ回路を前記参照電位に選択的に連結する
ことを特徴とする請求項7に記載の不揮発性メモリ装置のページバッファ。 - 前記少なくとも一度のMSB検証動作は、前記スイッチ回路が前記キャッシュラッチ回路と前記メインラッチ回路を遮断する“01”検証動作を含む
ことを特徴とする請求項8に記載の不揮発性メモリ装置のページバッファ。 - 前記不揮発性メモリ装置はナンドタイプフラッシュメモリセルを含む
ことを特徴とする請求項1に記載の不揮発性メモリ装置のページバッファ。
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020050059779A KR100634458B1 (ko) | 2005-07-04 | 2005-07-04 | 단일의 페이지 버퍼 구조로 멀티-비트 및 단일-비트프로그램 동작을 수행하는 플래시 메모리 장치 |
KR10-2005-0059779 | 2005-07-04 | ||
US11/416,320 US7391649B2 (en) | 2005-07-04 | 2006-05-03 | Page buffer and non-volatile memory device including the same |
US11/416,320 | 2006-05-03 |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2012228629A Division JP5383889B2 (ja) | 2005-07-04 | 2012-10-16 | ページバッファとそれを含む不揮発性メモリ装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2007018689A JP2007018689A (ja) | 2007-01-25 |
JP5165215B2 true JP5165215B2 (ja) | 2013-03-21 |
Family
ID=37697497
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2006177272A Active JP5165215B2 (ja) | 2005-07-04 | 2006-06-27 | ページバッファとそれを含む不揮発性メモリ装置 |
Country Status (2)
Country | Link |
---|---|
JP (1) | JP5165215B2 (ja) |
DE (1) | DE102006031575A1 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2013012298A (ja) * | 2005-07-04 | 2013-01-17 | Samsung Electronics Co Ltd | ページバッファとそれを含む不揮発性メモリ装置 |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101513714B1 (ko) * | 2008-07-09 | 2015-04-21 | 삼성전자주식회사 | 플래시 메모리 장치 및 그것의 프로그램 방법 |
KR20210010227A (ko) * | 2019-07-19 | 2021-01-27 | 에스케이하이닉스 주식회사 | 반도체 메모리 장치 |
KR20210028886A (ko) * | 2019-09-05 | 2021-03-15 | 에스케이하이닉스 주식회사 | 캐시 래치 회로를 구비하는 반도체 메모리 장치 |
KR20210153475A (ko) * | 2020-06-10 | 2021-12-17 | 에스케이하이닉스 주식회사 | 반도체 메모리 장치, 그의 동작 방법, 및 반도체 메모리 시스템 |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH11242891A (ja) * | 1997-12-26 | 1999-09-07 | Sony Corp | 不揮発性半導体記憶装置およびそのデータ書き込み方法 |
JP3983969B2 (ja) * | 2000-03-08 | 2007-09-26 | 株式会社東芝 | 不揮発性半導体記憶装置 |
KR100471167B1 (ko) * | 2002-05-13 | 2005-03-08 | 삼성전자주식회사 | 프로그램된 메모리 셀들을 검증하기 위한 페이지 버퍼를구비한 반도체 메모리 장치 |
KR100512181B1 (ko) * | 2003-07-11 | 2005-09-05 | 삼성전자주식회사 | 멀티 레벨 셀을 갖는 플래시 메모리 장치와 그것의 독출방법 및 프로그램 방법 |
-
2006
- 2006-06-27 JP JP2006177272A patent/JP5165215B2/ja active Active
- 2006-06-30 DE DE102006031575A patent/DE102006031575A1/de not_active Withdrawn
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2013012298A (ja) * | 2005-07-04 | 2013-01-17 | Samsung Electronics Co Ltd | ページバッファとそれを含む不揮発性メモリ装置 |
Also Published As
Publication number | Publication date |
---|---|
DE102006031575A1 (de) | 2007-02-22 |
JP2007018689A (ja) | 2007-01-25 |
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