JP5103758B2 - Thin film transistor manufacturing method - Google Patents

Description

  The present invention relates to a method for manufacturing a thin film transistor.

  With the widespread use of information terminals, there is an increasing need for flat panel displays as computer displays. In addition, with the progress of computerization, the information provided by paper media has increased the opportunity to be provided electronically, and as a mobile display medium that is thin, light and easy to carry, electronic paper or digital The need for paper is also increasing.

  In general, in a flat display device, a display medium is formed using an element utilizing liquid crystal, organic EL, electrophoresis, or the like. In such a display medium, a technique using an active drive element formed of a thin film transistor (TFT) as an image drive element has become mainstream in order to ensure uniformity of screen brightness, screen rewrite speed, and the like.

  Here, the TFT element is usually formed on a glass substrate, mainly a semiconductor thin film such as a-Si (amorphous silicon) or p-Si (polysilicon), or a metal thin film such as a source, drain, or gate electrode on the substrate. Manufactured by sequentially forming. The production of flat panel displays using TFTs usually requires high-precision photolithography methods in addition to vacuum equipment such as CVD and sputtering, and thin film formation processes that require high-temperature treatment processes. The load of is very large. Furthermore, along with the recent needs for larger display screens, their costs have become enormous.

  In recent years, research and development of organic TFT elements using organic semiconductor materials has been actively promoted as a technique to compensate for the disadvantages of conventional TFT elements (see, for example, Patent Document 1 and Non-Patent Document 1). Since this organic TFT element can be manufactured by a low-temperature process, it is said that a light and difficult-to-break resin substrate can be used, and that a flexible display using a resin film as a substrate can be realized (for example, non- Patent Document 2). Further, by using an organic semiconductor material that can be manufactured by a wet process such as printing or coating under atmospheric pressure, a display with excellent productivity and a very low cost may be realized.

  However, in manufacturing by a wet process such as printing or coating, there is a problem that patterning accuracy is poor and performance variation of organic TFT elements tends to increase.

  As a method for improving the accuracy of patterning, a self-assembled monolayer is selectively and precisely arranged in the gate electrode projection region on the surface of the insulating film, and the orientation order of the organic semiconductor film is adjusted outside the gate electrode projection region. A method has been proposed in which the light irradiation portion does not improve but is selectively improved only within the gate electrode projection region (see, for example, Patent Document 2).

  In addition, when the insulating film is irradiated with light, the surface state of the portion exposed to light changes, and a latent image of surface energy is formed. When a coating material is applied on the exposed insulating film, the surface energy is applied to the base in advance so that the coating material can be repelled or adapted according to the surface energy. A method of forming a latent image is proposed (for example, see Non-Patent Document 3).

  In any of these methods, light irradiation is necessary. When light irradiation is performed, there is a problem that a substrate or an insulating film made of an organic material or the like deteriorates and reliability of the organic TFT element deteriorates.

As a patterning method that does not perform light irradiation, a method has been proposed in which a desired pattern is obtained by physically cutting an insulating film or the like (see, for example, Patent Document 3).
Japanese Patent Laid-Open No. 10-190001 JP 2005-79560 A Japanese translation of PCT publication No. 2004-517737 Advanced Material 2002 2002 No. 2 page 99 (Review) SID'0 Digest P57 AM-LCD04 Digest of technical Paper P37

  However, in the method disclosed in JP-A-2001-318, there is a problem that fine chips are generated when the film is cut, and the yield is lowered in the manufacturing process.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a method of manufacturing a thin film transistor that enables highly accurate patterning without causing deterioration due to light irradiation.

1.
In a method for manufacturing a thin film transistor having at least a gate electrode, a gate insulating layer, a semiconductor layer, a source electrode, and a drain electrode on a substrate,
After the step of forming the gate insulating layer,
A method of manufacturing a thin film transistor, comprising a step of deforming or altering a part of the gate insulating layer by bringing a pressure contact member into contact with the gate insulating layer.

2.
In the step of deforming or altering a part of the gate insulating layer,
2. The method of manufacturing a thin film transistor according to 1, wherein the pressure contact member is heated.

3.
2. The method for manufacturing a thin film transistor according to 1, wherein a semiconductor layer is formed in a deformed or altered portion on the gate insulating layer.

4).
4. The method for producing a thin film transistor according to 3, wherein the semiconductor layer is applied by a dot coating method.

5.
4. The method of manufacturing a thin film transistor according to 3, wherein the semiconductor layer is applied by a surface coating method, and then unnecessary portions of the semiconductor layer are removed using a squeegee.

6).
2. The method of manufacturing a thin film transistor according to 1, wherein a conductive layer is formed on the deformed or altered portion of the gate insulating layer.

7).
7. The method of manufacturing a thin film transistor according to 6, wherein the conductive layer is applied by a dot coating method.

8).
7. The method of manufacturing a thin film transistor according to 6, wherein the conductive layer is applied by a planar coating method, and then unnecessary portions of the conductive layer are removed using a squeegee.

9.
In creating a plurality of the thin film transistors on the substrate,
The pressure contact member is:
9. The method of manufacturing a thin film transistor according to any one of 1 to 8, wherein the thin film transistors are arranged in a row at right angles to a feeding direction in which the substrate is moved by a predetermined distance.

10.
10. The method of manufacturing a thin film transistor according to claim 1, wherein a portion of the pressure contact member that contacts the gate insulating layer is made of silicon rubber.

11.
In the method of manufacturing the thin film transistor, in which the gate electrode and the gate insulating layer are stacked in this order on the substrate.
The thin film transistor according to any one of claims 1 to 9, wherein a measurement electrode is provided in a portion of the pressure contact member that contacts the gate insulating layer, and a capacitance between the gate electrode and the measurement electrode is measured. Production method.

12
12. The method of manufacturing a thin film transistor according to 11, wherein the thickness of the gate insulating layer deformed by the pressure contact member is controlled based on a result of measuring a capacitance between the gate electrode and the measurement electrode.

  ADVANTAGE OF THE INVENTION According to this invention, the manufacturing method of the thin-film transistor which enables highly accurate patterning can be provided.

  Hereinafter, the present invention will be described in detail with reference to embodiments, but the present invention is not limited thereto.

  An organic thin film transistor (hereinafter referred to as an organic TFT) obtained by the production method of the present invention has a gate electrode on a substrate and a bottom gate type having a source electrode and a drain electrode in contact with an organic semiconductor layer through a gate insulating layer. And a top gate type having a source electrode and a drain electrode in contact with an organic semiconductor layer on a substrate, and a gate electrode on the gate electrode via a gate insulating layer. One example of the layer structure of specific elements of the bottom gate type and the top gate type is shown in FIGS.

  FIG. 1 is a cross-sectional view showing an example of a layer structure of a bottom gate type organic thin film transistor (hereinafter referred to as a bottom gate type organic TFT) according to the present invention.

  A gate electrode 7 is provided on the substrate 1, and an organic semiconductor layer 2 is formed in a recess on the upper gate insulating layer 8. A source electrode 3 and a drain electrode 4 are formed on the gate insulating layer 8 so as to be in contact with the organic semiconductor layer 2.

  FIG. 2 is a cross-sectional view showing an example of the layer structure of a top gate type organic thin film transistor (hereinafter referred to as a top gate type organic TFT) according to the present invention.

  On the substrate 1, an organic semiconductor layer 2 and a source electrode 3 and a drain electrode 4 bonded to the organic semiconductor layer 2 are formed. Further, a gate electrode 7 is provided in the recess on the upper gate insulating layer 8.

  FIG. 3 is an explanatory view for explaining a first embodiment of a method for producing a bottom gate type organic TFT according to the present invention. 3 (x) to 3 (d) show cross sections of the channel portion of the organic TFT formed on the substrate 1. FIG. A manufacturing method for deforming the gate insulating layer 8 to provide a recess and forming the organic semiconductor layer 2 in the recess will be described in order with reference to FIG.

  First, the previous process will be described with reference to FIG.

  A photosensitive resist is applied onto the substrate 1 on which the conductive thin film is formed, and then exposed and developed through a photomask having a pattern corresponding to the gate electrode to be formed, thereby forming a resist layer having an electrode pattern. Next, the substrate 1 is etched to form the gate electrode 7.

  The material of the substrate 1 is not particularly limited, but a film substrate such as PEN, PES, PC, and TAC is desirable. For example, the conductive thin film may be a low-resistance metal material such as Al, Cr, Ta, Mo, or Ag as a conductive thin film on the substrate 1 using a method such as vapor deposition, sputtering, or CVD, or a laminated structure of these metals. Further, a material doped with another material can be used for improving the heat resistance of the metal thin film, improving the adhesion to the support substrate 1, and preventing defects. A transparent electrode such as ITO, IZO, SnO, or ZnO can also be used.

Next, steps S1 to S4 will be described.
S1... Step of forming gate insulating layer 8 S2... Step of deforming or altering part of gate insulating layer S3... Step of forming organic semiconductor layer 2 S4. ... Process for forming source electrode 3 and drain electrode 4 Hereinafter, each process will be described in order.

  S1 Step for forming the gate insulating layer 8.

  As shown in FIG. 3A, the gate insulating layer 8 is formed.

  The gate insulating layer 8 is formed by, for example, a spin coat method. As the gate insulating layer 8, an acrylic resin, a urethane resin, an epoxy resin, a polyimide resin, or the like is particularly desirable in order to ensure flexibility. The resin includes a thermoplastic resin and a thermosetting resin, and any of them can be used. On the other hand, an insulating film such as an inorganic film is not suitable because it has poor flexibility and is difficult to process.

S2... Step of deforming or altering a part of the gate insulating layer 8 As shown in FIG. 3B, the pressure contact member 40 is brought into contact with the gate insulating layer 8 so that a part of the gate insulating layer 8 is formed. Deform or alter.

  The pressure contact member 40 is driven in a direction indicated by an arrow in FIG. 3B by a driving unit (not shown in FIG. 3) and contacts the gate insulating layer 8. FIG. 3B illustrates a state where the thickness of the portion of the gate insulating layer concave portion 8a pressed by the pressure contact member 40 of the gate insulating layer 8 is thin and concave. As will be described later, by providing the gate insulating layer recess 8a, the organic semiconductor layer 2 having a highly accurate pattern shape can be formed by applying a liquid semiconductor material to the gate insulating layer recess 8a.

  FIG. 5 is an explanatory view illustrating an example of a manufacturing apparatus used in this step. In this example, 3 × 5 total 15 organic TFTs are formed on the substrate 1. 5A is an explanatory view for explaining the case where the press contact members 40 arranged in a row are used, and FIG. 5B is an explanatory view for explaining the case where the press contact members 40 arranged on the roller 62 are used.

  First, the case where the press contact members 40 arranged in a row are used will be described with reference to FIG.

  FIG. 5A shows a state in which the substrate 1 that has finished the process of step S1 is sent in the direction of the arrow X. The pressure contact members 40a, 40b, and 40c are arranged in a row. A control device 60 having a CPU inside controls the pressure contact member drive unit 61 to drive the pressure contact members 40a, 40b, 40c in a direction perpendicular to the substrate 1 as indicated by arrows X.

  The control device 60 controls a feeding device for the substrate 1 (not shown). The control device 60 stops once the substrate 1 is sent by a predetermined amount. Next, the control device 60 presses the pressing member driving unit 61 by moving the pressing members 40a, 40b, and 40c by a predetermined amount toward the substrate 1 to form the gate insulating layer recess 8a.

  After the gate insulating layer recess 8a is formed, the pressure contact member drive unit 61 raises the pressure contact members 40a, 40b, and 40c under the control of the control device 60, and the substrate 1 feeding device feeds the substrate 1 by a predetermined amount.

  In this way, 3 × 5 gate insulating layer recesses 8 a are formed on the surface of the gate insulating layer 8.

  FIG. 5B also shows a state in which the substrate 1 that has finished the process of step S1 is sent in the direction of arrow X. The pressure contact members 40 a, 40 b, and 40 c are arranged on the roller 62, and the pressure contact member drive unit 61 rotates in synchronization with the feeding of the substrate 1 under the control of the control device 60. Since the pressure contact members 40a, 40b, and 40c are disposed at positions that are in pressure contact with the gate insulating layer 8, when the roller 62 rotates, the gate insulating layer recess 8a is formed.

  In this way, 3 × 5 gate insulating layer recesses 8 a are formed on the surface of the gate insulating layer 8.

Although the material and shape of the pressure contact member 40 are not particularly limited, it is desirable to use a metal such as iron, aluminum, or silver for the portion of the pressure contact member 40 that contacts the gate insulating layer 8. The amount of force with which the pressure contact member 40 is pressed is preferably in the range of about 1 × 10 ⁵ N / m ² to 1 × 10 ⁹ N / m. If the pressure is lower than this range, the desired deformation cannot be obtained. On the other hand, if the pressure is too high, the insulating film or the substrate may be damaged.

In the case where the material of the gate insulating layer 8 is a thermoplastic resin, when the pressure contact member 40 is heated and pressed with a heater or the like, the resin becomes soft due to heat and can be easily deformed. For example, at room temperature, a pressure of about 1 × 10 ⁸ N / m ² is required, but when heated to 100 ° C., it can be deformed with a light pressure of about 1 × 10 ⁶ N / m ^2. As an example of the thermoplastic resin used for the gate insulating layer 8, polyamic acid or the like can be used. Since polyamic acid changes to polyimide when heated, the heated portion contracts and can be easily deformed.

  In the case of a thermosetting resin, the pressure contact member 40 is not heated but deformed by pressure. Even in the case of a thermoplastic resin, the pressing member 40 may be pressed without heating.

  S3 Step for forming the organic semiconductor layer 2.

  As shown in FIG. 3 (c), an organic semiconductor material is applied to a portion obtained by deforming or altering a part of the gate insulating layer 8 by the pressure contact member 40 by a known coating method such as a dot coating method or a planar coating method. Apply pattern.

  FIG. 7 is an explanatory view for explaining a coating method according to the present invention. In this example, 3 × 5 total 15 organic TFTs are formed on the substrate 1. 7A is an explanatory diagram for explaining the dot coating method, and FIG. 7B is an explanatory diagram for explaining the planar coating method.

First, the dot coating method will be described with reference to FIG. 7A. FIG. 7A shows the substrate 1 that has undergone the process of deforming or altering a part of the gate insulating layer 8 in step S2 in the direction of arrow X. It shows the state. On the surface of the gate insulating layer 8, a 3 × 5 gate insulating layer recess 8a is provided.

  Reference numeral 53 denotes a head array 53 used in a dot coating method provided in a direction perpendicular to the feeding direction of the substrate 1. For example, three ejection heads 53 a, 53 b, and 53 c are arranged in the head array 53. As shown by the arrows in FIG. 7A from the discharge heads 53a, 53b, and 53c, liquid is discharged from the discharge heads 53a, 53b, and 53c at a predetermined timing to the gate insulating layer recess 8aa that is sent to the corresponding position immediately below. The semiconductor material is dropped. The dot coating method includes an inkjet method and a dispenser method, and any of them may be used.

  The gate insulating layer recess 8ab shown in FIG. 7A shows a state in which the semiconductor material is dropped into the gate insulating layer recess 8aa, the gate insulating layer recess 8ab is filled with the semiconductor material, and the organic semiconductor layer 2 is formed. ing. Thus, the organic semiconductor layer 2 can be formed in a desired shape with high accuracy.

Next, the planar coating method will be described with reference to FIG. 7B. FIG. 7B also shows that the substrate 1 that has finished the process of deforming or altering part of the gate insulating layer 8 in step S2 is sent in the direction of arrow X. It shows the state that has been. On the surface of the gate insulating layer 8, a 3 × 5 gate insulating layer recess 8a is provided.

  52 is a planar coating machine 52 used for the planar coating method provided in a direction perpendicular to the feeding direction of the substrate 1, and the feeding direction of the substrate 1 from the planar coating machine 52 as shown in FIG. A liquid semiconductor material is discharged in the direction perpendicular to the surface. When the substrate 1 is sent directly under the planar coater 52, the semiconductor material discharged from the planar coater 52 is applied to the surface of the substrate 1.

  The squeegee 51 is disposed so as to contact the surface of the substrate 1. When the substrate 1 is sent, unnecessary semiconductor material applied to the surface of the substrate 1 is scraped and removed. In this way, as shown in FIG. 7B, the gate insulating layer recess 8ab is filled with the semiconductor material, and the organic semiconductor layer 2 can be formed. Thus, the organic semiconductor layer 2 can be formed in a desired shape with high accuracy.

  The organic semiconductor material may be any material. Not only organic polymer materials but also low molecular materials such as pentacene can be used.

  Typical examples of materials that can be applied include polythiophenes such as poly (3-hexylthiophene), aromatic oligomers such as oligothiophene having a side chain based on the hexamer of thiophene, and pentacene with substituents and dissolution. Any soluble semiconductor can be used, such as pentacenes with enhanced properties, a copolymer of fluorene and bithiophene (F8T2), polythienylene vinylene or phthalocyanine. In particular, pentacenes include silylethynylpentacene including 6,13-bistriisopropylsilylethynylpentacene and 6,13-bistriethylsilylethynylpentacene. This is disclosed in U.S. Pat. No. 6,690,029 as a patent document, and in J. Pat. AM. CHEM. Journal 2005, No. 127, pages 4986-4987, which is a material in which two substituents are provided in pentacene to control the interaction between molecules and realize high mobility.

S4... Process for forming source electrode 3 and drain electrode 4 As shown in FIG. 3D, the source electrode 3 and the drain electrode 4 are formed. The source electrode 3 and the drain electrode 4 are formed, for example, by depositing gold by sputtering. In addition, although gold was illustrated here, various materials, such as platinum, silver, copper, and aluminum, can be used without specifically limiting the material to gold. Alternatively, a conductive organic material typified by PEDOT / PSS or a coating material in which metal nanoparticles are dispersed can be used as the coating material.

  Thus, since the organic semiconductor layer 2 is formed by applying the organic semiconductor material to the gate insulating layer recess 8a formed by contacting the pressure contact member 40, the organic semiconductor layer 2 is not deteriorated and is not manufactured. There is no occurrence of chips. Therefore, a highly reliable organic TFT can be manufactured. In addition, it is possible to pattern with high accuracy into a shape determined by the tip shape of the pressure contact member 40.

  In addition, the process demonstrated so far is an example, and this invention is not limited to these processes.

  Next, a manufacturing method in which a part of the gate insulating layer 8 is altered and the organic semiconductor layer 2 is formed in the altered portion will be described with reference to FIG.

  FIG. 4 is an explanatory view for explaining a second embodiment of a method for producing a bottom gate type organic TFT according to the present invention. 4A to 4C show a cross section of the channel portion of the organic TFT formed on the substrate 1.

  Since the process up to the step S1 of forming the gate insulating layer 8 is the same as that in FIG.

  S2: A step of deforming or altering a part of the gate insulating layer 8.

  In FIG. 4A, the pressure contact member 40 is pressure-contacted with a pressure that does not change the thickness of the gate insulating layer 8, and the portion 8b of the gate insulating layer 8 is altered to form a gate insulating layer altered portion 8b.

  For example, the pressure contact member 40 may be pressure-contacted with a pressure that does not change the thickness of the gate insulating layer 8 to reduce the surface roughness of the gate insulating layer 8 to form the gate insulating layer altered portion 8b. As will be described later, when a liquid semiconductor material is applied to the portion pressed by the pressure contact member 40, it does not spread to a portion having a large surface roughness and remains in a range of a portion having a small surface roughness. The organic semiconductor layer 2 having a shape can be formed.

  Alternatively, the wettability of the portion of the gate insulating layer 8 that is in contact with the pressure contact member 40 may be increased by using silicon rubber or the like for the portion of the pressure contact member 40 that is in contact with the gate insulating layer 8. As will be described later, when a liquid semiconductor material is applied to the portion pressed by the pressure contact member 40, the liquid semiconductor material does not spread to the portion with low wettability, but remains in the range of the portion with high wettability. The organic semiconductor layer 2 can be formed.

  In addition, the manufacturing apparatus demonstrated in FIG. 5 can be used for this process by changing the quantity which the press-contact member 40 contacts with the gate insulating layer 8. FIG.

  S3 Step for forming the organic semiconductor layer 2.

  A liquid organic semiconductor material is pattern-coated by the dot coating method described with reference to FIG. 7A on the gate insulating layer altered portion 8b that has been transformed by bringing the pressure contact member 40 into contact with the gate insulating layer 8. As shown in FIG. 4B, the dropped organic semiconductor material remains in the gate insulating layer altered portion 8b due to surface tension, and the organic semiconductor layer 2 having a desired pattern can be formed.

S4... Process for forming source electrode 3 and drain electrode 4 This is the same as the process described in FIG.

  Thus, since the organic semiconductor material 2 is formed by applying the organic semiconductor material to the gate insulating layer altered portion 8b formed by contacting the pressure contact member 40, the organic semiconductor layer 2 is not deteriorated, and the manufacturing process is also performed. There is no chipping. Therefore, a highly reliable organic TFT can be manufactured. In addition, it is possible to pattern with high accuracy into a shape determined by the tip shape of the pressure contact member 40.

  Next, a manufacturing method in which the gate insulating layer 8 is deformed to form a recess and a conductive layer is formed in the recess to form the gate electrode 7 will be described in order with reference to FIGS.

  FIG. 6 is an explanatory view for explaining an example of a method for producing a top gate type organic TFT according to the present invention. 6 (x) to 6 (d) show cross sections of the channel portion of the organic TFT formed on the substrate 1. FIG.

  First, the previous process will be described with reference to FIG.

  After applying a photosensitive resist on the substrate 1 on which the conductive thin film is formed, exposure and development are performed through a photomask having a pattern of the source electrode 3 and the drain electrode 4 to form a resist layer of each electrode pattern. Next, the substrate 1 is etched to form the source electrode 3 and the drain electrode 4.

  The substrate 1 can use the same material as described in FIG.

Next, steps S11 to S14 after the previous step will be described.
S11... Organic semiconductor layer 2 forming step S12... Gate insulating layer 8 forming step S13... Part of gate insulating layer 8 being deformed or altered S14. ... Process for forming gate electrode 7 (conductive layer) Each process will be described below in order.

S11... Step of Forming Organic Semiconductor Layer 2 The organic semiconductor layer 2 is formed by applying the organic semiconductor material described above between the source electrode 8 and the drain electrode 9. The organic semiconductor layer 2 can be formed by any method such as a spin coating method, an ink jet method, or a micro contact printing method.

  S12: A step of forming the gate insulating layer 8.

  As shown in FIG. 6B, the gate insulating layer 8 is formed.

  The materials and manufacturing methods described in S1 of FIG. 3 can be applied.

  S13: A step of deforming or altering a part of the gate insulating layer 8.

  The pressure contact member 40 is brought into contact with the gate insulating layer 8 to deform or alter a part of the gate insulating layer 8. FIG. 6C shows an example in which the gate insulating layer recess 8a is formed. As described with reference to FIG. 4, the gate insulating layer altered portion 8 b may be provided without changing the thickness of the gate insulating layer 8.

S14... Step of Forming Gate Electrode 7 (Conductive Layer) FIG. 6D shows a state in which the gate electrode 7 (conductive layer) is formed in the gate insulating layer recess 8a. As in the case of the organic semiconductor material described with reference to FIG. 7, when the gate insulating layer recess 8a is formed, the gate electrode 7 (conductive layer) is formed by applying a conductive material using a dot coating method or a planar coating method. can do.

  6D, when the gate insulating layer altered portion 8b (not shown) is formed, the gate electrode 7 (conductive layer) can be formed by applying a conductive material using a dot coating method.

  In addition to conductive organic materials typified by PEDOT / PSS, the conductive material is made of metal nanoparticles such as Ag (silver), Au (gold), Cu (copper), and Pt (platinum) dispersed in a binder. A coating material can also be used.

  Thus, since the gate electrode 7 (conductive layer) is formed by applying the conductive material to the gate insulating layer altered portion 8b formed by contacting the pressure contact member 40, chips and the like are not generated in the manufacturing process. Therefore, a highly reliable organic TFT can be manufactured. In addition, it is possible to pattern with high accuracy into a shape determined by the tip shape of the pressure contact member 40.

  In addition, the process demonstrated so far is an example, and this invention is not limited to these processes.

  Next, a manufacturing method for accurately forming the thickness d of the gate insulating layer recess 8a will be described with reference to FIGS.

  FIG. 8 is an explanatory diagram for explaining a method of measuring the thickness d of the gate insulating layer recess 8a of the bottom gate type organic TFT. 8A shows a state before the pressure contact member 40 contacts the gate insulating layer 8, and FIG. 8B shows a state where the pressure contact member 40 forms a gate insulating layer recess 8a having a thickness d in the gate insulating layer 8. FIG. . In addition, the same number is attached | subjected to the same component as the description so far, and description is abbreviate | omitted.

  First, FIG. 8A will be described. The pressure contact member 40 is provided with a measurement electrode 41 for measuring the thickness d at the tip.

  FIG. 8B shows a state in which the gate insulating layer recess 8a is formed by pressing the gate insulating layer 8 until the pressure contact member 40 has a desired thickness d. A parallel plate capacitor 80 in which the gate insulating layer 8 is sandwiched between the measurement electrode 41 and the gate electrode 7 is formed.

  The capacitance C of the parallel plate capacitor 80 is expressed by Equation 1.

[Formula 1] C = εS / d
ε is the dielectric constant of the gate insulating layer 8 sandwiched between the electrodes, S is the area of the measurement electrode 41 and the gate electrode 7, and d is the thickness of the gate insulating layer recess 8a. Therefore, if the capacitance C of the parallel plate capacitor 80 constituted by the measurement electrode 41 and the gate electrode 7 is obtained, the thickness d can be obtained.

  FIG. 9 is a block diagram illustrating control for driving the pressure contact member 40 while measuring the capacitance C to form the gate insulating layer recess 8a having a desired depth.

  It should be noted that the functional elements described so far are denoted by the same reference numerals and description thereof is omitted.

  The control device 60 has a microcomputer 70, and the thickness control unit 63 of the microcomputer 70 controls the driving of the pressure contact member 40 and the like. The capacitance measuring unit 62 measures the capacitance of the parallel plate capacitor 80 according to a command from the thickness control unit 63, and transmits the result to the thickness control unit 63.

  The capacitance measuring unit 62 includes, for example, a measurement electrode 41 provided at one end of the press contact members 40 arranged in a row as described in FIG. 5A and a gate at a corresponding position on the substrate 1. A parallel plate capacitor 80 composed of electrodes 7 is connected.

  The capacitance C can be measured by Equation 2.

[Formula 2] C = i × t / V
i is a current flowing into the parallel plate capacitor 80, t is time, and V is a voltage of the parallel plate capacitor 80. The capacitance measuring unit 62 short-circuits both ends of the parallel plate capacitor 80 and then charges a constant current i for a time t by an internal constant current source. Next, the capacitance measuring unit 62 measures the voltage of the parallel plate capacitor 80 with an internal voltmeter, obtains the capacitance C, and transmits it to the thickness control unit 63.

  FIG. 10 is a flowchart for forming the gate insulating layer recess 8a having a desired depth by automatically controlling the pressing member driving unit 61. In FIG. 10, the substrate 1 described in FIG. 5A is sent to a predetermined position, and the pressing member driving unit 61 starts driving the pressing member 40.

  S101: This is a step of driving the pressure contact portion 70 in the direction of the substrate 1 by a predetermined amount.

  The thickness control unit 63 instructs the pressure contact member drive unit 61 to drive the pressure contact member 40 in a direction toward the substrate 1 by a predetermined amount.

  S102: This is a step of measuring the capacitance C.

  The thickness control unit 63 instructs the capacitance measuring unit 62 to measure the capacitance C of the parallel plate capacitor 80.

  S103: A step of determining whether or not the capacitance C is equal to or greater than a predetermined value Cd.

  The thickness control unit 63 determines whether or not the capacitance C measured by the capacitance measurement unit 62 is equal to or greater than a predetermined value Cd. The predetermined value Cd is a capacitance at a desired thickness d.

  If the capacitance C is equal to or less than the predetermined value Cd (step S103; No), the drive amount of the pressure contact portion 40 is insufficient, and the process returns to step S101 and is driven again.

  If the capacitance C is equal to or greater than the predetermined value Cd (step S103; Yes), the gate insulating layer recess 8a having a desired thickness d has been formed, and the process proceeds to step S104.

  S104: This is a step of moving the pressure contact portion 40 to the initial position.

  The thickness control unit 63 instructs the pressure contact member drive unit 61 to drive the pressure contact member 40 in the direction away from the substrate 1 to the initial position.

  As described above, the gate insulating layer recesses 8a having a desired thickness d can be formed on the substrate 1 for one row.

  Hereinafter, although the Example performed in order to confirm the effect of this invention is described, this invention is not limited to these.

[Example]
In this example, a roll film substrate having a width of 150 mm and a thickness of 200 μm was used as the substrate 1, and a total of 10,000 organic TFTs of 100 × 100 were formed on the substrate 1 at intervals of 1 mm in both the line direction and the feeding direction. The size of the organic TFT is 50 μm × 200 μm.

[Production of organic TFT]
Since it produced in the process of S1-S4 demonstrated in FIG. 3, it attaches | subjects the number of each process and demonstrates in order, and abbreviate | omits description in common.
.

  A polycarbonate substrate was used as the substrate 1, and a gate electrode was formed by a photolithographic method.

  Next, steps S1 to S4 will be described.

S1... Process for forming gate insulating layer 8 As a material for gate insulating layer 8, a solution of thermoplastic urethane resin dissolved in dimethylformamide is used and applied to substrate 1 with a thickness of 1 μm by spin coating. To do. After spin coating, baking was performed at 150 ° C. to remove the solvent of the gate insulating layer 8.
S2... Process for deforming or altering a part of the gate insulating layer 8 The gate insulating layer 8 shown in FIG. The material of the pressure contact member 40 is iron, and the shape of the tip portion is a rectangle of 50 μm × 160 μm. The pressure contact member 40 is driven while measuring the capacitance C of the parallel plate capacitor 80, and the pressure contact member 40 is driven until the measured capacitance C becomes the capacitance Cd when the thickness d is 0.5 μm. .
S3: Step of forming organic semiconductor layer 2 A solution obtained by dissolving pentacene in toluene was applied to the formed gate insulating layer recess 8a by a dot coating method, and the solvent component was dried after coating.
S4... Process for forming source electrode 3 and drain electrode 4 PEDOT / PSS was applied to form source electrode 3 and drain electrode 4.

  The organic TFT fabricated in this manner was able to form an organic semiconductor layer pattern with high accuracy. Moreover, when the mobility and ON / OFF current ratio of organic TFT were evaluated, it had sufficient performance and there was little variation.

  Thus, in Example 3 of the present invention, the light shielding layer 6 and the gate electrode 7 are electrically connected in the manufacturing process S7 of the bottom gate type organic TFT, and the conductive light shielding layer 6 is used as the second gate electrode. Since it functions, a high-performance organic TFT element can be manufactured.

  As described above, a method for manufacturing a thin film transistor that enables highly accurate patterning can be provided.

It is explanatory drawing explaining an example of a layer structure of the bottom gate type organic thin-film transistor (henceforth a bottom gate type organic TFT) concerning this invention. It is explanatory drawing explaining an example of a layer structure of the top gate type organic thin-film transistor (henceforth a top gate type organic TFT) concerning this invention. It is explanatory drawing explaining 1st Embodiment of the manufacturing method of the bottom gate type organic TFT concerning this invention. It is explanatory drawing explaining 2nd Embodiment of the manufacturing method of the bottom gate type organic TFT concerning this invention. It is explanatory drawing explaining the coating method concerning this invention. It is explanatory drawing explaining an example of the manufacturing method of the top gate type organic TFT concerning this invention. It is explanatory drawing explaining an example of the manufacturing apparatus used for this process. It is explanatory drawing explaining the method to measure the thickness d of the gate insulating-layer recessed part 8a of bottom gate type organic TFT. It is a block diagram explaining the control which drives the press-contact member 40, measuring the electrostatic capacitance C, and forms the gate insulating-layer recessed part 8a of desired depth. It is a flowchart which forms the gate insulating-layer recessed part 8a of the desired depth by automatically controlling the press-contact member drive part 61. FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Board | substrate 2 Organic-semiconductor layer 3 Source electrode 4 Drain electrode 7 Gate electrode 8 Gate insulating layer 8a Gate insulating layer recessed part 8b Gate insulating layer alteration part 40 Pressure contact part 61 Pressure contact member drive part 62 Capacitance measurement part

Claims (10)

In a method for manufacturing a thin film transistor having at least a gate electrode, a gate insulating layer, a semiconductor layer, a source electrode, and a drain electrode on a substrate,
After the step of forming the gate insulating layer,
A step of bringing a pressure contact member into contact with the gate insulating layer , and changing a part of the gate insulating layer so as to reduce surface roughness or increase wettability without changing thickness. A method for manufacturing a thin film transistor. In the step of altering a part of the gate insulating layer,
The method of manufacturing a thin film transistor according to claim 1, wherein the pressure contact member is heated. 2. The method of manufacturing a thin film transistor according to claim 1, further comprising a step of forming a semiconductor layer in the altered portion on the gate insulating layer.   4. The method of manufacturing a thin film transistor according to claim 3, wherein the semiconductor layer is applied by a dot coating method. 2. The method of manufacturing a thin film transistor according to claim 1, further comprising a step of forming a conductive layer in the altered portion on the gate insulating layer. 6. The method of manufacturing a thin film transistor according to claim 5, wherein the conductive layer is applied by a dot coating method. In creating a plurality of the thin film transistors on the substrate,
The pressure contact member is:
The method of manufacturing a thin film transistor according to claim 1, wherein the thin film transistors are arranged in a row at right angles to a feeding direction in which the substrate is moved by a predetermined distance. The method of manufacturing a thin film transistor according to any one of claims 1 to 7, wherein a portion of the pressure contact member that contacts the gate insulating layer is made of silicon rubber. In a method for manufacturing a thin film transistor having at least a gate electrode, a gate insulating layer, a semiconductor layer, a source electrode, and a drain electrode on a substrate,
After the step of forming the gate insulating layer,
A step of deforming a part of the gate insulating layer by bringing a pressure contact member into contact with the gate insulating layer;
Laminating the gate electrode and the gate insulating layer in this order on the substrate;
A method of manufacturing a thin film transistor, comprising: providing a measurement electrode at a portion of the pressure contact member that is in contact with a gate insulating layer; and measuring a capacitance between the gate electrode and the measurement electrode. 10. The method of manufacturing a thin film transistor according to claim 9, wherein the thickness of the gate insulating layer deformed by the pressure contact member is controlled based on a result of measuring a capacitance between the gate electrode and the measurement electrode. .

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