JP5086572B2 - Delay-fixed loop clock driver controller - Google Patents

Delay-fixed loop clock driver controller Download PDF

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JP5086572B2
JP5086572B2 JP2006182746A JP2006182746A JP5086572B2 JP 5086572 B2 JP5086572 B2 JP 5086572B2 JP 2006182746 A JP2006182746 A JP 2006182746A JP 2006182746 A JP2006182746 A JP 2006182746A JP 5086572 B2 JP5086572 B2 JP 5086572B2
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signal
dll
clock
unit
delay
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JP2007095267A (en
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敬▲ふん▼ 金
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エスケーハイニックス株式会社SK hynix Inc.
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Priority to KR10-2005-0125353 priority
Priority to KR20050125353A priority patent/KR100753100B1/en
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    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08Details of the phase-locked loop
    • H03L7/081Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0814Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the phase shifting device being digitally controlled
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08Details of the phase-locked loop
    • H03L7/0805Details of the phase-locked loop the loop being adapted to provide an additional control signal for use outside the loop

Description

  The present invention relates to a semiconductor memory device, and more particularly, to a DLL (Delay Locked Loop) driver control device that can reduce the amount of current consumed by preventing unnecessary clock output.

  In a semiconductor memory device that operates at high speed, such as a DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory), data is transmitted in synchronization with an external clock. Clock synchronization is essential for high-speed operation. The delay locked loop DLL plays a role of synchronizing the data with the clock by controlling the timing of the data discharged from the inside of the DRAM based on the clock input from the outside of the DRAM. Put this on. As a result, this delay locked loop (DLL) receives an external clock and outputs data at the same time as the current clock.

  FIG. 1 is a block diagram of a DLL device according to the prior art.

  FIG. 2 shows a circuit diagram of a conventional DLL driver control unit 100.

  As shown in FIG. 1, the conventional DLL device includes a clock buffer, a delay line, a phase comparator, a delay control unit, and a delay replica model, and is phase-synchronized with an external clock by performing phase update (UPDATE). It includes a DLL clock generation unit 300 that generates DLL clocks irclk and ifclk, a DLL driver 200 that drives internal clock signals irclk and ifclk, and a DLL driver control unit 100 that controls the driving of the DLL driver. In particular, the DLL driver control unit 100 receives the signal PDM notifying whether or not to enter the power down mode and the signal SREF having information on self-refresh, and determines whether to operate the DLL driver. It consists of a NOR gate NR that outputs a signal DEN. (See Figure 2)

  The conventional delay locked loop (DLL) device thus configured turns off the DLL driver 200 when the memory is in a power down mode for low power consumption.

  Therefore, the DLL driver 200 controlled by the existing DLL driver control unit 100, when an external clock is input, regardless of whether or not the actual clock can be used and its use range, the power down mode described above. Except for the case of self-refreshing, the operation was performed in a format that outputs without condition. In other words, the DLL driver is always enabled in the active mode period, and the DLL clock is toggled even in a part of the active mode where the DLL clock is not required.

  However, in the conventional delay locked loop (DLL) configured as described above, its output is connected to many buffers and transistor gates in the output data path, and has a large capacitor value. In the delay locked loop (DLL) having such a large resistance, the amount of current consumed by the DRAM increases as the number of output clock toggles increases. Up to several tens of mA.

Therefore, the conventional delay locked loop (DLL) has a problem of wastefully consuming energy by always outputting the clock to a range where the clock is not used.
JP 08-130464 A

  In order to solve the above problems, an object of the present invention is to make a DLL useless for a section other than a necessary section in which a clock is actually used not only in a power down mode and a self-refresh mode but also in a normal mode operation. An object of the present invention is to provide a DLL device for preventing a clock from being toggled and reducing an operation current of a DRAM.

  In order to achieve the above technical problem, the DLL driver control apparatus proposed by the present invention controls the driving of the DLL driver in response to a DLL driver for driving a DLL clock and a signal having information on an active mode. And a DLL driver control unit that generates a control signal for performing the control.

  The DLL driver control unit counts a DLL clock and generates a multi-bit count value. The DLL driver control unit compares the count value with a multi-bit set value. A comparator for generating, and an SR latch for receiving the signal having the information related to the equal signal and the active mode and generating the control signal.

  As described above, the present invention enables the DLL clock to toggle only in a part of the active mode by a signal related to the active mode (read or write) in the middle while the DLL driver is turned off. It is to make.

  That is, the first invention includes a DLL driver that drives a DLL clock, and a DLL driver control unit that generates a control signal for controlling the driving of the DLL driver in response to a signal having information on an active mode. It is a DLL driver control device characterized by comprising.

  In a second aspect of the invention, the DLL driver control unit counts a DLL clock and generates a multi-bit count value, and the count value is compared with a multi-bit set value. A first invention comprising: a comparison unit that generates an activated equal signal; and an SR latch that receives the signal having information on the equal signal and the active mode and generates the control signal. It is the DLL driver control device concerning.

  A third invention is the DLL driver control device according to the second invention, wherein the counter unit is reset by receiving the control signal as a reset signal.

  In a fourth aspect of the invention, the comparison unit receives a plurality of exclusive NOR gates that respectively receive the corresponding bit values of the count value and the set value, and outputs of the plurality of exclusive NOR gates. A DLL driver control device according to a second aspect of the present invention comprises a NAND gate and an inverter that receives an output value of the NAND gate and generates an equal signal.

  According to a fifth aspect of the invention, the comparison unit activates the equal signal when the plurality of bit values of the count value and the plurality of bit values of the set value are respectively compared and matched. A DLL driver control device according to a second invention.

  In a sixth aspect of the invention, the SR latch activates the control signal when a signal having information on the active mode is activated, and deactivates the control signal when the equal signal is activated. A DLL driver control device according to the second aspect of the present invention.

  According to a seventh aspect of the invention, the SR latch has an inverter for receiving a signal having information on the active mode, a first NAND gate having the inverter output as one input, an output of the equal signal and the first NAND gate. The DLL driver control device according to the second aspect of the present invention comprises a second NAND gate that receives and provides its own output as another input of the first NAND gate.

  An eighth invention is the DLL driver control device according to the first invention, wherein the signal having information on the active mode is a read mode.

  A ninth invention is the DLL driver control device according to the first invention, wherein the signal having information on the active mode is a write mode.

  A tenth aspect of the invention controls the DLL driver in response to a DLL clock generation unit characterized by generating a DLL clock, a DLL driver for driving the DLL clock, and a signal having information on the active mode. And a DLL driver control unit that generates a control signal for performing a delay signal.

  In an eleventh aspect of the invention, a DLL clock generation unit receives and buffers an external clock to generate an internal clock, a phase delay unit that receives a source clock and delays and outputs the phase. A dummy phase delay unit having substantially the same configuration as the phase delay unit, and a delay replica model unit that models the output signal of the dummy phase delay unit by a delay element of a clock signal in a memory and outputs it as a feedback signal A phase comparator that receives a reference clock and the feedback signal and detects a phase difference between the two signals; an output signal received from the phase comparator; and the phase delay unit and the dummy phase delay unit A delay locked loop according to a tenth aspect of the invention, comprising a delay control unit that controls a phase delay.

  In a twelfth aspect of the invention, when the DLL driver control unit matches a counter unit that counts a DLL clock to generate a multi-bit count value and the count value is compared with a multi-bit set value, A tenth aspect of the present invention, comprising: a comparison unit that generates an activated equal signal; and an SR latch that receives the signal having information about the equal signal and the active mode and generates the control signal. 3 is a delay locked loop according to the invention.

  A thirteenth invention is the delay locked loop according to the twelfth invention, wherein the counter unit is reset by receiving the control signal as a reset signal.

  In a fourteenth aspect of the invention, the comparison unit receives a plurality of exclusive NOR gates that respectively receive the corresponding bit values of the count value and the set value, and outputs each of the plurality of exclusive NOR gates. The delay locked loop according to the twelfth aspect of the present invention comprises a NAND gate for receiving and an inverter for receiving an output value of the NAND gate and generating an equal signal.

  In a fifteenth aspect of the invention, the comparison unit compares a plurality of bit values of the count value with a plurality of bit values of the set value, and activates the equal signal when they all match. This is a delay locked loop according to the twelfth invention.

  In a sixteenth aspect of the invention, the SR latch activates the control signal when a signal having information on the active mode is activated, and deactivates the control signal when the equal signal is activated. This is a delay locked loop according to the twelfth aspect of the present invention.

  In an seventeenth aspect of the invention, the SR latch has an inverter that receives a signal having information on the active mode, a first NAND gate that receives the inverter output as one input, an equal signal, and an output of the first NAND gate. A delay locked loop according to the twelfth aspect of the present invention, comprising: a second NAND gate that receives and provides its output as another input of the first NAND gate.

  An eighteenth aspect of the invention is the delay locked loop according to the tenth aspect of the invention, wherein the signal having information relating to the active mode is a read mode.

  A nineteenth aspect of the invention is the delay locked loop according to the tenth aspect of the invention, wherein the signal having information relating to the active mode is a write mode.

  As the clock speed is increased by the configuration of the present invention, the current consumption is controlled, and the current flowing without meaning is reduced, so that the current consumption can be dramatically reduced.

  Hereinafter, a most preferred embodiment of the present invention will be described with reference to the accompanying drawings.

  FIG. 3 is a block diagram of a delay locked loop (DLL) device according to the present invention.

  As shown in FIG. 3, the DLL clocks irclk and ifclk that are phase-synchronized with the external clock by performing a phase update (UPDATE) comprising a clock buffer, a delay line, a phase comparator, a delay control unit, and a delay replica model. A DLL clock generator 500 for generating the DLL clock, the DLL driver 200 for driving the DLL clocks irclk and ifclk, and a control signal for controlling the driving of the DLL driver in response to a signal having information related to the active mode. A DLL driver control unit 100 is provided.

  FIG. 4 is a detailed block diagram of the DLL driver control unit 100 of the present invention.

  As shown in FIG. 4, the DLL driver control unit 100 counts the DLL clock irclk, generates a multi-bit count value, compares the count value with a multi-bit set value 320, and matches A comparator 330 that generates an activated equal signal (eqaul), and an SR latch 340 that receives the signal RD info including information about the equal signal and the active mode, and generates the control signal DEN. At this time, for the multi-bit set value 320, for example, latency-related information that is an MRS set value can be used. That is, there is BL (Burst length) or CL (Cas latency).

Referring to FIG. 3 and FIG. 4, the counter unit 310 counts the DLL clock irclk and generates a multi-bit count value when the DLL clock irclk is input from the outside. The count value is output to the comparison unit 330. The comparison unit 330 compares a plurality of bit values of the count value with a plurality of bit values of the set value 320, and activates the equal signal (equal) when they all match. The SR latch 340 inputs the activated equal signal (equal) and the signal RD info having information related to the active mode, and activates the control signal DEN. The counter unit 310 receives the activated control signal DEN as a reset signal RST, and is reset so that the DLL clock irclk is counted again from the beginning.

  FIG. 5 is an implementation circuit diagram of the comparison unit 330.

  The comparison unit 330 is configured to receive a plurality of exclusive NOR gates (EXNR) that respectively receive the corresponding bit values of the count value and the set value 320, and a NAND that receives outputs of the plurality of exclusive NOR gates EXNR. The gate ND3 includes an inverter INT2 that receives the output value ND3 of the NAND gate and generates an equal signal (eqaul).

  FIG. 6 is an implementation circuit diagram of the SR latch 340. An inverter INT1 that receives a signal RD info having information related to the active mode, a first NAND gate ND1 that receives the inverter output as one input, receives an equal signal and an output of the first NAND gate ND1, and outputs its own output The second NAND gate ND2 is provided as another input of the first NAND gate ND1. The SR latch 340 activates the control signal DEN when the signal RD info having information on the active mode is activated, and activates the control signal DEN when the equal signal (equal) is activated. Plays a deactivating role.

  As described above, when the DLL driver control unit 100 operates, the existing DLL driver control unit 100 controls the DLL driver 200 to be turned off only in a range in which no clock is used, such as the power down mode and the refresh mode. Unlike the normal mode, the DLL driver 200 is used only when the clock is required by performing an operation on whether the clock is actually required in the normal mode or, if necessary, how many clocks are required. By enabling the clock and selectively outputting the clock, the predetermined purpose of reducing unnecessary current consumption can be achieved.

  FIG. 7 is a detailed block diagram of the DLL clock generation unit 500 and shows a normal register control type DLL. As shown in FIG. 7, the DLL clock generation unit 500 is roughly divided into a clock buffer unit 10 (Clock buffer), a frequency divider 20 (Divider), a phase comparison unit 30 (Phase Comparator), a delay control unit 40 (Delay Controller), a phase delay unit 50 (Delay Line), a dummy phase delay unit 60 (Dummy Delay Line), and a delay replica model unit 70 (Delay Replica Model).

  The clock buffer unit 10 receives and buffers the external clocks clk and clkb and generates an internal clock signal iDvd_clk.

  The frequency divider 20 divides the internal clock iDvd_clk to generate a DLL source clock Dvd_clk, and further generates a reference clock ref_clk using the internal clock iDvd_clk. Usually, in order to reduce the power consumption of the delay locked loop circuit, the source clock Dvd_clk is generated by lowering the frequency of the clock received from the outside via a frequency divider.

  The phase comparison unit 30 is a device that detects the phase difference between two clocks by comparing the phases of the input clock and the output clock of the delay locked loop circuit. That is, the phase of the reference clock ref_clk and the feedback signal (Feed back Clock) fed back via the internal circuit of the delay locked loop circuit are compared, and the delay control unit 40 is controlled based on the result of this comparison.

  The delay control unit 40 includes logic that can determine the input path of the phase delay unit 50 and a bidirectional shift register that changes the direction of the path. The shift register receives four input signals (Signal) and performs a shifting operation. The signal input to the shift register is composed of two shifts on the right side (Shifting Right) and two on the left side (Shifting Left). For the shifting operation, a high signal is used so that the two signals do not overlap each other. It is good to have a section that is a level.

  The phase delay unit 50 is a circuit that delays the phase of an externally input clock. At this time, the degree of the phase delay is determined through the phase comparison unit 30 and is controlled by the delay control unit 40 to determine a delay path (Delay Path) for determining the phase delay. The delay line is composed of a large number of unit delay cells (Unit Delay Cells) connected by NAND and NAND. The input of each unit delay cell is connected to the shift register on a one-to-one basis, and the place where the value of the shift register output stage is high is determined as the path through which the clock is input via the clock buffer unit. . The delay line has a rising edge clock (Rising Clock) and a falling edge clock (Falling Clock). This is because the rising edge and the falling edge are processed in the same manner, and distortion (Duty Ratio Distortion) due to any duty ratio is suppressed to the maximum.

  The dummy phase delay unit 60 is a delay line for a feedback signal input to the phase comparator. The configuration is the same as that of the phase delay unit 50.

  The delay replica model unit 70 models delay elements from when a clock outside the chip is input to before the phase delay unit 50 and until the output clock of the phase delay unit 50 is output to the outside of the chip. The accurate delay element determines the distortion value in the performance of the DLL, and the delay replica model unit 70 reduces the basic circuit (Shrink), simplifies, or uses it as it is. There is a way to. Actually, the delay replica model unit 70 models a clock buffer, a fixed delay loop clock driver, an R / F divider (Divider), and an output buffer (Output Buffer) as they are.

  FIG. 8 is a timing diagram for explaining a DLL driver control method according to the present invention. As shown in FIG. 8, when a signal RDinfo having information relating to an active mode such as an externally input read or write mode is input, the control signals DENr and DENf are activated, and the count value B and the set value A At this time, the control signals DENr and DENf are deactivated by the activated equal signal (equal). The DLL clock driver 400 is driven and toggles the DLL clocks RCLK_DLL and FCLK_DLL only during the period in which the control signals DENr and DENf are activated. The rising DLL clock RCLK_DLL is toggled within the high pulse interval of the rising control signal DENr, and the falling DLL clock FCLK_DLL is toggled within the high pulse interval of the falling control signal DENf. This timing diagram may be partially changed depending on the operation state of the DRAM, and the timing diagram shown in the present invention corresponds to an example of this.

  On the other hand, according to another embodiment, when the present invention is not limited to one DLL clock driver but is separated for various uses, the DLL clock driver can be controlled by combining them.

  It should be noted that the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the scope of the technical idea related to the present invention. Belong to the scope.

Block diagram of DLL device according to prior art Circuit diagram of conventional DLL driver controller Block diagram of a delay locked loop DLL device according to the present invention Detailed configuration block diagram of DLL clock driver controller of the present invention One implementation circuit diagram of the comparison unit 330 One implementation circuit diagram of the SR latch 340 Detailed block diagram of DLL clock generator 500 Timing chart for explaining a DLL driver control method according to the present invention

Explanation of symbols

100 DLL driver control unit 200 DLL driver 500 DLL clock generation unit

Claims (17)

  1. A DLL driver that drives the DLL clock;
    A DLL driver control unit that generates a control signal for controlling the driving of the DLL driver in response to a signal having information on the active mode ;
    The DLL driver control unit
    A counter unit that counts the DLL clock and generates a multi-bit count value;
    A comparison unit that compares the count value with a set value of a plurality of bits and, if they match, generates an activated equal signal;
    An SR latch for receiving the equal signal and a signal having information on the active mode and generating the control signal;
    DLL driver control device characterized by comprising a.
  2. The counter unit is
    The DLL driver control device according to claim 1 , wherein the control is reset by receiving the control signal as a reset signal.
  3. The comparison unit is
    A plurality of exclusive NOR gates respectively receiving each corresponding bit value of the count value and the set value;
    A NAND gate receiving each output of the plurality of exclusive NOR gates;
    The DLL driver control device according to claim 1 , further comprising an inverter that receives an output value of the NAND gate and generates an equal signal.
  4. The comparison unit is
    When all matching by comparing a plurality of bit values of a plurality of bit values and the set value of the count value, respectively, DLL driver control device according to claim 1, characterized in that activating the equal signal.
  5. The SR latch is
    When a signal having information on the active mode is activated, the control signal is activated, when the equal signal is activated, to claim 1, characterized in that deactivates the control signal The DLL driver control device described.
  6. The SR latch is
    An inverter for receiving a signal having information on the active mode;
    A first NAND gate having the inverter output as one input;
    DLL driver control device according to claim 1, characterized in that it consists of a first 2NAND gate to provide their output to receive the output of the equal signal and the second 1NAND gate as another input of the first 1NAND gate.
  7.   The DLL driver control device according to claim 1, wherein the signal having information on the active mode is a read mode.
  8.   The DLL driver control device according to claim 1, wherein the signal having information on the active mode is a write mode.
  9. A DLL clock generator characterized by generating a DLL clock;
    A DLL driver that drives the DLL clock;
    A DLL driver control unit that generates a control signal for controlling the driving of the DLL driver in response to a signal having information on the active mode ;
    The DLL driver control unit
    A counter unit that counts the DLL clock and generates a multi-bit count value;
    A comparison unit that compares the count value with a set value of a plurality of bits and, if they match, generates an activated equal signal;
    An SR latch that receives the equal signal and a signal having information on the active mode and generates the control signal;
    Delay locked loop comprising the.
  10. The DLL clock generator
    A clock buffer that receives and buffers an external clock to generate an internal clock;
    A phase delay unit that receives the source clock and outputs the delayed phase;
    A dummy phase delay unit having substantially the same configuration as the phase delay unit;
    Modeling the output signal of the dummy phase delay unit with a delay element of the clock signal in the memory, and outputting a delay replica model unit as a feedback signal;
    A phase comparator that receives a reference clock and the feedback signal and detects a phase difference between the two signals;
    The delay locked loop according to claim 9 , further comprising a delay control unit that receives an output signal from the phase comparison unit and controls a phase delay of the phase delay unit and the dummy phase delay unit.
  11. The counter unit is
    The delay locked loop according to claim 9 , wherein the delay locked loop is reset by receiving the control signal as a reset signal.
  12. The comparison unit is
    A plurality of exclusive NOR gates respectively receiving respective corresponding bit values of the count value and the set value;
    A NAND gate receiving each output of the plurality of exclusive NOR gates;
    The delay locked loop according to claim 9 , further comprising an inverter that receives an output value of the NAND gate and generates an equal signal.
  13. The comparison unit is
    10. The delay locked loop according to claim 9 , wherein a plurality of bit values of the count value and a plurality of bit values of the set value are respectively compared, and when all match, the equal signal is activated.
  14. The SR latch is
    10. The control signal according to claim 9 , wherein the control signal is activated when a signal having information on the active mode is activated, and the control signal is deactivated when the equal signal is activated. The described delay lock loop.
  15. The SR latch is
    An inverter for receiving a signal having information on the active mode;
    A first NAND gate having the inverter output as one input;
    10. The delay locked loop according to claim 9 , comprising: a second NAND gate that receives the equal signal and an output of the first NAND gate and provides its own output as another input of the first NAND gate. 11.
  16. The delay locked loop according to claim 9 , wherein the signal having information on the active mode is a read mode.
  17. The delay locked loop according to claim 9 , wherein the signal having information on the active mode is a write mode.
JP2006182746A 2005-09-29 2006-06-30 Delay-fixed loop clock driver controller Expired - Fee Related JP5086572B2 (en)

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KR20050091650 2005-09-29
KR10-2005-0091650 2005-09-29
KR10-2005-0125353 2005-12-19
KR20050125353A KR100753100B1 (en) 2005-09-29 2005-12-19 Delay locked loop in semiconductor memory device

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