JP5072667B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device used in a high frequency band or the like.

  In recent years, for example, semiconductor devices used in a high-frequency band such as a gallium arsenide field effect transistor (hereinafter referred to as GaAsFET) have been increased in output and are required to cope with heat generated during operation.

  Here, a conventional semiconductor device will be described by taking a semiconductor device using GaAsFET as an example.

  For example, a GaAsFET is mounted on a metal base substrate as a heat generating semiconductor element used for power amplification or the like. A first dielectric substrate made of a material having a higher thermal conductivity than that of the base substrate is placed on one side of the GaAsFET. On the first dielectric substrate, for example, input side matching is performed. A circuit pattern constituting a circuit or the like is formed. On the other hand, on the other side of the GaAsFET, a second dielectric substrate made of a material having a higher thermal conductivity than the base substrate is placed. On the second dielectric substrate, for example, on the output side A circuit pattern constituting a matching circuit or the like is formed. Further, it surrounds the GaAsFET, the first and second dielectric substrates, and is formed at a height with a rectangular frame-shaped side wall on the base substrate. For example, a part of the side wall is made of metal except for a part, and the upper rectangular opening is sealed with a metal lid, for example.

  Further, the input side wall portion of the side wall is formed of an insulator, the input line penetrates through the input side wall portion, and the input lead wire is connected to the input line. The output side wall portion of the side wall is also formed of an insulating material, the output side line penetrates the output side side wall portion, and the output lead wire is connected to the output line.

  Also, between the input line and the circuit pattern on the first insulating substrate, between the circuit pattern and the semiconductor element, between the semiconductor element and the circuit pattern on the second insulating substrate, the pattern and the output Each lead wire is connected by a wire.

  In the configuration described above, an input signal input from the input line is amplified by the GaAs FET and output from the output line, but heat is generated from the FET during operation. This heat is transferred to the base substrate located directly under the GaAsFET. Furthermore, since dielectric substrates having higher thermal conductivity than the base substrate are mounted on both sides of the GaAsFET, the heat generated in the GaAsFET is also transmitted to the first and second dielectric substrates. And transmitted to the base substrate directly under these. Therefore, heat is transmitted to a wide region including the GaAsFET and the first and second dielectric substrates, and the heat radiation surface is widened, so that a semiconductor device with good heat dissipation is realized (Patent Document 1).

However, since the heat transferred by the first and second dielectric substrates is again radiated from the bottom through the base substrate having a relatively low thermal conductivity, the thermal conductivity of the base substrate itself is equivalent to the conventional one. The low thermal resistance performance of the first and second insulating substrates could not be fully utilized. Further, since the thermal expansion coefficients of the first and second dielectric substrates are greatly different from the thermal expansion coefficient of the base substrate, there is a problem that cracks occur if the strength is not maintained due to the difference in expansion due to heat dissipation. On the other hand, if the substrate is enlarged in order to maintain the strength, a large amount of material is used, resulting in an increase in production cost and a decrease in substrate yield.
JP 2006-190711 A

  An object of the present invention is to provide a semiconductor device having a high heat dissipation effect.

The semiconductor device according to the invention, the metal first base plate, formed on a first base substrate of this, high heat transfer layer comprising the material having high thermal conductivity than the first base substrate and formed in the high heat transfer layer, a second base plate made of the same metal as the first base substrate, is formed by the exposure the high heat transfer layer from the first base substrate side A substrate to be mounted, a semiconductor chip mounted on the second base substrate of the substrate , and a first chip mounted on the second base substrate of the substrate and electrically connected to the semiconductor chip . A first dielectric substrate having the circuit pattern formed thereon, and a second circuit pattern formed on the second base substrate of the substrate and electrically connected to the semiconductor chip . And 2 dielectric substrates. That.

The semiconductor device according to the present invention, a metal base plate having a convex portion, and this formed around the convex portions of the base substrate, high heat transfer made of a material having high thermal conductivity than the base substrate a substrate configured by a heat layer, a semiconductor chip placed on said convex portion of said base substrate of said substrate, is mounted on the high heat transfer layer on the substrate, electrically to said semiconductor chip A first dielectric substrate on which a first circuit pattern to be connected is formed, and a second circuit pattern placed on the high heat transfer layer of the substrate and electrically connected to the semiconductor chip And a second dielectric substrate on which is formed.

  According to the present invention, a semiconductor device having a high heat dissipation effect can be provided.

  Embodiments of the present invention will be described below with reference to FIGS.

(First embodiment)
FIG. 1 shows a semiconductor device according to a first embodiment of the present invention. FIG. 1 (a) shows a top view of the semiconductor device, and FIG. 1 (b) shows a broken line A in FIG. FIG. 6 shows a structural cross-sectional view along -A ′.

  The semiconductor device shown in FIG. 1 is formed on a first base substrate 11 made of, for example, copper as a metal material, and has a thermal conductivity higher than that of the first base substrate 11. It has a substrate 14 composed of a high heat transfer layer 12 and a second base substrate 13 formed on the high heat transfer layer 12 and made of copper, which is the same material as the first base substrate 11. is doing. On the substrate 14, for example, a GaAsFET 15 is mounted as a heat generating semiconductor element used for power amplification and the like. On both sides of the GaAsFET 15, a first dielectric substrate 16-1 made of, for example, ceramic, and A second dielectric substrate 16-2 is placed. An input matching circuit 17-1 and an output matching circuit 17-2 are formed on the first and second dielectric substrates 16-1 and 16-2, respectively. -2 and GaAsFET 15 are connected by a wire 18 such as gold. An input line 19 connected to each of the matching circuits 17-1 and 17-2 by wires 18 is provided on the periphery of the substrate 14 on which the GaAsFET 15 and the matching circuits 17-2 and 17-2 are formed. -1 and the output line 19-2 are partly formed, and a dielectric side wall 20 is formed, and the whole is sealed with a metal lid 21 provided on the side wall 20. The high heat transfer layer 12 uses carbon nanotubes having a higher thermal conductivity than copper, which is the material of the first and second base substrates 11 and 13, formed into a plate shape by heat treatment. This carbon nanotube is a material having a high thermal conductivity of about 600 W to 700 watts / mK, and is a flexible material, but also has a brittle property.

  The semiconductor device configured as described above generates heat when a voltage is applied to the GaAsFET 15. The heat generated in the GaAsFET 15 is dissipated toward the substrate 14 provided in the lower part. At this time, the heat generated in the GaAsFET 15 propagates to the high heat transfer layer 12 through the second base layer 13 immediately below, as indicated by an arrow in the figure. Since the high heat transfer layer 12 has a higher thermal conductivity than the second base layer 13, the heat transferred to the high heat transfer layer 12 is transferred earlier than the second base layer 13 and is provided below this. The heat is radiated to the outside through the first base layer 11.

  Thus, by providing the high heat transfer layer 12 having a higher thermal conductivity between the first base layer 11 and the second base layer 13, the thermal resistance from the GaAsFET 15 to the bottom surface can be reduced. Therefore, a high heat dissipation effect can be obtained. Furthermore, since the heat dissipation effect is excellent as described above, it is possible to use a semiconductor element with higher power than in the past.

(Second Embodiment)
Next, another embodiment of the present invention will be described with reference to FIG.

  FIG. 2 shows a semiconductor device according to a second embodiment of the present invention. FIG. 2A shows a top view of the semiconductor device, and FIG. 2B shows a bottom view of the semiconductor device. FIG. 4C is a structural cross-sectional view taken along the broken line AA ′ in FIG.

  The semiconductor device shown in FIG. 2 is characterized in that the high heat transfer layer 12 is exposed in the peripheral portion of the lower surface of the substrate 14 as compared with the semiconductor device of the first embodiment.

  Thus, by exposing the high heat transfer layer 12 having high thermal conductivity to the heat radiating surface which is the lower surface of the substrate 14, heat is released particularly in this exposed region. Therefore, as compared with the first embodiment, the thermal resistance from the GaAsFET 15 to the bottom surface can be further reduced, and a higher heat dissipation effect can be obtained. Furthermore, since the heat dissipation effect is excellent as described above, it is possible to use a semiconductor element with higher power than in the past.

  In addition, the modification in this embodiment is shown in FIG. FIG. 3 is a bottom view showing a semiconductor device which is a modification of the second embodiment. As shown in FIG. 3, even if the exposed region of the high heat transfer layer 12 is provided in a part of the peripheral portion of the lower surface of the substrate 14, as compared with the semiconductor device of the first embodiment, It becomes possible to obtain a higher heat dissipation effect, and furthermore, it is possible to use a semiconductor element with higher power than in the past.

(Third embodiment)
Next, another embodiment of the present invention will be described with reference to FIG.

  FIG. 4 shows a semiconductor device according to a third embodiment of the present invention. FIG. 4A shows a top view of the semiconductor device, and FIG. 4B shows a broken line A in FIG. FIG. 6 shows a structural cross-sectional view along -A ′.

  In the semiconductor device shown in FIG. 4, the high heat transfer layer 12 is formed on the base substrate 22 as compared with the semiconductor device of the first embodiment, and the first dielectric substrate 16 is formed on the high heat transfer layer 12. -1 and the second dielectric substrate 16-2 are placed thereon.

  Even in the semiconductor device formed as described above, the heat generated from the GaAsFET 15 is generated by the high heat transfer layer 12 formed below the first dielectric substrate 16-1 and the second dielectric substrate 16-2. The heat is dissipated from the heat dissipating surface, which is the lower surface of the base substrate 22, via Even with such a structure, the thermal resistance from the GaAsFET 15 to the bottom surface can be reduced, and a high heat dissipation effect can be obtained. Furthermore, since the heat dissipation effect is excellent as described above, it is possible to use a semiconductor element with higher power than in the past.

  Further, as described above, when carbon nanotubes are used as the high heat transfer layer 12, this material functions as a cushioning material because it is a flexible substance. That is, for example, when copper is used as the base substrate 22 and alumina is used as the dielectric substrates 16-1, 16-2 and the side wall 20, copper is a material having a relatively high coefficient of thermal expansion, but alumina is a comparison of the coefficients of thermal expansion. Small material. Therefore, in the conventional structure in which they are in contact, when they are heated by the heat generation of the GaAsFET 15, stress is generated due to the difference in the coefficient of thermal expansion at the contact location, and the dielectric substrates 16-1, 16-2 and the sidewall 20 are damaged. It was the cause. However, in the present embodiment, the high heat transfer layer 12 is provided between the base substrate 22 and the dielectric substrates 16-1 and 16-2 or between the base substrate 22 and the side wall 20. 12 functions as a buffer and can prevent the dielectric substrates 16-1 and 16-2 and the sidewall 20 from being damaged.

(Fourth embodiment)
Next, another embodiment of the present invention will be described with reference to FIG.

  FIG. 5 shows a semiconductor device according to a fourth embodiment of the present invention. FIG. 5A shows a top view of the semiconductor device, and FIG. 5B shows a bottom view of the semiconductor device. FIG. 4C is a structural cross-sectional view taken along the broken line AA ′ in FIG.

  The semiconductor device shown in FIG. 5 is characterized by the lower surface of the substrate 14 as compared with the semiconductor device of the third embodiment, and the high heat transfer layer 12 is exposed at the peripheral portion of the lower surface of the substrate 14. Structure.

  Thus, by exposing the high heat transfer layer 12 having high thermal conductivity to the heat radiating surface which is the lower surface of the substrate 14, heat is released particularly in this exposed region. Therefore, as compared with the third embodiment, the thermal resistance from the GaAsFET 15 to the bottom surface can be further reduced, and a higher heat dissipation effect can be obtained. Furthermore, since the heat dissipation effect is excellent as described above, it is possible to use a semiconductor element with higher power than in the past. Further, similarly to the semiconductor device according to the third embodiment, the dielectric substrates 16-1 and 16-2 and the side wall 20 can be prevented from being damaged.

  In addition, the modification in this embodiment is shown in FIG. FIG. 6 is a bottom view showing a semiconductor device which is a modification of the fourth embodiment. As shown in FIG. 6, even if the exposed region of the high heat transfer layer 12 is provided in a part of the peripheral portion of the lower surface of the substrate 14, as compared with the semiconductor device of the third embodiment, It becomes possible to have a higher heat dissipation effect, and furthermore, it becomes possible to use a semiconductor element with higher power than in the past.

(Fifth embodiment)
Next, another embodiment of the present invention will be described with reference to FIG.

  FIG. 7 shows a semiconductor device according to a fifth embodiment of the present invention. FIG. 7A shows a top view of the semiconductor device, and FIG. 7B shows a bottom surface of the main part of the semiconductor device. FIG. 4C is a structural cross-sectional view taken along the broken line AA ′ in FIG.

  The semiconductor device shown in FIG. 7 is a semiconductor device in which the high heat transfer layer 12 is exposed in the periphery of the lower surface of the substrate 14 as shown in FIG. 12, and a flange portion 23 composed of a part of the second base substrate 13 formed on the high heat transfer layer 12, and the flange portion 23 is composed of a heat sink 24 and a screw. 25 is pressure-bonded. Note that a hole is provided in the flange portion 23 in advance in order to enable crimping with the screw 25. This hole may be a notch (not shown).

  In such a semiconductor device, the heat generated in the GaAsFET 15 propagates to the heat sink 24 via the high heat transfer layer 12. At this time, the high heat transfer layer 12 and the heat radiating plate 24 exposed on the lower surface of the substrate 14 are pressure-bonded by screws 25. Generally, the heat-bonded portion has a low thermal resistance. However, in the present invention, since the high heat transfer layer is further pressure-bonded, heat is efficiently propagated from the high heat transfer layer 12 to the heat radiating plate 24 through the pressure-fixed region. To do.

  In this way, by heat-fixing the high heat transfer layer 12 exposed on the lower surface of the substrate 14 and the heat radiating plate 24, the heat generated in the GaAsFET 15 can be efficiently propagated to the heat radiating plate 24.

  In addition, the modification in this embodiment is shown in FIG. FIG. 8 is a bottom view of an essential part showing a semiconductor device which is a modified example of the fifth embodiment. As shown in FIG. 8, even if the exposed region of the high heat transfer layer 12 is provided in a part of the peripheral portion of the lower surface of the substrate 14, the high heat transfer layer is interposed through the region fixed by pressure bonding. Heat can be efficiently propagated from 12 to the heat sink 24.

  In the present embodiment, the same effect can be obtained even if the semiconductor device placed on the heat sink 24 is the semiconductor device according to the fourth embodiment shown in FIG.

  As mentioned above, although embodiment of this invention was shown, embodiment is not restricted to these.

  For example, in the embodiment of the present invention described above, the GaAsFET 15 is used as the heat generating element. However, the present invention is not limited to the MMIC (Monolithic Microwave Integrated Circuit) on the substrate 14 shown in FIG. The present invention can also be applied when an integrated circuit) is mounted. FIG. 9 shows a semiconductor device to which MMIC is applied.

  FIG. 9 shows a semiconductor device including an MMIC. FIG. 9A shows a top view of the semiconductor device, FIG. 9B shows a bottom view of the main part of the semiconductor device, and FIG. FIG. 3C is a structural cross-sectional view taken along the broken line AA ′ in FIG.

  The semiconductor device shown in FIG. 9 has substantially the same structure as the substrate 14 shown in FIG. 2, and the MMIC 26 is placed on the substrate 14. However, although the side wall 20 is provided on the second base substrate 13 in FIG. 2, the semiconductor device shown in FIG. 9 is integrally formed with the second base substrate 13 including the side wall portion 20 ′. Yes. The MMIC 26 placed is connected to the input line 19-1 and the output line 19-2 formed through the side wall portion 20 'by wires 18 together.

  The semiconductor device configured in this manner propagates heat generated during operation of the MMIC 26 to the high heat transfer layer 12 via the second base layer 13 provided below the MMIC 26. Since the high heat transfer layer 12 has a higher thermal conductivity than the second base layer 13, the heat transferred to the high heat transfer layer 12 is transferred earlier than the second base layer 13 and is provided below this. The heat is radiated to the outside through the first base layer 11.

  Thus, by providing the high heat transfer layer 12 having a higher thermal conductivity between the first base layer 11 and the second base layer 13, the thermal resistance from the MMIC 26 to the bottom surface can be reduced. Therefore, a high heat dissipation effect can be obtained. Furthermore, since the heat dissipation effect is excellent as described above, it is possible to use a semiconductor element with higher power than in the past.

  In the semiconductor device shown in FIG. 9, the high heat transfer layer 12 exposed from the lower surface of the substrate 14 is provided in the peripheral portion of the substrate 14. However, as shown in FIG. Even if the high heat transfer layer 12 is exposed on a part of the lower surface of the substrate 14, a higher heat dissipation effect can be obtained.

  Moreover, in embodiment mentioned above, the example which used the ceramic as the 1st, 2nd dielectric substrate 16-1, 16-2 was demonstrated. However, other materials may be used for the first and second dielectric substrates 16-1 and 16-2. For example, a dielectric having higher thermal conductivity than the base substrate is used as in the prior art. By using it, it is possible to obtain a higher heat dissipation effect.

  In the above-described embodiment, the case where the input matching circuit 17-1 and the output matching circuit 17-2 are formed as circuit patterns has been described. However, the circuit pattern is not limited to the input matching circuit 17-1 and the output matching circuit 17-2. For example, a circuit having a stub structure in which a circuit for further suppressing harmonics is provided on the input matching circuit 17-1 and the output matching circuit 17-2.

  In the above-described embodiment, an example in which carbon nanotubes are used as the high heat transfer layer 12 has been described. However, the high heat transfer layer 12 may be made of a material having a higher thermal conductivity than the base substrate. For example, diamond, silicon carbide, sapphire, aluminum nitride, carbon nanotube, carbon fiber, graphite sheet, or the like may be used.

1A is a semiconductor device according to a first embodiment of the present invention. FIG. 1A shows a top view of the semiconductor device, FIG. 2B shows a broken line AA ′ in FIG. FIG. FIG. 2A is a top view of the semiconductor device according to the second embodiment of the present invention, FIG. 2B is a bottom view of the semiconductor device, and FIG. FIG. 3C shows a structural cross-sectional view along the broken line AA ′ in FIG. It is a bottom view which shows the semiconductor device which is a modification of 2nd Embodiment. FIG. 4A shows a top view of the semiconductor device according to the third embodiment of the present invention. FIG. 2B shows a semiconductor device according to a broken line AA ′ in FIG. FIG. FIG. 4A shows a semiconductor device according to a fourth embodiment of the present invention. FIG. 1A shows a top view of the semiconductor device, FIG. 2B shows a bottom view of the semiconductor device, and FIG. FIG. 3C shows a structural cross-sectional view along the broken line AA ′ in FIG. It is a bottom view which shows the semiconductor device which is a modification of 4th Embodiment. FIG. 5A is a semiconductor device according to a fifth embodiment of the present invention, FIG. 1A shows a top view of the semiconductor device, FIG. 1B shows a bottom view of the main part of the semiconductor device, FIG. 4C shows a structural cross-sectional view along the broken line AA ′ in FIG. It is a bottom view of the principal part which shows the semiconductor device which is a modification of 5th Embodiment. A semiconductor device including an MMIC inside, which is another embodiment of the present invention, FIG. 1A shows a top view of the semiconductor device, and FIG. FIG. 2C shows a structural cross-sectional view taken along the broken line AA ′ in FIG. It is a bottom view which shows the semiconductor device which is the modification of other embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 11 ... 1st base substrate 12 ... Material layer 13 ... 2nd base substrate 14 ... Substrate 15 ... GaAsFET
16-1 ... 1st dielectric substrate 16-2 ... 2nd dielectric substrate 17-1 ... Input matching circuit 17-2 ... Output matching circuit 18 ... Wire 19-1 ... input line 19-2 ... output line 20 ... side wall 20 '... side wall part 21 ... lid 22 ... base substrate 23 ... flange part 24 ... heat sink 25 ... Screw 26 ... MMIC

Claims (7)

Metallic first base plate, the first formed in the base substrate, the high heat transfer layer made of a material having high thermal conductivity than the first base substrate of this, and the high heat transfer layer formed thereon, a second base plate made of the same metal as the first base substrate, is composed of a substrate wherein the high heat transfer layer is exposed from the first base substrate side,
A semiconductor chip mounted on the second base substrate of the substrate ;
A first dielectric substrate mounted on the second base substrate of the substrate and formed with a first circuit pattern electrically connected to the semiconductor chip ;
A second dielectric substrate mounted on the second base substrate of the substrate and formed with a second circuit pattern electrically connected to the semiconductor chip ;
A semiconductor device comprising: Metal base plate having a convex portion, and this formed around the convex portions of the base substrate, a substrate configured by the high heat transfer layer, the thermal conductivity is made of a material higher than the base substrate ,
A semiconductor chip mounted on said convex portion of said base substrate of said substrate,
A first dielectric substrate formed on the high heat transfer layer of the substrate and formed with a first circuit pattern electrically connected to the semiconductor chip ;
A second dielectric substrate formed on the high heat transfer layer of the substrate and formed with a second circuit pattern electrically connected to the semiconductor chip ;
A semiconductor device comprising: The semiconductor device according to claim 2, wherein the high heat transfer layer is exposed from a part of a lower surface of the substrate. A flange portion constituted by a part of the high heat transfer layer exposed from the first base substrate side of the substrate and a part of the second base substrate formed on the high heat transfer layer. A semiconductor device according to claim 1 ,
A heat sink on which the semiconductor device is mounted;
Comprising
The said flange part has a hole or a notch for crimping | fixing and fixing the said high heat-transfer layer of the said flange part to the said heat sink with a screw | thread. The semiconductor device according to claim 3, wherein a flange portion is provided in a part of the high heat transfer layer exposed from a part of the lower surface of the substrate;
  A heat sink on which the semiconductor device is mounted;
  Comprising
  The said flange part has a hole or a notch for crimping | fixing and fixing the said high heat-transfer layer of the said flange part to the said heat sink with a screw | thread. It said first circuit pattern is input matching circuit, the semiconductor device according to any one of claims 1 to 5, characterized in that said second circuit pattern is matching circuit output. The high heat transfer layer, diamond, silicon carbide, sapphire, semiconductor device according to any one of claims 1 to 6, characterized in that it is formed of aluminum nitride, carbon nanotubes, carbon fibers, in either of the graphite sheet .

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