JP5067134B2 - Display device and driving method of display device - Google Patents

Description

  The present invention relates to a display device and a display device driving method, and can be applied to, for example, an active matrix display device using an organic EL (Electro Luminescence) element. In the present invention, when the voltage between the terminals of the signal level holding capacitor is set to the threshold voltage of the driving transistor by discharging the voltage between the terminals of the signal level holding capacitor by the driving transistor in a plurality of periods. A capacitor is provided in the capacity between the gate and source of the write transistor, and the terminal voltage of the signal level holding capacitor is reduced by coupling with this capacitor, thereby correcting variations in the threshold voltage of the drive transistor in multiple steps. Even in this case, it is possible to correct the variation in the threshold voltage of the driving transistor correctly.

  2. Description of the Related Art Conventionally, an active matrix type display device using organic EL elements has a display unit formed by arranging pixel circuits based on pixels of organic EL elements and drive circuits for driving the organic EL elements in a matrix. Each pixel circuit is driven by a horizontal drive circuit and a vertical drive circuit arranged around the image display device to display a desired image.

  Regarding a display device using this organic EL element, Japanese Patent Application Laid-Open No. 2005-345722 discloses a method for correcting the variation in threshold voltage of a driving transistor for driving the organic EL element and setting the gradation of each pixel. A configuration has been proposed in which image quality deterioration due to variations in threshold voltage is prevented and high image quality can be ensured even when N-channel transistors are used. Japanese Patent Laid-Open No. 2007-133284 proposes a configuration in which the process of correcting the variation in threshold voltage is executed in a plurality of times. Japanese Patent Application Laid-Open No. 2007-133284 also discloses a method for preventing image quality deterioration due to variations in mobility of transistors that drive organic EL elements.

  FIG. 3 is a connection diagram showing the display device disclosed in Japanese Patent Laid-Open No. 2005-345722. In this display device 1, a horizontal drive circuit 3 is constituted by a horizontal selector (HSEL) 2, and a drive scanner (DSCN) 4A, a light scanner (WSCN) 4B, first and second auto-zero scanners (AZCN1 and AZCN2) 4C. And 4D constitute a vertical drive circuit 5.

  Here, the horizontal selector 2 distributes the image data D1 to the signal lines SIG by sequentially latching the input image data D1 by a plurality of latch circuits respectively corresponding to the signal lines SIG of the display unit 6. Further, the image data D1 distributed to each signal line SIG is subjected to digital-analog conversion processing, and a drive signal Ssig sequentially indicating the gradation of each pixel connected to each signal line SIG is generated for each signal line SIG. The horizontal selector 2 outputs this drive signal Ssig to the corresponding signal line SIG.

  The write scanner 4A, the drive scanner 4B, and the first and second auto zero scanners 4C and 4D sequentially transfer the reference signals generated by a signal generation circuit (not shown), thereby driving the driving signals DS, WS, AZ1 and AZ2 are generated, and the drive signals DS, WS, AZ1, and AZ2 are output to the corresponding scanning lines.

  The display unit 6 is formed by arranging predetermined pixel circuits 7 in a matrix. Here, the pixel circuit 7 is an organic light-emitting element that is a current-driven light-emitting element by an NMOS transistor TR1 (hereinafter referred to as a drive transistor) having a source follower circuit configuration in which both ends of a signal level holding capacitor C1 are connected to a gate and a source. The EL element 8 is driven. Here, Cp is a capacitance component of the organic EL element 8. Vcat is a cathode voltage of the organic EL element 8.

  The drive transistor TR1 has a drain connected to the drive power supply Vcc via an NMOS transistor TR2 that is turned on and off by a drive signal DS that is a drive signal output from the drive scanner 4B. Thereby, the pixel circuit 7 controls the supply of the power source Vcc to the drive transistor TR1 by the on / off control of the transistor TR2 by the drive signal DS, and the light emission and the non-light emission are controlled.

  The driving transistor TR1 is connected to NMOS transistors TR3 and TR4 which are turned on and off by first and second autozero signals AZ1 and AZ2, which are driving signals output from the first and second autozero scanners 4C and 4D, respectively. The gate and the source are connected to the first and second reference power sources Vini and Vss2. Thus, the pixel circuit 7 sets the potentials at both ends of the signal level holding capacitor C1 to the reference voltages Vini and Vss2, respectively, by controlling the transistors TR3 and TR4 with the first and second auto zero signals AZ1 and AZ2.

  The drive transistor TR1 has a gate connected to the signal line SIG via an NMOS transistor TR5 (hereinafter referred to as a write transistor) that is turned on and off by a write signal WS that is a drive signal output from the write scanner 4A. Thus, in the pixel circuit 7, the voltage of the drive signal Ssig output to the signal line SIG is set at one end of the signal level holding capacitor C1 by the control of the write transistor TR5 by the write signal WS.

  Here, FIG. 4 is a time chart for explaining the operation of the pixel circuit 7. Here, in the display unit 6, the gradation of each pixel circuit 7 is set by the line sequence in units of frames so as to show the connection of the signal line SIG to the driving transistor TR 1 by signal writing in FIG. In each pixel circuit 7, before and after one horizontal scanning period (1H) for setting the gradation, a certain period is set as the non-light emitting period T1, and the rest is set as the light emitting period T2 (FIG. 4B). .

  In the pixel circuit 7, when the non-light emission period T1 starts at the time point t1, the transistors TR3 and TR4 are set to the on state by the first and second auto zero signals AZ1 and AZ2 (FIGS. 4C and 4D). The gate voltage Vg and the source voltage Vs (FIGS. 4E and 4F) of the drive transistor TR1 are set to the reference voltages Vss2 and Vini, respectively. Here, the reference voltages Vss2 and Vini are set such that the potential difference Vss2−Vini is sufficiently larger than the threshold voltage Vth of the drive transistor TR1. Thereby, in the pixel circuit 7, the potential difference between both ends of the signal level holding capacitor C1 is set to a voltage larger than the threshold voltage Vth of the driving transistor TR1.

  Subsequently, at the time point t2, in the pixel circuit 7, the first auto-zero signal AZ1 is lowered, and the source-side transistor TR3 of the driving transistor TR1 is set to an off state. Thereby, in the pixel circuit 7, a driving current corresponding to the gate-source voltage Vgs of the driving transistor TR1 flows out from the source of the driving transistor TR1. Here, the gate-side reference voltage Vss2 of the drive transistor TR1 is set to the cathode voltage Vcat of the organic EL element 8 so that the drive current by the drive transistor TR1 charges the organic EL element 8 side end of the signal level holding capacitor C1. In comparison, the anode voltage of the organic EL element 8 is set to a voltage that maintains a sufficiently low voltage. As a result, in the pixel circuit 7, the voltage at the end of the signal level holding capacitor C1 on the organic EL element 8 side gradually increases due to charging by the driving transistor TR1, and the voltage between the terminals of the signal level holding capacitor C1 gradually decreases. When this inter-terminal voltage reaches the threshold voltage Vth of the driving transistor TR1, the driving transistor TR1 switches to an off state, and the decrease of the inter-terminal voltage of the signal level holding capacitor C1 stops. Thereby, in the pixel circuit 7, the potential difference between both ends of the signal level holding capacitor C1 is set to the threshold voltage Vth of the driving transistor TR1.

  In the pixel circuit 7, at the subsequent time t3, the second auto-zero signal AZ2 is lowered, the gate-side transistor TR4 of the drive transistor TR1 is set to the off state, and the drive signal DS is lowered to drive the drive transistor TR1. The supply of power Vcc to is stopped. At the subsequent time t4, the write signal WS is raised and the write transistor TR5 is set to the on state, whereby the gate of the drive transistor TR1 is connected to the signal line SIG. In the pixel circuit 7, the write signal WS is lowered at a predetermined timing and the write transistor TR5 is set to an off state, whereby the voltage Vsig of the drive signal Ssig output to the signal line SIG is changed to the signal level holding capacitor C1. Is held at one end. Thereby, the pixel circuit 7 corrects the threshold voltage Vth of the driving transistor TR1 set in the signal level holding capacitor C1, and the voltage between the terminals of the signal level holding capacitor C1 corresponds to the voltage Vsig of the driving signal Ssig. Set to the correct voltage.

  The pixel circuit 7 starts to supply the power source Vcc to the transistor TR1 at the start time t5 of the light emission period T2. As a result, the pixel circuit 7 drives the organic EL element 8 with the gate-source voltage Vgs based on the voltage between the terminals of the signal level holding capacitor C1 and drives the organic EL element 8 by the bootstrap operation with the capacitance Cp of the organic EL element 8. Make it emit light. Here, the drive current Ids of the organic EL element 8 by the drive transistor TR1 is expressed by the following equation. Here, Vgs is a gate-source voltage of the driving transistor TR1, and is a voltage difference between both ends of the signal level holding capacitor C1. Μ is the mobility of the transistor TR1, W is the channel width of the transistor TR1, L is the channel length of the transistor TR1, Cox is the capacitance of the gate insulating film per unit area of the transistor TR1, and Vth is the threshold voltage of the transistor TR1. is there.

  3 and 4, the voltage Vsig of the drive signal Ssig output to the signal line SIG after being corrected with the threshold voltage Vth of the drive transistor TR1 is set in the signal level holding capacitor C1. Therefore, it is possible to prevent deterioration in image quality due to variations in the threshold voltage Vth of the driving transistor TR1.

  In the configuration shown in FIG. 3, the voltage across the signal level holding capacitor C1 is set to the reference voltages Vini and Vss2 in advance, and the potential difference Vss2-Vini across the signal level holding capacitor C1 is set to the threshold of the driving transistor TR1. After setting the voltage sufficiently higher than the value voltage Vth, the potential difference across the signal level holding capacitor C1 is set to the threshold voltage Vth of the driving transistor TR1.

  Of the processing for setting the voltage across the signal level holding capacitor C1 to the reference voltages Vini and Vss2 in advance, the setting of the gate side voltage Vss2 of the drive transistor TR1 is performed by the signal line SIG via the write transistor TR5. In this case, the transistor TR4 can be omitted and the configuration of the pixel circuit 7 can be simplified. Further, it is considered that the source side voltage Vini of the driving transistor TR1 can be set by lowering the power supply voltage Vcc. In this way, it is considered that the number of transistors constituting the pixel circuit can be reduced and the display section can be further improved in resolution. In this case, if the technique disclosed in Japanese Patent Application Laid-Open No. 2007-133284 is applied, the process of setting the threshold voltage Vth of the drive transistor TR1 in the signal level holding capacitor C1 is executed in multiple steps. Even when the operating frequency is increased by increasing the resolution, a sufficient time for setting the threshold voltage Vth can be secured, and image quality deterioration due to variations in the threshold voltage Vth of the driving transistor TR1 can be ensured. It can be prevented. In addition, it is considered that the image quality can be further improved by applying the technique disclosed in Japanese Patent Application Laid-Open No. 2007-133284 for preventing the deterioration of the image quality due to the variation in the mobility of the drive transistor.

  FIG. 5 is a block diagram showing a display device that can be considered in consideration of these points. In the display device 11, a display unit 12 is formed on a predetermined insulating substrate, and a horizontal drive circuit 13 and a vertical drive circuit 14 are provided around the display unit 12. The horizontal drive circuit 13 is provided with a horizontal selector (HSEL) 15, and the vertical drive circuit 14 is provided with a write scanner (WSCN) 16A and a drive scanner (DSCN) 16B.

  The horizontal selector (HSEL) 15 distributes the image data D1 to each signal line SIG and performs a digital-analog conversion process in the same manner as the horizontal selector 2. The horizontal selector 15 alternately outputs a predetermined fixed voltage Vofs and the digital-analog conversion result, thereby indicating a gradation indicating the gradation of each pixel connected to the signal line SIG with the fixed voltage Vofs interposed therebetween. A drive signal Ssig based on the continuation of the voltage Vsig is output to each signal line SIG (see FIG. 7C).

  The write scanner 16A and the drive scanner 16B generate the drive signals DS and WS for each scanning line by sequentially transferring the reference signals generated by a signal generation circuit (not shown), respectively. The drive signals DS and WS correspond to the drive signals DS and WS, respectively. Output to the scanning line.

  The display unit 12 is created by arranging pixel circuits (PIX) 17 in a matrix. Here, as shown in FIG. 6, the pixel circuit 17 has a configuration related to the omission of the transistors TR3 and TR4 in that the transistors TR3 and TR4 related to the setting of the reference voltage to the signal level holding capacitor C1 are omitted. Except for the differences, the pixel circuit 7 is configured in the same manner as that of FIG.

  As shown in FIG. 7, in each pixel circuit 17, when the non-light emission period T1 for stopping the light emission of the organic EL element 8 starts at time t1, the voltage of the drive signal DS changes from the voltage Vcc of the light emission period T2 to the reference voltage Vini. It is lowered (FIG. 7B). Here, the reference voltage Vini is set to a voltage lower than a voltage obtained by adding the threshold voltage of the organic EL element 8 to the cathode voltage Vcat of the organic EL element 8. Thereby, in the pixel circuit 17, the drive signal DS side of the drive transistor TR1 functions as a source, the anode voltage of the organic EL element 8 falls, and the organic EL element 8 stops emitting light. Further, the accumulated charge is discharged from the end of the signal level holding capacitor C1 on the side of the organic EL element 8 via the driving transistor TR1, whereby the anode voltage of the organic EL element 8 falls and the organic EL element of the signal level holding capacitor C1. The voltage at the 8-side end (source voltage Vs of the driving transistor TR1) (FIG. 7E) is set to the voltage Vini.

  Subsequently, in the pixel circuit 17, when the signal line SIG falls to the predetermined voltage Vofs by the drive signal Ssig, the write transistor TR5 is switched on by the write signal WS at time t2 (FIGS. 7A and 7C). ). Thus, in the pixel circuit 17, the gate voltage Vg of the drive transistor TR1 is set to the voltage Vofs of the signal line SIG, and the voltage between the terminals of the signal level holding capacitor C1 is set to Vofs−Vini. Here, in the pixel circuit 17, the voltages Vofs and Vini are set so that the inter-terminal voltage Vofs−Vini has the threshold voltage of the drive transistor TR1 larger than Vth. Thus, in the pixel circuit 17, the voltage between the terminals of the signal level holding capacitor C1 is set to a voltage higher than the threshold voltage Vth of the driving transistor TR1 during the period from the time point t1 to the time point t2, and the signal level holding capacitor C1. A preparatory process for setting the threshold voltage Vth of the drive transistor TR1 is executed.

  Subsequently, the pixel circuit 17 maintains the write transistor TR5 in the ON state at the time point t3 during which the drive signal Ssig is held at the fixed potential Vofs, and the drive signal DS is at the voltage Vcc of the light emission period T2. And the supply of power to the driving transistor TR1 is started (FIG. 7B). Subsequently, at the time t4 immediately before the signal level of the signal line SIG is set to the gradation voltage Vsig, the write transistor TR5 is switched to the OFF state by the write signal WS.

  Thereby, the pixel circuit 17 is driven during the period Tth1 from the time point t3 to the time point t4 on the condition that the voltage between the terminals of the signal level holding capacitor C1 is larger than the threshold voltage Vth of the driving transistor TR1. A charging current flows to the organic EL element 8 side end of the signal level holding capacitor C1 through the transistor TR1, and the source voltage Vs of the driving transistor TR1 gradually rises (FIG. 7E). As a result, in the pixel circuit 17, the voltage between the terminals of the signal level holding capacitor C1 gradually approaches the threshold voltage Vth of the drive transistor TR1. Note that the pixel circuit 17 is set so that the organic EL element 8 does not emit light even when the voltage Vs at the side end of the organic EL element 8 is increased by setting the fixed potential Vofs.

  When the write transistor TR5 is switched to the OFF state by the write signal WS at the time point t4, the pixel circuit 17 starts the bootstrap operation by the capacitor Cp of the organic EL element 8, and the gate voltage Vg and the source voltage Vs of the drive transistor TR1. Gradually increases (FIGS. 7D and 7E).

  In the pixel circuit 17, when the signal level of the signal line SIG is set to the voltage Vofs again after a certain period of time, the writing transistor TR5 is switched on by the writing signal WS at time t5, and the gate of the driving transistor TR1 is turned on. Connected to the signal line SIG. Subsequently, at a time point t6 immediately before the signal level of the signal line SIG is set to the gradation voltage Vsig, the write transistor TR5 is switched off by the write signal WS.

  Accordingly, the pixel circuit 17 gradually increases the voltage between the terminals of the signal level holding capacitor C1 during the period Tth2 from the time point t5 to the time point t6 in the same manner as in the period Tth1. When the voltage between the terminals of the signal level holding capacitor C1 reaches the threshold voltage Vth of the drive transistor TR1, the increase in the source voltage Vs stops. Thereby, in the pixel circuit 17, the voltage between the terminals of the signal level holding capacitor C1 is set to the threshold voltage Vth of the drive transistor TR1. In this example, in the example of FIG. 7, the voltage between the terminals of the signal level holding capacitor C1 is set to the threshold voltage Vth of the drive transistor TR1 by two processes of the period Tth1 and the period Tth2. The number of repetitions can be repeated a sufficient number of times so that the voltage between the terminals of the signal level holding capacitor C1 becomes the threshold voltage Vth of the drive transistor TR1, and may be three or more.

  The pixel circuit 17 subsequently drives the write signal TR5 at the time t7 when the drive signal Ssig is set to the gradation voltage Vsig of the pixel circuit 17, and the write transistor TR5 is set to the on state, thereby driving. The gate of the transistor TR1 is connected to the signal line SIG. Further, at a time point t8 when a certain period Tμ has elapsed, the write signal WS is lowered, whereby the gradation voltage Vsig of the drive signal Ssig output to the signal line SIG is held at one end of the signal level holding capacitor C1. . As a result, the pixel circuit 17 corrects the threshold voltage Vth of the driving transistor TR1 set in the signal level holding capacitor C1, and the voltage between the terminals of the signal level holding capacitor C1 is a voltage corresponding to the gradation voltage Vsig. Set to Thereby, in this display device 11, it is possible to prevent image quality deterioration due to variations in the threshold voltage Vth of the drive transistor TR1.

  Here, in the period Tμ from time t7 to time t8, the power supply Vcc is supplied to the drive transistor TR1 with the gate voltage Vg of the drive transistor TR1 set to the gradation voltage Vsig. The source voltage Vs gradually rises according to the gate-source voltage Vgs. Here, the rising speed of the source voltage Vs is faster as the mobility of the driving transistor TR1 is larger according to the equation (1). Further, when the source voltage Vs increases, the gate-source voltage Vgs decreases, so that the source current hardly flows.

  As a result, the pixel circuit 17 reduces the voltage between the terminals of the signal level holding capacitor C1 in the driving transistor having a higher mobility during this fixed period Tμ, and corrects the variation in mobility to prevent the deterioration of the image quality. .

  When the write signal WS falls at time t8, the pixel circuit 17 starts the light emission period T2, and current-drives the organic EL element 8 with the gate-source voltage Vgs based on the voltage between the terminals of the signal level holding capacitor C1. In the light emission period T2, the pixel circuit 17 gradually increases the gate voltage Vg and the source voltage Vs of the drive transistor TR1 set in the period Tμ by the bootstrap operation of the drive transistor TR1 by the capacitor Cp of the organic EL element 8. Then, the organic EL element 8 starts to emit light, and eventually the rise of the gate voltage Vg and the source voltage Vs is stopped, and the gate voltage Vg and the source voltage Vs are held at a constant voltage.

  Incidentally, as shown in FIG. 8, during the period TX from the time point t4 to the time point t5 between the periods Tth1 and Tth2, in the pixel circuit 17, the source current of the driving transistor TR1 is generated by the source current of the driving transistor TR1 by the bootstrap operation of the driving transistor TR1. As a result, the source voltage Vs of the drive transistor TR1 rises. Here, in the pixel circuit 17, the gate voltage Vg of the driving transistor TR1 also increases due to the increase in the source voltage Vs. As a result, during the period TX from the time point t4 to the time point t5, between the gate and source of the driving transistor TR1. The voltage is held at a substantially constant voltage.

However, it is also predicted that the source voltage Vs will rise above the voltage Vofs−Vth due to the rise in the source voltage Vs of the driving transistor during the period from the time point t4 to the time point t5. In this case, when the pixel circuit 17 starts the second period Tth2 that continues at time t5, the inter-terminal voltage ΔV of the signal level holding capacitor C1 becomes equal to or lower than the threshold voltage Vth of the driving transistor TR1, and as a result, In the pixel circuit 17, there is a problem that it is difficult to correct the variation in threshold voltage of the driving transistor TR1 correctly, and the image quality of the display image is deteriorated.
JP 2005-345722 A JP 2007-133284 A

  The present invention has been made in consideration of the above points, and after setting the voltage between the terminals of the signal level holding capacitor to be equal to or higher than the threshold voltage of the driving transistor, the threshold voltage of the driving transistor is divided into a plurality of times. Therefore, it is an object of the present invention to propose a display device and a driving method of the display device that can correct the variation of the threshold voltage of the driving transistor correctly even when the variation of the display device is corrected.

  In order to solve the above-mentioned problems, the invention of claim 1 is directed to a display unit formed by arranging pixel circuits in a matrix, and a horizontal driving circuit and a vertical driving unit via signal lines and scanning lines of the display unit. The pixel circuit is applied to a display device that displays a desired image on the display unit by driving the pixel circuit by a circuit. The pixel circuit includes at least a light emitting element, a signal level holding capacitor, and the signal level holding A driving transistor for connecting both ends of the capacitor to a gate and a source, an anode of the light emitting element to the source, and driving the light emitting element with a driving current according to a voltage between the gate and the source; A write transistor that is turned on by an output write signal and connects a gate of the drive transistor to the signal line; The path outputs a driving signal based on a continuous gradation voltage indicating a gradation of each pixel sandwiching a predetermined fixed voltage to the corresponding signal line, and the vertical driving circuit stops light emission of the light emitting element. In the non-light emission period, the write transistor is turned on by the write signal in a period in which the drive signal is set to the fixed voltage, and the gate side end of the signal level holding capacitor is connected to the signal line By setting the gate side end of the signal level holding capacitor to the fixed voltage and setting the voltage between the terminals of the signal level holding capacitor to a voltage equal to or higher than the threshold voltage of the driving transistor, In the correction pause period in which the drive signal is set to the gradation voltage, the write transistor is turned off by the write signal, and the signal level holding capacitor In the first and second periods in which the drive signal is set to the fixed voltage, the gate-side end is separated from the signal line and at least the correction pause period is interposed therebetween, and the writing is performed by the write signal. The transistor is turned on, the gate side end of the signal level holding capacitor is connected to the signal line, and the light emitting element side end of the signal level holding capacitor is charged by the driving transistor by controlling the power supply of the driving transistor. By doing so, the voltage between the terminals of the signal level holding capacitor is set to the threshold voltage of the drive transistor, and then the write signal is used to set the drive signal to the threshold voltage. By turning on the write transistor and connecting the gate side end of the signal level holding capacitor to the signal line, The gate side end of the signal level holding capacitor is set to the gradation voltage, and the pixel circuit causes the write signal to fall by coupling due to a capacitance provided between the gate and source of the write transistor. The gate voltage and the source voltage of the driving transistor are lowered by the above, and the source voltage is held below the voltage obtained by subtracting the threshold voltage of the driving transistor from the fixed voltage during the correction pause period.

  According to a fourth aspect of the present invention, with respect to a display portion formed by arranging pixel circuits in a matrix, the pixel circuits are arranged by a horizontal drive circuit and a vertical drive circuit via signal lines and scanning lines of the display portion. The pixel circuit is applied at least to a light emitting element, a signal level holding capacitor, and both ends of the signal level holding capacitor. Is connected to the gate and the source, the anode of the light emitting element is connected to the source, and the driving transistor drives the light emitting element with a driving current according to the voltage between the gate and the source, and is output from the vertical driving circuit A write transistor that is turned on by a write signal and connects a gate of the drive transistor to the signal line, and the drive method includes a predetermined transistor A drive signal output step for outputting a drive signal to a corresponding signal line by a continuous gradation voltage indicating a gradation of each pixel sandwiching a constant voltage, and a non-light emission period for stopping light emission of the light emitting element, In a period in which the drive signal is set to the fixed voltage, the write transistor is turned on by the write signal, and a gate side end of the signal level holding capacitor is connected to the signal line. Preprocessing for threshold voltage setting in which the gate side end of the level holding capacitor is set to the fixed voltage and the voltage across the terminals of the signal level holding capacitor is set to a voltage equal to or higher than the threshold voltage of the driving transistor. The write transistor is turned off by the write signal in a correction pause period in which the drive signal is set to the gradation voltage, and the signal In the first and second periods in which the drive signal is set to the fixed voltage, the gate side end of the bell holding capacitor is separated from the signal line, and at least the correction pause period is interposed therebetween. The write transistor is turned on by a signal, the gate side end of the signal level holding capacitor is connected to the signal line, and the light emitting element side end of the signal level holding capacitor is controlled by the power supply of the driving transistor. A threshold voltage setting step of setting a voltage between terminals of the signal level holding capacitor to a threshold voltage of the driving transistor by charging with the driving transistor, and subsequently, the driving signal becomes the gradation voltage. In a set period, the write transistor is turned on by the write signal, and the signal level holding capacitor A gradation voltage setting step for setting the gate side end of the signal level holding capacitor to the gradation voltage by connecting the gate side end of the threshold voltage setting step to the threshold voltage setting step. Reduces the gate voltage and the source voltage of the driving transistor by the fall of the write signal due to the coupling by the capacitance provided between the gate and the source of the write transistor, and during the correction pause period, The source voltage is held below a voltage obtained by subtracting the threshold voltage of the driving transistor from a fixed voltage.

  According to the configuration of claim 1 or claim 4, during the correction suspension period, the signal side holding capacitor is charged at the source side via the driving transistor by the voltage across the signal level holding capacitor, so that the signal level holding capacitor Even when the source side voltage rises, this source voltage can be kept below the fixed voltage minus the threshold voltage of the driving transistor. Therefore, in the subsequent period, the threshold voltage of the driving transistor can be set to the voltage across the terminals of the signal level holding capacitor by the driving transistor to correct the variation in the threshold voltage of the driving transistor. Even when the threshold voltage of the driving transistor is set to be equal to or higher than the threshold voltage of the driving transistor and the variation of the threshold voltage of the driving transistor is corrected multiple times, the threshold voltage of the driving transistor is correctly set. Variations can be corrected.

  According to the present invention, even when the voltage between the terminals of the signal level holding capacitor is set to be equal to or higher than the threshold voltage of the driving transistor and then the variation in the threshold voltage of the driving transistor is corrected multiple times, Variations in the threshold voltage of the driving transistor can be corrected.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings as appropriate.

(1) Configuration of Embodiment FIG. 1 is a block diagram showing a display apparatus according to Embodiment 1 of the present invention in comparison with FIG. In this display device 21, the same components as those of the display device of FIG. 6 are denoted by the corresponding reference numerals, and redundant description is omitted. This display device 21 has the same configuration as the display device described above with reference to FIG. 6 except that a capacitor C2 is provided between the gate and source of the write transistor TR5 that connects the write transistor TR5 to the signal line SIG. The Here, the capacitor C2 is created by a wiring pattern.

  As shown in FIG. 2, the display device 21 is configured to set the voltage between the terminals of the signal level holding capacitor C1 to the threshold voltage Vth of the drive transistor TR1 in a plurality of periods Tth1 and Tth2. The terminal voltage of the signal level holding capacitor C1 is lowered by coupling by the capacitor C2 generated by the fall of the write signal WS, and thereby the signal is corrected during the correction pause period TX between the plurality of periods Tth1 and Tth2. The voltage at the end of the level holding capacitor C1 on the organic EL element 8 side is prevented from rising above the voltage Vofs−Vth. Therefore, the capacitance of the capacitor C2 varies even when the source voltage Vs of the drive transistor TR1 changes variously at the start of the correction pause period TX because the threshold voltage Vth of the drive transistor TR1 varies. Even when the degree μ varies and the rate of increase of the source voltage Vs during the correction pause period TX changes variously, the voltage at the end of the signal level holding capacitor C1 on the organic EL element 8 side is surely maintained during the correction pause period TX. It is set to a capacity that can be held below the voltage Vofs−Vth.

  Here, when the trailing edge of the signal level of the write signal WS is Va, the capacitance between the gate and source of the transistor TR1 is sufficiently small, so that the capacitance of the capacitor C2 (indicated by the symbol of the capacitor C2) and the driving transistor TR1. The gate voltage of the gate voltage Vg of the drive transistor TR1 is reduced by coupling by a voltage ΔVa obtained by dividing the voltage Va by the capacitance between the gate and the ground, and this voltage drop ΔVa can be expressed by the following equation. it can.

  Therefore, the source voltage Vs of the drive transistor TR1 drops by the voltage ΔVs shown in the following equation due to the fall of the signal level of the write signal WS.

  The capacitance of the capacitor C2 and the voltage of the write signal WS are set in consideration of the relationship between the expressions (2) and (3) and the variation of the drive transistor TR1. In FIG. 2, the gate voltage Vg and the source voltage Vs of the drive transistor TR1 according to this embodiment are indicated by solid lines, and the gate voltage Vg and the source voltage Vs described above with reference to FIG. 7 are indicated by broken lines.

(2) Operation of Example In the above configuration, in the display device 21 (FIG. 1), the display unit 22 is driven by the horizontal drive circuit 13 and the vertical drive circuit 14 to sequentially form the pixel circuit 27 of the display unit 22 in units of lines. The gradation voltage Vsig of the signal line SIG is set, the organic EL element 8 of each pixel circuit 27 emits light by the set gradation voltage Vsig, and a desired image is displayed on the display unit 22.

  That is, in the display device 21, in the non-light emission period T1 (see FIG. 7), one end of the signal level holding capacitor C1 provided in each pixel circuit 27 is set to the gradation voltage Vsig of the signal line SIG, and the light emission period T2 Then, the organic EL element 8 is driven by the drive transistor TR1 by the gate-source voltage Vgs based on the voltage between the terminals of the signal level holding capacitor C1. Thereby, in this display device, the organic EL element 8 of each pixel circuit 27 emits light with the light emission luminance corresponding to the gradation voltage Vsig of the signal line SIG.

  Prior to the setting of the gradation voltage Vsig, when the non-light emission period T1 starts, the display device 21 first sets the voltage difference between both ends of the signal level holding capacitor C1 to a voltage equal to or higher than the threshold voltage Vth of the drive transistor TR1. After the setting, the source side end of the signal level holding capacitor C1 is charged by a current according to the voltage between the terminals of the signal level holding capacitor C1, and the voltage between the terminals of the signal level holding capacitor C1 is changed to that of the driving transistor TR1. Set to threshold voltage. Thereafter, the display device 21 connects the gate of the driving transistor TR1 to the signal line SIG and sets the voltage at one end of the signal level holding capacitor C1 to the gradation voltage Vsig, whereby the threshold voltage of the driving transistor TR1 is set. Corrected by Vth, the voltage between the terminals of the signal level holding capacitor C1 is set to a voltage corresponding to the gradation voltage Vsig. Thereby, in the display device 21, image quality deterioration due to variations in the threshold voltage of the drive transistor TR1 is effectively avoided. Further, when setting the gradation voltage Vsig, the power is supplied to the driving transistor TR1 by being connected to the signal line SIG for a certain period Tμ, whereby the voltage between the terminals of the signal level holding capacitor C1 is moved by the driving transistor TR1. The image quality is prevented from being deteriorated due to variations in mobility of the drive transistor TR1.

  Further, in the pixel circuit 27, after the voltage between the terminals of the signal level holding capacitor C1 is set to a voltage equal to or higher than the threshold voltage Vth of the driving transistor TR1, the signal level holding is divided into two periods Tth1 and Tth2. The terminal voltage of the capacitor C1 is discharged by the drive transistor TR1 and set to the threshold voltage of the drive transistor TR1, so that the threshold voltage Vth is set even when the operating frequency is increased by increasing the resolution. It is possible to ensure a sufficient amount of time to prevent image quality deterioration due to variations in the threshold voltage Vth of the drive transistor TR1.

  However, when the voltage between the terminals of the signal level holding capacitor C1 is set to the threshold voltage of the driving transistor TR1 in this way divided into a plurality of periods Tth1 and Tth2, the signal level is held during the first period Tth1. There may be a case where it is difficult to make the voltage between the terminals of the capacitor C1 sufficiently close to the threshold voltage Vth of the drive transistor TR1. In this case, the source voltage Vs of the drive transistor TR1 rises to the voltage Vofs−Vth or more by the bootstrap operation of the drive transistor TR1 in the correction pause period TX between these periods Tth1 and Tth2, and eventually the signal level holding There is a risk that it is difficult to correctly set the voltage across the capacitor C1 to the threshold voltage of the drive transistor TR1.

  Therefore, in this embodiment, the capacitor C2 is arranged between the gate and the source of the write transistor TR5, and when the write signal WS falls and the first period Tth1 ends, the cup of the write signal WS by the capacitor C2 is terminated. The gate voltage Vg and the source voltage Vs of the transistor TR1 are lowered by the ring, and the source voltage Vs of the driving transistor TR1 is set so as not to exceed the voltage Vofs−Vth during the correction pause period TX.

  Thus, in this embodiment, the signal level holding capacitor is used in the subsequent second period Tth2 on the condition that the voltage between the terminals of the signal level holding capacitor C1 is larger than the threshold voltage Vth of the driving transistor TR1. The inter-terminal voltage of C1 is discharged through the driving transistor TR1, and the inter-terminal voltage of the signal level holding capacitor C1 can be correctly set to the threshold voltage Vth of the driving transistor TR1. Accordingly, it is possible to effectively avoid image quality deterioration due to variations in the threshold voltage Vth of the drive transistor TR1.

(3) Effects of the embodiment According to the above configuration, the voltage between the terminals of the signal level holding capacitor is discharged by the driving transistor in a plurality of periods, and the voltage between the terminals of the signal level holding capacitor is set to the driving transistor TR1. The threshold voltage of the drive transistor is divided into multiple times by reducing the terminal voltage of the signal level holding capacitor by coupling due to the capacitance between the gate and source of the write transistor. Even in the case of correcting the variation of the driving transistor, it is possible to correct the variation of the threshold voltage of the driving transistor correctly.

  In the above-described embodiment, the case where the capacitor C2 is created by the wiring pattern has been described. However, the present invention is not limited to this, and the capacitor C2 may be created by overlapping the gate and the source of the write transistor TR5.

  In the above-described embodiment, the case where the power source of the driving transistor TR1 is controlled by directly controlling the power source output to the scanning line has been described. However, the present invention is not limited to this, and as described above with reference to FIG. The transistor TR2 may be provided to control the power supply of the driving transistor.

  In the above-described embodiment, the drain voltage of the drive transistor TR1 is lowered to the predetermined voltage Vini, the voltage on the organic EL element side of the signal level holding capacitor C1 is lowered, and the terminal voltage of the signal level holding capacitor C1 is driven. Although the case where the threshold voltage is set to be equal to or higher than the threshold voltage of the transistor has been described, the present invention is not limited to this, and as described above with reference to FIG. The present invention can also be widely applied when the capacitor terminal voltage is set to be equal to or higher than the threshold voltage of the driving transistor.

  In the above-described embodiments, the case where an organic EL element is used as a light-emitting element has been described. However, the present invention is not limited to this, and can be widely applied to cases where various current-driven light-emitting elements are used.

  The present invention can be applied to, for example, an active matrix display device using organic EL elements.

It is a block diagram which shows the display apparatus of Example 1 of this invention. 2 is a time chart for explaining the operation of the display device of FIG. 1. It is a connection diagram which shows the conventional display apparatus. 4 is a time chart for explaining the operation of the display device of FIG. 3. It is a block diagram which shows the display apparatus considered when setting the voltage of the one end of the signal level holding | maintenance capacitor | condenser by a signal line. FIG. 6 is a connection diagram of the display device of FIG. 5. 6 is a time chart for explaining the operation of the display device of FIG. 5. It is a time chart with which it uses for description when a threshold voltage cannot be set correctly.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1, 11, 21 ... Display apparatus, 3, 13 ... Horizontal drive circuit, 5, 15 ... Vertical drive circuit, 6, 16, 22 ... Display part, 7, 17, 27 ... Pixel circuit, 8 ... ... Organic EL element, C1 ... Signal level holding capacitor, C2 ... Capacitor, TR1 to TR5 ... Transistor

Claims (4)

By driving the pixel circuit with a horizontal driving circuit and a vertical driving circuit via a signal line and a scanning line of the display unit with respect to a display unit formed by arranging pixel circuits in a matrix, the display unit In a display device that displays a desired image at
The pixel circuit includes:
At least a light emitting element;
A signal level holding capacitor;
A driving transistor for connecting both ends of the signal level holding capacitor to a gate and a source; connecting an anode of the light emitting element to the source; and driving the light emitting element with a driving current according to a voltage between the gate and the source;
A write transistor that is turned on by a write signal output from the vertical drive circuit and connects a gate of the drive transistor to the signal line;
The horizontal drive circuit includes:
A drive signal based on a continuation of gradation voltages indicating the gradation of each pixel sandwiching a predetermined fixed voltage is output to the corresponding signal line;
The vertical drive circuit includes:
In a non-light emitting period for stopping light emission of the light emitting element,
In a period in which the drive signal is set to the fixed voltage, the write transistor is turned on by the write signal, and a gate side end of the signal level holding capacitor is connected to the signal line. After setting the gate side end of the level holding capacitor to the fixed voltage and setting the voltage between the terminals of the signal level holding capacitor to a voltage equal to or higher than the threshold voltage of the driving transistor,
In the correction pause period in which the drive signal is set to the gradation voltage, the write transistor is turned off by the write signal, and the gate side end of the signal level holding capacitor is disconnected from the signal line,
In the first and second periods in which the drive signal is set to the fixed voltage, with at least the correction pause period in between, the write transistor is turned on by the write signal to hold the signal level The gate side end of the capacitor is connected to the signal line, and the light emitting element side end of the signal level holding capacitor is charged by the driving transistor by controlling the power supply of the driving transistor. Set the terminal voltage to the threshold voltage of the drive transistor,
Subsequently, in a period in which the drive signal is set to the gradation voltage, the write transistor is turned on by the write signal, and the gate side end of the signal level holding capacitor is connected to the signal line. By setting the gate side end of the signal level holding capacitor to the gradation voltage,
The pixel circuit includes:
The gate voltage and the source voltage of the driving transistor are lowered by a fall of the write signal by coupling due to a capacitance provided between the gate and the source of the write transistor, and the fixed voltage is applied during the correction pause period. The display device is characterized in that the source voltage is held below a voltage obtained by subtracting a threshold voltage of the driving transistor from The vertical drive circuit includes:
By reducing the drain voltage of the drive transistor, the source-side voltage of the signal level holding capacitor is lowered via the drive transistor, whereby the voltage across the terminals of the signal level holding capacitor is reduced. The display device according to claim 1, wherein the display device is set to a voltage equal to or higher than a threshold voltage. The display device according to claim 1, wherein the capacitor is formed by an overlap of a gate and a source of the write transistor. By driving the pixel circuit with a horizontal driving circuit and a vertical driving circuit via a signal line and a scanning line of the display unit with respect to a display unit formed by arranging pixel circuits in a matrix, the display unit In the driving method of the display device for displaying a desired image at
The pixel circuit includes:
At least a light emitting element;
A signal level holding capacitor;
A driving transistor for connecting both ends of the signal level holding capacitor to a gate and a source; connecting an anode of the light emitting element to the source; and driving the light emitting element with a driving current according to a voltage between the gate and the source;
A write transistor that is turned on by a write signal output from the vertical drive circuit and connects a gate of the drive transistor to the signal line;
The driving method is:
A drive signal output step for outputting a drive signal to a corresponding signal line by a continuous gradation voltage indicating a gradation of each pixel sandwiching a predetermined fixed voltage;
In a non-light emitting period for stopping light emission of the light emitting element,
In a period in which the drive signal is set to the fixed voltage, the write transistor is turned on by the write signal, and a gate side end of the signal level holding capacitor is connected to the signal line. Preprocessing for threshold voltage setting in which the gate side end of the level holding capacitor is set to the fixed voltage and the voltage across the terminals of the signal level holding capacitor is set to a voltage equal to or higher than the threshold voltage of the driving transistor. Steps,
In a correction pause period in which the drive signal is set to the gradation voltage, the write transistor is turned off by the write signal, and the gate side end of the signal level holding capacitor is disconnected from the signal line, at least In the first and second periods in which the drive signal is set to the fixed voltage with the correction pause period in between, the write transistor is turned on by the write signal, and the signal level holding capacitor A terminal of the signal level holding capacitor by connecting the gate side end of the signal level holding capacitor to the signal line and charging the light emitting element side end of the signal level holding capacitor by the driving transistor by controlling the power supply of the driving transistor. A threshold voltage setting step for setting an inter-voltage to a threshold voltage of the drive transistor;
Subsequently, in a period in which the drive signal is set to the gradation voltage, the write transistor is turned on by the write signal, and the gate side end of the signal level holding capacitor is connected to the signal line. A gradation voltage setting step for setting the gate side end of the signal level holding capacitor to the gradation voltage,
The threshold voltage setting step includes:
The gate voltage and the source voltage of the driving transistor are lowered by a fall of the write signal by coupling due to a capacitance provided between the gate and the source of the write transistor, and the fixed voltage is applied during the correction pause period. The method for driving a display device, characterized in that the source voltage is held below a voltage obtained by subtracting a threshold voltage of the driving transistor from

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