JP5051995B2 - Display system - Google Patents

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JP5051995B2
JP5051995B2 JP2005278433A JP2005278433A JP5051995B2 JP 5051995 B2 JP5051995 B2 JP 5051995B2 JP 2005278433 A JP2005278433 A JP 2005278433A JP 2005278433 A JP2005278433 A JP 2005278433A JP 5051995 B2 JP5051995 B2 JP 5051995B2
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data
correction data
display panel
pixels
display
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JP2007086678A (en
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政俊 佐藤
仁志 安田
智紀 松室
和順 高井
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三洋電機株式会社
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Description

  The present invention relates to a display system including an active matrix display panel, and more particularly to a display system that stores correction data in a memory and corrects image data based on the correction data read from the memory.

  In recent years, organic EL display devices using organic electroluminescence (hereinafter referred to as “EL”) elements have attracted attention as display devices that replace CRTs and LCDs. In particular, an organic EL display device having a thin film transistor (hereinafter abbreviated as “TFT”) as a switching element for driving the organic EL element has been developed.

  FIG. 8 shows an equivalent circuit diagram of the organic EL display panel 300. A plurality of gate signal lines 11 for supplying gate signals are arranged extending in the Y direction, and a plurality of data lines 12 for supplying display data Vsig are arranged extending in the X direction. Pixels are arranged in a matrix at intersections of these two signal lines, and these pixels form the display screen 10. Each pixel includes a pixel selection TFT 13, an organic EL element 14, a driving TFT 15 that drives the organic EL element 14, and a storage capacitor 16 that temporarily holds display data Vsig.

  A gate signal line 11 is connected to the gate of the pixel selection TFT 13 to supply a gate signal, and a data line 12 is connected to the drain of the pixel selection TFT 13 to supply display data Vsig. The source of the pixel selecting TFT 13 is connected to the gate of the driving TFT 15. The gate signal is output from the vertical drive circuit 30. The display data Vsig is supplied through the horizontal drive circuit 20.

  A positive potential PVdd is supplied to the source of the driving TFT 15, and the source of the driving TFT 15 is connected to the anode of the organic EL element 14. A negative potential CV is supplied to the cathode of the organic EL element 14.

  The operation of the organic EL display device having the above-described configuration will be described. When the gate signal becomes high level for one horizontal period, the pixel selection TFT 13 is turned on. Then, the display data Vsig is applied from the data line 12 to the gate of the driving TFT 15 through the pixel selecting TFT 13.

  Then, the conductance of the driving TFT 15 changes according to the display data Vsig supplied to the gate, and the corresponding driving current is supplied to the organic EL element 14 through the driving TFT 15, and the organic EL element 14 is lit. When the driving TFT 15 is in an OFF state in accordance with the display data supplied to the gate, no current flows through the driving TFT 15, so the organic EL element 14 is also turned off.

  However, there is a problem that display defects occur due to variations in characteristics of TFTs (particularly, driving TFTs 15) of each pixel. The content of the display failure is that, for example, display unevenness such as horizontal stripes or vertical stripes appears on the display screen 10 of the organic EL display panel 300 due to variations in drive current of the driving TFT 15.

Therefore, in order to take measures against such a display defect as a circuit, as shown in FIG. 9, correction data reflecting display unevenness of each pixel is transferred to a flash memory 40 having a serial interface function (hereinafter referred to as a serial I / F). The correction data is stored in advance in a flash memory, and the correction data is transferred from the serial I / F flash memory 40 to the high-speed SRAM 41 built in the driving LSI 50 and copied, and the correction data stored in the high-speed SRAM 41 is high-speed. The correction data read from the high-speed SRAM 41 and the input image data input from the outside are combined by the combining circuit 42 in the driving LSI 50 to generate corrected display data Vsig, and this display data Vsig Is output to the organic EL display panel 300.
JP 2002-175029 A

  However, the display system shown in FIG. 8 has a problem that the drive LSI 50 incorporates a high-speed SRAM 41, and the correction data increases as the number of pixels increases. It was.

  Therefore, the display system of the present invention includes a thin film transistor, a display panel in which a plurality of color pixels each having a light emitting element driven by the thin film transistor are arranged in a matrix, and correction data corresponding to each of the plurality of pixels. Is stored in advance, the memory for outputting the correction data to a plurality of data buses, the image data input from the outside, and the correction data read from the memory via the data bus are combined in real time for each pixel and displayed. And a driving LSI for outputting to the panel.

  Further, in addition to the above configuration, the memory is configured to continuously output the upper 2 bits of the correction data to one data bus among the plurality of data buses. Is.

  In addition to the above configuration, the memory is configured to continuously output the same bit data of correction data corresponding to adjacent pixels of the same color in the display panel to each data bus. Is.

  According to the display system of the present invention, since a high-speed SRAM for storing correction data in the driving LSI is not required, the chip area of the driving LSI is reduced, and the cost can be significantly reduced. Since the correction data output to each data bus is set using the regularity of the correction data, the correction data output rate to the data bus is reduced and corrected. The power consumption of the memory that stores and outputs data can be reduced.

  Next, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 is a system diagram of a display system according to an embodiment of the present invention. In this display system, correction data reflecting display unevenness of each pixel is stored in the high-speed serial I / F flash memory 40A in advance, and the correction data is read from the high-speed serial I / F flash memory 40A at high speed. The data and the input image data input from the outside are combined in real time by the combining circuit 42A in the driving LSI 50A to generate corrected display data Vsig, and this display data Vsig is output to the organic EL display panel 300. A flash memory is a memory that can be electrically written to and read from and can erase data collectively.

  The combining circuit 42A basically adds or subtracts the correction data to the input image data, but actually performs complex calculation processing including multiplication of coefficients. The drive LSI 50A is operated by the master clock MCLK, but the correction data is read from the high-speed serial I / F flash memory 40A based on the serial clock SCK synchronized with the master clock MCLK.

  In the real-time correction method of input image data based on such correction data, first, using a test apparatus, predetermined test input image data is sent to each display panel 300 without correction to the display panel 300, and the display panel 300. Is displayed. Then, correction data corresponding to the display result is calculated for each pixel, and the calculated correction data for each pixel is written in the high-speed serial I / F flash memory 40A in association with the pixel arrangement. The high-speed serial I / F flash memory 40A is built in the display panel 300. Then, as described above, the correction data is read from the high-speed serial I / F flash memory 40A at high speed, and the input image data is corrected. In such a display system, since it is not necessary to incorporate the high-speed SRAM 41 in the driving LSI 50 as in the prior art, the chip area of the driving LSI 50A is reduced, and the cost can be greatly reduced.

  In the system of the high-speed serial I / F flash memory 40A, as illustrated in FIG. 2, the chip select signal CS and the serial clock SCK for determining the read timing are supplied from the drive LSI 50A to the high-speed serial I / F flash memory 40A. Based on this, the correction data stored in the high-speed serial I / F flash memory 40A is serially output to the serial data buses SIO0 to SIO3 (bus width 4). More specifically, as shown in the timing chart of FIG. 3, a high-speed read start command CMD is sent from the driving LSI 50A to the serial data buses SIO0 to SIO3 while the chip select signal CS is low, and then the chip select signal CS is high. During the period, address data ADR for designating a head address for starting reading is sent from the driving LSI 50A to the serial data buses SIO0 to SIO3.

  Then, the high-speed serial I / F flash memory 40A is set to the high-speed read mode, and the correction corresponding to each address is performed based on the serial clock SCK while sequentially incrementing (or decrementing) the head address specified by the address data ADR. Data is read and output to serial data buses SIO0 to SIO3. Thus, the correction data stored in the high-speed serial I / F flash memory 40A is transferred to the drive LSI 50A via the serial data buses SIO0 to SIO3.

  Next, a correction data transfer format from the high-speed serial I / F flash memory 40A to the driving LSI 50A will be described. First, the first transfer format will be described with reference to the pixel arrangement of the organic EL display panel 300 in FIG. 4 and the timing chart in FIG. The organic EL display panel 300 includes pixels of four colors of white, blue, green, and red. As shown in FIG. 4, the arrangement is such that the first white pixel W1, the first, The blue pixel B1, the first green pixel G1, the first red pixel R1, the second white pixel W2, the second blue pixel B2, the second green pixel G2, the second red pixel R2,. They are arranged in this order. The configuration of each pixel is the same as that shown in FIG. 8. The pixel selecting TFT 13, the organic EL element 14, the driving TFT 15 for driving the organic EL element 14, and the holding capacitor 16 for temporarily holding display data Vsig. It has.

  In the organic EL display panel 300, the organic EL element 14 that emits white light is used in each pixel, and in order to form blue, green, and red pixels, a color filter of each color is formed for each pixel. The reason why white pixels are provided in addition to these three primary color pixels is to ensure high luminance of the display screen 10 of the organic EL display panel 300.

  If the data width of the correction data corresponding to each pixel is 8 bits, the correction data is represented by 8-bit data (D0, D1, D2, D3, D4, D5, D6, D7). Here, D0 to D7 are “0” or “1”. D0 is the least significant bit and D7 is the most significant bit. As shown in FIG. 5, in the first transfer format, correction data (D4, D0) corresponding to each color pixel is assigned to the serial data bus SIO0, and (D5, D1) is assigned to the serial data bus SIO1. , (D6, D2) are assigned to the serial data bus SIO2, and (D7, D3) are assigned to the serial data bus SIO3.

  Then, based on both rising and falling edges of the serial clock SCK, the bit data of the correction data is output from the high-speed serial I / F flash memory 40A to the respective serial data buses SIO0 to SIO3 in the above-described format.

  More specifically, in one transfer cycle, 8-bit correction data (D0 to D7) corresponding to the first white pixel W1 is continuously output to the serial data buses SIO0 to SIO3 in units of 2 bits. Then, 8-bit correction data (D0 to D7) corresponding to the first blue pixel B1 is continuously output to the serial data buses SIO0 to SIO3 every 2 bits, and then 8 corresponding to the first green pixel G1. The bit correction data (D0 to D7) is output to the serial data buses SIO0 to SIO3 continuously every two bits, and then the 8-bit correction data (D0 to D7) corresponding to the first red pixel R1 is 2 Bits are continuously output to serial data buses SIO0 to SIO3. (Same below) That is, correction data is sequentially transferred to the drive LSI 50A corresponding to the pixel arrangement of one line of W1, B1, G1, R1, W2, B2, G2, R2,. Is done.

  The correction data corresponding to each pixel transferred to the driving LSI 50A is combined with the corresponding input image data, and sequentially output to the organic EL display panel 300 as display data Vsig. Thereby, the corrected display data Vsig is supplied through the data line 12 to each pixel of W1, B1, G1, R1, W2, B2, G2, R2,. The In the next transfer cycle, the same correction data transfer is repeated, and the corrected display data Vsig is supplied to the next line on the organic EL display panel 300. In the following, the above operation is repeated until the last line, and one screen is displayed.

  However, in the first transfer format described above, since the correction data differs for each pixel, the correction data output to the serial data buses SIO0 to SIO3 has a high toggle rate, and the high-speed serial drive for driving the serial data buses SIO0 to SIO3. There is a problem that the power consumption of the I / F flash memory 40A is large.

  Therefore, by devising the transfer format using the regularity of the correction data, the correction data output to the serial data buses SIO0 to SIO3 is reduced, and the power consumption of the high-speed serial I / F flash memory 40A is reduced. Reduced. As shown in FIG. 6, such a second transfer format is such that one serial data bus SIO3 of the serial data buses SIO0 to SIO3 has upper 2 bits of data (D7) of 8-bit correction data D0 to D7. , D6) and a transfer format in which these data (D7, D6) are continuously output for the serial data bus SIO3. (D5, D4) is assigned to the serial data bus SIO2, (D3, D2) is assigned to the serial data bus SIO1, and (D1, D0) is assigned to the serial data bus SIO0.

  In general, the upper 2 bits of the correction data (D7, D6) have a low usage rate, and both are likely to be “0”. Therefore, according to the second transfer format described above, the toggle rate of the correction data can be made very small for the serial data bus SIO3. Thereby, the power consumption of the high-speed serial I / F flash memory 40A can be greatly reduced. According to the experiments by the present inventors, the power consumption of the high-speed serial I / F flash memory 40A can be reduced to 20% in the second transfer format compared to the first transfer format.

  Next, in the third transfer format, the same bit data of correction data corresponding to adjacent pixels of the same color in the organic EL display panel 300 is continuously output to each serial data bus SIO0 to SIO3. It is. In the example of FIG. 7, eight pixels W1, B1, G1, R1, W2, B2, G2, and R2 are managed together as one group. The correction data corresponding to adjacent pixels of the same color, that is, W1 and W2, B1 and B2, G1 and G2, and R1 and R2 are the same, or the difference between them is highly probable. The serial data buses SIO0 to SIO3 are continuously output. For example, for W1 and W2, the most significant bit data D7 corresponding to W1 and the most significant bit data D7 corresponding to W2 are continuously output to the serial data bus SIO3, and the serial data bus SIO2 corresponds to W1. The bit data D6 and the bit data D6 corresponding to W2 are continuously output. Thereby, the toggle rate of the correction data output to the serial data buses SIO0 to SIO3 is reduced, and the power consumption of the high-speed serial I / F flash memory 40A is reduced.

  For each of the correction data corresponding to the eight pixels W1, B1, G1, R1, W2, B2, G2, and R2, the first data group of the upper 4 bits (D7, D6, D5, D4) and the lower data The data is divided into 4-bit (D3, D2, D1, D0) second data groups. First, the first data group is output first, and then the second data group is output. The first data group includes upper 2 bits of data (D7, D6), and there is a high probability that these data are “0”. Therefore, the toggle rate of the serial data buses SIO2 and SIO3 is lowered, and the power consumption of the high-speed serial I / F flash memory 40A is further reduced.

  According to the experiments by the present inventors, the power consumption of the high-speed serial I / F flash memory 40A in the third transfer format can be reduced to 30% to 35% as compared with the first transfer format. In the third transfer format, correction data corresponding to two adjacent pixels of the same color (for example, W1 and W2) are grouped into one group, but three adjacent pixels of the same color (for example, W1 and W2) are combined. The correction data corresponding to W3) may be transferred together in one group.

  Further, in the above-described embodiment, a case where the organic EL display panel 300 is configured with pixels of four colors WBGR (white, blue, green, and red) in the first, second, and third transfer formats will be described. However, the present invention is not limited to this, and the same transfer format is used when the organic EL display panel 300 is composed of pixels of three primary colors of RGB (red, green, and blue) excluding W (white). can do.

  In the above-described embodiment, 8-bit correction data is serially output to the serial data buses SIO0 to SIO3 using the high-speed serial I / F flash memory 40A. However, the parallel I / F flash memory is used. In a system that outputs 8-bit correction data in parallel to an 8-bit parallel data bus, it is possible to reduce the toggle rate (data inversion rate) of the correction data and reduce the power consumption of the memory. . Note that the first to third transfer formats in the above-described embodiment are merely examples, and other transfer formats are also conceivable in accordance with the spirit of the present invention.

1 is a system diagram of a display system according to an embodiment of the present invention. FIG. 2 is a system diagram of a high-speed serial I / F flash memory 40A in FIG. It is an operation timing chart of the high-speed serial I / F flash memory 40A. 4 is a diagram showing a pixel arrangement of an organic EL display panel 300. FIG. It is a timing diagram explaining a 1st transfer format. It is a timing diagram explaining a 2nd transfer format. It is a timing diagram explaining a 3rd transfer format. 3 is an equivalent circuit diagram of an organic EL display panel 300. FIG. It is a system diagram of a conventional display system.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Display screen 11 Gate signal line 12 Data line 13 Pixel selection TFT 14 Organic EL element 15 Driving TFT
16 Holding Capacitance 20 Horizontal Drive Circuit 30 Vertical Drive Circuit 40A High-Speed Serial I / F Flash Memory 50A Drive LSI
42A Synthesis Circuit SIO0-SIO3 Serial Data Bus

Claims (5)

  1. A thin film transistor;
    A display panel in which a plurality of pixels of a plurality of colors including light emitting elements driven by a driving current flowing through the thin film transistor are arranged in a matrix;
    Correction data corresponding to display unevenness of the plurality of pixels is stored in advance, and a memory that outputs the correction data to a plurality of data buses;
    The correction data read through the data bus and the image data input from the outside from the memory and synthesized in real time for each pixel and a driving LSI to be outputted to the display panel,
    The memory is configured to continuously output the isotope bit data of the correction data corresponding to the pixels of adjacent same color in the display panel to the data bus, and wherein the upper bit data of the correction data each A display system configured to output to a data bus and then output the remaining lower-order bit data of the correction data to each data bus .
  2. The display system according to claim 1 , wherein the memory is a nonvolatile memory such as a flash memory.
  3. The display system according to claim 1 , wherein the display panel includes pixels of three primary colors of blue, green, and red.
  4. The display system according to claim 1 , wherein the display panel includes three primary color pixels of blue, green, and red and a white pixel.
  5. The display system according to claim 1, wherein the light emitting element is an organic EL electroluminescence element.
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JP5384184B2 (en) 2009-04-23 2014-01-08 グローバル・オーエルイーディー・テクノロジー・リミテッド・ライアビリティ・カンパニーGlobal Oled Technology Llc. Display device
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JPH11282420A (en) * 1998-03-31 1999-10-15 Sanyo Electric Co Ltd Electroluminescence display device
JP2000122598A (en) * 1998-10-20 2000-04-28 Matsushita Electric Ind Co Ltd Display device
JP4447200B2 (en) * 2002-07-19 2010-04-07 Necエレクトロニクス株式会社 Video data transfer method, display control circuit, and liquid crystal display device
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