JP5013450B2 - Semiconductor integrated circuit and single chip microcomputer - Google Patents

Description

  The present invention relates to a single-chip microcomputer having a nonvolatile memory and further to a semiconductor integrated circuit, and more particularly to a technique effective when used for a single-chip microcomputer having a built-in nonvolatile flash memory that can be electrically written and erased. Is.

  Patent Document 1 describes a single-chip microcomputer incorporating a nonvolatile flash memory. This single-chip microcomputer includes a flash memory together with a random access memory (RAM) for data storage connected to a central processing unit (CPU). The flash memory is used for storing CPU programs and data. The contents of the flash memory can be rewritten at any time and the usability can be improved. In the microcomputer described in Patent Document 1, an operation mode in which the built-in CPU controls writing / erasing of the on-chip flash memory and an operation mode in which the external PROM writer controls are selectable. When controlling with the built-in CPU, the built-in CPU executes erasing by repeating the application of the erasing voltage and the control of erasing verification while sequentially executing a dedicated program for controlling writing and erasing. Write is executed by repeating the write verify control. When the operation mode controlled by the PROM writer is set, the microcomputer looks like a flash memory single chip from the outside. In this state, the PROM writer executes erasing by controlling the erasing voltage application and erasing verification, and executes writing by applying the writing voltage and controlling the programming verification.

  On the other hand, the flash memory as a single memory chip described in Patent Document 2 has dedicated hardware that internally controls writing and erasing in response to a write command and an erase command supplied from the outside. When the dedicated hardware is provided, the host CPU outside the system only has to issue commands for writing and erasing to the flash memory, and the host CPU is not occupied by control operations for writing and erasing the flash memory.

JP-A-5-266220 Japanese Patent Laid-Open No. 10-92958

  Prior to the present invention, the present inventors engaged in the development of a single chip microcomputer in which a flash memory module and a main CPU were mounted on a chip. The flash memory module includes a flash memory and a flash control unit, and control of writing and erasing of the flash memory of the flash memory module is performed by program control of a sub CPU of the flash control unit.

  When the main CPU of the microcomputer issues a predetermined command for writing or erasing the flash memory to the sub CPU of the flash control unit, the sub CPU writes or erases the flash memory by sequentially executing instructions in response to the predetermined command. Do. As a result, the main CPU can execute other data processing operations other than access to the flash memory in parallel with the flash memory writing or erasing operation by the sub CPU of the flash control unit, improving the real-time performance. can do.

  In the flash memory of such a single chip microcomputer, instructions of a program executed by the main CPU are stored, and data of a result of executing the instructions of the program by the main CPU is also stored. Prior to the present invention, when developing a single-chip microcomputer equipped with a flash memory, the frequency of storing instruction instructions is high while the frequency of storing program instructions in the flash memory is relatively low. In addition, in order to improve the performance of a single-chip microcomputer, it is necessary to improve the read speed of program instructions stored in the flash memory, and the data size of the program stored in the flash memory is relatively large. On the other hand, the data size of the instruction execution result stored in the flash memory is relatively small as a result of studies by the present inventors.

  For this reason, the flash memory of a single-chip microcomputer is divided into a program storage flash memory and a data storage flash memory that can be read at high speed, and the size of data written to the program storage flash memory is increased while the data storage flash It was considered to reduce the size of data written to the memory. In addition, in order to improve the read performance of the program storage flash memory, it was also considered to access the two program storage flash memories in an interleaved manner.

  However, in a single-chip microcomputer developed in the past, flash memory writing by the sub CPU of the flash control unit only supports a fixed write data size, but does not support different write data sizes. The problem was revealed. Moreover, the flash memory writing by the sub CPU of the flash control unit only supports the writing mode for one flash memory, and does not support the writing mode for two flash memories that are accessed by interleaving. The problem was also revealed.

  The present invention has been made on the basis of the study by the present inventors prior to the present invention as described above, and the object of the present invention is to store program storage nonvolatile memory and data having different write data sizes and write modes. It is an object of the present invention to provide a single chip microcomputer and a semiconductor integrated circuit capable of executing writing to any nonvolatile memory with a storage nonvolatile memory by a common nonvolatile control unit.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The following is a brief description of an outline of typical inventions disclosed in the present application.

  A single chip microcomputer (1) according to one embodiment of the present invention includes a main CPU (2) and an electrically writable and erasable nonvolatile memory module (FLM).

  The nonvolatile memory module (FLM) includes a nonvolatile memory (5, 6, 9) and a nonvolatile control unit (8).

  In response to a command issued from the main CPU (2), the nonvolatile control unit (8) controls writing and erasing of the nonvolatile memory (5, 6, 9).

  The nonvolatile memory (5, 6, 9) includes a program storing nonvolatile memory (5, 6) for storing a program executed by the main CPU (2), and data of an instruction execution result of the program by the main CPU. And a data storage nonvolatile memory (9).

  The data size of the program write to the program storing nonvolatile memory (5, 6) by the nonvolatile control unit (8) is the data size of the data writing to the data storing nonvolatile memory (9) by the nonvolatile control unit (8). It is set to a size different from the data size.

  When the main CPU (2) requests the nonvolatile control unit (8) to write a program to the program storing nonvolatile memory (5, 6), first size information corresponding to the data size of the program writing (H'80) is supplied to the nonvolatile control unit (8).

  When the main CPU (2) requests the nonvolatile control unit (8) to write data to the data storage nonvolatile memory (9), second size information (H corresponding to the data size of the data write) '40) is supplied to the nonvolatile control unit (8).

  The non-volatile control unit (8) responds to the first size information (H′80) and the second size information (H′40) supplied from the main CPU (2) in response to the non-volatile memory ( 5, 6, 9) The program and data are written into the program storing nonvolatile memory (5, 6) and the data storing nonvolatile memory (9) (see FIGS. 1 and 3).

  According to the means according to the one aspect of the present invention, the main CPU (2) can store the program storage nonvolatile memory (5, 6) or the data storage nonvolatile memory of the nonvolatile memory (5, 6, 9). The main CPU (2) supplies data size information (H'80, H'40) to the nonvolatile control unit (8) in response to whether a program or data write is requested to (9). Therefore, the nonvolatile control unit (8) can execute writing to the program storing nonvolatile memory (5, 6) and the data storing nonvolatile memory (9) having different writing data sizes.

  Further, by changing the first data size information (H′80) and the second data size information (H′40) to arbitrary values, the program write data size is made larger than the data write data size. Can be increased, and the write data size can be reduced.

  In the single chip microcomputer (1) according to one preferred embodiment of the present invention, the data size of the program write to the program storing nonvolatile memory (5, 6) by the nonvolatile control unit (8) is the nonvolatile control. It is larger than the data size of data writing to the data storage nonvolatile memory (9) by the unit (8).

  In a single chip microcomputer (1) according to one preferred embodiment of the present invention, the data storage nonvolatile memory includes at least one flash memory (9), and the program storage nonvolatile memory includes at least two flash memories. (5, 6) are included.

  In the single-chip microcomputer (1) according to one more preferred form of the present invention, the nonvolatile control unit (8) writes information in response to the operation mode (H'E8) supplied from the main CPU (2). Data (WD1... WD128) is serially transferred to the two flash memories (5, 6) of the program storing nonvolatile memory (see FIG. 3).

  In the single-chip microcomputer (1) according to one more preferred form of the present invention, the nonvolatile control unit (8) is responsive to another operation mode (H'E9) supplied from the main CPU (2). Write data (WD1... WD128) is alternately transferred to the two flash memories (5, 6) of the program storing nonvolatile memory by interleaving (see FIG. 4).

  In the single-chip microcomputer (1) according to one more preferred mode of the present invention, the operation mode (H′E8) supplied from the main CPU (2) in the writing to the data storage nonvolatile memory (9). In response, the nonvolatile control unit (8) serially transfers write data (WD1... WD64) to the data storage nonvolatile memory (9) (see FIG. 3).

  In the single chip microcomputer (1) according to one specific form of the present invention, the nonvolatile control unit (8) includes a sub CPU (FCPU 12) and a control memory (CRAM 15).

  In the program storing nonvolatile memory (5, 6), writing / erasing for controlling writing and erasing of the nonvolatile memory (5, 6, 9) by the sub CPU (FCPU 12) of the nonvolatile control unit (8) A control program is stored.

  When the system is activated, the program / erase control program stored in the program storing nonvolatile memory (5, 6) is transferred to the control memory (CRAM 15) of the nonvolatile control unit (8).

  Control of writing and erasing of the nonvolatile memory (5, 6, 9) is performed by the sub CPU (FCPU 12) of the nonvolatile control unit (8) in response to a command issued from the main CPU. ) Is executed by executing the instruction of the write / erase control program transferred to (1).

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  In other words, according to the present invention, it is possible to execute writing to any nonvolatile memory of a program storage nonvolatile memory and a data storage nonvolatile memory having different write data sizes and write modes by a common nonvolatile control unit. .

≪Overall configuration of single-chip microcomputer≫
FIG. 1 is a block diagram illustrating a single chip microcomputer according to an embodiment of the present invention.

  The circuit elements constituting the single chip microcomputer 1 shown in the figure are formed on a single semiconductor substrate of single crystal silicon by a CMOS flash memory manufacturing process.

  The microcomputer 1 includes a main CPU 2, a random access memory (RAM) 3, a bus controller (BSC) 4, a flash memory module (FLM), a system controller 10, a peripheral circuit (PRHRL) 11, and an I / O port (IOP) 12. Have.

  The flash memory module (FLM) includes a first program storage flash memory (FLP_A) 5, a second program storage flash memory (FLP_B) 6, a program storage flash read buffer (FLBUF) 7, and a flash for flash write / erase control A control unit (FCU) 8 and a data storage flash memory (FLD) 9 are included.

  The peripheral circuit 11 includes a timer, a pulse output circuit, a serial communication interface, an A / D converter, and the like. Although not shown, circuit modules such as an interrupt controller and a clock oscillator are also mounted.

  The main CPU 2 includes an instruction control unit that fetches and decodes instructions from the program storage flash memories 5 and 6, and an instruction execution unit that performs an operation and the like based on an instruction decode result by the instruction control unit. The random access memory 3 is a work area for the main CPU 2.

  The system controller 10 is connected to external mode terminals MD0 to MD2, a reset terminal RESET, and the like. When the reset terminal RESET is set to the low level, internal initialization is started. When the reset terminal RESET is set to the high level and the reset instruction is released, the main CPU 2 fetches an instruction at the head address of the program, for example, Start the execution operation. When the reset instruction is canceled, the operation mode of the microcomputer is determined according to the state of the mode terminals MD0 to MD2. For example, the operation mode is set to the normal mode or the test mode. The test mode is not particularly limited, but is an operation mode in which functions for device test, device evaluation, and system evaluation can be used as compared with the normal mode.

≪Flash memory module≫
In the flash memory module (FLM), the program storing flash memories 5 and 6 are used for storing a program of the main CPU 2, and the data storing flash memory 9 stores data to be stored in a nonvolatile manner such as data of an instruction execution result by the main CPU 2. Used for These flash memories 5, 6, and 9 have a plurality of nonvolatile memory cells including nonvolatile memory transistors that can be electrically erased and written. For the nonvolatile memory transistor, for example, a stacked gate structure in which a charge storage region such as a floating gate and a control gate are stacked on a channel formation region between a source and a drain can be employed. Alternatively, a split structure in which a selection gate and a memory gate are separately arranged on the channel formation region and a charge storage region such as silicon nitride is formed between the memory gate and the channel formation region may be employed. it can.

  The threshold voltage of the transistor of the nonvolatile memory cell is increased by writing in which electrons are injected into the charge storage region, and the threshold voltage is decreased by discharging electrons accumulated by writing or injecting holes. For example, writing is performed by forming a high electric field between the memory gate and the substrate and injecting hot electrons generated by the source-drain current into the charge storage region. In the case of erasing, hot holes may be generated and injected into the charge storage region, or electrons may be emitted from the charge storage region by a tunnel effect due to a high electric field. In order to form a high electric field, writing pulse voltage is used for writing and erasing pulse voltage is used for erasing. The transistor of the nonvolatile memory cell stores information as a difference in threshold voltage. Information storage by one memory cell is a binary value of a low threshold voltage indicating 1 bit and a high threshold voltage, or a high intermediate value between a low threshold voltage indicating 2 bits and a low intermediate threshold voltage. Any of multi-values such as four values of threshold voltage and high threshold voltage may be used.

≪Bus configuration≫
The single chip microcomputer 1 has an internal bus IBUS, a peripheral bus PBUS, and an external bus EXBUS. Each bus includes signal lines such as a bus request signal, a bus acknowledge signal, a bus command (or a read signal, a write signal, a bus size signal), and a ready signal (or a wait signal) in addition to the address bus and the data bus. .

  The internal bus IBUS is a bus directly connected to the main CPU 2 and other internal bus masters such as a data transfer controller (DTC) and a direct memory access controller (DMAC) (not shown). A small number of circuit modules such as a RAM 3, a bus controller 4, a program storage flash read buffer (FLBUF) 7, and an I / O port 8 are connected to the internal bus IBUS.

  When the main CPU 2 or the like does not use the peripheral bus PBUS, the peripheral bus PBUS is separated from the internal bus IBUS via the bus controller 4. Thereby, it is possible to speed up access by reducing the load on the internal bus IBUS used mainly by the program read of the main CPU 2 or the like. Furthermore, when the main CPU 2 or the like does not use the peripheral bus PBUS, it is possible to maintain the state of the peripheral bus, thereby reducing power consumption. When the main CPU 2 accesses the internal I / O register in the circuit module connected to the peripheral bus PBUS, the access is performed via the internal bus IBUS and the bus controller 4. Access to the internal I / O register is performed in two states. Since the number of connection destinations of the peripheral bus PBUS is larger than that of the internal bus IBUS, the physical scale increases when the bus width of the peripheral bus PBUS is increased. Therefore, the peripheral bus PBUS has, for example, a 16-bit data bus.

  The read operation of the flash memory 4 in the normal mode is performed via the internal bus IBUS. However, a command and data for instructing writing and erasing are supplied to the flash control unit 8 via the peripheral bus PBUS. The writing and erasing operations take time in themselves, and the frequency of the writing and erasing operations is not so high, and is considered to be significantly less than the reading operation via at least the internal bus IBUS. Further, if the flash control unit 8 is directly connected to the internal bus IBUS, the load on the internal bus IBUS is greatly increased.

  The internal bus IBUS and the external bus EXBUS are interfaced by an external bus buffer circuit (BUF) 13. The external bus buffer circuit 13 is included in the input / output port 12. The bus controller 4 performs bus control for the peripheral bus PBUS and the external bus EXBUS.

≪Program storage flash memory and data storage flash memory≫
The program storage flash memories FLP_A (5) and FLP_B (6) are flash memories for storing programs executed by the main CPU 2, and are required to be able to execute reading at high speed. FLP_A (5) and FLP_B (6) are memories having a read data width of 32 bits which is the same as the data width of the internal bus IBUS, but two states are required for access to the internal bus IBUS for read execution. In addition, at least one of FLP_A (5) and FLP_B (6) includes FLP_A (5), FLP_B (6), and data storage flash memory (FLD) 9 by the sub CPU in the flash control unit (FCU) 8. A writing / erasing program for executing writing and control is stored.

  The program storage flash read buffer (FLBUF) 7 is a buffer circuit for storing read data of FLP_A (5) and FLP_B (6). When the main CPU 2 accesses the internal bus IBUS to the flash memory for storing the program and the access destination data does not exist in the buffer in the FLBUF 7, the FLBUF 7 accesses the FLP_A (5) and FLP_B (6). Issue. The 64-bit data read by the access is stored in the buffer in the FLBUF 7 and at the same time, the 32-bit data to be accessed is output to the main CPU 2 via the internal bus IBUS. In this case, since the read time for two states of access to the internal bus IBUS is required, it is possible to ensure the same read performance as when FLP_A (5) and FLP_B (6) are read directly. When the access destination data exists in the buffer in the FLBUF 7, the FLBUF 7 selects the 32-bit data corresponding to the access destination from the 64-bit data stored in the buffer, and passes through the internal bus IBUS. Output to CPU2. In this case, since it is possible to execute reading in the time of one state for accessing the internal bus IBUS, it is possible to realize a reading performance faster than direct reading of FLP_A (5) and FLP_B (6).

  The data storage flash memory (FLD) 9 is a flash memory for storing the program processing result of the main CPU 2 and does not need to be read at high speed. Therefore, the FLD 9 is connected to the peripheral bus PBUS, which is slower than the internal bus IBUS, without a buffer circuit such as the FLBUF 7.

  FIG. 2 is a diagram showing the address arrangement of FLP_A (5) and FLP_B (6) in the address space of the main CPU 2. In order to support 64-bit reading by FLBUF 7, FLP_A (5) is arranged on the upper 32 bits side and FLP_B (6) is arranged on the lower 32 bits side in the address space of the main CPU 2. When writing to a continuous space in the flash memory for storing programs, it is necessary to write FLP_A (5) and FLP_B (6), so writing must be executed in units of 256 bytes. On the other hand, since only the FLD 9 is arranged in the flash memory space for data storage, writing in units of 128 bytes can be executed.

≪Flash control unit≫
A flash control unit (FCU) 8 is a sequencer for executing writing / erasing of FLP_A (5), FLP_B (6), and FLD9. Writing to each of FLP_A (5), FLP_B (6), and FLD9 by the FCU 8 is executed in units of 128 bytes.

  The FCU 8 includes a sub CPU (FCPU) as will be described in detail later. In the normal mode, the sub CPU (FCPU) executes sequential instructions in response to commands issued from the main CPU 2 to control writing and erasing with respect to the flash memories 5, 6, and 9. As a result, the main CPU 2 is released from the writing and erasing control of the flash memories 5, 6, and 9 after issuing the command. However, in the test mode, the main CPU 2 can freely perform trial evaluation and test evaluation of write and erase operations on the flash memory 4 by executing arbitrary various sequential instructions. As a result, it is possible to freely perform writing and erasing control for testing and verification according to a program with a high degree of freedom of the main CPU 2 without being limited to the operation program of the FCPU 12 stored in the flash memories 5 and 6.

<< Operation to write to flash memory >>
FIG. 3 is a diagram illustrating a write operation to a flash memory according to one embodiment of the present invention.

  When a peripheral bus PBUS write is issued to an address assigned for issuing a flash memory write command by issuing a store instruction by the main CPU 2, the FCU 8 executes a process corresponding to the contents of the peripheral bus PBUS write.

  The first write access (C1) data of the peripheral bus PBUS is a cycle for determining the type of command. When the main CPU 2 requests the FCU 8 to write to the flash memory, the peripheral to which H′E8 is written A bus PBUS access may be issued.

  The next write access (S1) of the peripheral bus PBUS is a cycle for the main CPU 2 to determine the size of write data in units of 16 bits. In the case of writing 256 bytes in total for FLP_A (5) and FLP_B (6), the main CPU 2 issues a peripheral bus PBUS access for writing H'80 and writes 128 bytes in total for FLD9. In this case, the main CPU 2 may issue a peripheral bus PBUS access for writing H'40.

  The write access (D1 to D128) of the peripheral bus PBUS after the access S1 is a cycle for transferring write data in units of 16 bits (2 bytes).

  As shown in the upper part of FIG. 3, in the case of writing a total of 256 bytes to FLP_A (5) and FLP_B (6), 128 times (D1 to D128) write access of the peripheral bus PBUS is issued. The FCU 8 continuously serially transfers the data from the first (D1) to the 128th (D128) to the data latches of FLP_A (5) and FLP_B (6) by interleaving. Since FLP_A (5) and FLP_B (6) are alternately accessed by interleaving, the odd-numbered (D1, D3,..., D127) data is stored in the FLP_A (5) data latch, and the even-numbered ( The data of D2, D4,..., D128) are stored in the data latch of FLP_B (6).

  As shown in the lower part of FIG. 3, in the case of writing 128 bytes to the FLD 9, serial data transfer is continuously performed to the data latch of the FLD 9 by issuing 64 (D1 to D64) write accesses to the peripheral bus PBUS. Is executed.

Further, the address of the flash memory to be written is determined by the address of the peripheral bus PBUS access in the D1 cycle. After the transfer of the write data is completed, the access (F1) of the peripheral bus PBUS for writing H′D0 is issued. Then, in the case of 256-byte writing in the upper part of FIG. 3, the FCU 8 performs parallel internal write processing to the flash memory array on the data of WD1 to W128 transferred to the latch with respect to FLP_A (5) and FLP_B (6). . In the case of 128-byte writing in the lower part of FIG. 3, the FCU 8 executes an internal write process for continuously writing the data of WD1 to W64 from the latch to the flash memory array.

  In the write command preceding the write data in the flash memory, there is an S1 cycle for specifying the write size. Therefore, the FCU 8 only has to wait for completion of transfer of the write data of the size specified in the S1 cycle, and the control of the FCU 8 can be simplified. When the transfer of the write data is completed, the FCU 8 executes an internal write process by repeating the program and verify the data transferred to the flash memory latch to the flash memory array. If the S1 cycle does not exist, it is necessary for the FCU 8 to determine the type of flash memory to be written to determine the size of write data, and the control becomes complicated.

  Even when writing to flash memories having completely different write sizes, there is no need to change the control for waiting for completion of transfer of write data of the size specified in the S1 cycle. For this reason, even if addition or change of the flash memory occurs, it is possible to cope without changing the FCU 8.

  The time required for the cycle (S1) for designating the write size is shorter than the time required for the data transfer cycle (D1 to D128) and the flash memory write processing by the FCU 8. Therefore, there is almost no adverse effect on the time required for the write operation to the flash memory in the S1 cycle.

  FIG. 4 is a diagram illustrating a write operation to a flash memory according to another embodiment of the present invention. This operation is a 256-byte interleaved writing in which the flash memory to which data transfer is performed every 16 bits (2 bytes) is alternated between FLP_A (5) and FLP_B (6). The command for performing the interleaved write is different from the 256-byte write command in FIG. 3 in that the value of the write data in the first cycle (C2) is H′E9.

  When a write access to the peripheral bus PBUS corresponding to the final cycle (F1) of the 256-byte interleaved write command is issued, the FCU 8 starts internal write processing for FLP_A (5) and FLP_B (6). In the write process for the interleave write command, the FCU 8 first transfers odd-numbered data WD1, WD3,. To do. After that, the FCU 8 transfers the even-numbered data WD2, WD4... WD128 128-byte data from the FLP_B (6) latch to the FLP_B (6) flash memory array and executes internal writing.

  When the FCU 8 executes the write requested by the 256-byte interleave write command shown in FIG. 4, the transfer data is prepared in advance by classifying the write data for FLP_A (5) and FLP_B (6). To do. After that, it is necessary to transfer pre-preparation data in an order different from that written in the write access of the peripheral bus PBUS when the command is issued.

  On the other hand, in the 256-byte write command shown in FIG. 3, the FCU 8 transfers data to FLP_A (5) and FLP_B (6) in the same order as the write access of the peripheral bus PBUS at the time of command issuance. The 256-byte interleave command shown in FIG. 4 specifies that interleave writing is performed in the first cycle (C2). Therefore, it is not necessary for the FCU 8 to determine the type of flash memory to be written and to switch the writing order of the write data, and it is only necessary to transfer the preparatory data, so that the control of the FCU 8 can be simplified.

  A high voltage needs to be applied to the write destination memory during a period of writing data for the write unit in the flash memory. In the case of the upper method in FIG. 3 in which 256-byte data is written in parallel to FLP_A (5) and FLP_B (6), it is necessary to apply a high voltage to FLP_A (5) and FLP_B (6) simultaneously. Therefore, the power supply capacity must be increased. In the method of FIG. 4, since 128 bytes of data are first internally written to FLP_A (5) and then 128 bytes of data are internally written to FLP_B (6), FLP_A (5) and FLP_B (6) It is not necessary to apply a high voltage simultaneously, and it is not necessary to increase the power supply capability.

≪Configuration of flash control unit≫
FIG. 5 is a diagram showing an internal configuration of a flash control unit (FCU) 5 inside the single chip microprocessor 1 of FIG.

  As shown in the figure, in addition to the sub CPU (FCPU) 12, the FCU 8 includes a flash CPU interface controller (FIMC) 13, a flash bus control circuit (FBSC) 14, a control RAM (CRAM) 15, and a flash write / erase control circuit. (FLC) 16, an error correction circuit (ECC) 33, and a flash bus FBUS. The FCU 8 is arranged in the address space of the main CPU 2, and the main CPU 2 can access the inside of the FCU 8 via the peripheral bus PBUS. That is, the flash CPU interface controller 13 (FIMC) is connected to the peripheral bus PBUS, and performs overall control of the FCU 8 for access from the main CPU 2. The FIMC 13 issues an interrupt request signal IRQ and a corresponding vector to the FCPU 12 to activate the FCPU 12. The FIMC 13 issues a bus command to the flash bus control circuit (FBSC) 14 to control the control RAM 15 and the FLC 16 via the flash bus FBUS. The control RAM 15 is used as a storage area for the flash CPU write / erase operation program of the FCPU 12 or a work area of the FCPU 12. The FLC 16 has an operation control register (FCNTR) 18, an erase block designation register (EBLKR) 17, and a trimming register for the flash memories 5, 6, and 9. The FLC 16 controls the write / erase operation of the flash memories 5, 6, 9 according to the state of the control bit set in the operation control register 18. The control bits of the operation control register 18 are, for example, a write enable bit WE, a write instruction bit P, and an erase instruction bit E. The write enable bit WE indicates the validity of a write / erase operation instruction by a logical value “1”. The write instruction bit P instructs application of a write pulse voltage by a logical value “1”. The erase instruction bit E instructs application of an erase pulse voltage by a logical value “1”. The trimming register of the FLC 16 includes fine adjustment of the voltage levels of the write pulse voltage, the erase pulse voltage, the drain voltage, the source voltage, and the verify voltage of the flash memories 5, 6, 9, and the pulse of the write pulse voltage and the erase pulse voltage. Trimming data for fine adjustment of the width is set.

  The initial values of the trimming data and the write / erase operation program of the FCPU 12 are held in the flash memory 9, and the trimming data and the write / erase operation program are transmitted to the main CPU 2 and the data transfer controller (DTC) in response to a power-on reset. , Not shown) or a direct memory access controller (DMAC, not shown) can be internally transferred to the trimming data register and the control RAM 15, respectively. In the normal mode, the trimming data register and the program area of the control RAM 15 are protected from writing access from the main CPU 2 executing the user program. However, in the test mode, these are freely accessible by the main CPU 2. An erase block or an erase address is set in the erase block designation register 17. Write data and write address are set in the data register and address register in the flash memory.

  The activation of the FCPU 12 by interruption will be described. The FIMC 13 includes an internal I / O register (IIOR) 20, a control register (CNTR) 21, a status register (STSR) 22, an interrupt control register (INTR) 31, which are accessible from the main CPU 2 via the peripheral bus PBUS. A CRAM control register (CRCNTR) 32 is provided. The control register 21 is a setting area for a write / erase flag FENTRY and the like, which is writable by the main CPU 2 and readable by the FCPU 12. The status register 22 is a storage area for a busy flag BUSY, a command end flag CMDE, and the like, which is writable by the FCPU 12 and readable by the main CPU 2. Further, the FCPU 12 writes to the status register 22 from the path 23. If the error bit ERR of the status register 22 is set by the error correction circuit 33 while the interrupt enable bit INTEN of the interrupt control register 31 is set, the error interrupt signal ERRINT is asserted and passed through the bus controller 4. An interrupt request is notified to the main CPU 2. When the error correction circuit 33 detects a data error due to a software error in the write / erase control program of the FCU 12 stored in the control RAM 15, the error correction circuit 33 sets the error bit ERR in the status register 22, and the FCU 12 from the flash memory 5, 6 to the CRAM 15. Requests retransfer of the program / erase control program. The CRAM access enable bit CREN of the CRAM control register 32 is set in order to write the re-transferred program / erase control program of the FCU 12 to the CRAM 15. The CRAM access enable bit CREN is reflected in the CRAM access notification signal CRAMEN, and the CRAM access notification signal CRAMEN is supplied to the bus controller 4. Since the bus controller 4 transfers the write / erase control program of the FCU 12 read from the flash memories 5 and 6 on the internal bus IBUS to the peripheral bus PBUS, any of the main CPU 2, DTC, and DMAC passes through the BSC 4 Retransfer of the FCU 12 write / erase control program to the CRAM 15 is executed.

  When the write / erase flag FENTRY = “1” in the normal mode, when the FIMC 13 detects an access for writing data from the main CPU 2 to the address mapped to the nonvolatile memory array of the flash memory 5, 6, 9, the write access is detected. The FIMC 13 recognizes it as a flash write command. When the FIMC 13 detects an access for writing an erase address or erase block designation information from the main CPU 2 to the erase block designation register 17, the FIMC 13 recognizes the write access as a flash erase command. The FIMC 13 activates the interrupt request signal IRQ to the FCPU 12 according to the command interpretation and issues a vector corresponding to the command. As a result, the FCPU 12 fetches the write control program or erase control program specified by the vector from the control RAM 15 and executes it. When responding to the flash write command, the FCPU 12 fetches the address and data related to the write access recognized as the flash write command in accordance with the write control program from the internal IO register 20 to the control RAM 15 and transfers them to the flash memory. Write to the flash memories 5, 6, 9 while sequentially setting the WE, P bits, and the like. When responding to the flash erase command, the FCPU 12 fetches the erase block designation data recognized as the flash erase command from the internal IO register 20 to the control RAM 15 according to the erase control program, transfers it to the flash memory, and transfers the WE of the FCNTR 18 inside the FLC 16. While the E bit and the like are sequentially set, the flash memory 5, 6, 9 is erased.

  The write / erase flag FENTRY from the FCU 8 is supplied from the FIMC 13 to the bus controller (BSC) 6. When the BSC 4 detects a write access from the main CPU 2 to the mapping addresses of the flash memories 5, 6, 9 or the erase block designation register 17 when the write / erase flag FENTRY = “0” in the normal mode, for example, an address error is generated. Thus, the writing operation to the flash memories 5, 6, 9 is invalidated. Accordingly, when the write / erase flag FENTRY = “0” in the normal mode, the flash memories 5, 6, 9 can only be read accessed via the internal bus IBUS. In the test mode, the write / erase flag FENTRY is used only for controlling the access path to the flash memories 5, 6, and 9 by the BSC 4. That is, when the FENTRY = 1 in the test mode, only the access via the BSC 4 and the peripheral bus PBUS is allowed for the flash memories 5, 6, and 9, and when the FENTRY = “0”, only the read access via the internal bus IBUS is allowed. Is acceptable.

  The access control of the control RAM 15 and the FLC 16 via the flash bus control circuit (FBSC) 14 will be described. In both the normal mode and the test mode, the CPU for the access from the main CPU 2 or DTC or DMAC to the mapping address of the flash control unit (FCU) 5 (excluding the mapping address of the erase block designation register 17) is used. The interface controller (FIMC) 13 issues an access command to the FBSC 14. The FBSC 14 can perform read access and write access to the control RAM 15 and FLC 16 by controlling the flash bus FBUS in accordance with the issued access command. Although not particularly limited, free access to the trimming register of the FLC 16 is not permitted in the normal mode. However, in the test mode, even if there is an access for writing data to the mapping addresses of the flash memories 5, 6, and 9 from the main CPU 2, and there is an access for writing data to the erase block designation register 17 from the main CPU 2. The CPU interface controller 13 does not activate the FCPU 12 and issues a corresponding access command to the FBSC 14. Accordingly, the FBSC 14 controls the flash bus FBUS, supplies the write data and write address held in the internal IO register 20 of the CPU interface controller 13 to the flash memory 5, 6, 9 or erases the erase block address. This is supplied to the block designation register 17. Thereafter, the main CPU 2 can directly operate the erase bit E and the program bit P by issuing a write access to the register 18 of the FLC 16 to perform an erase operation or a write operation.

  In the test mode, since the main CPU 2 can directly operate the trimming register of the FLC 16, depending on the setting of the trimming data, for example, the write pulse voltage, the erase pulse voltage, the pulse application time, the drain in the flash memories 5, 6, 9 The voltage, the source voltage and the like can be finely adjusted. By finely adjusting such voltage and time, optimum writing and optimum erasing control can be performed in accordance with the manufacturing process of the microcomputer 1, the element configuration of the nonvolatile memory, or individual differences of the microcomputer 1. Made possible. These voltages and time should be fixed during mass production, but at least should be variable during trial evaluation.

  Further, in the test mode, the main CPU 2 can rewrite the program / erase control program of the FCPU 12 stored in the control RAM 15. At the time of prototype evaluation, it is possible to check basic functions and necessary parameters by executing writing / erasing by executing a control program by the main CPU 2 in the test mode. During prototype evaluation, device control is not performed, so there is no need to consider interrupt processing that requires real-time performance.

  The error correction circuit (ECC) 33 of the FCU 8 shown in FIG. 5 is a circuit for detecting that the data stored in the control RAM (CRAM) 15 is destroyed. When writing to the CRAM 15 is executed via the flash bus FBUS, the ECC 33 generates an error correction code corresponding to the data output from the FBUS, and writes the error correction code together with the write data to the CRAM 15. When reading to the CRAM 15 is executed via the flash bus FBUS, the ECC 33 generates read data based on the data read from the CRAM 15 and the error correction code, and outputs the read data to the flash bus FBUS. When the ECC 33 detects an error in the data read from the CRAM 15 or the error correction code when the read data is generated, the ECC error signal ECCERR is asserted. The error bit ERR of the status register (STSR) 22 of the FIMC 13 is a flag that is set when the ECC error signal ECCERR is asserted. If the error bit ERR of the STSR 22 is set while the interrupt enable bit INTEN of the interrupt control register (INTR) 31 is set, the error interrupt signal ERRINT is asserted and the main CPU 2 is notified of the interrupt request. Then, using any of the main CPU 2, DTC, and DMAC, the data of the write / erase control program of the flash memory 5, 6, 9 by the FCPU 12 of the FCU 8 stored in the flash memory 5, 6 is retransferred to the CRAM 15 of the FCU 8. To do.

  The CRAM access enable bit CREN of the CRAM control register (CRCNTR) 32 is a bit for controlling permission / prohibition of access to the CRAM 15. When the CRAM access enable bit CREN is “0”, access to the CRAM 15 is prohibited, and when it is “1”, access to the CRAM 15 is permitted. The CRAM access notification signal CRAMEN is a signal for notifying the value of the CRAM access enable bit CREN from the FCU 8 to the BSC 4. The BSC 4 propagates the access of the internal bus IBUS to the CRAM 15 to the peripheral bus PBUS only when the CRAM access notification signal CRAMEN is asserted. However, access to the CRAM 15 issued in a state where the CRAM access notification signal CRAMEN is negated is invalidated.

  In this microcomputer 1, in parallel with the execution of the user program stored in the flash memory 4 after the system is started by the main CPU 2, either the DTC or DMAC is used to transfer the flash memory 5, 6 to the CRAM 15 by the FCPU 12 of the FCU 8. It is possible to transfer a program / erase control program for the flash memories 5, 6, 9. It is also possible for the main CPU 2 to transfer the write / erase control program for the flash memories 5, 6, 9 by the FCPU 12 from the flash memories 5, 6 to the CRAM 15 after the system is activated.

  Further, in the microcomputer 1, it is possible to read out the error bit ERR of the STSR 22 of the FIMC 13 of the FCU 8 by the main CPU 2 or to determine whether the stored data of the CRAM 15 is destroyed by the error interrupt signal ERRINT. When the data stored in the CRAM 15 is destroyed, the program of the write / erase control program of the flash memory 5, 6, 9 by the FCPU 12 of the FCU 8 is transferred from the flash memory 5, 6 to the CRAM 15 by the main CPU 2, DTC, or DMAC. Since retransfer is performed, it is possible to prevent malfunction of the FCU 8 and improve the reliability of the microcomputer.

  Although the invention made by the present inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof.

  In the above description, the case where the invention made mainly by the present inventor is applied to a single chip microcomputer which is a field of use as the background has been described. However, the present invention is not limited thereto, and other semiconductor integrated circuit devices, For example, the present invention can be applied to a semiconductor integrated circuit device centered on a microcontroller and a digital signal processor (DSP).

  Further, as a nonvolatile memory, for example, a phase change memory can be employed in addition to a type in which charges are injected into or discharged from a charge storage region such as a flash memory. For example, erasing a phase change memory causes a current to flow through the resistance of the memory cell, melts the resistance, and then sharply reduces the current to make it polycrystallized to have a high resistance. This can be realized by reducing the current by gradually reducing the current after melting the resistance by flowing it into a single crystal. Even in this phase change memory, the erase process and the write process are repeated processes of applying an erase or write current pulse and a verify operation. The present invention can be applied to at least a semiconductor integrated circuit device incorporating a nonvolatile memory and a data processing device.

FIG. 1 is a block diagram illustrating a single chip microcomputer according to an embodiment of the present invention. FIG. 2 is a diagram showing the address arrangement of the program storing flash memories 5 and 6 in the address space of the main CPU 2 of the microprocessor of FIG. FIG. 3 is a diagram illustrating a write operation to a flash memory according to one embodiment of the present invention. FIG. 4 is a diagram illustrating a write operation to a flash memory according to another embodiment of the present invention. FIG. 5 is a diagram showing an internal configuration of the flash control unit 5 in the single chip microprocessor of FIG.

Explanation of symbols

1 Single-chip microcomputer 2 Central processing unit (CPU)
3 Random access memory (RAM)
4 Bus controller (BSC)
FLM flash module 5 Program storage flash 6 Program storage flash 7 Program storage flash read buffer 8 Flash control unit 9 Data storage flash 10 System controller (SYSC)
MD0 to MD2 Mode terminal 11 Peripheral circuit (PRHRL)
12 I / O port (IOP)
Internal bus IBUS Internal bus Peripheral bus PBUS Peripheral bus EXBUS External bus

Claims (18)

Comprising a main CPU and an electrically writable and erasable nonvolatile memory module;
The nonvolatile memory module includes a nonvolatile memory and a nonvolatile control unit,
In response to a command issued from the main CPU, the nonvolatile control unit controls writing and erasing of the nonvolatile memory,
The nonvolatile memory includes a program storing nonvolatile memory for storing a program executed by the main CPU, and a data storing nonvolatile memory for storing data of an instruction execution result of the program by the main CPU,
The data size of the program write to the program storage nonvolatile memory by the nonvolatile control unit is set to a size different from the data size of the data write to the data storage nonvolatile memory by the nonvolatile control unit,
The main CPU supplies first size information corresponding to the data size of the program writing to the nonvolatile control unit when making a request for writing the program to the program storing nonvolatile memory to the nonvolatile control unit,
When the main CPU requests the nonvolatile control unit to write data to the data storage nonvolatile memory, the main CPU supplies second size information corresponding to the data size of the data write to the nonvolatile control unit,
The nonvolatile control unit executes a program write to the program storing nonvolatile memory of the nonvolatile memory in response to the first size information supplied from the main CPU, and is supplied from the main CPU. A semiconductor integrated circuit that executes data writing to the data storage nonvolatile memory of the nonvolatile memory in response to the second size information .   The data size of the program writing to the program storing nonvolatile memory by the nonvolatile control unit is larger than the data size of the data writing to the data storing nonvolatile memory by the nonvolatile control unit. Semiconductor integrated circuit.   3. The semiconductor integrated circuit according to claim 1, wherein the data storage nonvolatile memory includes at least one flash memory, and the program storage nonvolatile memory includes at least two flash memories.   4. The semiconductor according to claim 3, wherein said nonvolatile control unit serially transfers write data to said two flash memories of said program storing nonvolatile memory in response to an operation mode supplied from said main CPU. Integrated circuit.   4. The non-volatile control unit is configured to alternately transfer write data to the two flash memories of the program storing non-volatile memory by interleaving in response to another operation mode supplied from the main CPU. A semiconductor integrated circuit according to 1. The nonvolatile control unit includes a sub CPU and a control memory,
The program storing nonvolatile memory stores a writing / erasing control program for controlling writing and erasing of the nonvolatile memory by the sub CPU of the nonvolatile control unit,
At the time of system startup, the program / erase control program stored in the program storage nonvolatile memory is transferred to the control memory of the nonvolatile control unit,
Control of writing and erasing of the non-volatile memory is performed in response to a command issued from the main CPU, and the sub CPU of the non-volatile control unit executes a command of the writing / erasing control program transferred to the control memory. The semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuit is performed by: Comprising a main CPU and an electrically writable and erasable nonvolatile memory module;
The nonvolatile memory module includes a nonvolatile memory and a nonvolatile control unit,
In response to a command issued from the main CPU, the nonvolatile control unit controls writing and erasing of the nonvolatile memory,
The nonvolatile memory includes a program storing nonvolatile memory for storing a program executed by the main CPU, and a data storing nonvolatile memory for storing data of an instruction execution result of the program by the main CPU,
The data size of the program write to the program storage nonvolatile memory by the nonvolatile control unit is set to a size different from the data size of the data write to the data storage nonvolatile memory by the nonvolatile control unit,
The main CPU supplies the nonvolatile control unit with the first size information corresponding to the data size of the program write when requesting the nonvolatile control unit to write the program to the program storage nonvolatile memory.
When the main CPU requests the nonvolatile control unit to write data to the data storage nonvolatile memory, the main CPU supplies second size information corresponding to the data size of data writing to the nonvolatile control unit,
The nonvolatile control unit executes a program write to the program storing nonvolatile memory of the nonvolatile memory in response to the first size information supplied from the main CPU, and is supplied from the main CPU. A single-chip microcomputer for executing data writing in the data storage nonvolatile memory of the nonvolatile memory in response to the second size information .   The data size of the program writing to the program storing nonvolatile memory by the nonvolatile control unit is set larger than the data size of the data writing to the data storing nonvolatile memory by the nonvolatile control unit. Single chip microcomputer.   9. The single-chip microcomputer according to claim 7, wherein the data storage nonvolatile memory includes at least one flash memory, and the program storage nonvolatile memory includes at least two flash memories.   10. The information according to claim 9, wherein the nonvolatile control unit is configured to serially transfer write data to the two flash memories of the program storing nonvolatile memory in response to an operation mode supplied from the main CPU. Single chip microcomputer.   10. The nonvolatile control unit is configured to alternately transfer write data to the two flash memories of the program storing nonvolatile memory by interleaving in response to another operation mode supplied from the main CPU. A single-chip microcomputer as described in 1. The nonvolatile control unit includes a sub CPU and a control memory,
The program storing nonvolatile memory stores a writing / erasing control program for controlling writing and erasing of the nonvolatile memory by the sub CPU of the nonvolatile control unit,
At the time of system startup, the program / erase control program stored in the program storage nonvolatile memory is transferred to the control memory of the nonvolatile control unit,
Control of writing and erasing of the non-volatile memory is performed in response to a command issued from the main CPU, and the sub CPU of the non-volatile control unit executes a command of the writing / erasing control program transferred to the control memory. The single-chip microcomputer according to any one of claims 7 to 11, wherein the single-chip microcomputer is performed by the following. The write command for the nonvolatile memory from the main CPU is:
Size information corresponding to the data size of the data or program write,
3. The semiconductor integrated circuit according to claim 2, further comprising data information to be written. The write command for the nonvolatile memory from the main CPU is:
Size information corresponding to the data size of the data or program write,
9. The single chip microcomputer according to claim 8, wherein the single chip microcomputer includes data information to be written. A first bus to which the main CPU is connected;
A second bus to which the nonvolatile control unit is connected,
The program storing nonvolatile memory performs a read operation from the main CPU via the first bus,
The semiconductor integrated circuit according to claim 1, wherein the data storage nonvolatile memory performs a read operation from the main CPU via the second bus. A first bus to which the main CPU is connected;
A second bus to which the nonvolatile control unit is connected,
The program storing nonvolatile memory performs a read operation from the main CPU via the first bus,
The single-chip microcomputer according to claim 7 or 14, wherein the data storage nonvolatile memory performs a read operation from the main CPU via the second bus. The nonvolatile control unit is connected to the second bus,
16. The semiconductor integrated circuit according to claim 15, wherein the write command from the main CPU is supplied via the second bus. The nonvolatile control unit is connected to the second bus,
17. The single-chip microcomputer according to claim 16, wherein the write command from the main CPU is supplied via the second bus.

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