JP4967580B2 - Semiconductor light emitting device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a semiconductor light emitting device having a light emitting functional layer having a light emitting function and a method for manufacturing the same.

  Silicon-based substrates (such as silicon (Si) substrates and silicon carbide substrates (SiC) substrates) are inexpensive and have good heat dissipation. Therefore, when forming a semiconductor light emitting element having a light emitting functional layer, it is desirable to epitaxially grow the light emitting functional layer on the upper surface of the silicon-based substrate. At this time, in order to eliminate the lattice constant difference between the compound semiconductor constituting the light emitting functional layer and the silicon-based substrate and to grow the light emitting functional layer satisfactorily, a buffer is provided between the light emitting functional layer and the silicon-based substrate. It is necessary to provide a layer. For example, a structure in which a buffer layer formed by growing an AlN (aluminum nitride) or AlGaN / AlN layer at about 750 ° C. between a silicon substrate and a GaN (gallium nitride) layer is known.

However, when an AlN layer is formed on a silicon-based substrate, the AlN layer becomes a potential barrier between the silicon-based substrate and the compound semiconductor layer having a light emitting function, and the driving voltage (forward voltage) of the semiconductor light emitting element increases. There is a problem. Therefore, as in Patent Document 1, by forming a metal compound region between the silicon substrate and the AlN layer, the potential barrier between the silicon substrate and the AlN layer can be easily overcome, and silicon A structure that can improve the electrical connection between the system substrate and the AlN layer and lowers the driving voltage of the semiconductor light emitting element is disclosed.
JP 2002-208729 A

  According to the technique described in Patent Document 1, the driving voltage of the semiconductor light emitting element can be further reduced as the metal compound region is formed thicker. However, if the metal compound region is to be formed thick, it is necessary to increase the thickness of the reaction source supply layer that is the supply source of the constituent material. If the reaction source supply layer is formed to be thick, the reaction source supply layer and the layer below it are present. There is a problem that cracks occur in the reaction source supply layer due to the stress caused by the difference in linear expansion coefficient with the silicon-based substrate.

  The present invention has been made in view of the above-described problems, and provides a semiconductor light-emitting element having a low driving voltage and a method for manufacturing the same while suppressing the generation of cracks in the reaction source supply layer. Objective.

The present invention has been made to solve the above-described problem, and is a semiconductor light emitting device having a first region and a second region, a silicon-based substrate containing silicon as a constituent element, and the silicon-based substrate. A metal compound region formed of a metal compound including gallium, indium, and silicon as constituent elements formed on the substrate, an aluminum nitride layer formed of aluminum nitride formed on the metal compound region, and the aluminum nitride layer A reaction source supply layer formed of a nitride compound semiconductor including gallium and indium as constituent elements, and a light emitting functional layer formed on the reaction source supply layer, including the nitride compound semiconductor, and having a light emission function If has, above the silicon substrate in the second region, the main surface of the metal compound region is formed, irregularities are formed, the second The metal compound region in the region is formed thicker than the metal compound region in the first region, and the aluminum nitride layer in the second region is formed thinner than the aluminum nitride layer in the first region. It is a semiconductor light emitting element characterized by being manufactured.

In the semiconductor light emitting device of the present invention , a metal film is formed on the second region of the main surface on the main surface of the silicon-based substrate in the second region where the metal compound region is formed. Thus, silicide is formed by alloying the metal and silicon in the silicon-based substrate .

  The semiconductor light emitting device of the present invention is formed on the first light emitting functional layer in the first region and on the light emitting functional layer in the second region via an insulating film. And a second electrode electrically connected to the first electrode.

  In the semiconductor light emitting device of the present invention, the light emitting functional layer includes an active layer, and the light emitting functional layer in the second region is deeper than a surface of the light emitting functional layer than a bottom surface of the active layer. A groove that is dug down is formed.

  Further, the semiconductor light emitting device of the present invention includes a first electrode formed on the light emitting functional layer in the first region, a side surface of the groove formed in the light emitting functional layer in the second region, and It further has a second electrode formed on the bottom surface through an insulating film and electrically connected to the first electrode.

  The semiconductor light emitting device of the present invention further includes a Schottky metal layer in Schottky contact with the portion of the light emitting functional layer exposed by the hole penetrating the insulating film and electrically connected to the second electrode. It is characterized by having.

The present invention is also a method for manufacturing a semiconductor light emitting device having a first region and a second region, wherein an aluminum nitride layer made of aluminum nitride is formed on a silicon-based substrate containing silicon as a constituent element. Forming a reaction source supply layer made of a nitride compound semiconductor containing gallium and indium as constituent elements on the aluminum nitride layer, and forming gallium and silicon between the silicon substrate and the aluminum nitride layer. A step of forming a metal compound region made of a metal compound containing indium and silicon as constituent elements, and a step of forming irregularities on a main surface of the silicon-based substrate in the second region where the metal compound region is formed. When, in the reaction source supplying layer comprises a nitride compound semiconductor, comprising the steps of forming a light-emitting function layer having a light emitting function, wherein the second The metal compound region in the region is formed thicker than the metal compound region in the first region, and the aluminum nitride layer in the second region is formed thinner than the aluminum nitride layer in the first region. A method for manufacturing a semiconductor light-emitting device.

In the method for manufacturing a semiconductor light emitting device of the present invention , a metal film is formed on the main surface of the silicon-based substrate in the second region where the metal compound region is formed, and on the second region of the main surface. And a step of forming a silicide obtained by alloying the formed metal and silicon in the silicon-based substrate .

  In the method for manufacturing a semiconductor light emitting device according to the present invention, an insulating film is formed on the light emitting functional layer in the second region, and a first electrode is formed on the light emitting functional layer in the first region. And forming a second electrode electrically connected to the first electrode over the insulating film in the second region.

  In the method for manufacturing a semiconductor light emitting device according to the present invention, the light emitting functional layer includes an active layer, and the light emitting functional layer in the second region is dug from the surface to form a groove deeper than the bottom surface of the active layer. The method further includes the step of forming.

  The method for manufacturing a semiconductor light emitting device according to the present invention includes a step of forming an insulating film on a side surface and a bottom surface of the groove formed in the light emitting functional layer in the second region, and the light emission in the first region. Forming a first electrode on the functional layer, and forming a second electrode electrically connected to the first electrode on the insulating film in the second region. Features.

  The method of manufacturing a semiconductor light emitting device according to the present invention includes a step of forming a hole penetrating the insulating film, a Schottky contact with a portion of the light emitting functional layer exposed by the hole, and an electrical connection with the second electrode. And a step of forming a Schottky metal layer connected to the portion of the light emitting functional layer exposed by the hole.

  According to the present invention, the semiconductor light emitting device has a first region and a second region, and the first region has a thicker AlN layer than the second region, and supplies a reaction source more than the second region. Since the layer is formed to be thin, it is possible to suppress the generation of cracks in the reaction source supply layer and to suppress the deterioration of the crystallinity of the light emitting functional layer formed on the reaction source supply layer. it can. In the second region, the insulating AlN layer is thinner than the first region, and the metal compound region contributing to lower resistance between the silicon-based substrate and the reaction source supply layer is smaller than the first region. Therefore, the semiconductor light emitting device can realize a low driving voltage.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
First, a first embodiment of the present invention will be described. FIG. 1 shows a cross-sectional structure of the semiconductor light emitting device according to the present embodiment. The silicon-based substrate 1 having the main surfaces 1a and 1b facing each other is a substrate containing silicon as a constituent element, and is composed of a silicon (Si) substrate, a silicon gallium (SiGa) substrate, a silicon carbide (SiC) substrate, or the like. It has conductivity. The silicon substrate 1 has a function as a base for epitaxially growing the light emitting functional layer 5 on the silicon substrate 1, a function as a current path of the semiconductor light emitting element, and a function of holding the light emitting functional layer 5. Have.

In order to reduce the resistivity of the silicon-based substrate 1 at low cost, for example, it contains a group 3 element such as boron (B), has a P-type impurity concentration of about 5 × 10 ^{18 to} 5 × 10 ¹⁹ cm ^−3, and has a resistivity of A substrate of 0.0001 to 0.01 [Ω · cm] can be used as the silicon substrate 1. Of course, an N-type silicon substrate, P-type or N-type silicon carbide substrate or silicon gallium substrate containing a Group 5 element such as phosphorus (P) instead of a Group 3 element such as boron (B) as a conductivity determining impurity. May be used. The thickness of the silicon-based substrate 1 is, for example, 200 to 500 μm.

  The structure of the main surface 1a of the silicon-based substrate 1 is different between a region A corresponding to the first region of the present invention and a region B corresponding to the second region of the present invention. While the main surface 1a in the region A is flattened, the main surface 1a in the region B is roughened, and the unevenness 10 is formed. Since the lattice constant of silicon is about 5 angstroms, the difference in height of the irregularities of the main surface 1a in the region A is desirably 10 angstroms (2 atoms) or less. Further, in the region B, the lateral width between the vertices of the concave portion 10a and the convex portion 10b constituting the unevenness 10 is, for example, 10 nm to 100 μm, and the height difference between the vertexes of the concave portion 10a and the convex portion 10b is, for example, 10 nm 10 μm.

  The metal compound region 2 is formed in a region including the main surface 1 a of the silicon substrate 1. The metal compound region 2 includes gallium (Ga) and indium (In) diffused from a reaction source supply layer 4 described later, and aluminum (Al) and nitrogen (N) constituting an AlN layer 3 (aluminum nitride layer) described later. And silicon (Si) constituting the silicon-based substrate 1 are formed by reaction, and contain Ga, In, and Si at least as constituent elements. The portions of the metal compound region 2 corresponding to the recesses 10a and the protrusions 10b formed on the main surface 1a of the silicon substrate 1 take over the main surface 1a of the silicon substrate 1, and the upper and lower surfaces of the metal compound region 2 are The region B has irregularities. Furthermore, the metal compound region 2 formed by the manufacturing method described later is formed thicker than the region A in the region B (in other words, thinner than the region B in the region A) (d1> d2 in FIG. 2). The thicknesses of the metal compound region 2 and the AlN layer 3 in the region B refer to the thicknesses (d1 to d4) in the recesses as shown in FIG.

  An AlN layer 3 made of aluminum nitride (AlN) is formed on the metal compound region 2. The AlN layer 3 functions as a buffer layer (buffer layer) for forming the reaction source supply layer 4 and the light emitting functional layer 5 having a crystal lattice different from that of the silicon substrate 1 on the silicon substrate 1. However, in the region B, since the crystallinity of the AlN layer 3 is deteriorated as described later, this function is worse than that in the region A. Although it is difficult to directly form a nitride compound semiconductor layer having a plane orientation different from that of the silicon substrate 1 on the silicon substrate 1, the AlN layer 3 whose lattice constant is close to the lattice constant of the silicon substrate 1 Since the AlN layer 3 takes over the plane orientation of the silicon-based substrate 1, a nitride-based compound semiconductor layer having relatively good crystallinity can be formed on the silicon-based substrate 1. However, in the region B, the AlN layer 3 takes over the concave portions 10a and the convex portions 10b formed on the main surface 1a of the silicon-based substrate 1, and concave portions and convex portions are formed on the upper surface of the corresponding AlN layer 3, The crystallinity of the nitride-based compound semiconductor layer is deteriorated more than that in the region A.

  An AlN layer 3 formed by a manufacturing method described later is thinner in region B than region A (in other words, thicker than region B in region A) (d3 <d4 in FIG. 2). In the region B, the AlN layer 3 is thinner at the concave portion than at the convex portion, but the thickness of the AlN layer 3 in the region B is the thickness of the concave portion. Thereby, in the region A, the AlN layer 3 has a function of delaying the diffusion start timing of Ga and In diffused from the reaction source supply layer 4 to the silicon-based substrate 1 compared to the region B. The delay of the diffusion start time means that, in the initial stage of forming the reaction source supply layer 4, Ga and In supplied from the reaction source supply layer 4 diffuse into the silicon-based substrate 1 and the AlN layer 3 and the silicon-based substrate 1 That the formation of the metal compound region 3 between the two is suppressed.

A reaction source supply layer 4 made of a nitride compound semiconductor containing Ga and In as constituent elements is formed on the AlN layer 3. More specifically, reactive sources supplying layer 4 is composed of _{In X Al 1-X-Y} Ga Y N (0 <X ≦ 1,0 <Y ≦ 1,0 <X + Y ≦ 1), the present embodiment Then, the reaction source supply layer 4 is composed of N-type In _0.5 Ga _0.5 N. The thickness of the reaction source supply layer 4 is 30 nm in the region A, for example. The reaction source supply layer 4 is a semiconductor layer having relatively good crystallinity in the region A, but is a semiconductor layer having crystallinity deteriorated more than that in the region A in the region B. In the region B, the top surface of the reaction source supply layer 4 is uneven, but the difference between the concave and convex portions is smaller than the difference between the concave and convex portions of the corresponding AlN layer 3. A reaction source supply layer 4 may be formed.

On the reaction source supply layer 4, a light emitting functional layer 5 containing a nitride compound semiconductor and having a light emitting function is formed. The light emitting functional layer 5 has a structure in which a first cladding layer 6 made of N-type GaN, an active layer 7 made of P-type InGaN, and a second cladding layer 8 made of P-type GaN are sequentially stacked. . The thickness of the first cladding layer 6 is, for example, 2 μm in the region A, and the impurity concentration is, for example, 3 × 10 ¹⁸ cm ⁻³ , which is sufficiently lower than the impurity concentration of the silicon-based substrate 1. The thickness of the active layer 7 is, for example, 30 nm in the region A, and the impurity concentration is, for example, 3 × 10 ¹⁷ cm ⁻³ . The thickness of the second cladding layer 8 is, for example, 500 nm, and the impurity concentration is, for example, 3 × 10 ¹⁸ cm ⁻³ . The active layer 7 may be N-type InGaN. Further, in the region B of FIG. 1, the upper surface of the first cladding layer 6 takes over the concave portions 10a and the convex portions 10b formed in the main surface 1a of the silicon-based substrate 1, and the first cladding layer 6 has a corresponding shape corresponding thereto. Although unevenness is formed on the upper surface, the upper surface in the region B of the first cladding layer 6 may be substantially flattened.

A surface electrode 9 electrically connected to the light emitting functional layer 5 is formed on the light emitting functional layer 5. In order to enable extraction of light emitted from the light emitting functional layer 5, the surface electrode 9 is formed of a material having optical transparency. Further, low resistance contact (ohmic contact) is obtained at the interface between the light emitting functional layer 5 and the surface electrode 9. The surface electrode 9 is made of ITO (Indium Tin Oxide), that is, indium oxide (In ₂ O ₃ ) mixed with a small amount (several percent) of tin oxide (SnO ₂ ), and its thickness is, for example, 100 nm. .

  When the second cladding layer 8 is a P-type semiconductor, one type of metal selected from nickel (Ni), platinum (Pt), palladium (Pd), rhodium (Rh), gold (Au), or any of these The surface electrode 9 may be composed of an alloy containing one of them. When the second cladding layer 8 is an N-type semiconductor, it is made of one kind of metal selected from aluminum (Al), chromium (Cr), titanium (Ti), etc., or an alloy containing any one of these metals. The surface electrode 9 may be configured.

  A pad electrode 11 for external connection of the semiconductor light emitting element is formed at substantially the center (region A) of the upper surface of the surface electrode 9. The pad electrode 11 is made of Au or Al. The pad electrode 11 needs to have a thickness that can withstand a bonding process for connecting an external connection wire, and has a thickness of, for example, 100 nm to 100 μm.

  A back electrode 12 is formed on the main surface 1 b of the silicon substrate 1. The back electrode 12 is formed by vacuum-depositing a metal such as Au, Au and Ge, Au and Ge and Ni, Ti and TiN (titanium nitride), or Ti and Al, which is capable of low resistance contact with the silicon-based substrate 1. Is formed. The back electrode 12 is electrically and mechanically connected to the silicon-based substrate 1.

Next, the method for manufacturing the semiconductor light emitting device according to the present embodiment will be described with reference to FIGS. A main surface 1a ′ of the silicon-based substrate 1 is subjected to a roughening process by etching using HF (hydrofluoric acid), HNO ₃ (nitric acid), and H ₂ O (water), and from the center of the semiconductor light emitting device Concavities and convexities 10 are formed in the region B on the side as viewed. Alternatively, an etching mask having opening windows with micrometer order intervals may be formed on the main surface 1a ′ by photolithography, and the main surface 1a ′ may be roughened by etching. For example, by using the silicon-based substrate 1 whose main surface 1a ′ is mirror-finished and protecting the region of the main surface 1a ′ corresponding to the region A, the region A is flattened by performing the above processing. A silicon-based substrate 1 having a roughened B is formed (FIG. 3A).

Subsequently, the silicon-based substrate 1 is put into a reaction chamber of a known OMVPE (Organometallic Vapor Phase Epitaxy), that is, an organic metal vapor phase growth apparatus, and the temperature is raised to 1150 ° C. After performing thermal cleaning at 1150 ° C. for 10 minutes to remove the oxide film on the surface of the silicon-based substrate 1, the temperature is lowered to 1100 ° C. and stabilized. Thereafter, a predetermined amount of TMA (trimethylaluminum), for example, 63 μmol (20 cc) / min, a predetermined amount of silane (SiH ₄ ), for example, 20 nmol (200 cc) / min, and a predetermined amount of ammonia, for example, 0.14 mol (3 liters) / min. The AlN layer 3 is epitaxially grown on the main surface 1a ′ of the silicon-based substrate 1 by flowing for min (FIG. 3B).

  At this time, the AlN layer 3 is formed so that the thickness of the AlN layer 3 in the region A becomes a thickness that delays the diffusion start timing of Ga and In diffused from the reaction source supply layer 4, that is, 2 to 60 nm. Is desirable. In the region B, since the unevenness 10 is formed on the main surface 1a 'of the silicon substrate 1, the crystallinity of the AlN layer 3 is deteriorated compared to the region A, and the AlN layer 3 is formed thin. More specifically, in the region B, the portion formed by taking over the concave portion 10a formed on the main surface 1a of the silicon-based substrate 1 is thin, and the portion formed by taking over the convex portion 10b is formed relatively thick. . Further, when the lateral growth of AlN is suppressed, the AlN layer 3 may be formed only in the vicinity of the apex (corner) of the convex portion 10b.

Subsequently, the supply of TMA gas is stopped, and the temperature of the silicon-based substrate 1 is lowered to 700 ° C. When the temperature of the silicon-based substrate 1 is lowered to 700 ° C., a predetermined amount of trimethylindium gas (TMI gas), for example, 59 μmol / min, a predetermined amount of trimethylgallium gas (TMG gas), for example, 6.2 μmol / min, A predetermined amount (for example, 0.23 mol / min) of ammonia gas and a predetermined amount (for example, 20 nmol / min) of silane gas are supplied, and an N-type In _0.5 Ga _{0. A} reaction source supply layer 4 made of 5N is formed. The reason why the silane gas is supplied is to introduce silicon as an N-type impurity into the reaction source supply layer 4.

  In the region A, the AlN layer 3 is formed to a thickness capable of delaying the diffusion start timing of Ga and In supplied from the reaction source supply layer 4. Therefore, in the initial stage of forming the reaction source supply layer 4, Ga and In supplied from the reaction source supply layer 4 do not diffuse into the silicon-based substrate 1. Therefore, in the region A, the crystallinity of the reaction source supply layer 4 to be formed is unlikely to deteriorate. Further, after the initial stage of forming the reaction source supply layer 4, Ga and In are diffused from the already formed reaction source supply layer 4 into the silicon-based substrate 1. Then, Ga and In diffused from the reaction source supply layer 4 at the interface between the silicon-based substrate 1 and the AlN layer 3 (region including the surface of the silicon-based substrate 1), Al that is an element constituting the AlN layer 3, A metal compound region 2 in which N and Si that is one of the elements constituting the silicon-based substrate 1 are reacted is formed, and the upper surface of the silicon-based substrate 1 becomes the main surface 1a. In this way, the reaction source supply layer 4 is formed, and the metal compound region 2 is formed (FIG. 3C).

  The presence of the metal compound region 2 formed between the silicon substrate 1 and the AlN layer 3 can easily overcome the potential barrier between the silicon substrate 1 and the AlN layer 3. And the electrical connection between the AlN layer 3 is improved. Further, since the AlN layer 3 functioning as a buffer layer is formed between the silicon-based substrate 1 and the reaction source supply layer 4, the reaction source supply layer 4 with good crystallinity and the silicon substrate 1 are formed. The light emitting functional layer 5 can be formed.

  On the other hand, since the AlN layer 3 in the region B is thinner than the AlN layer 3 in the region A, the diffusion start timing of Ga and In supplied from the reaction source supply layer 4 is earlier in the region B than in the region A. In the initial stage of forming the reaction source supply layer 4, Ga and In supplied from the reaction source supply layer 4 are not diffused in the region A but are diffused in the region B. Further, in the region B, the AlN layer 3 is thinner than the region A.

  For these reasons, in the region B, Ga and In supplied from the reaction source supply layer 4 are more easily diffused into the silicon-based substrate 1 than in the region A, and further react for a longer time. Accordingly, the metal compound region 2 in the region B is formed thicker than the metal compound region 2 in the region A. The metal compound region 2 is also formed in the region A slightly later than the metal compound region 2 in the region B. Thereby, the crystallinity of the reaction source supply layer 4 in the region A can be made relatively good.

  Following the formation of the reaction source supply layer 4 and the metal compound region 2, the light emitting functional layer 5 is formed on the reaction source supply layer 4. First, the temperature of the silicon substrate 1 is raised to 1040 ° C. When the temperature of the silicon-based substrate 1 rises to 1040 ° C., a predetermined amount of trimethylgallium gas (TMG gas), for example, 4.3 μmol / min, a predetermined amount of ammonia gas, for example, 53.6 mmol / min, and silane gas are placed in the reaction chamber. First, for example, 1.5 nmol / min is supplied, and a first cladding layer 6 made of N-type GaN and having a thickness of about 2 μm is formed on the reaction source supply layer 4 in both the region A and the region B.

  As described above, since the crystallinity of the reaction source supply layer 4 in the region A is good and the crystallinity of the reaction source supply layer 4 in the region B is deteriorated, the crystallinity of the first cladding layer 6 in the region A is deteriorated. Is good, but the crystallinity of the first cladding layer 6 in the region B is deteriorated. If the crystallinity of the first cladding layer 6 in the region B is deteriorated, the deterioration may be propagated to the first cladding layer 6 in the region A, which may be affected. Therefore, the crystallinity deterioration of the entire first cladding layer 6 may be suppressed by sandwiching a GaN layer as a known low-temperature buffer layer between the reaction source supply layer 4 and the first cladding layer 6.

Subsequently, the temperature of the silicon substrate 1 is lowered to 800.degree. When the temperature of the silicon-based substrate 1 is lowered to 800 ° C., a predetermined amount of trimethylgallium gas (TMG gas), for example, 1.1 μmol / min, an ammonia gas, for example, 67 mmol / min, trimethylindium gas (TMI) is added to the reaction chamber. Gas) is supplied in a predetermined amount, for example, 4.5 μmol / min, and biscyclopentagenyl magnesium gas (Cp ₂ Mg gas) is supplied in a predetermined amount, for example, 12 nmol / min, and the thickness in the region A is formed on the first cladding layer 6. An active layer 7 made of P-type InGaN having a thickness of about 30 nm is formed. The reason why the biscyclopentagenyl magnesium gas is supplied is to introduce Mg as a P-type impurity into the active layer 7.

Subsequently, the temperature of the silicon-based substrate 1 is increased to 1040 ° C. When the temperature of the silicon substrate 1 rises to 1040 ° C., a predetermined amount of trimethyl gallium gas (TMG gas), for example, 4.3 μmol / min, ammonia gas, a predetermined amount, for example, 53.6 μmol / min, biscyclopenta A predetermined amount of, for example, 0.12 μmol / min of jenyl magnesium gas (Cp ₂ Mg gas) is supplied to form a second cladding layer 8 made of P-type GaN having a thickness of about 500 nm on the active layer 7 ( FIG. 4 (a)).

  Subsequently, ITO that is in low resistance contact with the second cladding layer 8 is deposited on almost the entire surface of the second cladding layer 8 by a vacuum evaporation method, a sputtering method, a CVD (Chemical Vapor Deposition) method, or the like. Form. Further, Au is deposited on the surface electrode 9 to form the pad electrode 11. Further, Au is deposited on the main surface 1b of the silicon-based substrate 1 by a vacuum deposition method or the like to form the back electrode 12. Subsequently, annealing is performed to improve the adhesion between each electrode and the semiconductor in contact therewith, and improve the transparency of the surface electrode 9 (FIG. 4B). Through the above steps, the structure shown in FIG. 1 is completed.

  In the region A, the light emitting functional layer 5 formed as described above is formed on the reaction source supply layer 4 having good crystallinity (growth using the reaction source supply layer 4 as a nucleus). For this reason, the light emitting functional layer 5 having good crystallinity and high emission luminance can be formed. On the other hand, in the region B, since the light emitting functional layer 5 is formed on the reaction source supply layer 4 with deteriorated crystallinity, the crystallinity is deteriorated and light cannot be emitted satisfactorily. Therefore, in order to realize higher light extraction efficiency, it is desirable that the pad electrode 11 is formed in the region A as far as possible from the region B.

  In the manufacturing method described above, when the AlN layer 3 and the reaction source supply layer 4 are formed, crystals grow not only in the vertical direction (thickness direction) but also in the horizontal direction (width direction) with respect to the silicon-based substrate 1. In the present embodiment, the AlN layer 3 in the region B has a lower crystallinity than the region A, and the thickness is not uniform, and it is desired to be thinned by the recess 10a. If it increases, the AlN layer 3 in the region B becomes a thick film having relatively good crystallinity, and the effect of the present invention cannot be obtained. Therefore, when the AlN layer 3 is formed, by adjusting the manufacturing conditions and suppressing the lateral growth, the AlN layer 3 in the region B has a lower crystallinity than the region A so that the thickness is reduced. Can be formed.

  In particular, in the concave portion 10a of the concave and convex portion 10, since the reaction gas hardly enters the concave portion, the crystal is difficult to grow and the AlN layer 3 becomes thin. On the contrary, in the vicinity of the convex portion 10b, the reactive gas hits the convex portion 10b, and the AlN layer 3 having deteriorated crystallinity (abnormally grown) is likely to grow. Therefore, in the region B, Ga and In are easily diffused from the reaction source supply layer 4 to the silicon-based substrate 1, and the metal compound region 2 is formed thicker in the convex portion 10b than in the concave portion 10a.

  In this embodiment, the unevenness 10 is formed in the region B of the main surface 1a of the silicon-based substrate 1, but instead of this, the region B of the main surface 1a of the silicon-based substrate 1 is made of amorphous silicon, polysilicon, or the like. The polycrystalline film may be formed to a thickness of about 1 nm to 1 μm by sputtering or CVD. Alternatively, a silicide film may be formed in the region B of the main surface 1a of the silicon-based substrate 1 by forming a metal film on the region B of the main surface 1a of the silicon-based substrate 1 and alloying the metal and silicon. Alternatively, the silicide layer may be formed in the region B of the main surface 1 a of the silicon substrate 1 by directly attaching silicide to the region B of the main surface 1 a of the silicon substrate 1.

  FIG. 5 shows a cross-sectional structure of a semiconductor light emitting device (modified example of this embodiment) in which a silicide layer is formed in the region B of the main surface 1a of the silicon-based substrate 1 instead of the unevenness. The structure shown in FIG. 5 is formed as follows. After the silicide layer 21 is formed on the main surface 1a of the silicon substrate 1, the AlN layer 3 is formed on almost the entire surface of the main surface 1a '. On the silicide layer 21 provided in the region B, AlN having deteriorated crystallinity is polycrystallized and sparsely formed. Therefore, the AlN layer 3 in the region B can be partially (sparsely) thin and thicker than that (FIG. 6A). Incidentally, in the region A, the upper surface of the AlN layer 3 is flattened compared to the region B, and the AlN layer 3 in the region A has better crystallinity than the region B.

  Subsequently, when the reaction source supply layer 4 is formed on the AlN layer 3, as described above, Ga and In are diffused from the reaction source supply layer 4 to the silicon substrate 1, and the interface between the silicon substrate 1 and the AlN layer 3 is diffused. Thus, the metal compound region 2 is formed. In the region B, since the silicide layer 21 is formed on the upper surface of the silicon-based substrate 1, the metal compound region 2 is formed at the interface between the silicide layer 21 and the AlN layer 3. At this time, in the portion where the AlN layer 3 in the region B is thin, the metal compound region 2 is formed thicker than the metal compound region 2 in the region A, and the lower surface of the metal compound region 2 has irregularities (FIG. 6 ( b)). Thereafter, the light emitting functional layer 5, the front electrode 9, and the back electrode 12 are formed through the same process as described with reference to FIG.

  As described above, according to the first embodiment of the present invention, the semiconductor light emitting device has the region A (first region) and the region B (second region). Since the AlN layer 3 is thicker and the reaction source supply layer 4 is thinner than the region B, the generation of cracks in the reaction source supply layer 4 in the region A is suppressed, and the reaction source supply layer 4 It can suppress that the crystallinity of the light emission functional layer 5 formed on it deteriorates. In other words, relatively good light emission can be obtained in the region A. In the region B, the insulating AlN layer 3 is thinner than the region A, and the metal compound region 2 contributing to lower resistance between the silicon-based substrate 1 and the reaction source supply layer 4 is thicker than the region A. Thus, the semiconductor light emitting element can realize a low driving voltage.

  FIG. 7 schematically shows a path of current flowing through the semiconductor light emitting device according to the present embodiment. The current flowing from the surface electrode 9 mainly passes through the second cladding layer 8, the active layer 7, and the first cladding layer 6 in the regions A and B. Since the resistance value between the silicon-based substrate 1 and the reaction source supply layer 4 is lower in the region B than in the region A, most of the current reaching the first cladding layer 6 in the region A is the first in the region B. One of the cladding layer 6, the reaction source supply layer 4, the AlN layer 3, and the metal compound region 2 gathers in the region B and flows to the back electrode 12 via the silicon-based substrate 1 in the region B. A low drive voltage can be realized by the current flowing through such a path.

  Further, by forming the unevenness 10 or the silicide layer 21 or the like on the main surface 1a of the silicon-based substrate 1 in the region B, the AlN layer 3 can be formed thin and the metal compound region 2 can be formed thick. The effects of this embodiment can be obtained. Furthermore, by forming the projections and depressions 10, the contact area between the silicon substrate 1 and the metal compound region 2 can be increased, and the driving voltage of the semiconductor light emitting element can be further reduced. Further, as shown in the modification of the first embodiment described above, by forming the silicide layer 21 having good adhesion to both the silicon-based substrate 1 and the metal compound region 2, the silicon-based substrate 1 and the metal compound are formed. The resistance value between the region 2 can be further reduced.

(Second Embodiment)
Next, a second embodiment of the present invention will be described. FIG. 8 shows a cross-sectional structure of the semiconductor light emitting device according to the present embodiment. In the present embodiment, the insulating film 13 is formed on the second cladding layer 8 in the region B. The surface electrode 9 includes a first electrode 14 formed on the second cladding layer 8 in the region A, and a second electrode 15 formed on the insulating film 13 and electrically connected to the first electrode 14. It consists of and. A pad electrode 11 is formed on the second electrode 15.

  Hereinafter, the method for fabricating the semiconductor light emitting device according to the present embodiment will be described with reference to FIG. Since the steps until the second cladding layer 8 is formed are the same as those in the first embodiment except that the positions of the region A and the region B are different, the description thereof is omitted. After forming the second cladding layer 8, an insulating film 13 is formed on the second cladding layer 8 in the region B (FIG. 9A). Subsequently, a surface electrode 9 is formed on the exposed second cladding layer 8 and the insulating film 13, a pad electrode 11 is formed on the surface electrode 9, and a back electrode 12 is formed on the main surface 1b of the silicon-based substrate 1 in this order. Processing is performed (FIG. 9B). The structure shown in FIG. 8 is completed through the above steps.

  FIG. 10 schematically shows a path of current flowing through the semiconductor light emitting device according to the present embodiment. The current that flows from the pad electrode 11 to the second electrode 15 tends to flow to the light emitting functional layer 5 immediately below the pad electrode 11 (region B). However, since the insulating film 13 is provided between the surface electrode 9 and the second cladding layer 8, the current flows toward the first electrode 14, that is, toward the side of the semiconductor light emitting element. The current mainly passes through the second cladding layer 8, the active layer 7, and the first cladding layer 6 in the region A. Since the resistance value between the silicon-based substrate 1 and the reaction source supply layer 4 is lower in the region B than in the region A, most of the current reaching the first cladding layer 6 in the region A is the first cladding layer 6. In any one of the reaction source supply layer 4, the AlN layer 3, and the metal compound region 2, they gather in the region B and flow to the back electrode 12 through the silicon-based substrate 1 in the region B. A low drive voltage can be realized by the current flowing through such a path.

  In addition, since the surface electrode 9 has the above-described structure, a current flows from the surface of the second cladding layer 8 in the region A, and more current flows in the active layer 7 in the region A than in the active layer 7 in the region B. Can flow. Therefore, it is possible to suppress current from flowing through the active layer 7 in the region B where the crystallinity is deteriorated, and to obtain good light emission. Furthermore, by providing the pad electrode 11 above the region B where it is difficult to obtain good light emission, the light emitted from the active layer 7 in the region A is prevented from being blocked by the pad electrode 11 and the light extraction efficiency is improved. be able to. In FIG. 8, the insulating film 13 is formed in the region B. However, the insulating film 13 may be formed only directly under the region B where the pad electrode 11 is provided, or a part of the insulating film 13 may be formed. The area B may protrude from the area B. Further, the insulating film 13 may not be formed on the second cladding layer 8, and may be formed between the active layer 7 and the surface electrode 9.

(Third embodiment)
Next, a third embodiment of the present invention will be described. FIG. 11 shows a cross-sectional structure of the semiconductor light emitting device according to the present embodiment. In the present embodiment, a groove 16 dug from the surface (upper surface) of the light emitting functional layer 5 is formed in the light emitting functional layer 5 in the region B. The bottom surface 16a of the groove 16 reaches the first cladding layer 6, and at least a part of the active layer 7 in the region B (the entire active layer 7 in the region B in FIG. 11) is removed. A surface electrode 9 and a pad electrode 11 are formed on the second cladding layer 8 in the region A.

  Hereinafter, the method for fabricating the semiconductor light emitting device according to the present embodiment will be described with reference to FIG. The steps until the second cladding layer 8 is formed are the same as those in the first embodiment except for the position where the region A and the region B are formed, and thus the description thereof is omitted. After forming the second cladding layer 8, in the region B, etching is performed from the upper surface of the second cladding layer 8 to form a groove 16 deeper than the bottom surface of the active layer 7 and shallower than the bottom surface of the first cladding layer 6. (FIG. 12A). Subsequently, after forming the surface electrode 9, the pad electrode 11, and the back electrode 12 on the main surface 1b of the silicon-based substrate 1 in this order on the second cladding layer 8 in the region A, annealing is performed (FIG. 12B). )). Through the above steps, the structure shown in FIG. 11 is completed. Note that the order of the steps is reversed and the second cladding layer 8 is formed, and then the surface electrode 9 is formed on almost the entire upper surface of the second cladding layer 8, the pad electrode 11 is formed on the surface electrode 9, and the silicon-based substrate. The back electrode 12 may be formed on the main surface 1b of 1b, and the groove 16 may be formed subsequently.

  As shown by the current path I5 in FIG. 13, the current flowing from the surface electrode 9 into the second cladding layer 8 in the region A passes through the second cladding layer 8, the active layer 7, and the first cladding layer 6 in the region A. . Since the resistance value between the silicon-based substrate 1 and the reaction source supply layer 4 is lower in the region B than in the region A, most of the current reaching the first cladding layer 6 in the region A is the first cladding layer 6. In any one of the reaction source supply layer 4, the AlN layer 3, and the metal compound region 2, they gather in the region B and flow to the back electrode 12 through the silicon-based substrate 1 in the region B. A low drive voltage can be realized by the current flowing through such a path.

  Even when unevenness or the like is provided in the region B of the main surface 1a of the silicon substrate 1, even if the low-temperature buffer layer described above is formed or the first cladding layer 6 is formed thick by causing lateral growth. In addition, crystal defects are generated in the active layer 7 in the region B. Therefore, by forming the groove 16 and removing the active layer 7 in the region B in which the crystallinity is deteriorated, a current can be supplied only to the active layer 7 having a good crystallinity, and a good light emission can be obtained. .

  The position of the bottom surface 16 a of the groove 16 may not be shallower than the position of the bottom surface of the first cladding layer 6. As long as the region A and the region B are electrically connected even in the layer above the AlN layer 3, the bottom surface 16 a of the groove 16 only needs to be shallower than the bottom surface of the reaction source supply layer 4. . In order to achieve higher light extraction efficiency, it is desirable that the pad electrode 11 is formed in the region A as far as possible from the region B.

(Fourth embodiment)
Next, a fourth embodiment of the present invention will be described. FIG. 14 shows a cross-sectional structure of the semiconductor light emitting device according to the present embodiment. Also in this embodiment, as in the third embodiment, a groove 16 dug down from the surface of the light emitting functional layer 5 is formed in the light emitting functional layer 5 in the region B. Since the crystallinity of the active layer 7 in the region B is relatively deteriorated, the bottom surface 16a of the groove 16 reaches the first cladding layer 6, and at least a part of the active layer 7 in the region B is removed. . An insulating film 17 is formed on the bottom surface 16 a and the side surface 16 b of the groove 16. The surface electrode 9 includes a first electrode 18 formed on the second cladding layer 8 in the region A, and a second electrode 19 formed on the insulating film 17 and electrically connected to the first electrode 18. It consists of and. A pad electrode 11 is formed on the second electrode 19. The pad electrode 11 is desirably formed so as to fill the groove 16.

  Hereinafter, the method for fabricating the semiconductor light emitting device according to the present embodiment will be described with reference to FIG. Since the steps until the second cladding layer 8 is formed are the same as those in the first embodiment, description thereof is omitted. After forming the second cladding layer 8, in the region B, etching is performed from the upper surface of the second cladding layer 8 to form a groove 16 deeper than the bottom surface of the active layer 7 and shallower than the bottom surface of the first cladding layer 6. . Subsequently, an insulating film 17 is formed on the bottom surface 16a and the side surface 16b of the groove (FIG. 15A). Subsequently, the surface electrode 9 was formed on the exposed portion of the upper surface of the second cladding layer 8 and the insulating film 17, the pad electrode 11 was formed on the surface electrode 9, and the back electrode 12 was formed on the main surface 1b of the silicon substrate 1 in this order. Thereafter, annealing is performed (FIG. 15B). Through the above steps, the structure shown in FIG. 14 is completed.

  The current that flows from the pad electrode 11 to the second electrode 19 flows toward the first electrode 18, that is, toward the side of the semiconductor light emitting element. Then, as indicated by current paths I 6 and I 7 in FIG. 16, the current mainly passes through the second cladding layer 8, the active layer 7, and the first cladding layer 6 in the region A. Since the resistance value between the silicon-based substrate 1 and the reaction source supply layer 4 is lower in the region B than in the region A, most of the current reaching the first cladding layer 6 in the region A is the first cladding layer 6. In any one of the reaction source supply layer 4, the AlN layer 3, and the metal compound region 2, they gather in the region B and flow to the back electrode 12 through the silicon-based substrate 1 in the region B. A low drive voltage can be realized by the current flowing through such a path.

  Further, since the active layer 7 in the region B where the crystallinity is deteriorated is removed by forming the groove 16, a main current can be passed through the active layer 7 having a good crystallinity to obtain a good light emission. it can. Furthermore, by providing the pad electrode 11 in the region B where it is difficult to obtain good light emission, the light emitted from the active layer 7 in the region A can be prevented from being blocked by the pad electrode 11 and the light extraction efficiency can be improved. it can.

(Fifth embodiment)
Next, a fifth embodiment of the present invention will be described. FIG. 17 shows a cross-sectional structure of the semiconductor light emitting device according to the present embodiment. Also in the present embodiment, as in the fourth embodiment, the groove 16 is formed in the light emitting functional layer 5 in the region B, and the insulating film 17 is formed on the bottom surface 16 a and the side surface 16 b of the groove 16. The surface electrode 9 is composed of a first electrode 18 and a second electrode 19, and a pad electrode 11 is formed on the second electrode 19. Here, it is desirable that the pad electrode 11 has a groove 16 formed therein. In the region B, a hole penetrating the insulating film 17 (a hole 17a in FIG. 19 described later) is formed. A Schottky metal film 20 that is in Schottky contact with the light emitting functional layer 5 exposed through the hole (forms a Schottky junction with the light emitting functional layer 5) and is electrically connected to the second electrode 19 is formed. . The Schottky metal film 20 is, for example, selected from nickel (Ni), platinum (Pt), palladium (Pd), rhodium (Rh), and gold (Au) when the second cladding layer 8 is an N-type semiconductor. It is made of a kind of metal or an alloy containing any one of them. When the second cladding layer 8 is a P-type semiconductor, it is made of one kind of metal selected from aluminum (Al), chromium (Cr), titanium (Ti), etc., or an alloy containing any one of these metals. It is formed.

  A light-emitting element using a compound-based semiconductor for a light-emitting layer has a relatively small resistance to electrostatic breakdown. Therefore, when a surge voltage higher than 100 V, for example, is applied, breakdown may occur. Therefore, for electrostatic protection of the semiconductor light emitting element, it is conceivable to mount a protective element such as a diode or a capacitor together with the light emitting element in the same package. Accordingly, the semiconductor light emitting device according to the present embodiment is formed so as to function as an antiparallel connection circuit of the light emitting diode 61 as the light emitting device shown in FIG. 18 and the Schottky barrier diode 62 as the protection device.

  The Schottky barrier diode 62 becomes conductive when a reverse overvoltage (for example, surge voltage) of a predetermined value or more is applied to the light emitting diode 61. Thereby, the voltage of the light emitting diode 61 is limited to the forward voltage of the Schottky barrier diode 62, and the light emitting diode 61 is protected from the reverse overvoltage due to static electricity or the like.

  The forward conduction start voltage of the Schottky barrier diode 62 is set to be equal to or lower than the maximum allowable reverse voltage of the light emitting diode 61. That is, the forward conduction start voltage of the Schottky barrier diode 62 is set to a value lower than the voltage at which the light emitting diode 61 may be destroyed. Note that the forward conduction start voltage of the Schottky barrier diode 62 is higher than the reverse voltage applied to the light emitting diode 61 during normal operation (the voltage at which the light emitting diode 61 is turned on), and the light emitting diode 61 is destroyed. It is desirable that the voltage be lower than the potential reverse voltage.

  Next, with reference to FIGS. 19 and 20, the method for fabricating the semiconductor light emitting device according to the present embodiment will be explained. Since the steps until the second cladding layer 8 is formed are the same as those in the first embodiment, description thereof is omitted. After forming the second cladding layer 8, in the region B, etching is performed from the upper surface of the second cladding layer 8 to form a groove 16 deeper than the bottom surface of the active layer 7 and shallower than the bottom surface of the first cladding layer 6. . Subsequently, an insulating film 17 is formed on the bottom surface 16a and the side surface 16b of the groove (FIG. 19A).

  Subsequently, a hole 17a is formed by removing a part of the insulating film 17 on the bottom surface 16a of the groove 16, and the bottom surface 16a is exposed (FIG. 19B). A metal that is in Schottky contact with the second cladding layer 8 is attached to the bottom surface 16a exposed by the formation of the hole 17a to form a Schottky metal film 20 (FIG. 20A). Further, after forming the front electrode 9, the pad electrode 11, and the back electrode 12, an annealing process is performed (FIG. 20B). Through the above steps, the structure shown in FIG. 17 is completed.

  The current that flows from the pad electrode 11 to the second electrode 19 flows toward the first electrode 18, that is, toward the side of the semiconductor light emitting element. Then, as indicated by current paths I8 and I9 in FIG. 21, the current mainly passes through the second cladding layer 8, the active layer 7, and the first cladding layer 6 in the region A. Since the resistance value between the silicon-based substrate 1 and the reaction source supply layer 4 is lower in the region B than in the region A, most of the current reaching the first cladding layer 6 in the region A is the first cladding layer 6. In any one of the reaction source supply layer 4, the AlN layer 3, and the metal compound region 2, they gather in the region B and flow to the back electrode 12 through the silicon-based substrate 1 in the region B. A low drive voltage can be realized by the current flowing through such a path.

  Further, since the active layer 7 in the region B where the crystallinity is deteriorated is removed by forming the groove 16, a current is allowed to flow only in the active layer 7 having a good crystallinity, and a good light emission can be obtained. . Furthermore, by providing the pad electrode 11 in the region B where it is difficult to obtain good light emission, the light emitted from the active layer 7 in the region A can be prevented from being blocked by the pad electrode 11 and the light extraction efficiency can be improved. it can.

  In addition, since the protective element formed in the region B is disposed below the pad electrode 11 in plan view, the protective element can be formed while suppressing the reduction of the light extraction area of the semiconductor light emitting element. Therefore, it is possible to reduce the size of the semiconductor light emitting element with a built-in protection element. Furthermore, since the pad electrode 11 and the second electrode 19 function as an interconnection portion between the light emitting diode 61 and the Schottky barrier diode 62 and also function as an external connection conductor, the configuration of the semiconductor light emitting element is improved. Simplified and can achieve downsizing and cost reduction.

  As described above, the embodiments of the present invention have been described in detail with reference to the drawings. However, the specific configuration is not limited to these embodiments, and includes design changes and the like without departing from the gist of the present invention. . For example, in the second to fifth embodiments, the semiconductor light emitting device in which the main surface 1a of the silicon-based substrate 1 is provided with unevenness has been described. However, as described as a modification of the first embodiment, amorphous silicon or A polycrystalline film such as polysilicon or a silicide film may be formed instead of the unevenness. Further, the present invention may be applied to a semiconductor light emitting element using a bonded metal. In the fifth embodiment, instead of the Schottky metal film 20, a second semiconductor layer having a conductivity type different from that of the first semiconductor layer exposed by the holes 17a is formed on the surface of the first semiconductor layer, The interface between the first semiconductor layer and the second semiconductor layer may be a PN junction.

1 is a schematic cross-sectional view showing a cross-sectional structure of a semiconductor light emitting device according to a first embodiment of the present invention. 1 is a schematic cross-sectional view showing a partial cross-sectional structure of a semiconductor light emitting device according to a first embodiment of the present invention. It is a schematic cross section for demonstrating the manufacturing method of the semiconductor light-emitting device by the 1st Embodiment of this invention. It is a schematic cross section for demonstrating the manufacturing method of the semiconductor light-emitting device by the 1st Embodiment of this invention. It is a schematic cross section which shows the cross-section of the semiconductor light-emitting device by the modification of the 1st Embodiment of this invention. It is a schematic cross section for demonstrating the manufacturing method of the semiconductor light-emitting device by the modification of the 1st Embodiment of this invention. FIG. 3 is a schematic cross-sectional view for explaining a path of a current flowing through the semiconductor light emitting element according to the first embodiment of the present invention. It is a schematic cross section which shows the cross-section of the semiconductor light-emitting device by the 2nd Embodiment of this invention. It is a schematic cross section for demonstrating the manufacturing method of the semiconductor light-emitting device by the 2nd Embodiment of this invention. FIG. 6 is a schematic cross-sectional view for explaining a path of a current flowing through a semiconductor light emitting element according to a second embodiment of the present invention. It is a schematic cross section which shows the cross-section of the semiconductor light-emitting device by the 3rd Embodiment of this invention. It is a schematic cross section for demonstrating the manufacturing method of the semiconductor light-emitting device by the 3rd Embodiment of this invention. FIG. 6 is a schematic cross-sectional view for explaining a path of a current flowing through a semiconductor light emitting element according to a third embodiment of the present invention. It is a schematic cross section which shows the cross-section of the semiconductor light-emitting device by the 4th Embodiment of this invention. It is a schematic cross section for demonstrating the manufacturing method of the semiconductor light-emitting device by the 4th Embodiment of this invention. It is a schematic cross section for demonstrating the path | route of the electric current which flows through the semiconductor light-emitting device by the 4th Embodiment of this invention. It is a schematic cross section which shows the cross-section of the semiconductor light-emitting device by the 5th Embodiment of this invention. It is a circuit diagram which shows the equivalent circuit of the semiconductor light-emitting device by the 5th Embodiment of this invention. It is a schematic cross section for demonstrating the manufacturing method of the semiconductor light-emitting device by the 5th Embodiment of this invention. It is a schematic cross section for demonstrating the manufacturing method of the semiconductor light-emitting device by the 5th Embodiment of this invention. FIG. 10 is a schematic cross-sectional view for explaining a path of a current flowing through a semiconductor light emitting element according to a fifth embodiment of the present invention.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Silicon-type substrate, 2 ... Metal compound area | region, 3 ... AlN layer, 4 ... Reaction source supply layer, 5 ... Light emission functional layer, 6 ... 1st clad layer, 7 ... Active layer, 8 ... Second clad layer, 9 ... Front electrode, 10 ... Unevenness, 11 ... Pad electrode, 12 ... Back electrode, 13, 17 ... Insulating film , 14, 18 ... first electrode, 15, 19 ... second electrode, 20 ... Schottky metal film, 21 ... silicide layer

Claims (12)

A semiconductor light emitting device having a first region and a second region,
A silicon-based substrate containing silicon as a constituent element;
A metal compound region formed on the silicon-based substrate and made of a metal compound containing gallium, indium, and silicon as constituent elements;
An aluminum nitride layer made of aluminum nitride and formed on the metal compound region;
A reaction source supply layer formed on the aluminum nitride layer and made of a nitride compound semiconductor containing gallium and indium as constituent elements;
A light emitting functional layer formed on the reaction source supply layer, including a nitride compound semiconductor, and having a light emitting function;
Have,
Concavities and convexities are formed on the main surface of the silicon-based substrate in the second region where the metal compound region is formed,
The metal compound region in the second region is formed thicker than the metal compound region in the first region, and the aluminum nitride layer in the second region is the aluminum nitride layer in the first region. A semiconductor light-emitting element, characterized in that the semiconductor light-emitting element is formed thinner. A metal film is formed on the main surface of the silicon-based substrate in the second region where the metal compound region is formed to form the metal and the silicon-based substrate in the second region of the main surface. 2. The semiconductor light emitting device according to claim 1, wherein a silicide obtained by alloying silicon is formed. A first electrode formed on the light emitting functional layer in the first region;
A second electrode formed on the light emitting functional layer in the second region via an insulating film and electrically connected to the first electrode;
The device according to claim 1 or claim 2, characterized in that it further comprises a. The light emitting functional layer includes an active layer, and the light emitting functional layer in the second region has a groove that is dug deeper from the surface of the light emitting functional layer than the bottom surface of the active layer. the device according to claim 1 or claim 2, characterized in. A first electrode formed on the light emitting functional layer in the first region;
A second electrode formed on the side and bottom surfaces of the groove formed in the light emitting functional layer in the second region via an insulating film and electrically connected to the first electrode;
The semiconductor light emitting device according to claim 4 , further comprising: 6. The semiconductor device according to claim 5 , further comprising a Schottky metal layer in Schottky contact with the portion of the light emitting functional layer exposed by the hole penetrating the insulating film and electrically connected to the second electrode. The semiconductor light emitting element as described. A method of manufacturing a semiconductor light emitting device having a first region and a second region,
Forming an aluminum nitride layer made of aluminum nitride on a silicon-based substrate containing silicon as a constituent element;
A reaction source supply layer made of a nitride compound semiconductor containing gallium and indium as constituent elements is formed on the aluminum nitride layer, and gallium, indium and silicon are interposed between the silicon substrate and the aluminum nitride layer. Forming a metal compound region composed of a metal compound containing a constituent element as
Forming irregularities on the main surface of the silicon-based substrate in the second region where the metal compound region is formed;
Forming a light emitting functional layer including a nitride compound semiconductor and having a light emitting function on the reaction source supply layer;
The metal compound region in the second region is formed thicker than the metal compound region in the first region, and the aluminum nitride layer in the second region is formed in the first region. The method for manufacturing a semiconductor light emitting element, wherein the semiconductor light emitting element is formed thinner than the aluminum nitride layer. Forming a metal film on the second region of the main surface on the main surface of the silicon-based substrate in the second region where the metal compound region is formed ;
8. The method of manufacturing a semiconductor light emitting device according to claim 7 , further comprising a step of forming a silicide obtained by alloying the formed metal and silicon in the silicon-based substrate . Forming an insulating film on the light emitting functional layer in the second region;
A first electrode is formed on the light emitting functional layer in the first region, and a second electrode electrically connected to the first electrode is formed on the insulating film in the second region. And a process of
The method of manufacturing a semiconductor light emitting device according to claim 7 or claim 8, characterized in that it further comprises a. The light emitting functional layer includes an active layer, and further includes a step of digging the light emitting functional layer in the second region from a surface to form a groove deeper than a bottom surface of the active layer. The manufacturing method of the semiconductor light-emitting device of Claim 7 or Claim 8 . Forming an insulating film on a side surface and a bottom surface of the groove formed in the light emitting functional layer in the second region;
A first electrode is formed on the light emitting functional layer in the first region, and a second electrode electrically connected to the first electrode is formed on the insulating film in the second region. And a process of
The method of manufacturing a semiconductor light emitting element according to claim 10, further comprising: Forming a hole penetrating the insulating film;
Forming a Schottky metal layer in Schottky contact with a portion of the light emitting functional layer exposed by the hole and electrically connected to the second electrode on the portion of the light emitting functional layer exposed by the hole; ,
The method of manufacturing a semiconductor light emitting element according to claim 11 , further comprising:

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