JP4938843B2 - 構成可能なキャッシュを有するグラフィックスシステム - Google Patents
構成可能なキャッシュを有するグラフィックスシステム Download PDFInfo
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- JP4938843B2 JP4938843B2 JP2009507929A JP2009507929A JP4938843B2 JP 4938843 B2 JP4938843 B2 JP 4938843B2 JP 2009507929 A JP2009507929 A JP 2009507929A JP 2009507929 A JP2009507929 A JP 2009507929A JP 4938843 B2 JP4938843 B2 JP 4938843B2
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T1/00—General purpose image data processing
- G06T1/60—Memory management
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T15/00—3D [Three Dimensional] image rendering
- G06T15/005—General purpose rendering architectures
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T17/00—Three dimensional [3D] modelling, e.g. data description of 3D objects
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
- G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
Description
110 グラフィックスプロセッサ
130 キャッシュメモリシステム
170 メインメモリ
200 グラフィックスシステム
210 グラフィックスプロセッサ
230 キャッシュメモリシステム
270 メインメモリ
320 状態機械
232 制御ユニット
240 クロスバー
500 グラフィックスシステム
510 グラフィックスプロセッサ
530 キャッシュメモリシステム
570 メインメモリ
600 プロセス
700 ワイヤレスアンテナ
712 アンテナ
714 レシーバ
716 トランスミッタ
720 デジタルセクション
770 メインメモリ
780 デイスプレイユニット
Claims (25)
- 下記を備える装置:
グラフィックス画像をレンダリングするためのグラフィックス動作を行うように構成された複数の処理ユニット;
前記複数の処理ユニットのうちの少なくとも1つの処理ユニットに対するデータを記憶するように構成された複数の構成可能なキャッシュ;
前記複数の処理ユニットによるメモリ利用を確認しかつメモリ利用に基づいて前記複数のキャッシュを前記少なくとも1つの処理ユニットに割り当てるように構成された制御ユニット、なお、前記制御ユニットは、フレームのコヒレンシに基づいて、前記構成可能なキャッシュを処理ユニットに割り当て、コヒレンシは、連続した2D/3Dフレームにおける変化の量に関連し、より高いコヒレンシに対してはより少ないキャッシュが割り当てられ、より低いコヒレンシに対してはより多いキャッシュが割り当てられる;および、
前記複数のキャッシュを前記少なくとも1つの処理ユニットに結合するように構成されたクロスバー。 - 前記複数のキャッシュのそれぞれが前記複数の処理ユニットのうちの任意の1つに割り当て可能である、請求項1の装置。
- 前記複数のキャッシュのそれぞれが前記複数の処理ユニットの各部分集合の任意の1つに割り当て可能である、請求項1の装置。
- 請求項1記載の装置、ここにおいて、
前記複数のキャッシュは、1つまたは複数の処理ユニットに割り当てられる1つまたは複数の専用キャッシュおよび残りの処理ユニットに割り当て可能な少なくとも1つの構成可能なキャッシュを備える。 - 各構成可能なキャッシュは、前記残りの処理ユニットの各部分集合の任意の1つに割り当て可能である、請求項4の装置。
- 前記残りの処理ユニットは、デプステストエンジンおよびテクスチャマッピングエンジンを含む、請求項4の装置。
- 請求項1記載の装置、ここにおいて、
前記制御ユニットは、先行するグラフィックス画像に対するメモリ利用に基づいて、レンダリングされるべき各グラフィックス画像に対して前記複数のキャッシュを割り当てるように構成されている。 - 請求項1記載の装置、ここにおいて、
前記制御ユニットは、前記処理ユニットによるデータ要求、キャッシュヒット/ミス統計、またはそれらの組み合わせに基づいてメモリ利用を確認するように構成されている。 - 請求項1記載の装置、ここにおいて、
前記制御ユニットは、画像のレンダリング時に前記複数の処理ユニットによるメモリ利用の変化を検知しかつメモリ利用の検知された変化に基づいて前記複数のキャッシュを再割り当てするように構成されている。 - 更に下記を備える請求項1記載の装置:
実行されているグラフィックスアプリケーションによるメモリ利用に基づいて前記複数のキャッシュを前記少なくとも1つの処理ユニットに割り当てるように構成された前記制御ユニット。 - 請求項1記載の装置、ここにおいて、
前記クロスバーは、複数のインタフェースユニットを備え、各インタフェースユニットは、関連付けられた処理ユニットを該処理ユニットに割り当てられたキャッシュの組に結合するように構成されている。 - 請求項11記載の装置、ここにおいて、
各インタフェースユニットは、前記関連付けられた処理ユニットにより要求されたデータが該処理ユニットに割り当てられた前記キャッシュの組の任意の1つに記憶されるか否かを判定するように構成された状態機械を備える。 - 請求項12記載の装置、ここにおいて、
各インタフェースユニットに対する前記状態機械は、前記複数のキャッシュからのキャッシュヒット/ミスインジケーターおよび前記関連付けられた処理ユニットに割り当てられた前記キャッシュの組を示す制御を受信する。 - 請求項12記載の装置、ここにおいて、
各インタフェースユニットに対する前記状態機械は、キャッシュミスが生じた場合に、前記関連付けられた処理ユニットに割り当てられた前記キャッシュの組の1つを満たすように構成されている。 - 前記複数のキャッシュは、キャッシュの少なくとも2つのレベルを有する階層構造に配列されている、請求項1の装置。
- 前記階層構造における少なくとも1つのレベルは構成可能な数のキャッシュを有する、請求項15の装置。
- 前記階層構造における少なくとも1つのレベルは、構成可能なキャッシュサイズを有する、請求項15の装置。
- 前記複数のキャッシュは、階層構造において構成可能な数のレベルに配列されている、請求項1の装置。
- 前記複数のキャッシュは、構成可能なキャッシュサイズを有する、請求項1の装置。
- 前記複数のキャッシュに結合されかつ前記複数のキャッシュとメインメモリとの間のデータ交換を容易にするように構成されたアービターをさらに含む、請求項1の装置。
- 前記複数の処理ユニットは、デプステストエンジンおよびテクスチャマッピングエンジンを含む、請求項1の装置。
- 請求項21記載の装置、ここにおいて、
前記複数の処理ユニットは、パイプラインに配列されており、かつ前記デプステストエンジンは、前記パイプラインにおいて前記テクスチャマッピングエンジンよりも早期に配置されている。 - 下記を備える集積回路:
グラフィックス画像をレンダリングするためのグラフィックス動作を行うように構成された複数の処理ユニット;
前記複数の処理ユニットのうちの少なくとも1つの処理ユニットに対するデータを記憶するように構成された複数の構成可能なキャッシュ;
前記複数の処理ユニットによるメモリ利用を確認しかつメモリ利用に基づいて前記複数のキャッシュを前記少なくとも1つの処理ユニットに割り当てるように構成された制御ユニット、なお、前記制御ユニットは、フレームのコヒレンシに基づいて、前記構成可能なキャッシュを処理ユニットに割り当て、コヒレンシは、連続した2D/3Dフレームにおける変化の量に関連し、より高いコヒレンシに対してはより少ないキャッシュが割り当てられ、より低いコヒレンシに対してはより多いキャッシュが割り当てられる;および、
前記複数のキャッシュを前記少なくとも1つの処理ユニットに結合するように構成されたクロスバー。 - 前記複数のキャッシュのそれぞれが前記複数の処理ユニットの各部分集合の任意の1つに割り当て可能である、請求項23の集積回路。
- 更に下記を備える請求項23記載の集積回路:
前記複数の処理ユニットによるメモリ利用を確認しかつメモリ利用に基づいて前記複数のキャッシュを前記少なくとも1つの処理ユニットに割り当てるように構成された前記制御ユニット。
Applications Claiming Priority (3)
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US11/412,678 US8766995B2 (en) | 2006-04-26 | 2006-04-26 | Graphics system with configurable caches |
US11/412,678 | 2006-04-26 | ||
PCT/US2007/067325 WO2007127745A1 (en) | 2006-04-26 | 2007-04-24 | Graphics system with configurable caches |
Publications (2)
Publication Number | Publication Date |
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JP2009535710A JP2009535710A (ja) | 2009-10-01 |
JP4938843B2 true JP4938843B2 (ja) | 2012-05-23 |
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JP2009507929A Expired - Fee Related JP4938843B2 (ja) | 2006-04-26 | 2007-04-24 | 構成可能なキャッシュを有するグラフィックスシステム |
Country Status (9)
Country | Link |
---|---|
US (1) | US8766995B2 (ja) |
EP (1) | EP2011079B1 (ja) |
JP (1) | JP4938843B2 (ja) |
KR (1) | KR101018999B1 (ja) |
CN (1) | CN101427282B (ja) |
BR (1) | BRPI0712834A2 (ja) |
CA (1) | CA2649567C (ja) |
RU (1) | RU2412469C2 (ja) |
WO (1) | WO2007127745A1 (ja) |
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KR20090026124A (ko) | 2009-03-11 |
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US8766995B2 (en) | 2014-07-01 |
WO2007127745A1 (en) | 2007-11-08 |
CA2649567C (en) | 2012-01-17 |
CA2649567A1 (en) | 2007-11-08 |
JP2009535710A (ja) | 2009-10-01 |
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