JP4902601B2 - Driving method of plasma display device - Google Patents

Description

  The present invention relates to a plasma display (PDP) device and a driving method thereof, and more particularly to an ALIS (Alternate Lighting of Surfaces) type PDP device in which display lines are formed on both sides of each sustain discharge electrode to perform interlaced display and a driving method thereof. About.

  Japanese Patent No. 20001933 (Patent Document 1) discloses an ALIS PDP apparatus that realizes high-definition display at low cost. FIG. 1 is a block diagram showing a schematic configuration of an ALIS PDP apparatus disclosed in this document. As shown in the figure, the ALIS PDP apparatus includes first electrodes (X electrodes) X-1, X-2,... And second electrodes (Y electrodes) Y-1, Y-2,. ..., the panel 1 provided with the address electrodes A-1, A-2, ..., the control circuit 11, the address driver 13, the scan driver 12, the odd-number Y sustain discharge (sustain) circuit 16, and the even-number Y A sustain discharge (sustain) circuit 17, an odd number X sustain discharge (sustain) circuit 14, an even number X sustain discharge (sustain) circuit 15, and a power supply circuit 18 are provided. Since the configuration and operation of each element are disclosed in Patent Document 1, detailed description thereof is omitted here.

  The feature of the ALIS system is that a first display line is formed between the X electrodes adjacent to the upper side of each Y electrode, and a second display line is formed between the X electrodes adjacent to the lower side. By displaying interlaced display of displaying the first display line and displaying the second display line in the even field, this feature provides twice as many display lines as before with the same number of X electrodes and Y electrodes. It is a point that can be made high definition.

  In the PDP device, various techniques have been proposed for improving display quality and reliability, reducing power consumption, and reducing costs. The present invention relates to a reset operation. As a technique related to this, for example, Japanese Patent Laid-Open No. 2000-75835 (Patent Document 2) uses a reset pulse having a voltage waveform with a gentle slope in an ALIS panel. A technique for improving the contrast by using it is disclosed. Japanese translation of PCT publication No. 2000-501199 (Patent Document 3) discloses a reset method using a ramp wave. Further, Japanese Patent Laid-Open No. 2000-242224 (Patent Document 4) discloses a technique for improving contrast by applying a reset pulse accompanied by lighting of all display cells only to the first subfield. Further, Japanese Patent Laid-Open No. 2000-29431 (Patent Document 5) discloses a technique for stabilizing the operation by changing the reset voltage in accordance with the subfield emission pixel ratio, and Japanese Patent Laid-Open No. 2000-172224 (Patent Document). 6) discloses a technique for reducing malfunctions by setting a reset pulse voltage according to the number of sustain discharges in the immediately preceding subfield.

  In recent years, the display performance of PDP devices has been remarkably improved, and performance close to that of a cathode ray tube has been obtained in terms of brightness, definition, contrast, and the like. However, with the evolution of broadcasting and video software, further improvement in performance is desired on the display device side, and further improvement in darkroom contrast is desired. The brightness of black display, which is the cause of lowering the dark room contrast, is light emission due to reset discharge to stabilize discharge, and sufficient reset discharge is necessary to address many display lines at high speed. Therefore, a discharge with a certain level of luminance is necessary. Thus, stable operation and darkroom contrast are in a contradictory relationship. According to Patent Document 4, a reset pulse accompanied by lighting of all display cells is applied once in one field, that is, only in one subfield, and in other subfields, the display is lit in the previous subfield. By executing only the erasing discharge only in the cell, the background light emission (black luminance) is greatly reduced and the darkroom contrast is improved.

On the other hand, in the ALIS PDP apparatus disclosed in Patent Document 1, a darkroom contrast of about 500: 1 is obtained by using the reset pulse having the slope waveform disclosed in Patent Document 2. However, since this method performs reset discharge for all display cells in all subfields, the luminance is about 10 times higher than the luminance of background light emission when the technique disclosed in Patent Document 4 is applied. It has become. In a panel or high-definition panel that uses all electrode gaps as a display line as in the ALIS system, coupling between display cells adjacent vertically is strong, and charge diffusion from a lighted cell to a light-off cell tends to occur. Therefore, the state of the display cell changes even when the address discharge or the sustain discharge is not performed after the reset. Therefore, in order to stably perform the address discharge in the next subfield, it is necessary to perform reset discharge for all display cells including the extinguished cells.
Patent No. 20001933 JP 2000-75835 A Special Table 2000-501199 JP 2000-242224 A JP 2000-29431 A JP 2000-172224 A

  FIG. 2 shows how charges are diffused to adjacent display cells by sustain discharge in an ALIS panel. In the ALIS panel, the sustain electrodes (X electrode, Y electrode) are arranged at equal intervals, and the discharge can be performed in the gaps of all the electrodes. This figure shows the operation in the case where a lighted cell is formed between the X2 electrode and the Y2 electrode in the odd field. FIG. 2A shows the initial state of the sustain discharge period. Charged particles such as electrons and positive ions generated by the discharge move in the discharge space by an electric field. In an ALIS panel or a high-definition panel, an electrode of an adjacent cell is in the vicinity of a lighting cell, and a strong electric field is applied to the electrode, so that charges easily move and accumulate. In this case, most of the charges diffusing into the adjacent cells are electrons having high mobility.

  FIG. 2B shows a state in the second half of the sustain discharge period of the subfield in which the sustain discharge is repeatedly performed, that is, the number of sustain discharge pulses is large (the sustain discharge period is long). At the stage of shifting to the next subfield, if reset (erase) is performed only on the lighted cell as disclosed in Patent Document 4, the charge of the light-off cell adjacent to the lighted cell remains as it is. become. In this state, the address period starts, and as shown in FIG. 2C, when a scan pulse is applied to the Y1 electrode, a voltage due to the negative charge accumulated in the Y1 electrode is superimposed on -170 V of the scan pulse. Is done. For this reason, an address pulse is not applied to the extinguished cell, and a discharge occurs between the X electrode and the Y electrode even in a display cell where there is no discharge between the address electrode A and the Y electrode. This display cell emits light in the next sustain discharge period, resulting in erroneous display. As shown in FIG. 2D, when negative charges are accumulated in the X3 electrode, a scan pulse is applied to the Y3 electrode, an address pulse is applied to the address electrode A, and the Y3 electrode and the address are addressed. Even if a discharge is performed between the electrodes, the negative charge on the X electrode side lowers the effective voltage, so the discharge between the X electrode and the Y electrode does not occur, the wall charge necessary for the sustain discharge is not formed, and the sustain discharge Will not be done. That is, it is not lit.

  As described above, in a panel in which electrodes of adjacent cells are present nearby such as an ALIS system panel, reset discharge for all display cells in all subfields is indispensable. In addition, a reset voltage is set assuming that the accumulated charge is the largest, and the reset is performed with the voltage in all subfields. For this reason, the reset voltage is increased, it is difficult to reduce the background light emission to a certain level, and the darkroom contrast is not sufficiently improved.

  The present invention solves such a problem, and even in a panel in which electrodes of adjacent cells are present nearby such as an ALIS system panel, background light emission can be sufficiently reduced and dark room contrast can be further improved. An object is to realize a driving method and a PDP device.

In order to achieve the above object, according to the present invention , a first electrode extending in a first direction and a second electrode are disposed adjacent to each other, and one display field includes a plurality of subfields having a reset period, an address period, and a sustain discharge period. A plasma display device driving method comprising: at least a writing discharge step and an erasing discharge step, wherein the reset period includes a voltage value that gradually increases in time as time passes. A voltage having a first slope waveform with a gradually changing slope is applied to the second electrode, and the voltage value gradually changes in a decreasing direction as time passes during the erasing discharge process. A voltage having a second slope waveform is applied to the second electrode, and the voltage of the first slope waveform in at least two subfields of the plurality of subfields. Varying the arrival voltage value.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows. According to the present invention, since a voltage larger than necessary is not applied in the reset discharge of each subfield, the background luminance can be reduced and the darkroom contrast can be improved.

  Hereinafter, embodiments of the present invention will be described. Here, a case where the present invention is applied to an ALIS system PDP apparatus having the configuration shown in FIG. 1 disclosed in Patent Document 1 will be described as an example.

  FIG. 3 is a diagram showing a drive waveform of the PDP device according to the embodiment of the present invention, and shows a drive waveform in an odd field. The present invention is characterized by the drive waveform in the reset period, and the address period and the sustain discharge period are the same as those in the conventional example. Therefore, the description is omitted here, and the voltage waveform in the reset period is described.

  FIG. 4 is a diagram showing voltage waveforms applied to the X electrode and the Y electrode during the reset period in the embodiment of the present invention. In the reset period, a pulse having a gentle slope waveform that gradually reaches −Vwx (−120 V) is applied to the X electrode. By using such a waveform, the wall charge of the display cell that was lit in the previous subfield is erased. This is the first erase period. Next, a pulse having a slope waveform is applied to the Y electrode in a state where the voltage of the X electrode is maintained, and all the display cells are discharged to form wall charges. This is the writing period. Thereafter, a pulse having a slope waveform reaching −Vey (−160 V) is applied to the Y electrode while the voltage Vx (90 V) is further applied to the X electrode. This is the second erase period.

  The present invention is characterized in that the voltage applied between the X electrode and the Y electrode is adjusted in the first erasing period and the writing period. As shown in FIG. 4, the applied voltage has a slope waveform and gradually changes. Therefore, adjusting the voltage here means adjusting the voltage level to be finally applied. The voltage adjustment method includes a method of adjusting the voltage on the Y electrode side, a method of adjusting the voltage on the X electrode side, and a method of adjusting both. In FIG. 4, the final voltage reached by the slope waveform applied to the X electrode changes in the range from -Vwx1 to -Vwx2, and the final voltage reached by the slope waveform applied to the Y electrode changes in the range from Vw1 to Vw2. To do. -Vwx2 is -120V, which is the same as the prior art, and -Vwx1 is -50V, and is set to a predetermined value for each subfield within this range. Further, Vw2 is 200 V, which is the same as the conventional one, and Vw1 is 100 V, and is set to a predetermined value within this range according to the subfield conditions and display state.

  FIG. 5 is a diagram showing the configuration of a drive circuit that generates the reset waveform as described above. The odd X sustain circuit 14, the even X sustain circuit 15, the odd Y sustain circuit 16, and the even Y sustain circuit 17 shown in FIG. It corresponds to the part. Reference numeral 31 is a circuit for generating a sustain discharge pulse to be applied to the X electrode, and 41 is a circuit for generating a sustain discharge pulse to be applied to the Y electrode. In this drive circuit, four types of reset voltage values are prepared in advance on both the X electrode side and the Y electrode side. The voltage applied to the Y electrode of the display cell 21 of the panel 1 is outputted by selectively turning on any of the switches 42 to 45. On the X electrode side, a power source having the lowest voltage (−the largest absolute value) −Vwx is provided. When outputting this voltage, the switch 35 is turned on and then the switch 35 is turned on. When a higher voltage (small absolute value) is output, the switch 38 or 39 is turned on with the switch 37 turned off, or both are turned off and the switch 35 is turned on. When the switch 37 is turned on, the voltage -Vwx is output to the X electrode of the display cell 21 of the panel 1, and in other cases, a voltage obtained by subtracting the voltage defined by one to three Zener diodes is output. The In this embodiment, an output voltage is generated from a plurality of power sources on the Y electrode side and a single power source on the X electrode side using a Zener diode. It is also possible to realize with either method. In this embodiment, there are four types of voltage values that can be taken by the output voltage. Even at this level, background light emission can be sufficiently reduced.

  FIG. 6 is a diagram showing a reset waveform of each subfield in the first embodiment of the present invention. Since the PDP device can only control whether light is emitted or not, gradation level is displayed by composing one field with a plurality of subfields and combining the lighted subfields. In the first embodiment, one field (odd field or even field) is composed of 10 subfields, the sustain discharge period of the first subfield and the 10th subfield is the longest, and the sustain discharge pulse is the most. So brightest. The sustain discharge period is shorter in the central subfield. This is a display sequence for reducing false color contours, which is a phenomenon of image quality deterioration unique to PDP devices.

  In the first embodiment, only the voltage Vw applied to the Y electrode during the writing period of the reset period is made variable, and this is called a reset voltage. In the first embodiment, the reset voltage of the first subfield is set to the largest value for the reason described below. The first reason is that, in the case of the ALS method, since the odd-numbered display and the even-numbered display are switched in the first subfield, it is necessary to activate the electrode pair side that was not lit in the previous field. It is. The second reason is that the period of the field is synchronized with a vertical synchronization signal input from the outside of the display device. For this reason, in the case of a video signal having a long period of the vertical synchronization signal, the time from the end of the last subfield to the start of the first subfield becomes long, and the priming effect that affects the stability of discharge is reduced. This is because it is necessary to perform a relatively strong discharge on all the display cells again to generate space charges. The third reason is that since the number of sustain discharges in the tenth subfield is large, a large amount of electrons may be accumulated in the adjacent cell as shown in FIG. The electrons accumulated on the Y electrode side require a high voltage to lower the effective value of the reset voltage (Vw). For the above reason, the reset voltage of the first subfield needs to be set to about 200V. Conventionally, since the necessary voltage of 200 V is applied in all subfields, the applied voltage is excessive except in the first subfield.

  Although the number of sustain discharges in the immediately preceding first subfield is large, the reset voltage of the second subfield can be lower than that of the first subfield because there is no first and second reasons described above.

  The number of sustain discharges in the fifth subfield is the fewest, and there is almost no charge accumulation in the adjacent display cells described with reference to FIG. The formed state is maintained. Therefore, the reset voltage in the sixth subfield thereafter is the lowest and is set to about 100V. Since the discharge threshold voltage between the X electrode and the Y electrode is about 220 V, the extinguished cell hardly discharges.

  The reset voltage of the third subfield to the fifth subfield is a value between the reset voltages of the second subfield and the sixth subfield, and the reset voltage of the seventh subfield to the tenth subfield is a sustain discharge period. Is set to be slightly higher than the reset voltage of the sixth subfield accordingly. In the first embodiment, the length of the reset period is fixed.

  FIG. 7 is a diagram showing a reset waveform of each subfield in the second embodiment of the present invention. The difference from the first embodiment of FIG. 6 is that the voltage Vw applied to the Y electrode is changed and the voltage applied to the electrode is changed according to various conditions. The applied voltage to the X electrode in the first erasing period of the reset period of the first subfield and the applied voltage to the Y electrode in the writing period are both increased in absolute value for the same reason as described above. In the first embodiment, the reset voltage of the subfield is lowered. In the second embodiment, the voltage applied to the Y electrode is kept high, and the absolute value of the voltage on the X electrode side is reduced. (Because it is a negative voltage, it is increased.) The reason is as follows. In the sustain discharge period, the address electrode becomes a cathode on average, so that the negative charge formed on the address electrode side by the address discharge is exposed to the sustain discharge and gradually erased. However, when the number of sustain discharges is small, it is difficult to erase. If the charge remains as it is, it is not preferable because it acts in the direction of lowering the effective value of the address pulse voltage. Therefore, in order to erase the negative charge on the address electrode side in the reset period, the voltage between the X electrode and the Y electrode is set to be small even if the voltage between the X electrode and the Y electrode is set small. The function of erasing the negative charge on the address electrode side by the discharge between the electrode and the Y electrode is strengthened.

  FIG. 8 is a diagram showing the configuration of the sustain electrode drive circuit of the third embodiment of the present invention. In the drive circuits of the first and second embodiments in FIG. 5, a plurality of power supplies having different voltages are provided or an output voltage is generated from a single power supply using a Zener diode. The circuit is different in that the voltage applied to the electrode is gradually changed, the voltage of the electrode is monitored, and the voltage application is stopped when a predetermined value is reached. It is assumed that the X electrode side drive circuit 30 of the third embodiment has the same configuration as the X electrode side drive circuit of FIG. The reset voltage Vw is applied to the Y electrode of the display cell 21 via the current limiter 55 by turning on the switch 54. Since the current limiter 55 is provided, the current flowing into the panel 1 is limited, and the voltage of the Y electrode changes with a slope waveform with a gentle slope. Further, the reset pulse voltage applied to the Y electrode is monitored by the voltage detector 56, and when the voltage reaches a predetermined voltage, the switch 54 is turned off by the reset voltage control circuit 53. The reset voltage control circuit 53 receives information on the subfield being executed from the display sequence control circuit 51, information on the number of sustain discharges, and the like, and determines the reset application voltage from these information.

  In the third embodiment, when the reset voltage reaches a predetermined value and the switch 54 is turned off, the process proceeds to the next erase step. FIG. 9 is a diagram showing a reset waveform of each subfield in the third embodiment. 6 and 7, the voltage of the Y electrode is held for a while after reaching the predetermined value, whereas in the third embodiment, the voltage is applied immediately after the voltage of the Y electrode reaches the predetermined value. The operation is stopped and the operation is shifted to the next erasing period. Thereby, the operation time can be shortened, and the shortened time can be used, for example, for extending the sustain discharge period.

  Although the first to third embodiments have been described above, it goes without saying that optimum values are set according to the design of the panel and the driving conditions as to which set voltage and which voltage are output.

  FIG. 10 is a diagram for explaining the effect of the present invention. As shown in the first to third embodiments, the intensity of reset light emission when the reset voltage of each subfield is controlled to be optimum is shown in FIG. It is shown in contrast with the case of. As shown in the figure, the light emission intensity due to the reset pulse at the center is reduced, the background luminance is reduced from about 1/2 to 1/3 of the conventional one, and the darkroom contrast is improved from 2 times to 3 times.

  As described above, when the number of sustain discharges is large, a large cause is that charges generated by discharge are diffused and accumulated in the electrodes of adjacent display cells. Therefore, when the number of sustain discharges in the previous field is small, the reset voltage in the next field can be lowered. For example, in a PDP device, when the display rate is high, the length of the sustain discharge period is shortened to limit the power increase. In such a case, the reset voltage in the write discharge process may be reduced. Is possible.

  (Supplementary Note 1) First electrodes and second electrodes extending in a first direction are alternately arranged adjacent to each other, a first display line is formed between the first electrode adjacent to one of the second electrodes, A plasma display that performs interlaced display in which a second display line is formed between the second electrode and the first electrode adjacent to the other of the second electrodes, and the first display line and the second display line are alternately displayed in separate fields. An apparatus driving method, wherein one display field includes a plurality of subfields, and each subfield includes at least a reset period, an address period, and a sustain discharge period, and the reset period includes at least an address discharge process. In the method of driving the plasma display device comprising the erasing discharge process, the voltage of the write discharge process is different in at least some subfields. A driving method of a plasma display apparatus which comprises causing (1).

  (Additional remark 2) It is a drive method of the plasma display apparatus of Additional remark 1, Comprising: The voltage of the said write discharge process of the said reset period of the subfield after a subfield with few sustain discharge frequency in the said sustain discharge period is made small. Driving method of plasma display apparatus.

  (Supplementary note 3) The plasma display device driving method according to supplementary note 1, wherein the plasma display device further includes a third electrode extending in a direction perpendicular to the first and second electrodes, and the write discharge In the step, the driving method of the plasma display device (2), wherein the voltage applied to the first electrode and / or the voltage applied to the second electrode is changed while a predetermined voltage is applied to the third electrode. .

  (Supplementary note 4) The plasma display device driving method according to supplementary note 1, wherein the writing in the reset period of the first subfield of the next field after the field for displaying the first or second display line is completed. A method for driving a plasma display apparatus, wherein a voltage in a discharge process is made larger than that in other subfields.

  (Additional remark 5) It is a drive method of the plasma display apparatus of Additional remark 1, Comprising: Time of one field becomes short, and after the last subfield in a field is complete | finished, it starts until the first subfield of the next field is started A method of driving a plasma display apparatus, wherein when a pause period occurs between the first and second subfields, the voltage in the write discharge process is increased in accordance with the length of the pause period.

  (Supplementary note 6) The plasma display device driving method according to supplementary note 1, wherein the voltage waveform in the write discharge step is a slope waveform in which the voltage gradually changes.

  (Supplementary note 7) The driving method of the plasma display device according to supplementary note 6, wherein the time of the writing discharge process is constant, and after reaching a predetermined voltage for each subfield, the voltage is set to the end of the writing discharge process. A method of driving a plasma display device that maintains a maximum of.

  (Supplementary note 8) The plasma display device driving method according to supplementary note 6, wherein the voltage change rate of the voltage waveform in the write discharge step is the same in all subfields, and immediately after the voltage reaches a predetermined value. Driving method of plasma display apparatus which shifts to the erasing process.

  (Supplementary Note 9) A first electrode and a second electrode that extend in a first direction and are alternately arranged adjacent to each other, and a drive circuit that applies a drive voltage to the first and second electrodes, and the second electrode A first display line is formed between the first electrode adjacent to one of the first electrodes, a second display line is formed between the first electrode adjacent to the other of the second electrodes, and the first display line Interlaced display in which the second display lines are alternately displayed in separate fields is performed. One display field is composed of a plurality of subfields, and each subfield is composed of at least a reset period, an address period, and a sustain discharge period. Further, in the plasma display device including at least a write discharge process and an erasure discharge process in the reset period, the drive circuit includes at least a part of the subfields. In came narrowing discharge process, a plasma display apparatus and outputs a different voltage (4).

  (Additional remark 10) It is a plasma display apparatus of Additional remark 9, Comprising: The said drive circuit is provided with the several voltage source for write discharge, The plasma display apparatus which selects this several voltage source and makes a voltage differ.

  (Additional remark 11) It is a plasma display apparatus of Additional remark 9, Comprising: The said drive circuit is a voltage source circuit from which a voltage increases gradually to predetermined value as time passes, and the voltage which monitors the voltage applied to an electrode A plasma display device comprising a monitoring circuit and interrupting voltage application when the voltage of the electrode reaches a predetermined value.

(Additional remark 12) The 1st electrode extended in the 1st direction and the 2nd electrode are alternately arranged adjacently, a 1st display line is formed between the 1st electrode adjacent to one side of the 2nd electrode, A plasma display that performs interlaced display in which a second display line is formed between the second electrode and the first electrode adjacent to the other of the second electrodes, and the first display line and the second display line are alternately displayed in separate fields. A device driving method, wherein one display field is composed of a plurality of subfields,
Each subfield includes at least a reset period, an address period, and a sustain discharge period, and the reset period includes at least a writing discharge process and an erasing discharge process in a driving method of a plasma display apparatus when a display rate is high. The length of the sustain discharge period is controlled according to a display rate so as to limit the increase in power by shortening the length of the sustain discharge period, and when the sustain discharge period is short, the final voltage of the write discharge process (5) A method of driving a plasma display device, wherein

  The present invention is applicable to a plasma display device.

It is a block diagram which shows schematic structure of the plasma display apparatus (PDP apparatus) of an ALIS system. It is a figure explaining the problem of a prior art. It is a figure which shows the drive waveform in the Example of this invention. It is a figure which shows the reset waveform of an Example. It is a figure which shows the structure of the sustain electrode drive circuit of an Example. It is a figure which shows the reset waveform of each subfield in 1st Example of this invention. It is a figure which shows the reset waveform of each subfield in 2nd Example of this invention. It is a figure which shows the structure of the sustain electrode drive circuit of 3rd Example of this invention. It is a figure which shows the reset waveform of each subfield in 3rd Example. It is a figure explaining the effect of this invention.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Plasma display panel, 11 ... Control circuit, 12 ... Scan circuit, 13 ... Address driver, 14 ... Odd X sustain discharge (sustain) circuit, 15 ... Even X sustain discharge (sustain) circuit, 16 ... Odd Y sustain discharge ( (Sustain) circuit, 17 ... even Y sustain discharge (sustain) circuit, 18 ... power supply circuit.

Claims (2)

A driving method of a plasma display apparatus, wherein a first electrode extending in a first direction and a second electrode are disposed adjacent to each other, and one display field has a plurality of subfields having a reset period, an address period, and a sustain discharge period,
The address period is a period in which a negative scan pulse is applied to the second electrode,
The sustain discharge period is a period in which a sustain pulse for performing a sustain discharge is applied to at least one of the first electrode and the second electrode,
The reset period includes at least a write discharge step and an erase discharge step,
During the write discharge step, a voltage having a first slope waveform with a gentle slope in which the voltage value gradually changes in an increasing direction as time passes is applied to the second electrode,
During the erasing discharge step, a voltage having a second slope waveform with a gentle slope in which the voltage value gradually changes in a decreasing direction with the passage of time is applied to the second electrode,
The voltage between the first and second electrodes at the maximum voltage of the first slope waveform in the subfield immediately after the second subfield in which the number of sustain pulses applied is greater than that in the first subfield. The first difference is greater than the voltage difference between the first and second electrodes at the maximum voltage reached in the first slope waveform in the subfield immediately after the first subfield . the driving method of a plasma display device according to claim racemase Rukoto different arrival voltage value of the voltage of the first slope waveform. The driving method of the plasma display device according to claim 1,
The method of driving a plasma display device, wherein the voltage of the first slope waveform in the write discharge step is a voltage of a slope waveform having a predetermined slope with a constant voltage change amount per unit time.

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