JP4881339B2 - Semiconductor integrated circuit device - Google Patents

Description

  The present invention relates to a semiconductor integrated circuit device, for example, a semiconductor integrated circuit device including a transistor used by applying a substrate bias.

  In recent years, with the miniaturization of CMOS, variations in the manufacturing process between CMOSs are increasing, which is one of the causes of increasing performance variations between IC chips. When designing an IC, it is necessary to consider both the worst condition of operation speed and the worst condition of power consumption. However, the increase in performance variation between IC chips makes it difficult to cope with these worst conditions. There is a risk of increasing the difficulty of IC design.

  A substrate bias technique is known as a technique for suppressing performance variations between IC chips. In the substrate bias technology, the substrate potential (back gate) is set higher than the source potential, and the forward bias substrate bias is generated to control the threshold voltage of the transistor.

  The forward bias is generated, for example, by connecting a voltage source to the substrate node. However, since a PN forward junction exists between the substrate and the source, when the substrate voltage exceeds the PN forward junction voltage, a large leakage current is generated in the substrate. Further, the PN forward junction voltage changes according to the temperature, and at a high temperature, a large leakage current is generated with a substrate voltage smaller than 0.6 V, which is a normal PN forward junction voltage. Therefore, in consideration of the temperature change, the substrate voltage must be a voltage sufficiently smaller than 0.6V (for example, 0.45V).

  In addition, for example, a method is known in which a current is supplied to a substrate using a current source circuit and a forward voltage generated in a PN forward junction is used as a substrate bias (see, for example, Patent Document 1). In this method, by supplying a predetermined amount of current to the PN forward junction, the maximum substrate bias allowed at each temperature can be provided even when a temperature change occurs.

  In this method, when the control signal of the current source circuit fluctuates due to the influence of crosstalk noise or the like, the substrate current amount may change greatly.

Furthermore, it is necessary to estimate the substrate current amount according to the scale of the logic circuit (PN junction area). However, the ratio of the logic circuit area to the integrated circuit area (cell utilization: utilization) varies from integrated circuit to integrated circuit, and the circuit design of the integrated circuit can be changed over and over again through logic synthesis and optimization. Therefore, it is difficult to specify the scale of the logic circuit. Therefore, it is not easy to estimate the substrate current amount according to the scale of the logic circuit.
JP 2004-289107 A

  The present invention relates to a semiconductor integrated circuit device capable of generating a substrate bias by passing a current through a substrate, and an object thereof is to optimize the substrate current amount.

  According to the semiconductor integrated circuit device of one embodiment of the present invention, the first first connected in series between the semiconductor substrate, the first power supply line, and the second substrate well provided on the semiconductor substrate. A first conductivity type transistor and a first first conductivity type transistor, wherein a source or drain of the first first conductivity type transistor is connected to the first power supply line, and the first first conductivity type A first control signal input from the outside is input to the gate of the transistor, and the source or drain of the second first conductivity type transistor is connected to the second substrate well, and the second second well is connected to the second substrate well. A gate of the one conductivity type transistor is connected to a second power supply line, and a first connected in series between the second power supply line and a first substrate well provided on the semiconductor substrate. Second conductivity type transistor and second conductivity type A second conductivity type transistor, the source or drain of the first second conductivity type transistor is connected to the second power supply line, and the gate of the first second conductivity type transistor is externally connected The input second control signal is input, the source or drain of the second second conductivity type transistor is connected to the first substrate well, and the gate of the second second conductivity type transistor is It is connected to the first power supply line.

  According to another aspect of the semiconductor circuit device of the present invention, there is provided a semiconductor substrate, a first power source line, and a second substrate well provided on the semiconductor substrate, connected in series. A first conductivity type transistor and a first second conductivity type transistor, wherein a source or drain of the first first conductivity type transistor is connected to the first power supply line, and the first first conductivity type transistor is connected to the first power source line. A first control signal input from the outside is input to the gate of the first conductivity type transistor, and the source or drain of the first second conductivity type transistor is connected to the second substrate well, and A gate of one second conductivity type transistor is connected to the first power supply line, and is connected in series between the second power supply line and a first substrate well provided on the semiconductor substrate. A second first conductivity type transistor; A second conductivity type transistor, and a source or drain of the second second conductivity type transistor is connected to the second power supply line, and a gate of the second second conductivity type transistor is connected to the gate of the second second conductivity type transistor. The second control signal input from the outside is input, the source or drain of the second first conductivity type transistor is connected to the first substrate well, and the second first conductivity type transistor is connected. The gate is connected to the second power supply line.

  Examples of the present invention will be described below.

The embodiment of the present invention stably generates the substrate bias voltage by using the following (1) and (2).
(1) A substrate bias is generated using a parasitic diode caused by a PN junction using a substrate bias generation circuit.
(2) Using a PN junction placed in a portion (fill cell) other than the logic cell in the integrated circuit,
Create a constant PN junction area in an integrated circuit regardless of the usage rate of logic cells.

  First, the substrate bias generating circuit described in (1) and its arrangement on the substrate will be described using the first to fourteenth embodiments.

  Next, in the fifteenth embodiment and thereafter, a method for producing the constant PN junction area described in (2) in the integrated circuit will be described.

(First embodiment)
FIG. 1 is a side sectional view of a semiconductor integrated circuit device 101 according to the first embodiment. The semiconductor integrated circuit device 101 according to the first embodiment includes a pMOS 121 (hereinafter referred to as pMOS), an nMOS 122 (hereinafter referred to as nMOS), a substrate bias generation circuit 113 for pMOS, and a substrate bias generation circuit 114 for nMOS. It comprises. FIG. 1 further shows the gate (G), source (S), drain (D), and body (B) of each of the pMOS 121 and the nMOS 122.

  The semiconductor integrated device circuit 101 includes a substrate 301. In the substrate 301, there are an N well 311 as a first substrate well corresponding to a deep N well and a P well 312 as a second substrate well. The pMOS 121 is formed on the N well 311, and the nMOS 122 is formed on the P well 312. Further, an n + diffusion region 321 surrounded by an N well 311 and a p + diffusion region 322 surrounded by a P well 312 exist in the substrate 301.

  As will be described later, the substrate bias generation circuit 113 for pMOS has a current source transistor 131 for pMOS. The pMOS current source transistor 131 is connected to the n + diffusion region 321. Further, as described later, the nMOS substrate bias generation circuit 114 includes an nMOS current source transistor 141. The nMOS current source transistor 141 is connected to the p + diffusion region 322.

  In the semiconductor integrated circuit device 101, parasitic diodes 123, 124, 125, and 126 between the SB of the pMOS 121 (between the source and body), between the DB of the pMOS 121 (between the drain and body), between the SB of the nMOS 122, and between the DB of the nMOS 122, respectively. And parasitic bipolars 127, 128, 129, and 130 exist. Each of the parasitic diodes 123 to 126 is a diode formed by a PN structure in the substrate 101. The parasitic bipolar 127-130 is a bipolar formed by a PNP structure or an NPN structure in the substrate 101, respectively.

  In this embodiment, the current Ibp of the current source transistor 131 flows in the forward direction through the parasitic diodes 123 and 124, thereby generating the substrate bias voltage Vbp in the N well 311 (the body of the pMOS 121). Also in this embodiment, the current Ibn of the current source transistor 141 flows in the forward direction through the parasitic diodes 125 and 126, thereby generating the substrate bias voltage Vbn in the P well 312 (the body of the nMOS 122). These further details will be specifically described below.

  FIG. 2 is a circuit configuration diagram of the semiconductor integrated circuit device 101 of the first embodiment. FIG. 2 conceptually shows the circuit configuration of the semiconductor integrated circuit device 101. The semiconductor integrated circuit device 101 includes a logic circuit 111 and a substrate bias generation circuit 112. The logic circuit 111 and the substrate bias generation circuit 112 are provided on the same substrate, and the semiconductor integrated circuit device 101 can generate a substrate bias by flowing a current through the substrate. Here, the substrate is a semiconductor substrate such as a silicon substrate, for example, a bulk semiconductor substrate such as a bulk silicon substrate.

  The logic circuit 111 includes a logic cell 211 and a fill cell 212. The logic cell 211 is an inverter in this embodiment, and includes a pMOS transistor 121 and an nMOS transistor 122 that constitute a CMOS. The gate (G), source (S), drain (D), and body (B) of each of the pMOS 121 and the nMOS 122 are shown in FIG. The source of the pMOS 121 and the source of the nMOS 122 are connected to the power supply line VDD as the first power supply line and the ground line VSS as the second power supply line, respectively. The drain of the pMOS 121 and the drain of the nMOS 122 are connected to a common output terminal OUT. The body of the pMOS 121 and the body of the nMOS 122 are connected to the substrate bias line Vbp for pMOS and the substrate bias line Vbn for nMOS, respectively. Parasitic diodes 123 and 124 exist between the SB of the pMOS 121 (between the source and body) and between the DB (between the drain and body), respectively. Parasitic diodes 125 and 126 exist between the SB and DB of the nMOS 122, respectively. The logic cell 211 is an inverter in this embodiment, but may have a configuration of a logic circuit other than an inverter having a pMOS transistor or an nMOS transistor. The fill cell 212 will be described in detail in the fifteenth embodiment and later (FIG. 36 and later). 6, 7, 14, 16, and 18, only the logic cell 211 is displayed for convenience of explanation.

  The substrate bias generation circuit 112 includes a substrate bias generation circuit 113 for pMOS and a substrate bias generation circuit 114 for nMOS. The substrate bias generation circuit 113 for pMOS has a current source transistor 131, a switch transistor 132, and a switch transistor 133 as MOS transistors. The nMOS substrate bias generation circuit 114 includes a current source transistor 141, a switch transistor 142, and a switch transistor 143 as MOS transistors. FIG. 2 shows gates (G), sources (S), drains (D), and bodies (B) of the transistors 131, 132, 133, 141, 142, and 143, respectively.

  The current source transistor 131 is a current source transistor for pMOS, and generates a substrate current Ibp for pMOS. When a substrate current Ibp flows through the body of the pMOS 121, a substrate bias is generated in the pMOS 121. The substrate bias is a voltage generated when the substrate current Ibp flows through the parasitic diodes 123 and 124. On the other hand, the current source transistor 141 is a current source transistor for nMOS, and generates a substrate current Ibn for nMOS. When a substrate current Ibn flows through the body of the nMOS 122, a substrate bias is generated in the nMOS 122. The substrate bias is a voltage generated when the substrate current Ibn flows through the parasitic diodes 125 and 126. The gates of the current source transistor 131 and the current source transistor 141 are connected to the power supply line VDD and the ground line VSS, respectively. The sources of the current source transistors 131 and 141 are connected to the drains of the switch transistors 133 and 143, respectively. The drains of the current source transistors 131 and 141 are connected to substrate bias lines Vbp and Vbn for substrate bias by the substrate currents Ibp and Ibn, respectively, and output the substrate currents Ibp and Ibn. The bodies of the current source transistors 131 and 141 are connected to the substrate bias lines Vbn and Vbp, respectively. However, when the logic circuit 111 and the well are separated, they may be connected to the ground line VSS and the power supply line VDD.

  The switch transistor 132 is a pMOS switch transistor, and switches ON / OFF of the substrate bias for pMOS according to the control signal Cbp for pMOS. On the other hand, the switch transistor 142 is a switch transistor for nMOS, and switches ON / OFF of the substrate bias for nMOS according to the control signal Cbn for nMOS. Control signals Cbp and Cbn are input to the gates of the switch transistors 132 and 142, respectively. The sources of the switch transistors 132 and 142 are connected to the power supply line VDD and the ground line VSS, respectively. The drains of the switch transistors 132 and 142 are connected to substrate bias lines Vbp and Vbn, respectively. The bodies of the switch transistors 132 and 142 are connected to the substrate bias lines Vbp and Vbn, respectively. However, when the well in which the switch transistors 132 and 142 are formed and the well in which the logic circuit 111 is formed are separated, the power supply It may be connected to the line VDD and the ground line VSS (see FIG. 35 for the well).

  The switch transistor 133 is a switch transistor for the current source transistor 131, is connected in series with the current source transistor 131, and switches the current source transistor 131 on and off according to the control signal Cbp for pMOS. On the other hand, the switch transistor 143 is a switch transistor for the current source transistor 141, is connected in series with the current source transistor 141, and switches the current source transistor 141 on and off according to the control signal Cbn for nMOS. Control signals Cbp and Cbn are input to the gates of the switch transistors 133 and 143, respectively. The sources of the switch transistors 133 and 143 are connected to the ground line VSS and the power supply line VDD, respectively. The drains of the switch transistors 133 and 143 are connected to the sources of the current source transistors 131 and 141, respectively. The bodies of the switch transistors 133 and 143 are connected to the substrate bias lines Vbn and Vbp, respectively. However, when the logic circuit 111 and the well are separated, they may be connected to the ground line VSS and the power supply line VDD.

  When the control signal Cbp for pMOS is turned on (High), the switch transistor 132 is turned off, the switch transistor 133 is turned on, and the switch transistor 133 makes the current source transistor 131 conductive. This means that a predetermined value of current flows through the pMOS. As a result, a substrate current Ibp is generated from the current source transistor 131, and the substrate bias voltage Vbp becomes lower than VDD (substrate bias ON state).

  On the other hand, when the control signal Cbp for pMOS is turned OFF (Low), the switch transistor 132 is turned ON, the switch transistor 133 is turned OFF, and the switch transistor 133 makes the current source transistor 131 nonconductive. This means that a predetermined value of current does not flow through the pMOS. As a result, the substrate bias line for pMOS and the power supply line become equipotential, and the substrate bias voltage Vbp becomes VDD, that is, zero bias (substrate bias OFF state).

  When the control signal Cbn for nMOS is turned on (Low), the switch transistor 142 is turned off, the switch transistor 143 is turned on, and the switch transistor 143 brings the current source transistor 141 into a conductive state. This means that a predetermined value of current flows through the nMOS. As a result, a substrate current Ibn is generated from the current source transistor 141, and the substrate bias voltage Vbn becomes higher than VSS (substrate bias ON state).

  On the other hand, when the control signal Cbn for nMOS is turned OFF (High), the switch transistor 142 is turned ON, the switch transistor 143 is turned OFF, and the switch transistor 143 makes the current source transistor 141 non-conductive. This means that a predetermined value of current does not flow through the nMOS. As a result, the substrate bias line for nMOS and the ground line become equipotential, and the substrate bias voltage Vbn becomes VSS, that is, zero bias (substrate bias OFF state).

  FIG. 3 shows an example of the wiring layout of the substrate bias generation circuit 112 of the first embodiment. FIG. 3 shows an example of the layout of the power supply line VDD, the ground line VSS, the substrate bias line Vbp for pMOS, the substrate bias line Vbn for nMOS, the control signal line Cbp for pMOS, and the control signal line Cbn for nMOS. Has been. 3 further shows a current source transistor 131 for pMOS, a switch transistor 132 for pMOS, a switch transistor 133 for pMOS, a current source transistor 141 for nMOS, a switch transistor 142 for nMOS, and a switch transistor 143 for nMOS. An example layout is shown.

  As shown in FIG. 3, the gate length of the pMOS current source transistor 131 is longer than the gate length of the pMOS switch transistor 133. Therefore, the pMOS current source transistor 131 can improve the processing accuracy in the manufacturing process and reduce manufacturing variations compared to the pMOS switch transistor 133. Since the pMOS switch transistor 133 has a faster switching operation than the pMOS power transistor 131, the substrate bias current can be controlled earlier.

  Similarly, as shown in FIG. 3, the gate length of the nMOS current source transistor 141 is longer than the gate length of the nMOS switch transistor 143. Therefore, the nMOS current source transistor 141 can improve the processing accuracy in the manufacturing process and reduce manufacturing variations compared to the nMOS switch transistor 143. Further, since the nMOS switch transistor 143 has a faster switching operation than the nMOS power transistor 141, the substrate bias current can be controlled earlier.

  In this embodiment, the gate length of the pMOS current source transistor 131 is longer than the gate length of the pMOS switch transistor 133, but the gate width of the pMOS current source transistor 131 is pMOS. A configuration smaller than the gate width of the switch transistor 133 may be used. Similarly, the gate width of the nMOS current source transistor 141 may be smaller than the gate width of the nMOS switch transistor 143.

  FIG. 4 shows the diode characteristics of the parasitic diode 123-126. As shown in FIG. 4, the current I flowing through the parasitic diode 123-126 increases exponentially according to the forward bias voltage Vf. The forward bias voltage Vf is fixed at a value commensurate with the substrate currents Ibp and Ibn. When the forward bias voltage Vf is applied to the MOS transistors 121 and 122, the threshold voltage Vth of the MOS transistors 121 and 122 is lowered, and the operating speed of the MOS transistors 121 and 122 is improved. As shown in FIG. 4, the current I flowing through the parasitic diode 123-126 increases with temperature.

  The semiconductor integrated circuit device 101 of this embodiment includes a current source transistor 131, a current source transistor 141, switch transistors 132 and 142, a switch transistor 133, and a transistor for generating a substrate bias by flowing a current through the substrate. 143. The gates of the current source transistors 131 and 141 are connected to the power supply line VDD and the ground line VSS, not to the control signal lines Cbp and Cbn, respectively. As a result, the inputs of the current source transistors 131 and 141 are not the control signals Cbp and Cbn that are relatively susceptible to noise, but the power supply potential VDD and the ground potential VSS that are relatively less susceptible to noise. Thereby, the amounts of the substrate currents Ibp and Ibn are stabilized, and the voltage values of the substrate bias lines Vbp and Vbn are fixed. Note that the gates of the switch transistors 132 and 142 and the gates of the switch transistors 133 and 143 are connected to the control signal lines Cbp and Cbn, respectively.

  Here, the embodiment of FIG. 2 is compared with the comparative example of FIG. FIG. 5 is a circuit configuration diagram of the semiconductor integrated circuit device 101 of the comparative example. The semiconductor integrated circuit device 101 of this comparative example includes current source transistors 131 and 141 and switch transistors 132 and 142, but does not include switch transistors 133 and 143. The gates of the current source transistors 131 and 141 and the gates of the switch transistors 132 and 142 are connected to control signal lines Cbp and Cbn, respectively. Therefore, when comparing the embodiment of FIG. 2 with the comparative example of FIG. 5, the input of the current source transistors 131 and 141 of the embodiment of FIG. 2 is less susceptible to noise, and the comparison of the comparative example of FIG. The inputs of the current source transistors 131 and 141 are more susceptible to noise. Therefore, the present embodiment is superior in the stability of the current amounts of the substrate currents Ibp and Ibn, and the voltage values of the substrate bias lines Vbp and Vbn are more fixed.

  The substrate bias generation circuit 112 of this embodiment includes a substrate bias generation circuit 113 for pMOS and a substrate bias generation circuit 114 for nMOS, but may include only a substrate bias generation circuit 113 for pMOS. However, only the substrate bias generating circuit 114 for nMOS may be provided. One of the pMOS transistor 121 and the nMOS transistor 122 corresponds to an example of a first conductivity type transistor, and the other of the pMOS transistor 121 and the nMOS transistor 122 corresponds to an example of a second conductivity type transistor.

  Hereinafter, various modified embodiments of the present embodiment will be described, and these modified embodiments will be described focusing on differences from the present embodiment.

(Second embodiment)
FIG. 6 is a circuit configuration diagram of the semiconductor integrated circuit device 101 of the second embodiment. The semiconductor integrated circuit device 101 includes a logic circuit 111 and a substrate bias generation circuit 112. As described above, the logic circuit 111 includes the logic cell 211 and the fill cell 212. However, for convenience of explanation, only the logic cell 211 is displayed in FIG. The substrate bias generation circuit 112 includes a substrate bias generation circuit 113 for pMOS and a substrate bias generation circuit 114 for nMOS. A side sectional view of the semiconductor integrated circuit device 101 is as shown in FIG.

  In the first embodiment, the current source transistors 131 and 141 are nMOS and pMOS, respectively, whereas in the second embodiment, the current source transistors 131 and 141 are pMOS and nMOS, respectively. Furthermore, in the first embodiment, the sources of the current source transistors 131 and 141 are connected to the power supply line VDD and the ground line VSS, respectively, whereas in the second embodiment, the sources of the current source transistors 131 and 141 are connected. Are connected to the ground line VSS and the power supply line VDD, respectively. Furthermore, in the first embodiment, the bodies of the current source transistors 131 and 141 are connected to the substrate bias lines Vbn and Vbp, respectively, whereas in the second embodiment, the bodies of the current source transistors 131 and 141 are These are connected to substrate bias lines Vbp and Vbn, respectively. The bodies of the current source transistors 131 and 141 may be connected to the power supply line VDD and the ground line VSS, respectively, when the logic circuit 111 and the well are separated.

  As shown in FIG. 4, the current flowing through the parasitic diode 123-126 at a low temperature is very small as compared to that at a high temperature. In the first embodiment, since the currents flowing through the current source transistors 131 and 141 at the low temperature are substantially the same as those at the high temperature, the substrate bias voltages Vbp and Vbn greatly increase at the low temperature. However, in the second embodiment, as the substrate bias voltages Vbp and Vbn increase, the gate voltage applied to the current source transistors 131 and 141 decreases, and the current flowing through the current source transistors 131 and 141 decreases. An increase in the bias voltages Vbp and Vbn can be suppressed. In the second embodiment, since the source potentials of the current source transistors 131 and 141 are the substrate bias potentials Vbp and Vbn, respectively, such an operation is possible.

  As described above, in the second embodiment, the current source transistors 131 and 141 are current sources for flowing current between VSS and VDD and Vbp and Vbn, respectively, are pMOS and nMOS, and have gates connected to VSS and VDD. The switch transistors 133 and 143 are nMOS and pMOS, respectively. When Vbp and Vbn rise, the gate voltage applied to the current source transistors 131 and 141 decreases due to the action of the current source transistors 131 and 141, and the current flowing through the current source transistors 131 and 141 decreases. An excessive increase in Vbp and Vbn is suppressed.

(Third embodiment)
FIG. 7 is a circuit diagram of the semiconductor integrated circuit device 101 of the third embodiment. The semiconductor integrated circuit device 101 includes a logic circuit 111, a first substrate bias generation circuit 112A, and a second substrate bias generation circuit 112B. As described above, the logic circuit 111 includes the logic cell 211 and the fill cell 212. However, for convenience of explanation, only the logic cell 211 is displayed in FIG. The first substrate bias generation circuit 112A includes a first substrate bias generation circuit 113A for pMOS and a first substrate bias generation circuit 114A for nMOS. The second substrate bias generation circuit 112B includes a second substrate bias generation circuit 113B for pMOS and a second substrate bias generation circuit 114B for nMOS.

  The first substrate bias generation circuit 112A has the same circuit configuration as the substrate bias generation circuit 112 of the first embodiment. On the other hand, the second substrate bias generation circuit 112B has a circuit configuration obtained by removing the switch transistors 132 and 142 from the substrate bias generation circuit 112 of the first embodiment. In FIG. 7, the suffix “A” is attached to the reference number of each transistor constituting the first substrate bias generation circuit 112A, and the reference number of each transistor constituting the second substrate bias generation circuit 112B is attached to the reference number. The subscript “B” is attached.

  In the first substrate bias generation circuit 112A, the first control signal Cbp1 for pMOS is input to the gates of the switch transistors 132A and 133A. The first control signal Cbn1 for nMOS is input to the gates of the switch transistors 142A and 143A. On the other hand, in the second substrate bias generation circuit 112B, the second control signal Cbp2 for pMOS is input to the gate of the switch transistor 133B. The second control signal Cbn2 for nMOS is input to the gate of the switch transistor 143B.

  In the third embodiment, the substrate bias can be switched ON / OFF by the first control signals Cbp1 and Cbn1. The substrate bias for pMOS is turned on / off by the control signal Cbp1 for pMOS, and the substrate bias for nMOS is turned on / off by the control signal Cbn1 for nMOS.

  In the third embodiment, the amount of substrate current can be changed by the second control signals Cbp2 and Cbn2. If only the first control signal is turned on, only the current source transistor of the first bias generation circuit is turned on. If the first and second control signals are turned on, the first and second bias generation circuits are turned on. This is because the current source transistor is turned on. The amount of substrate current for pMOS is changed by the control signal Cbp2 for pMOS, and the amount of substrate current for nMOS is changed by the control signal Cbn2 for nMOS.

  As described above, in the third embodiment, the amount of substrate current can be changed. Therefore, in the third embodiment, not only can the substrate biases Vbp and Vbn be switched on and off, but also the voltage values of the substrate biases Vbp and Vbn can be changed. Here, the current source transistors 131A and 131B are nMOSs having the same structure, and the current source transistors 141A and 141B are pMOSs having the same structure. Therefore, when both the current source transistors 131A and 131B are ON, the amount of substrate current for the pMOS is doubled compared to when only the current source transistor 131A is ON, and both the current source transistors 141A and 141B are ON. In this case, the amount of substrate current for the nMOS is doubled compared to the case where only the current source transistor 141A is ON. In the third embodiment, the first substrate bias generation circuit 112A is provided with the switch transistors 132 and 142, but the second substrate bias generation circuit 112B is not provided with the switch transistors 132 and 142. . This is because the switch transistors 132 and 142 are zero bias control switch transistors, and it is sufficient to provide one each.

  FIG. 8A shows the relationship between the control signals Cbp1 and Cbp2 and the substrate bias Vbp, and FIG. 8B shows the relationship between the control signals Cbn1 and Cbn2 and the substrate bias Vbn.

  As shown in FIG. 8A, when the control signals Cbp1 and Cbp2 are L and L, respectively, the substrate bias Vbp becomes VDD (0 bias). When the control signals Cbp1 and Cbp2 are H and L, respectively, the substrate bias Vbp becomes the first voltage value Vbp1. This corresponds to the substrate bias when the current source transistor 131A is ON and the current source transistor 131B is OFF. When the control signals Cbp1 and Cbp2 are H and H, respectively, the substrate bias Vbp becomes the second voltage value Vbp2. This corresponds to a substrate bias when the current source transistor 131A and the current source transistor 131B are both ON. Here, VDD> Vbp1> Vbp2> VSS.

  As shown in FIG. 8B, when the control signals Cbn1 and Cbn2 are H and H, respectively, the substrate bias Vbn becomes VSS (0 bias). When the control signals Cbn1 and Cbn2 are L and H, respectively, the substrate bias Vbn becomes the first voltage value Vbn1. This corresponds to the substrate bias when the current source transistor 141A is ON and the current source transistor 141B is OFF. When the control signals Cbn1 and Cbn2 are L and L, respectively, the substrate bias Vbn becomes the second voltage value Vbn2. This corresponds to a substrate bias when the current source transistor 141A and the current source transistor 141B are both ON. Here, VSS <Vbn1 <Vbn2 <VDD.

  The semiconductor integrated circuit device 101 according to the third embodiment includes the two substrate bias generation circuits 112, but may include three or more substrate bias generation circuits 112 according to a desired current value. FIG. 9 is a circuit configuration diagram of the semiconductor integrated circuit device 101 including the N substrate bias generation circuits 112. N is an integer of 3 or more.

  The semiconductor integrated circuit device 101 of FIG. 9 includes a logic circuit 111, first to Nth substrate bias generation circuits 112-1, 2,..., N, and a control circuit 115. The first substrate bias generation circuit 112-1 has the same circuit configuration as the substrate bias generation circuit 112 of the first embodiment, and has the same circuit configuration as the substrate bias generation circuit 112A of FIG. On the other hand, the second to Nth substrate bias generation circuits 112-2,..., N have a circuit configuration obtained by removing the switch transistors 132 and 142 from the substrate bias generation circuit 112 of the first embodiment. The circuit configuration is the same as that of the substrate bias generation circuit 112B.

  In the embodiment of FIG. 9, the first to Nth control signals Cbp1, 2,... N for pMOS are output from the control circuit 115, and the first to Nth substrate bias generation circuits 112-1, 2,. ,, N. Similarly, first to Nth control signals Cbn1, 2,... N for nMOS are output from the control circuit 115, and are sent to the first to Nth substrate bias generation circuits 112-1, 2,. Entered. In the embodiment of FIG. 9, the substrate bias can be switched ON / OFF by the first control signals Cbp1 and Cbn1. Furthermore, the amount of substrate current can be changed by the second to Nth control signals Cbp2,..., N, Cbn2,. Therefore, in the embodiment of FIG. 9, it is possible to finely change the amount of substrate current and finely change the voltage values of the substrate biases Vbp and Vbn.

(Fourth embodiment)
FIG. 10 is a circuit diagram of the semiconductor integrated circuit device 101 of the fourth embodiment. The semiconductor integrated circuit device 101 includes a logic circuit 111, a first substrate bias generation circuit 112A, a second substrate bias generation circuit 112B, a control circuit 115, and a temperature monitor 116. The first substrate bias generation circuit 112A has the same circuit configuration as the first substrate bias generation circuit 112A in FIG. Similarly, the second substrate bias generation circuit 112B has the same circuit configuration as the second substrate bias generation circuit 112B in FIG.

  In this embodiment, a temperature monitor 116 is mounted on the control circuit 115, and a temperature measurement result is provided from the temperature monitor 116 to the control circuit 115. Then, the control circuit 115 changes the substrate current amount according to the temperature measurement result. In this embodiment, the control circuit 115 operates the first and second substrate bias generation circuits 112A and 112B at a high temperature, causes a larger substrate current to flow, and operates only the first substrate bias generation circuit 112A at a low temperature. , Suppress the substrate current. Thereby, in the present embodiment, it is possible to suppress the substrate bias voltages Vbp and Vbn from rising at a low temperature. Note that the semiconductor integrated circuit device 101 of this embodiment may include three or more substrate bias generation circuits 112 as in FIG. Thereby, it becomes possible to cope with finer temperature changes with finer current control.

  FIG. 11A shows the relationship between the operation mode and the control signals Cbp1, Cbp2, and FIG. 11B shows the relationship between the operation mode and the control signals Cbn1, Cbn2.

  As shown in FIG. 11A, in the standby mode, the control signals Cbp1 and Cbp2 are L and L, respectively. In the low temperature operation mode, the control signals Cbp1 and Cbp2 become H and L, respectively. In the high temperature operation mode, the control signals Cbp1 and Cbp2 become H and H, respectively.

  As shown in FIG. 11B, in the standby mode, the control signals Cbn1 and Cbn2 are H and H, respectively. In the low temperature operation mode, the control signals Cbn1 and Cbn2 are L and H, respectively. In the high temperature operation mode, the control signals Cbn1 and Cbn2 are L and L, respectively.

(5th Example)
FIG. 12 is a circuit configuration diagram of the semiconductor integrated circuit device 101 of the fifth embodiment. The semiconductor integrated circuit device 101 includes a logic circuit 111, a first substrate bias generation circuit 112A, a second substrate bias generation circuit 112B, a control circuit 115, and a temperature monitor 116. The first substrate bias generation circuit 112A has the same circuit configuration as the first substrate bias generation circuit 112A in FIG. Similarly, the second substrate bias generation circuit 112B has the same circuit configuration as the second substrate bias generation circuit 112B in FIG.

  In this embodiment, a temperature monitor 116 is mounted on the control circuit 115, and a temperature measurement result is provided from the temperature monitor 116 to the control circuit 115. Then, the control circuit 115 changes the substrate current amount according to the temperature measurement result. However, the control circuit 115 according to the fifth embodiment is opposite to the control circuit 115 according to the fourth embodiment, and operates the first and second substrate bias generation circuits 112A and 112B at a low temperature so that a larger substrate current flows. When the temperature is high, only the first substrate bias generation circuit 112A is operated to suppress the substrate current. Thereby, in the present embodiment, the substrate bias voltages Vbp and Vbn at high temperatures can be suppressed, and the leakage current at high temperatures can be suppressed. Note that the semiconductor integrated circuit device 101 of this embodiment may include three or more substrate bias generation circuits 112 as in FIG. Thereby, it becomes possible to cope with finer temperature changes with finer current control.

  FIG. 13A shows the relationship between the operation mode and the control signals Cbp1, Cbp2, and FIG. 13B shows the relationship between the operation mode and the control signals Cbn1, Cbn2.

  As shown in FIG. 13A, in the standby mode, the control signals Cbp1 and Cbp2 are L and L, respectively. In the low temperature operation mode, the control signals Cbp1 and Cbp2 become H and H, respectively. In the high temperature operation mode, the control signals Cbp1 and Cbp2 become H and L, respectively.

  As shown in FIG. 13B, in the standby mode, the control signals Cbn1 and Cbn2 are H and H, respectively. In the low temperature operation mode, the control signals Cbn1 and Cbn2 are L and L, respectively. In the high temperature operation mode, the control signals Cbn1 and Cbn2 are L and H, respectively.

(Sixth embodiment)
FIG. 14 is a circuit configuration diagram of the semiconductor integrated circuit device 101 of the sixth embodiment. The semiconductor integrated circuit device 101 includes a logic circuit 111 and a substrate bias generation circuit 112. As described above, the logic circuit 111 includes the logic cell 211 and the fill cell 212. However, for convenience of explanation, only the logic cell 211 is displayed in FIG. The substrate bias generation circuit 112 includes a substrate bias generation circuit 113 for pMOS and a substrate bias generation circuit 114 for nMOS. A side sectional view of the semiconductor integrated circuit device 101 is as shown in FIG.

  In the first embodiment, the source of the switch transistor 132 is connected to VSS and the drain and body are connected to Vbn, whereas in the sixth embodiment, the source and body of the switch transistor 132 are connected to the third power supply line Vbnr. In addition, the drain is connected to Vbn. Furthermore, in the first embodiment, the source of the switch transistor 142 is connected to VDD, and the drain and body are connected to Vbp, whereas in the sixth embodiment, the source and body of the switch transistor 142 are connected to the fourth power source. The drain is connected to the line Vbpr and Vbp.

  When the control signal Cbp is L, the substrate bias Vbp becomes the reverse bias Vbpr. When the control signal Cbp is H, the substrate bias Vbp becomes the forward bias Vbpf. This corresponds to the substrate bias when the switch transistor 132 is turned off, the switch transistor 133 is turned on, and the current source transistor 131 is turned on. Here, VSS <Vbpf <VDD <Vbpr.

  When the control signal Cbn is H, the substrate bias Vbn becomes the reverse bias Vbnr. When the control signal Cbn is L, the substrate bias Vbn becomes the forward bias Vbnf. This corresponds to the substrate bias when the switch transistor 142 is turned off, the switch transistor 143 is turned on, and the current source transistor 141 is turned on. Here, VDD> Vbnf> VSS> Vbnr.

(Seventh embodiment)
FIG. 15 is a side sectional view of the semiconductor integrated circuit device 101 of the seventh embodiment. The semiconductor integrated circuit device 101 according to the first embodiment includes the pMOS current source transistor 131 and the nMOS current source transistor 141, whereas the semiconductor integrated circuit device 101 according to the seventh embodiment includes: The pMOS current source transistor 131 is provided, but the nMOS current source transistor 141 is not provided. Therefore, in the seventh embodiment, the pMOS 121 is used with a substrate bias applied, but the nMOS 122 is used without a substrate bias applied.

  In this embodiment, a substrate bias is applied to the pMOS 121, but no substrate bias is applied to the nMOS 122. Thus, in this embodiment, current flows through the base terminals of the parasitic bipolars 127 and 128 between the SBs of the pMOS 121 and between the DBs, but almost no current flows through the base terminals of the parasitic bipolars 129 and 130 between the SBs of the nMOS 122 and between the DBs. Does not flow. Thus, in this embodiment, the base current (current flowing through the bipolar base) is suppressed, and latch-up is unlikely to occur. In this embodiment, the deep N well is not necessary.

  FIG. 16 shows a circuit configuration diagram of the semiconductor integrated circuit device 101 of the seventh embodiment. The semiconductor integrated circuit device 101 includes a logic circuit 111 and a substrate bias generation circuit 112. As described above, the logic circuit 111 includes the logic cell 211 and the fill cell 212. However, for convenience of explanation, only the logic cell 211 is displayed in FIG. The substrate bias generation circuit 112 includes a substrate bias generation circuit 113 for pMOS, but does not include a substrate bias generation circuit 114 for nMOS.

  The substrate bias generation circuit 112 of this embodiment includes a substrate bias generation circuit 113 for pMOS and does not include a substrate bias generation circuit 114 for nMOS, but conversely includes a substrate bias generation circuit 114 for nMOS and includes a pMOS. The substrate bias generation circuit 113 may not be provided. In this case, the nMOS 122 is used with a substrate bias applied, and the pMOS 121 is used without a substrate bias applied.

  The substrate bias generation circuit 112 of the present embodiment has a circuit configuration in which the substrate bias generation circuit 114 for the nMOS is removed from the substrate bias generation circuit 112 of the first embodiment, but the second to sixth embodiments. The circuit configuration may be such that the substrate bias generation circuit 114 for nMOS is removed from any one of the substrate bias generation circuits 112.

(Eighth embodiment)
FIG. 17 is a side sectional view of the semiconductor integrated circuit device 101 of the eighth embodiment. Similar to the semiconductor integrated circuit device 101 of the first embodiment, the semiconductor integrated circuit device 101 of the eighth embodiment includes a pMOS 121, an nMOS 122, a pMOS current source transistor 131, and an nMOS current source transistor 141. . In the eighth embodiment, similarly to the first embodiment, the substrate bias Vbp for pMOS is generated by the current source transistor 131, and the substrate bias Vbn for nMOS is generated by the current source transistor 141. The pMOS 121 is used with a substrate bias Vbp applied, and the nMOS 122 is used with a substrate bias Vbn applied.

  The semiconductor integrated circuit device 101 of the eighth embodiment further includes a pMOS limiter transistor 151 and an nMOS limiter transistor 161. The limiter transistor is a transistor for suppressing the voltage amplitude below a set voltage. The limiter transistors 151 and 161 will be described in detail with reference to FIG.

  FIG. 18 is a circuit diagram of the semiconductor integrated circuit device 101 of the eighth embodiment. The semiconductor integrated circuit device 101 includes a logic circuit 111 and a substrate bias generation circuit 112. As described above, the logic circuit 111 includes the logic cell 211 and the fill cell 212. However, for convenience of explanation, only the logic cell 211 is displayed in FIG. The substrate bias generation circuit 112 includes a substrate bias generation circuit 113 for pMOS, a substrate bias generation circuit 114 for nMOS, a limiter transistor 151 for pMOS, and a limiter transistor 161 for nMOS.

  The limiter transistor 151 is a MOS transistor used as a pMOS limiter. On the other hand, the limiter transistor 161 is a MOS transistor used as an nMOS limiter. The gates of the limiter transistors 151 and 161 are connected to substrate bias lines Vbp and Vbn, respectively. The sources of the limiter transistors 151 and 161 are connected to the power supply line VDD and the ground line VSS, respectively. The drains of the limiter transistors 151 and 161 are connected to the substrate bias lines Vbp and Vbn, respectively. The bodies of the limiter transistors 151 and 161 are connected to the substrate bias lines Vbp and Vbn, respectively. The voltage values of the substrate bias lines Vbp and Vbn are determined by the threshold voltages Vth of the limiter transistors 151 and 161, respectively.

  In this embodiment, most of the currents output from the current source transistors 131 and 141 are caused to flow through the limiter transistors 151 and 161, respectively, thereby suppressing the base current (current flowing through the bipolar base) and avoiding latch-up. Can do.

  The substrate bias generation circuit 112 according to the present embodiment includes one pMOS limiter transistor 151 and one nMOS limiter transistor 161. However, the pMOS limiter transistor 151 and the nMOS limiter transistor 161 each include a pMOS limiter transistor 151 and an nMOS limiter transistor 161. And a plurality of each of them may be provided.

(Ninth embodiment)
FIG. 19 is a circuit configuration diagram of the semiconductor integrated circuit device 101 of the ninth embodiment.

  FIG. 19 shows the logic circuit 111 and the substrate bias generation circuit 112 according to any one of the first to third embodiments. FIG. 19 further shows a control circuit 115 that outputs a control signal Cb. The control signal Cb in FIG. 19 represents the control signal Cbn or Cbp. FIG. 19 further shows the substrate bias Vb. The substrate bias Vb in FIG. 19 represents the substrate bias Vbn or Vbp.

  Details of Cb and Vb will be described in the following text. The following description for Cb and Vb may apply to Cbn and Vbn only (ie nMOS only), Cbp and Vbp only (ie pMOS only), or both. Also good.

  In this embodiment, attention is paid to the relationship between the operating speed of the IC chip and the power supply voltage. The operation speed of the IC chip tends to be strongly influenced by the power supply voltage. Accordingly, when the power supply voltage is higher than a predetermined value, generally, the operation speed of the IC chip is sufficiently secured, and it is not necessary to apply a forward substrate bias to the IC chip. In the present embodiment, a control circuit 115 that controls the forward substrate bias according to the voltage supplied to the power supply line VDD will be described. The control circuit 115 of the present embodiment controls the substrate bias Vb to zero bias when the voltage supplied to the power supply line VDD is higher than a predetermined reference voltage.

  The semiconductor integrated circuit device 101 in FIG. 19 includes a comparator 401.

  The comparator 401 is a two-input one-output comparator. The comparator 401 compares the voltage input to one input terminal with the voltage input to the other input terminal, and outputs a comparison result COMP. In this embodiment, one input terminal of the comparator 401 is connected to the power supply line VDD, and the other input terminal is connected to the reference voltage Vref. The comparator 401 compares VDD and Vref. When VDD> Vref, the comparator 401 outputs COMP = L so that the substrate bias Vb becomes zero bias (ZBB), and when VDD ≦ Vref, the substrate bias Vb. COMP = H is output so that can be a forward bias (FBB). The setting of H and L in COMP may be opposite to the above logic.

  The control circuit 115 is a circuit that outputs a control signal Cb. The control circuit 115 controls the value of the control signal Cb according to the comparison result COMP and the chip information CHIP_ID. The chip information CHIP_ID is a value determined according to the relationship between the chip threshold value Vth and the target threshold value Vth_target in the logic circuit 111. In this embodiment, when Vth> Vth_target, it is necessary to apply a forward substrate bias to the chip to lower the chip threshold (that is, increase the operating speed), so CHIP_ID = H. On the other hand, when Vth ≦ Vth_target, it is not necessary to apply a forward substrate bias to the chip, so CHIP_ID = L. The setting of H and L in CHIP_ID may be opposite to the above logic.

  In this embodiment, when the control signal Cb is H, the substrate bias Vb is set to FBB, and when the control signal Cb is L, the substrate bias Vb is set to ZBB. The setting of H and L in the control signal Cb may be opposite to the above logic. As shown in FIG. 20, the control circuit 115 receives the comparison result COMP and the chip information CHIP_ID, and controls the control signal Cb so that the forward substrate bias is applied to the chip only when VDD ≦ Vref and Vth> Vth_target. To do.

  When the semiconductor integrated circuit device 101 does not include the control circuit 115 and the comparator 401 as in this embodiment, the forward substrate bias is applied to the chip even when the power supply voltage exceeds a predetermined value. The In this case, the higher the power supply voltage, the higher the substrate bias Vb and the power consumption increases. On the other hand, in the present embodiment, when the power supply voltage exceeds a predetermined reference voltage, the substrate bias Vb becomes zero bias, and thus an increase in power consumption is suppressed.

  FIG. 21 shows a specific example of the circuit of FIG. In FIG. 21, the control circuit 115 is composed of an AND circuit X. The AND circuit X receives the comparison result COMP and the chip information CHIP_ID. A control signal Cb is output from the AND circuit X.

(Tenth embodiment)
FIG. 22 is a circuit configuration diagram of the semiconductor integrated circuit device 101 of the tenth embodiment. The present embodiment is a modified embodiment of the ninth embodiment, and the present embodiment will be described with a focus on differences from the ninth embodiment.

  In the ninth embodiment, as shown in FIG. 23, the voltage supplied to the power supply line VDD may be in the vicinity of the reference voltage Vref. In this case, the ZBB mode and the FBB mode are frequently switched by noise superimposed on the power supply line VDD. The ZBB mode refers to a mode in which the substrate bias Vb is set to ZBB (zero bias), and the FBB mode refers to a mode in which the substrate bias Vb is set to FBB (forward bias). Such frequent switching of modes makes the operation of the IC chip unstable. Therefore, in this embodiment, the mode control is performed using the first reference voltage Vref1 and the second reference voltage Vref2. In the present embodiment, when the voltage supplied to the power supply line VDD is equal to or higher than the first reference voltage Vref1, the substrate bias Vb is controlled to zero bias, and the voltage supplied to the power supply line VDD is the second reference voltage. When Vref2 or less, the substrate bias Vb can be controlled to the forward bias.

  The semiconductor integrated circuit device 101 of FIG. 22 includes a comparator 401 and a selection switch 402.

  The selection switch 402 is a switch that has two inputs and one output and outputs one of the two input signals. The selection switch 402 switches the output signal according to the reference voltage control signal REF. In the present embodiment, the first reference voltage Vref1 and the second reference voltage Vref2 are input to the selection switch 402. There is a relationship of Vref1> Vref2 between the first reference voltage Vref1 and the second reference voltage Vref2. The reference voltage control signal REF is a signal output by a control circuit (not shown). The selection switch 402 outputs Vref1 when REF is logically H (= High), and outputs Vref2 when REF is logically L (= Low). The setting of H and L in the reference voltage control signal REF may be opposite to the above logic.

  The comparator 401 is a two-input one-output comparator. The comparator 401 compares the voltage input to one input terminal with the voltage input to the other input terminal, and outputs a comparison result COMP. In this embodiment, one input terminal of the comparator 401 is connected to the power supply line VDD, and the other input terminal is connected to the output of the selection switch 402. Therefore, in this embodiment, Vref 1 or Vref 2 is input to the comparator 401 via the selection switch 402.

  The control circuit 115 is a circuit that outputs a control signal Cb. The control circuit 115 controls the value of the control signal Cb according to the comparison result COMP, the reference voltage control signal REF, and the chip information CHIP_ID and at a timing specified by the set signal SET. Therefore, the control circuit 115 has four input terminals and one output terminal. Each of these input terminals receives a comparison result COMP, a reference voltage control signal REF, chip information CHIP_ID, or a set signal SET.

  The set signal SET is a signal for determining the timing at which the control circuit 115 takes in the states of the comparison result COMP and the reference voltage control signal REF. Note that there is no need to limit the timing of incorporating the state of the chip information CHIP_ID. The control circuit 115 of this embodiment takes in the states of COMP and REF at the timing when SET rises. Instead of using the rising edge of SET as the reference for incorporation, the falling edge of SET may be used as the reference for incorporation. The chip information CHIP_ID is the same as that in the ninth embodiment.

  A control signal Cb is output from the output terminal of the control circuit 115. When Cb is H, the substrate bias Vb is set to FBB, and when Cb is L, the substrate bias Vb is set to ZBB. The setting of H and L in Cb may be opposite to the above logic.

  The value of the control signal Cb is controlled according to the comparison result COMP, the reference voltage control signal REF, and the chip information CHIP_ID as shown in FIG. In the case of CHIP_ID = H, as shown in FIG. 24, Vref1 is selected if REF = H, and Vref2 is selected if REF = L. When Vref1 is selected, if VDD> Vref1, the substrate bias Vb is set to ZBB, and if VDD ≦ Vref1, the control signal Cb maintains the previous value (see FIG. 24). When Vref2 is selected, the substrate bias Vb is set to FBB if VDD ≦ Vref2, and the control signal Cb maintains the previous value if VDD> Vref2 (see FIG. 24). On the other hand, when CHIP_ID = L, since it is not necessary to apply a forward substrate bias to the chip, the control signal Cb is always L. That is, the substrate bias Vb is always ZBB.

  As described above, in this embodiment, VDD is compared with Vref1 and Vref2, and the substrate bias Vb is controlled according to the comparison result.

  The effect of this embodiment is particularly clear when the potential difference between Vref1 and Vref2 is larger than the amplitude of the external noise, as shown in FIG. In the case of FIG. 25, frequent switching between the ZBB mode and the FBB mode is avoided, and the mode of the semiconductor integrated circuit device 101 settles to one of the modes. In this case, the control signal Cb takes a constant value as shown in FIGS. 26 and 27 and does not switch frequently. FIG. 27 shows a timing chart when COMP = H. In this embodiment, when REF = H, COMP is taken into the control circuit 115 at the rise of SET, and Cb is output from the control circuit 115 at the fall of SET. The reference voltage control signal REF is repeatedly turned on and off at a constant period, whereby VDD is compared with both Vref1 and Vref2.

  FIG. 28 shows a specific example of the circuit of FIG. In FIG. 28, the control circuit 115 includes an AND circuit X1, a NOR circuit X2, an ExOR circuit X3, a NOT circuit X4, and flip-flops Y1, Y2, and Y3. A, B, and REF 'shown in FIG. 28 correspond to A, B, and REF' shown in FIG. 27, respectively.

  This embodiment can be applied not only to the forward substrate bias but also to the reverse substrate bias. For example, when VDD <Vref2, the substrate bias Vb is set to zero bias, and when VDD> Vref1, the control signal Cb may be controlled so that the substrate bias Vb can be set to a reverse bias. .

(Eleventh embodiment)
FIG. 29 is a circuit diagram of the semiconductor integrated circuit device 101 of the eleventh embodiment. The present embodiment is a modified embodiment of the tenth embodiment, and the present embodiment will be described with a focus on differences from the tenth embodiment.

  The semiconductor integrated circuit device 101 in FIG. 29 includes a comparator 401, a selection switch 402, and a counter 403.

  The selection switch 402 is a switch that has two inputs and one output and outputs one of the two input signals. The selection switch 402 switches the output signal according to the reference voltage control signal REF. Details of the selection switch 402 of this embodiment are the same as those of the selection switch 402 of the tenth embodiment.

  The comparator 401 is a two-input one-output edge trigger type comparator. The comparator 401 compares the voltage input to one input terminal with the voltage input to the other input terminal, and outputs a comparison result COMP. The comparator 401 of this embodiment performs a comparison operation a fixed number of times within a fixed time according to the clock signal CLK.

  The counter 403 has one input and one output, and is a counter that counts the number of times the input signal becomes H. The counter 403 may be a counter that counts the number of times the input signal becomes L. In this embodiment, the comparison result COMP is input to the counter 403. The counter 403 counts the number of times the comparison result COMP becomes H and outputs a count value N. The count number of the counter 403 is reset in response to the reset signal RESET. The reset signal RESET is a signal for determining the timing at which the counter 403 resets the count number.

  The control circuit 115 is a circuit that outputs a control signal Cb. The control circuit 115 controls the value of the control signal Cb according to the count value N, the reference voltage control signal REF, and the chip information CHIP_ID and at a timing specified by the set signal SET.

  When REF = H, the count value N represents the number of times VDD> Vref1. In this case, the control circuit 115 sets the control signal Cb to L if the count value N is equal to or greater than a certain value. In this case, the substrate bias Vb is set to ZBB. On the other hand, when REF = L, the count value N represents the number of times VDD> Vref2. In this case, the control circuit 115 sets the control signal Cb to H if the count value N is equal to or less than a certain value. In this case, the substrate bias Vb is set to FBB. Thereby, in the present embodiment, the value of VDD is averaged, and the influence of noise on the value of VDD is reduced. As a result, in this embodiment, the potential difference between Vref1 and Vref2 can be made smaller than that in the tenth embodiment, and the value of VDD can be lowered.

  FIG. 30 shows a timing chart in the eleventh embodiment. The selection switch 402 selects the first reference voltage Vref1 or the second reference voltage Vref2 according to REF, and outputs the selected reference voltage. The comparator 401 performs a comparison operation according to CLK and outputs a comparison result COMP. The counter 403 resets the number of counts when RESET becomes H. The counter 403 counts the number of times the comparison result COMP becomes H after resetting the count, and outputs a count value N. The control circuit 115 takes in the count value N at a timing defined by SET, and compares the count value N with a comparison value NUM (see FIG. 31). The control circuit 115 outputs a control signal Cb corresponding to the comparison result between N and NUM. Note that the reference voltage control signal REF is repeatedly turned on and off at a constant cycle, whereby the VDD is compared with both Vref1 and Vref2.

  FIG. 31 shows a specific example of the circuit of FIG. In FIG. 31, the control circuit 115 includes an AND circuit X1, a NOR circuit X2, an ExOR circuit X3, a NOT circuit X4, flip-flops Y1, Y2, and Y3, and a digital comparator Z1.

  The present embodiment can be applied not only to the forward substrate bias but also to the reverse substrate bias, as in the tenth embodiment.

(Twelfth embodiment)
FIG. 32 is a circuit configuration diagram of the semiconductor integrated circuit device 101 of the twelfth embodiment. The present embodiment is a modified embodiment of the tenth embodiment, and the present embodiment will be described with a focus on differences from the tenth embodiment.

  The semiconductor integrated circuit device 101 of FIG. 32 includes a comparator 401 and a selection switch 402.

  The selection switch 402 is a switch that has four inputs and one output, and outputs one of the four input signals. The selection switch 402 switches the output signal according to the reference voltage control signal REF and the operation mode signal MODE.

  In the present embodiment, the value of VDD changes according to the operation mode. In the operation mode A, the value of VDD is VDDa, and in the operation mode B, the value of VDD is VDDb. Therefore, in this embodiment, it is necessary to change the value of the reference voltage according to the operation mode.

  In this embodiment, four reference voltages Vref1a, Vref2a, Vref1b, and Vref2b are input to the selection switch 402. Reference voltages Vref1a and Vref2a represent first and second reference voltages in the operation mode A, respectively. There is a relationship of Vref1a> Vref2a between the first reference voltage Vref1a and the second reference voltage Vref2a. These reference voltages are selected when the operation mode signal MODE is H. On the other hand, the reference voltages Vref1b and Vref2b represent the first and second reference voltages in the operation mode B, respectively. There is a relationship of Vref1b> Vref2b between the first reference voltage Vref1b and the second reference voltage Vref2b. These reference voltages are selected when the operation mode signal MODE is L. The setting of H and L in the operation mode signal MODE may be opposite to the above logic.

  The comparator 401 is a two-input one-output comparator. The comparator 401 compares the voltage input to one input terminal with the voltage input to the other input terminal, and outputs a comparison result COMP. Details of the comparator 401 of this embodiment are the same as those of the comparator 401 of the tenth embodiment.

  This embodiment is applicable not only when there are two types of VDD values, but also when there are n types of VDD values. n is an integer of 3 or more. In this case, 2n types of reference voltages are input to the selection switch 402.

(Thirteenth embodiment)
FIG. 33 is a circuit configuration diagram of the semiconductor integrated circuit device 101 of the thirteenth embodiment. The semiconductor integrated circuit device 101 in FIG. 33 includes a clock control circuit 411. The clock control circuit 411 generates a clock signal CLK2 from the clock signal CLK1 and supplies the clock signal CLK2 to the logic circuit 111. The present embodiment is a modified embodiment of the ninth to twelfth embodiments, and this embodiment will be described with a focus on differences from the ninth to twelfth embodiments.

  In the ninth to twelfth embodiments, the control signal Cb may change due to a change in VDD. Therefore, it is necessary to guarantee the operation when the control signal Cb is switched. Therefore, in this embodiment, when the control signal Cb is switched, the operation is guaranteed by stopping the supply of the clock signal CLK2 to the logic circuit 111 and waiting until the substrate bias Vb becomes stable. An example of this standby process is shown in the timing chart of FIG.

(14th embodiment)
FIG. 35 is a circuit configuration diagram of the semiconductor integrated circuit device 101 of the fourteenth embodiment. The semiconductor integrated circuit device 101 includes one or more logic circuits 111 and one or more substrate bias generation circuits 112. The circuit configuration of each logic circuit 111 is the same as that of any one of the logic circuits 111 of the first to thirteenth embodiments. The circuit configuration of each substrate bias generation circuit 112 is the same as the circuit configuration of the substrate bias generation circuit 112 in any of the first to thirteenth embodiments.

  In the fourteenth embodiment, the body of each pMOS and the body of each nMOS in each substrate bias generation circuit 112 are connected to the substrate bias line Vbp for pMOS and the substrate bias line Vbn for nMOS, respectively. FIG. 2 (first embodiment), FIG. 6 (second embodiment), FIG. 7 (third embodiment), FIG. 14 (sixth embodiment), FIG. 16 (seventh embodiment), FIG. 18 (eighth embodiment). For example, the bodies of the switch transistors 133 and 143 are connected to the substrate bias lines Vbn and Vbp, respectively.

  Thus, in the fourteenth embodiment, the substrate bias generation circuit 112 and the logic circuit 111 to which the substrate bias is applied can be arranged on the same well. In FIG. 35, the substrate bias generation circuit 1 and the logic circuits 1 and 2 are both disposed on the P well 1 and the N well 1. Further, both the substrate bias generation circuit 2 and the logic circuits 1 and 2 are disposed on the P well 3 and the N well 3. Further, both the substrate bias generation circuit 3 and the logic circuits 1 and 2 are disposed on the P well 5 and the N well 5.

  Thus, in the fourteenth embodiment, as shown in FIG. 35, the substrate bias generation circuit 112 can be disposed in a region where no element such as a power supply strap is disposed. Thus, in the fourteenth embodiment, an increase in circuit area due to the mounting of the substrate bias generation circuit 112 can be suppressed.

(15th embodiment)
FIG. 36 is a circuit diagram of the semiconductor integrated circuit device 101 of the fifteenth embodiment. The semiconductor integrated circuit device 101 includes a logic cell portion and a portion other than the logic cell (fill cell portion). FIG. 36 shows a logic cell 211 and a fill cell 212 that constitute the semiconductor integrated circuit device 101. The logic cell 211 and the fill cell 212 are provided on the same substrate, and the semiconductor integrated circuit device 101 can generate a substrate bias by passing a current through the substrate. Here, the substrate is a semiconductor substrate such as a silicon substrate, for example, a bulk semiconductor substrate such as a bulk silicon substrate.

  In the logic cell 211, a pMOS 121 and an nMOS 122 constituting a CMOS are arranged. The pMOS 121 and the nMOS 122 of the fifteenth embodiment are transistors having the same configuration as the pMOS 121 and the nMOS 122 of the first embodiment, respectively. The connection destination of the gate, source, drain, and body of the pMOS 121 is the same as that of the pMOS 121 of the first embodiment. The connection destination of the gate, source, drain, and body of the nMOS 122 is the same as that of the nMOS 122 of the first embodiment. As in the first embodiment, parasitic diodes 123 and 124 exist between the SB and DB of the pMOS 121, respectively. As in the first embodiment, parasitic diodes 125 and 126 exist between the SB and DB of the nMOS 122, respectively. As in the first embodiment, the pMOS 121 and the nMOS 122 constitute an inverter here, but they may not constitute an inverter.

  In a cell-based design in which various logic cells are arranged, a fill cell is arranged in an area where no logic cell is arranged. In the fifteenth embodiment, a PN junction is connected between the power supply line VDD and the substrate bias line Vbp or between the ground line VSS and the substrate bias line Vbn by using a PN junction placed in such a fill cell. .

  A pMOS transistor 221 and an nMOS transistor 222 are arranged in the fill cell 212. The gate of the pMOS 221 and the gate of the nMOS 222 are connected to the power supply line VDD and the ground line VSS, respectively. The source of the pMOS 221 and the source of the nMOS 222 are also connected to the power supply line VDD and the ground line VSS, respectively. The drain of the pMOS 221 and the drain of the nMOS 222 are also connected to the power supply line VDD and the ground line VSS, respectively. The body of the pMOS 221 and the body of the nMOS 222 are connected to the substrate bias line Vbp for pMOS and the substrate bias line Vbn for nMOS, respectively. Parasitic diodes 223 and 224 exist between the SB and DB of the pMOS 221, respectively. Parasitic diodes 225 and 226 exist between the SB and DB of the nMOS 222, respectively.

  Thus, in this embodiment, the pMOS 221 and the nMOS 222 are arranged in the fill cell 212 which is an empty space. In this embodiment, the source and drain of the pMOS 221 are connected to the power supply line VDD, and the source and drain of the nMOS 222 are connected to the ground line VSS. Therefore, in this embodiment, the parasitic diodes 223 and 224 are interposed between the power supply line VDD and the substrate bias line Vbp, and the parasitic diodes 225 and 226 are interposed between the ground line VSS and the substrate bias line Vbn. Intervene. As a result, in this embodiment, the PN junction area of the semiconductor integrated circuit device 101 is increased by the amount of the parasitic diodes 223-226 as compared with the case where the pMOS 211 and the nMOS 222 are not provided.

  By using such pMOS 221 and nMOS 222, the PN junction area of the semiconductor integrated circuit device 101 can be adjusted. This is because the number of such pMOS 221 and nMOS 222 may be increased if the PN junction area is increased, and the number of such pMOS 221 and nMOS 222 may be decreased if the PN junction area is decreased. Therefore, in this embodiment, the variation in the PN junction area in the logic cell 211 is absorbed by the variation in the PN junction area in the fill cell 212, so that the PN junction area of the semiconductor integrated circuit device 101 is converted into a cell utilization rate (utilization). Regardless, it can be kept constant. Thereby, in this embodiment, the substrate current amount can be optimized. Note that the pMOS 221 and the nMOS 222 of the fill cell 212 can also be used to adjust the diffusion region area and gate wiring area of the semiconductor integrated circuit device 101. Further, if the AA in the fill cell 212 is connected to the power supply line VDD with a metal, this becomes a load capacitance between the power supply line VDD and the substrate. Thereby, fluctuations in the substrate potential can be suppressed.

  In the present embodiment, as described above, the source and drain of the pMOS 221 are both connected to the power supply line VDD, and the source and drain of the nMOS 222 are both connected to the ground line VSS. Thus, in this embodiment, the source and drain of the pMOS 221 are equipotential, and the source and drain of the nMOS 222 are equipotential. Thereby, in this embodiment, the influence of the leakage current on the pMOS 221 and the nMOS 222 is reduced.

  One of the above-described pMOS 221 and nMOS 222 corresponds to an example of a first conductivity type transistor disposed in a fill cell, and the other of the above-described pMOS 221 and nMOS 222 corresponds to an example of a second conductivity type transistor disposed in a fill cell. To do.

  42A and 42B show examples of the wiring layout of the semiconductor integrated circuit device 101 of the fifteenth embodiment. 42A and 42B show an example of the layout of the power supply line VDD and the ground line VSS, along with an example of the layout of the pMOS 221 and the nMOS 222 in the fill cell 212, respectively.

  Further, in this embodiment, the configuration example in which the pMOS transistor and the nMOS transistor are arranged in the fill cell 212 is shown, but the transistor is not necessarily a transistor, and the configuration in which the p-type diffusion portion and the n-type diffusion portion are arranged is also possible. I do not care.

(Sixteenth embodiment)
FIG. 37 is a circuit configuration diagram of the semiconductor integrated circuit device 101 of the sixteenth embodiment. The sixteenth embodiment is a modified embodiment of the fifteenth embodiment, and the sixteenth embodiment will be described focusing on the differences from the fifteenth embodiment.

  In the fifteenth embodiment, as shown in FIG. 36, the gate of the pMOS 221 and the gate of the nMOS 222 are connected to the power supply line VDD and the ground line VSS, respectively, whereas in the sixteenth embodiment, as shown in FIG. In addition, the gate of the pMOS 221 and the gate of the nMOS 222 are connected by wiring.

  In general, in the sub-100 nm process, it is said that the processing accuracy cannot be improved unless the gate wiring is regularly etched. In this regard, in this embodiment, since the gate shape of the transistor in the logic cell 211 and the gate shape of the transistor in the fill cell 212 are the same, the processing accuracy is good. In this embodiment, the gates of the pMOS 221 and the nMOS 222 are floating nodes. Thus, by using the gates of the pMOS 221 and the nMOS 222 as floating nodes, the wiring resources can be reduced and the gate leakage of the pMOS 221 and the nMOS 222 can be reduced. Conversely, in this embodiment, the floating node may be eliminated by connecting the gates of the pMOS 221 and the nMOS 222 to the power line VDD or the ground line VSS (or other fixed potential line).

  FIGS. 43A and 43B show examples of the wiring layout of the semiconductor integrated circuit device 101 according to the sixteenth embodiment. 43A and 43B show an example of the layout of the power supply line VDD and the ground line VSS, along with an example of the layout of the pMOS 221 and the nMOS 222 in the fill cell 212, respectively. 43A, the gates of pMOS 221 and nMOS 222 are floating nodes, and in FIG. 43B, the gates of pMOS 221 and nMOS 222 are connected to power supply line VDD. In FIG. 43B, as indicated by an arrow N, the wiring between the source of the nMOS 222 and the ground line VSS and the wiring between the drain and the ground line VSS are shared.

(Seventeenth embodiment)
FIG. 38 is a circuit configuration diagram of the semiconductor integrated circuit device 101 of the seventeenth embodiment. The seventeenth embodiment is a modified embodiment of the fifteenth embodiment, and the seventeenth embodiment will be described focusing on the differences from the fifteenth embodiment.

  In the fifteenth embodiment, as shown in FIG. 36, the gate of the pMOS 221 and the gate of the nMOS 222 are connected to the power supply line VDD and the ground line VSS, respectively, whereas in the seventeenth embodiment, as shown in FIG. Further, the gate of the pMOS 221 and the gate of the nMOS 222 are not connected to any wiring.

  Thereby, in this embodiment, it is not necessary to secure gate contact regions for the pMOS 221 and the nMOS 222, and the circuit area of the fill cell 212 can be reduced. In this embodiment, the gate voltages of the pMOS 221 and the nMOS 222 cannot be specified. However, since these sources and drains are equipotential and connected to the power supply line VDD or the ground line VSS, there is no particular problem. .

  FIG. 44 shows an example of the wiring layout of the semiconductor integrated circuit device 101 of the seventeenth embodiment. FIG. 44 shows an example of the layout of the power supply line VDD and the ground line VSS together with an example of the layout of the pMOS 221 and the nMOS 222 in the fill cell 212. In FIG. 44, as indicated by an arrow P, the wiring between the source of the pMOS 221 and the power supply line VDD and the wiring between the drain and the power supply line VDD are shared.

(Eighteenth embodiment)
FIG. 39 is a circuit configuration diagram of the semiconductor integrated circuit device 101 of the eighteenth embodiment. The eighteenth embodiment is a modified embodiment of the fifteenth embodiment, and the eighteenth embodiment will be described focusing on the differences from the fifteenth embodiment.

  In the fifteenth embodiment, as shown in FIG. 36, the gate of the pMOS 221 and the gate of the nMOS 222 are connected to the power supply line VDD and the ground line VSS, respectively, whereas in the eighteenth embodiment, as shown in FIG. In addition, the gate of the pMOS 221 and the gate of the nMOS 222 are connected to the ground line VSS and the ground line VDD, respectively.

  Thereby, in this embodiment, channels are formed in the pMOS 221 and the nMOS 222, and the effective PN junction area between the pMOS 211 and the nMOS 222 is increased.

  FIG. 45 shows an example of the wiring layout of the semiconductor integrated circuit device 101 of the eighteenth embodiment. FIG. 45 shows an example of the layout of the power supply line VDD and the ground line VSS along with an example of the layout of the pMOS 221 and the nMOS 222 in the fill cell 212. In FIG. 45, as indicated by an arrow P, the wiring between the source of the pMOS 221 and the power supply line VDD and the wiring between the drain and the power supply line VDD are shared.

(Nineteenth embodiment)
FIG. 40 is a circuit configuration diagram of the semiconductor integrated circuit device 101 of the nineteenth embodiment. The nineteenth embodiment is a modified embodiment of the fifteenth embodiment, and the nineteenth embodiment will be described focusing on the differences from the fifteenth embodiment.

  In the fifteenth embodiment, as shown in FIG. 36, the drain of the pMOS 221 and the drain of the nMOS 222 are connected to the power supply line VDD and the ground line VSS, respectively, whereas in the nineteenth embodiment, as shown in FIG. In addition, the drain of the pMOS 221 and the drain of the nMOS 222 are not connected to any wiring.

  Generally, a transistor for a logic circuit has a source connected to a power supply line or a ground line, and a drain connected to an output terminal. The drain potential varies depending on the output logic. For example, when the outputs of the pMOS and nMOS constituting the inverter are L, the substrate current flows in both the source and drain in the nMOS, but the substrate current flows only in the source in the pMOS. The drain-side PN junction may or may not affect the substrate current depending on the output logic value.

  In this embodiment, the influence of the drain-side PN junction is avoided in the fill cell transistor. In this embodiment, the gates of the pMOS 221 and the nMOS 222 are connected to the power supply line VDD and the ground line VSS, respectively, and the drains of the pMOS 221 and the nMOS 222 are not connected to any wiring. Therefore, among the parasitic diodes 223 to 226, the parasitic diodes 223 and 225 (source side PN junctions) are interposed between the power supply line VDD and the substrate bias line Vbp or between the ground line VSS and the substrate bias line Vbn. ) Only. This embodiment is suitable for use when, for example, it is desired to design the PN junction area accurately.

  In the semiconductor integrated circuit device 101, a plurality of fill cells 212 of the fifteenth embodiment and a plurality of fill cells 212 of the nineteenth embodiment may be arranged in an arbitrary number ratio. Alternatively, a plurality of fill cells 212 of the nineteenth embodiment and a plurality of fill cells 212 of the twentieth embodiment may be used. As a result, it is possible to realize a junction area equivalent to a state where the output logic values H and L are arbitrary in an actual logic cell.

  FIG. 46 shows an example of the wiring layout of the semiconductor integrated circuit device 101 of the nineteenth embodiment. FIG. 46 shows an example of the layout of the power supply line VDD and the ground line VSS along with an example of the layout of the pMOS 221 and the nMOS 222 in the fill cell 212.

(20th embodiment)
FIG. 41 is a circuit configuration diagram of the semiconductor integrated circuit device 101 of the twentieth embodiment. The twentieth embodiment is a modified embodiment of the eighteenth embodiment, and the twentieth embodiment will be described focusing on the differences from the eighteenth embodiment.

  In the eighteenth embodiment, as shown in FIG. 39, the drain of the pMOS 221 and the drain of the nMOS 222 are connected to the power supply line VDD and the ground line VSS, respectively, whereas in the twentieth embodiment, as shown in FIG. In addition, the drain of the pMOS 221 and the drain of the nMOS 222 are not connected to any wiring.

  In this embodiment, the drains of the pMOS 221 and the nMOS 222 are not connected to any wiring, but the gates of the pMOS 221 and the nMOS 222 are connected to the ground line VSS and the power supply line VDD, respectively. Therefore, in this embodiment, channels are formed in the pMOS 221 and the nMOS 222, and the drains of the pMOS 221 and the nMOS 222 are effectively equivalent to being connected to the power supply line VDD and the ground line VSS, respectively. That is, the PN junction area of the pMOS 221 and the nMOS 222 in the twentieth embodiment is the sum of the source PN junction area and the drain PN junction area, as in the eighteenth embodiment.

  However, in this embodiment, the drain wirings of the pMOS 221 and the nMOS 222 are unnecessary, so that other wirings can pass through the drain regions of the pMOS 221 and the nMOS 222, and the wiring routing is made efficient.

  FIGS. 47A and 47B show examples of the wiring layout of the semiconductor integrated circuit device 101 of the twentieth embodiment. 47A and 47B show an example of the layout of the power supply line VDD and the ground line VSS, along with an example of the layout of the pMOS 221 and the nMOS 222 in the fill cell 212, respectively. In FIG. 47A, the shape of the wiring to the pMOS 221 and the nMOS 222 is non-linear, and in FIG. 47B, the shape of the wiring to the pMOS 221 and the nMOS 222 is linear.

1 is a side sectional view of a semiconductor integrated circuit device according to a first embodiment. 1 is a circuit configuration diagram of a semiconductor integrated circuit device according to a first embodiment. FIG. An example of the wiring layout of the substrate bias generation circuit of the first embodiment is shown. The diode characteristic of a parasitic diode is shown. It is a circuit block diagram of the semiconductor integrated circuit device of a comparative example. It is a circuit block diagram of the semiconductor integrated circuit device of 2nd Example. It is a circuit block diagram of the semiconductor integrated circuit device of 3rd Example. The relationship between the control signals Cbp1 and Cbp2 and the substrate bias Vbp is shown. The relationship between the control signals Cbn1 and Cbn2 and the substrate bias Vbn is shown. It is a circuit block diagram of the semiconductor integrated circuit device of the modified example of 3rd Example. It is a circuit block diagram of the semiconductor integrated circuit device of 4th Example. The relationship between the operation mode and the control signals Cbp1 and Cbp2 is shown. The relationship between the operation mode and the control signals Cbn1 and Cbn2 is shown. It is a circuit block diagram of the semiconductor integrated circuit device of 5th Example. The relationship between the operation mode and the control signals Cbp1 and Cbp2 is shown. The relationship between the operation mode and the control signals Cbn1 and Cbn2 is shown. It is a circuit block diagram of the semiconductor integrated circuit device of 6th Example. It is a sectional side view of the semiconductor integrated circuit device of 7th Example. It is a circuit block diagram of the semiconductor integrated circuit device of 7th Example. It is side sectional drawing of the semiconductor integrated circuit device of 8th Example. It is a circuit block diagram of the semiconductor integrated circuit device of 8th Example. It is a circuit block diagram of the semiconductor integrated circuit device of 9th Example. It is a table | surface for demonstrating the control signal Cb of 9th Example. A specific example of the circuit of FIG. 19 is shown. It is a circuit block diagram of the semiconductor integrated circuit device of 10th Example. It is a figure for demonstrating the relationship between Vref and VDD. It is a table | surface for demonstrating the control signal Cb of 10th Example. It is a figure for demonstrating the relationship between Vref1, Vref2, and VDD. It is a table | surface for demonstrating the control signal Cb of 10th Example. 10 shows a timing chart in the tenth embodiment. A specific example of the circuit of FIG. 22 is shown. It is a circuit block diagram of the semiconductor integrated circuit device of 11th Example. 12 shows a timing chart in the eleventh embodiment. A specific example of the circuit of FIG. 29 is shown. It is a circuit block diagram of the semiconductor integrated circuit device of 12th Example. It is a circuit block diagram of the semiconductor integrated circuit device of 13th Example. A timing chart in the 13th embodiment is shown. It is a circuit block diagram of the semiconductor integrated circuit device of 14th Example. It is a circuit block diagram of the semiconductor integrated circuit device of 15th Example. It is a circuit block diagram of the semiconductor integrated circuit device of 16th Example. It is a circuit block diagram of the semiconductor integrated circuit device of 17th Example. It is a circuit block diagram of the semiconductor integrated circuit device of 18th Example. It is a circuit block diagram of the semiconductor integrated circuit device of 19th Example. It is a circuit block diagram of the semiconductor integrated circuit device of 20th Example. An example of the wiring layout of the semiconductor integrated circuit device according to the fifteenth embodiment is shown. An example of the wiring layout of the semiconductor integrated circuit device according to the fifteenth embodiment is shown. An example of a wiring layout of the semiconductor integrated circuit device according to the sixteenth embodiment is shown. An example of a wiring layout of the semiconductor integrated circuit device according to the sixteenth embodiment is shown. An example of a wiring layout of the semiconductor integrated circuit device according to the seventeenth embodiment is shown. An example of a wiring layout of a semiconductor integrated circuit device according to an eighteenth embodiment is shown. An example of a wiring layout of a semiconductor integrated circuit device according to a nineteenth embodiment is shown. An example of a wiring layout of the semiconductor integrated circuit device of the 20th embodiment is shown. An example of a wiring layout of the semiconductor integrated circuit device of the 20th embodiment is shown.

Explanation of symbols

DESCRIPTION OF SYMBOLS 101 Semiconductor integrated circuit device 111 Logic circuit 112 Substrate bias generation circuit 113 Substrate bias generation circuit for pMOS 114 Substrate bias generation circuit for nMOS 115 Control circuit 116 Temperature monitor 117 Reverse direction substrate bias generation circuit 121 pMOS
122 nMOS
123 Parasitic diode between pMOS SBs 124 Parasitic diode between pMOS DBs 125 Parasitic diode between nMOS SBs 126 Parasitic diode between nMOS DBs 127 Parasitic bipolar between SBs of pMOS 128 Parasitic bipolar between DBs of pMOS 129 nMOS SB parasitic bipolar 130 nMOS DB bipolar 131 Current source transistor 132 Switch transistor 133 Switch transistor 141 Current source transistor 142 Switch transistor 143 Switch transistor 151 Limiter transistor 161 Limiter transistor 211 Logic cell 212 Fill cell 221 pMOS
222 nMOS
223 Parasitic diode between SBs of pMOS 224 Parasitic diode between DBs of pMOS 225 Parasitic diode between SBs of nMOS 226 Parasitic diode between SBs of nMOS 301 Substrate 311 N well 312 P well 321 n + diffusion region 322 p + diffusion region 401 Comparator 402 selection switch 403 counter 411 clock control circuit

Claims (5)

A semiconductor substrate;
A first first conductivity type transistor and a second first conductivity type transistor connected in series between a first power supply line and a second substrate well provided on the semiconductor substrate;
The source or drain of the first first conductivity type transistor is connected to the first power supply line, and a first control signal input from the outside is applied to the gate of the first first conductivity type transistor. Entered,
A source or drain of the second first conductivity type transistor is connected to the second substrate well; a gate of the second first conductivity type transistor is connected to a second power supply line;
The semiconductor device further includes a first second conductivity type transistor and a second second conductivity type transistor connected in series between the second power supply line and a first substrate well provided on the semiconductor substrate. ,
The source or drain of the first second conductivity type transistor is connected to the second power supply line, and a second control signal input from the outside is applied to the gate of the first second conductivity type transistor. Entered,
The source or drain of the second second conductivity type transistor is connected to the first substrate well, and the gate of the second second conductivity type transistor is connected to the first power supply line. A semiconductor integrated circuit device. A semiconductor substrate;
A first first conductivity type transistor and a first second conductivity type transistor connected in series between a first power supply line and a second substrate well provided on the semiconductor substrate;
The source or drain of the first first conductivity type transistor is connected to the first power supply line, and a first control signal input from the outside is applied to the gate of the first first conductivity type transistor. Entered,
A source or drain of the first second conductivity type transistor is connected to the second substrate well; a gate of the first second conductivity type transistor is connected to the first power supply line;
A second first conductivity type transistor and a second second conductivity type transistor connected in series between a second power supply line and a first substrate well provided on the semiconductor substrate;
The source or drain of the second second conductivity type transistor is connected to the second power supply line, and a second control signal input from the outside is applied to the gate of the second second conductivity type transistor. Entered,
The source or drain of the second first conductivity type transistor is connected to the first substrate well, and the gate of the second first conductivity type transistor is connected to the second power supply line. A semiconductor integrated circuit device. A third conductivity type transistor connected between the second power line and the second substrate well;
The first control signal is input to the gate of the third second conductivity type transistor,
A third conductivity type transistor connected between the first power line and the first substrate well;
3. The semiconductor integrated circuit device according to claim 1, wherein the second control signal is input to a gate of the third first conductivity type transistor. A fourth conductivity type transistor connected between the second power line and the second substrate well;
A gate of the fourth second conductivity type transistor is connected to the second substrate well; one of a source and a drain of the fourth second conductivity type transistor is connected to the second power line; The other of the source and the drain is connected to the second substrate well;
A fourth conductivity type transistor connected between the first power supply line and the first substrate well;
A gate of the fourth first conductivity type transistor is connected to the first substrate well; one of a source and a drain of the fourth first conductivity type transistor is connected to the first power line; 3. The semiconductor integrated circuit device according to claim 1, wherein the other one of the source and the drain is connected to the first substrate well. A logic cell formed on the semiconductor substrate;
A fill cell disposed in a region different from the logic cell on the semiconductor substrate;
The fill cell includes a plurality of pairs each having one second conductivity type transistor formed on the second substrate well and one first conductivity type transistor formed on the first substrate well. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device is provided.

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